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authorciceron <ciceron@138bc75d-0d04-0410-961f-82ee72b054a4>2001-12-07 21:47:53 +0000
committerciceron <ciceron@138bc75d-0d04-0410-961f-82ee72b054a4>2001-12-07 21:47:53 +0000
commitd815c7518b8d20fcc5aa6bc4e60b799c37cae6d6 (patch)
tree3f5e1439af92960fbddad0cc509d9fea26d40f46 /gcc/config/sparc
parentffe45e288ba47014f904485af33a3bc70d872139 (diff)
downloadgcc-d815c7518b8d20fcc5aa6bc4e60b799c37cae6d6.tar.gz
* config/sparc/sparc.c (epilogue_renumber): Do not replace %fp
with %sp because it can cause the delayed instruction to load below the stack. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@47772 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/sparc')
-rw-r--r--gcc/config/sparc/sparc.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index ec3aa0e86eb..dec8b8c9389 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -5427,6 +5427,30 @@ epilogue_renumber (where, test)
case CONST_DOUBLE:
return 0;
+ /* Do not replace the frame pointer with the stack pointer because
+ it can cause the delayed instruction to load below the stack.
+ This occurs when instructions like:
+
+ (set (reg/i:SI 24 %i0)
+ (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
+ (const_int -20 [0xffffffec])) 0))
+
+ are in the return delayed slot. */
+ case PLUS:
+ if (GET_CODE (XEXP (*where, 0)) == REG
+ && REGNO (XEXP (*where, 0)) == FRAME_POINTER_REGNUM
+ && (GET_CODE (XEXP (*where, 1)) != CONST_INT
+ || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
+ return 1;
+ break;
+
+ case MEM:
+ if (SPARC_STACK_BIAS
+ && GET_CODE (XEXP (*where, 0)) == REG
+ && REGNO (XEXP (*where, 0)) == FRAME_POINTER_REGNUM)
+ return 1;
+ break;
+
default:
break;
}