diff options
| author | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-01-21 22:01:24 +0000 |
|---|---|---|
| committer | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-01-21 22:01:24 +0000 |
| commit | ffde65b31066f17eef243be882bb89a6e19370aa (patch) | |
| tree | ea876d041c0a63eefccdac5416a8678e75da4cfc /gcc/config/sparc | |
| parent | a8c7acc4db08ce7c8ac3ddcb943f9219e2893792 (diff) | |
| download | gcc-ffde65b31066f17eef243be882bb89a6e19370aa.tar.gz | |
[.]
2015-01-21 Basile Starynkevitch <basile@starynkevitch.net>
{{merged with trunk -i.e. GCC5.0 in stage4- using
svn merge -r209216:219879 svn+ssh://bstarynk@gcc.gnu.org/svn/gcc/trunk
but should probably have used
svn merge -r209216:219879 ^/trunk
we don't use svnmerge.py anymore since our svn is version 1.8.10
}}
VERY UNSTABLE
2015-01-20 Basile Starynkevitch <basile@starynkevitch.net>
Move previous topdir ChangeLog.MELT to ChangeLog.MELT.2008-2014
[contrib/]
2015-01-21 Basile Starynkevitch <basile@starynkevitch.net>
* MELT-Plugin-Makefile: Able to make upgrade-melt as a
plugin. Works for GCC 5.0. Remove GCC 4.7 old stuff.
Move previous contrib/ChangeLog.MELT to ChangeLog.MELT.2008-2014
[gcc/]
2015-01-21 Basile Starynkevitch <basile@starynkevitch.net>
{{merged with trunk -i.e. GCC5.0 in stage4- using
svn merge -r209216:219879 svn+ssh://bstarynk@gcc.gnu.org/svn/gcc/trunk
but should probably have used
svn merge -r209216:219879 ^/trunk
**@@@ UNSTABLE since libmelt-ana-gimple.melt not compiling, but
translator painfully bootstrapping!!@@@@ }}
* toplev.c: Merged manually by keeping MELT extra stuff.
* toplev.h: Likewise.
* gengtype.c: Add "melt-runtime.h" in list, but merged with trunk.
* melt-runtime.h (MELT_VERSION_STRING): Bump to "1.2-pre-merged".
(meltgc_walk_gimple_seq): Remove.
(gt_ggc_mx_gimple_statement_d): Same for GCC 4.9 & 5.0
* melt-runtime.cc: Update copyright year.
(ggc_alloc_cleared_melt_valuevector_st, melt_resize_scangcvect):
Call ggc_internal_cleared_alloc.
(melt_val2passflag): Skip TODO_verify_ssa, TODO_verify_flow,
TODO_verify_stmts, TODO_verify_rtl_sharing for GCC 5.0.
(meltgc_walkstmt_cb, meltgc_walktree_cb)
(melt_tree_walk_frame_size, meltgc_walk_gimple_seq): Remove.
(melt_gt_ggc_mx_gimple_seq_d): Call
gt_ggc_mx_gimple_statement_base.
* melt-build-script.tpl: Update copyright year. Don't symlink
meltrunsup.h anymore.
* melt-build-script.sh: Regenerate.
* melt/warmelt-base.melt: Update copyright year.
(valdesc_object, valdesc_mapobjects, valdesc_mapstrings)
(valdesc_multiple, valdesc_closure, valdesc_routine, valdesc_hook)
(valdesc_bucketlongs, valdesc_jsonobject, valdesc_string)
(valdesc_strbuf, valdesc_pair, valdesc_list, valdesc_int)
(valdesc_double, valdesc_mixint, valdesc_mixloc)
(valdesc_mixbigint, valdesc_real, valdesc_special_data): Use
ggc_internal_alloc & ggc_internal_cleared_alloc for GCC 5.0.
(json_canonical_name): Use ISUPPER, ISALPHA, TOUPPER instead of
their standard <ctype.h> lowercase macros.
* melt/warmelt-modes.melt: Update copyright year.
(generate_runtypesupport_forwcopy_fun): Emit both GCC 4.9 & 5.0
compatible code.
* melt/libmelt-ana-base.melt: Update copyright year.
* melt/libmelt-ana-gimple.melt: TO BE IMPROVED
* melt/generated/*: Painfully regenerated several times thru GCC
4.9 MELT plugin.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@219975 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/sparc')
47 files changed, 571 insertions, 546 deletions
diff --git a/gcc/config/sparc/biarch64.h b/gcc/config/sparc/biarch64.h index 12eed3d2249..f6821c63877 100644 --- a/gcc/config/sparc/biarch64.h +++ b/gcc/config/sparc/biarch64.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC, for Sun SPARC. - Copyright (C) 2001-2014 Free Software Foundation, Inc. + Copyright (C) 2001-2015 Free Software Foundation, Inc. Contributed by David E. O'Brien <obrien@FreeBSD.org>. This file is part of GCC. diff --git a/gcc/config/sparc/constraints.md b/gcc/config/sparc/constraints.md index 6295be0ef03..e12efa12fdf 100644 --- a/gcc/config/sparc/constraints.md +++ b/gcc/config/sparc/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for SPARC. -;; Copyright (C) 2008-2014 Free Software Foundation, Inc. +;; Copyright (C) 2008-2015 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -171,7 +171,7 @@ ;; define_register_constraint would. This currently means that we cannot ;; use LRA on Sparc, since the constraint processing of LRA really depends ;; upon whether an extra constraint is for registers or not. It uses -;; REG_CLASS_FROM_CONSTRAINT, and checks it against NO_REGS. +;; reg_class_for_constraint, and checks it against NO_REGS. (define_constraint "U" "Pseudo-register or hard even-numbered integer register" (and (match_test "TARGET_ARCH32") diff --git a/gcc/config/sparc/cypress.md b/gcc/config/sparc/cypress.md index 848adca3bae..5f942e1ba30 100644 --- a/gcc/config/sparc/cypress.md +++ b/gcc/config/sparc/cypress.md @@ -1,5 +1,5 @@ ;; Scheduling description for SPARC Cypress. -;; Copyright (C) 2002-2014 Free Software Foundation, Inc. +;; Copyright (C) 2002-2015 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/default-64.h b/gcc/config/sparc/default-64.h index e4342a4a0e5..b56d4991b83 100644 --- a/gcc/config/sparc/default-64.h +++ b/gcc/config/sparc/default-64.h @@ -1,7 +1,7 @@ /* Definitions of target machine for GCC, for bi-arch SPARC, defaulting to 64-bit code generation. - Copyright (C) 1999-2014 Free Software Foundation, Inc. + Copyright (C) 1999-2015 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/driver-sparc.c b/gcc/config/sparc/driver-sparc.c index 7896561dc83..778de2ccde3 100644 --- a/gcc/config/sparc/driver-sparc.c +++ b/gcc/config/sparc/driver-sparc.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2011-2014 Free Software Foundation, Inc. + Copyright (C) 2011-2015 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/freebsd.h b/gcc/config/sparc/freebsd.h index 371312bb4df..fa40d4e1617 100644 --- a/gcc/config/sparc/freebsd.h +++ b/gcc/config/sparc/freebsd.h @@ -1,5 +1,5 @@ /* Definitions for Sun SPARC64 running FreeBSD using the ELF format - Copyright (C) 2001-2014 Free Software Foundation, Inc. + Copyright (C) 2001-2015 Free Software Foundation, Inc. Contributed by David E. O'Brien <obrien@FreeBSD.org> and BSDi. This file is part of GCC. @@ -71,14 +71,6 @@ along with GCC; see the file COPYING3. If not see #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) -/* Define this to set long double type size to use in libgcc2.c, which can - not depend on target_flags. */ -#if defined(__arch64__) || defined(__LONG_DOUBLE_128__) -#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 -#else -#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 -#endif - /* Definitions for 64-bit SPARC running systems with ELF. */ #define TARGET_ELF 1 diff --git a/gcc/config/sparc/hypersparc.md b/gcc/config/sparc/hypersparc.md index ba10fb03714..0317dd01e4a 100644 --- a/gcc/config/sparc/hypersparc.md +++ b/gcc/config/sparc/hypersparc.md @@ -1,5 +1,5 @@ ;; Scheduling description for HyperSPARC. -;; Copyright (C) 2002-2014 Free Software Foundation, Inc. +;; Copyright (C) 2002-2015 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/leon.md b/gcc/config/sparc/leon.md index 82b6a0d9633..aca92fc7bf8 100644 --- a/gcc/config/sparc/leon.md +++ b/gcc/config/sparc/leon.md @@ -1,5 +1,5 @@ ;; Scheduling description for LEON. -;; Copyright (C) 2010-2014 Free Software Foundation, Inc. +;; Copyright (C) 2010-2015 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -29,11 +29,11 @@ ;; Use a double reservation to work around the load pipeline hazard on UT699. (define_insn_reservation "leon3_load" 1 - (and (eq_attr "cpu" "leon3") (eq_attr "type" "load,sload")) + (and (eq_attr "cpu" "leon3,leon3v7") (eq_attr "type" "load,sload")) "leon_memory*2") (define_insn_reservation "leon_store" 2 - (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "store")) + (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "store")) "leon_memory*2") ;; This describes Gaisler Research's FPU @@ -44,21 +44,21 @@ (define_cpu_unit "grfpu_ds" "grfpu") (define_insn_reservation "leon_fp_alu" 4 - (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fp,fpcmp,fpmul")) + (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fp,fpcmp,fpmul")) "grfpu_alu, nothing*3") (define_insn_reservation "leon_fp_divs" 16 - (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivs")) + (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpdivs")) "grfpu_ds*14, nothing*2") (define_insn_reservation "leon_fp_divd" 17 - (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivd")) + (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpdivd")) "grfpu_ds*15, nothing*2") (define_insn_reservation "leon_fp_sqrts" 24 - (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrts")) + (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpsqrts")) "grfpu_ds*22, nothing*2") (define_insn_reservation "leon_fp_sqrtd" 25 - (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrtd")) + (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpsqrtd")) "grfpu_ds*23, nothing*2") diff --git a/gcc/config/sparc/linux.h b/gcc/config/sparc/linux.h index c54ba2cb51c..56def4bcd47 100644 --- a/gcc/config/sparc/linux.h +++ b/gcc/config/sparc/linux.h @@ -1,5 +1,5 @@ /* Definitions for SPARC running Linux-based GNU systems with ELF. - Copyright (C) 1996-2014 Free Software Foundation, Inc. + Copyright (C) 1996-2015 Free Software Foundation, Inc. Contributed by Eddie C. Dost (ecd@skynet.be) This file is part of GCC. @@ -122,14 +122,6 @@ do { \ SPARC ABI says that long double is 4 words. */ #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) -/* Define this to set long double type size to use in libgcc2.c, which can - not depend on target_flags. */ -#ifdef __LONG_DOUBLE_128__ -#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 -#else -#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 -#endif - #undef DITF_CONVERSION_LIBFUNCS #define DITF_CONVERSION_LIBFUNCS 1 diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h index f00fb42ffab..fa805fd4432 100644 --- a/gcc/config/sparc/linux64.h +++ b/gcc/config/sparc/linux64.h @@ -1,5 +1,5 @@ /* Definitions for 64-bit SPARC running Linux-based GNU systems with ELF. - Copyright (C) 1996-2014 Free Software Foundation, Inc. + Copyright (C) 1996-2015 Free Software Foundation, Inc. Contributed by David S. Miller (davem@caip.rutgers.edu) This file is part of GCC. @@ -70,14 +70,6 @@ along with GCC; see the file COPYING3. If not see #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) -/* Define this to set long double type size to use in libgcc2.c, which can - not depend on target_flags. */ -#if defined(__arch64__) || defined(__LONG_DOUBLE_128__) -#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 -#else -#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 -#endif - #undef CPP_SUBTARGET_SPEC #define CPP_SUBTARGET_SPEC "\ %{posix:-D_POSIX_SOURCE} \ diff --git a/gcc/config/sparc/long-double-switch.opt b/gcc/config/sparc/long-double-switch.opt index 50b69834b19..fede08b928a 100644 --- a/gcc/config/sparc/long-double-switch.opt +++ b/gcc/config/sparc/long-double-switch.opt @@ -1,6 +1,6 @@ ; Options for the SPARC port of the compiler ; -; Copyright (C) 2005-2014 Free Software Foundation, Inc. +; Copyright (C) 2005-2015 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/sparc/netbsd-elf.h b/gcc/config/sparc/netbsd-elf.h index 949d333f67c..165660ce532 100644 --- a/gcc/config/sparc/netbsd-elf.h +++ b/gcc/config/sparc/netbsd-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for ELF on NetBSD/sparc and NetBSD/sparc64. - Copyright (C) 2002-2014 Free Software Foundation, Inc. + Copyright (C) 2002-2015 Free Software Foundation, Inc. Contributed by Matthew Green (mrg@eterna.com.au). This file is part of GCC. @@ -168,12 +168,6 @@ along with GCC; see the file COPYING3. If not see #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) -#if defined(__arch64__) || defined(__LONG_DOUBLE_128__) -#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 -#else -#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 -#endif - #undef CC1_SPEC #if DEFAULT_ARCH32_P #define CC1_SPEC CC1_SPEC32 @@ -195,9 +189,6 @@ along with GCC; see the file COPYING3. If not see #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 128 -#undef LIBGCC2_LONG_DOUBLE_TYPE_SIZE -#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 - #undef CC1_SPEC #define CC1_SPEC CC1_SPEC64 @@ -210,9 +201,6 @@ along with GCC; see the file COPYING3. If not see #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE 64 -#undef LIBGCC2_LONG_DOUBLE_TYPE_SIZE -#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 - #undef CC1_SPEC #define CC1_SPEC CC1_SPEC32 diff --git a/gcc/config/sparc/niagara.md b/gcc/config/sparc/niagara.md index d0d2d39bd06..ba80f5b28a9 100644 --- a/gcc/config/sparc/niagara.md +++ b/gcc/config/sparc/niagara.md @@ -1,5 +1,5 @@ ;; Scheduling description for Niagara. -;; Copyright (C) 2006-2014 Free Software Foundation, Inc. +;; Copyright (C) 2006-2015 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/niagara2.md b/gcc/config/sparc/niagara2.md index e4aa87bd968..ebebb4b0005 100644 --- a/gcc/config/sparc/niagara2.md +++ b/gcc/config/sparc/niagara2.md @@ -1,5 +1,5 @@ ;; Scheduling description for Niagara-2 and Niagara-3. -;; Copyright (C) 2007-2014 Free Software Foundation, Inc. +;; Copyright (C) 2007-2015 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/niagara4.md b/gcc/config/sparc/niagara4.md index 6e9fde5156e..e553a5d6097 100644 --- a/gcc/config/sparc/niagara4.md +++ b/gcc/config/sparc/niagara4.md @@ -1,5 +1,5 @@ ;; Scheduling description for Niagara-4 -;; Copyright (C) 2012-2014 Free Software Foundation, Inc. +;; Copyright (C) 2012-2015 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/openbsd1-64.h b/gcc/config/sparc/openbsd1-64.h index 6ff6478b78d..768b66942c7 100644 --- a/gcc/config/sparc/openbsd1-64.h +++ b/gcc/config/sparc/openbsd1-64.h @@ -1,5 +1,5 @@ /* Configuration file for sparc64 OpenBSD target. - Copyright (C) 1999-2014 Free Software Foundation, Inc. + Copyright (C) 1999-2015 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/openbsd64.h b/gcc/config/sparc/openbsd64.h index e158a636b2c..a84d2106e63 100644 --- a/gcc/config/sparc/openbsd64.h +++ b/gcc/config/sparc/openbsd64.h @@ -1,5 +1,5 @@ /* Configuration file for sparc64 OpenBSD target. - Copyright (C) 1999-2014 Free Software Foundation, Inc. + Copyright (C) 1999-2015 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md index 98ab4a3aebf..88537c64f0c 100644 --- a/gcc/config/sparc/predicates.md +++ b/gcc/config/sparc/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for SPARC. -;; Copyright (C) 2005-2014 Free Software Foundation, Inc. +;; Copyright (C) 2005-2015 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -124,7 +124,7 @@ (define_predicate "symbolic_operand" (match_code "symbol_ref,label_ref,const") { - enum machine_mode omode = GET_MODE (op); + machine_mode omode = GET_MODE (op); if (omode != mode && omode != VOIDmode && mode != VOIDmode) return false; @@ -260,11 +260,6 @@ return REG_P (op) && SPARC_FP_REG_P (REGNO (op)); }) -;; Return true if OP is an integer register. -(define_special_predicate "int_register_operand" - (ior (match_test "register_operand (op, SImode)") - (match_test "TARGET_ARCH64 && register_operand (op, DImode)"))) - ;; Return true if OP is an integer register of the appropriate mode ;; for a cstore result. (define_special_predicate "cstore_result_operand" diff --git a/gcc/config/sparc/rtemself.h b/gcc/config/sparc/rtemself.h index d6c2dd68e9b..6d1d4fdbc95 100644 --- a/gcc/config/sparc/rtemself.h +++ b/gcc/config/sparc/rtemself.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a SPARC using ELF. - Copyright (C) 1996-2014 Free Software Foundation, Inc. + Copyright (C) 1996-2015 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h index b50a937b26f..5a2144261c4 100644 --- a/gcc/config/sparc/sol2.h +++ b/gcc/config/sparc/sol2.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC, for SPARC running Solaris 2 - Copyright (C) 1992-2014 Free Software Foundation, Inc. + Copyright (C) 1992-2015 Free Software Foundation, Inc. Contributed by Ron Guilmette (rfg@netcom.com). Additional changes by David V. Henkel-Wallace (gumby@cygnus.com). @@ -109,8 +109,6 @@ along with GCC; see the file COPYING3. If not see #define CPP_CPU64_DEFAULT_SPEC "" #undef ASM_CPU32_DEFAULT_SPEC #define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plus" -#undef ASM_CPU_DEFAULT_SPEC -#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC #endif #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc @@ -120,8 +118,6 @@ along with GCC; see the file COPYING3. If not see #define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusa" #undef ASM_CPU64_DEFAULT_SPEC #define ASM_CPU64_DEFAULT_SPEC "-xarch=v9a" -#undef ASM_CPU_DEFAULT_SPEC -#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC #endif #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 @@ -131,8 +127,6 @@ along with GCC; see the file COPYING3. If not see #define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb" #undef ASM_CPU64_DEFAULT_SPEC #define ASM_CPU64_DEFAULT_SPEC "-xarch=v9b" -#undef ASM_CPU_DEFAULT_SPEC -#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC #endif #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara @@ -142,8 +136,6 @@ along with GCC; see the file COPYING3. If not see #define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb" #undef ASM_CPU64_DEFAULT_SPEC #define ASM_CPU64_DEFAULT_SPEC "-xarch=v9b" -#undef ASM_CPU_DEFAULT_SPEC -#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC #endif #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 @@ -153,8 +145,6 @@ along with GCC; see the file COPYING3. If not see #define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb" #undef ASM_CPU64_DEFAULT_SPEC #define ASM_CPU64_DEFAULT_SPEC "-xarch=v9b" -#undef ASM_CPU_DEFAULT_SPEC -#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC #endif #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 @@ -164,8 +154,6 @@ along with GCC; see the file COPYING3. If not see #define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plus" AS_NIAGARA3_FLAG #undef ASM_CPU64_DEFAULT_SPEC #define ASM_CPU64_DEFAULT_SPEC "-xarch=v9" AS_NIAGARA3_FLAG -#undef ASM_CPU_DEFAULT_SPEC -#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC #endif #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 @@ -175,8 +163,6 @@ along with GCC; see the file COPYING3. If not see #define ASM_CPU32_DEFAULT_SPEC AS_SPARC32_FLAG AS_NIAGARA4_FLAG #undef ASM_CPU64_DEFAULT_SPEC #define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA4_FLAG -#undef ASM_CPU_DEFAULT_SPEC -#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC #endif #undef CPP_CPU_SPEC @@ -361,6 +347,23 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); } \ while (0) +/* Solaris as has a bug: a .common directive in .tbss or .tdata section + behaves as .tls_common rather than normal non-TLS .common. */ +#undef ASM_OUTPUT_ALIGNED_COMMON +#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ + do \ + { \ + if (TARGET_SUN_TLS \ + && in_section \ + && ((in_section->common.flags & SECTION_TLS) == SECTION_TLS)) \ + switch_to_section (bss_section); \ + fprintf ((FILE), "%s", COMMON_ASM_OP); \ + assemble_name ((FILE), (NAME)); \ + fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \ + (SIZE), (ALIGN) / BITS_PER_UNIT); \ + } \ + while (0) + #ifndef USE_GAS /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes using the @@ -376,7 +379,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); /* Sun as requires doublequoted section names on SPARC. While GNU as supports that, too, we prefer the standard variant. */ -#undef SECTION_NAME_FORMAT #define SECTION_NAME_FORMAT "\"%s\"" #endif /* !USE_GAS */ diff --git a/gcc/config/sparc/sp-elf.h b/gcc/config/sparc/sp-elf.h index 28366e64f36..85da652a99d 100644 --- a/gcc/config/sparc/sp-elf.h +++ b/gcc/config/sparc/sp-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for SPARC running in an embedded environment using the ELF file format. - Copyright (C) 2005-2014 Free Software Foundation, Inc. + Copyright (C) 2005-2015 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/sp64-elf.h b/gcc/config/sparc/sp64-elf.h index f0a5fe1d447..2fbdfd0872f 100644 --- a/gcc/config/sparc/sp64-elf.h +++ b/gcc/config/sparc/sp64-elf.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC, for SPARC64, ELF. - Copyright (C) 1994-2014 Free Software Foundation, Inc. + Copyright (C) 1994-2015 Free Software Foundation, Inc. Contributed by Doug Evans, dje@cygnus.com. This file is part of GCC. diff --git a/gcc/config/sparc/sparc-c.c b/gcc/config/sparc/sparc-c.c index bb4e51ffb51..b49599d7252 100644 --- a/gcc/config/sparc/sparc-c.c +++ b/gcc/config/sparc/sparc-c.c @@ -1,5 +1,5 @@ /* Subroutines used for macro/preprocessor support on SPARC. - Copyright (C) 2011-2014 Free Software Foundation, Inc. + Copyright (C) 2011-2015 Free Software Foundation, Inc. This file is part of GCC. @@ -21,6 +21,15 @@ along with GCC; see the file COPYING3. If not see #include "system.h" #include "coretypes.h" #include "tm.h" +#include "hash-set.h" +#include "machmode.h" +#include "vec.h" +#include "double-int.h" +#include "input.h" +#include "alias.h" +#include "symtab.h" +#include "wide-int.h" +#include "inchash.h" #include "tree.h" #include "tm_p.h" #include "flags.h" diff --git a/gcc/config/sparc/sparc-modes.def b/gcc/config/sparc/sparc-modes.def index 8dc9625b6a7..8b12fe1d7cb 100644 --- a/gcc/config/sparc/sparc-modes.def +++ b/gcc/config/sparc/sparc-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC, for Sun SPARC. - Copyright (C) 2002-2014 Free Software Foundation, Inc. + Copyright (C) 2002-2015 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com). 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, at Cygnus Support. diff --git a/gcc/config/sparc/sparc-opts.h b/gcc/config/sparc/sparc-opts.h index 13b375ae164..7679d0d7c95 100644 --- a/gcc/config/sparc/sparc-opts.h +++ b/gcc/config/sparc/sparc-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for SPARC. - Copyright (C) 1996-2014 Free Software Foundation, Inc. + Copyright (C) 1996-2015 Free Software Foundation, Inc. This file is part of GCC. @@ -31,6 +31,7 @@ enum processor_type { PROCESSOR_HYPERSPARC, PROCESSOR_LEON, PROCESSOR_LEON3, + PROCESSOR_LEON3V7, PROCESSOR_SPARCLITE, PROCESSOR_F930, PROCESSOR_F934, diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h index 1d63e46406d..143143709d1 100644 --- a/gcc/config/sparc/sparc-protos.h +++ b/gcc/config/sparc/sparc-protos.h @@ -1,5 +1,5 @@ /* Prototypes of target machine for SPARC. - Copyright (C) 1999-2014 Free Software Foundation, Inc. + Copyright (C) 1999-2015 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com). 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, at Cygnus Support. @@ -30,7 +30,7 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree); extern unsigned long sparc_type_code (tree); #ifdef ARGS_SIZE_RTX /* expr.h defines ARGS_SIZE_RTX and `enum direction' */ -extern enum direction function_arg_padding (enum machine_mode, const_tree); +extern enum direction function_arg_padding (machine_mode, const_tree); #endif /* ARGS_SIZE_RTX */ #endif /* TREE_CODE */ @@ -49,47 +49,46 @@ extern void sparc_output_scratch_registers (FILE *); extern void sparc_target_macros (void); #ifdef RTX_CODE -extern enum machine_mode select_cc_mode (enum rtx_code, rtx, rtx); +extern machine_mode select_cc_mode (enum rtx_code, rtx, rtx); /* Define the function that build the compare insn for scc and bcc. */ extern rtx gen_compare_reg (rtx cmp); extern rtx sparc_emit_float_lib_cmp (rtx, rtx, enum rtx_code); -extern void sparc_emit_floatunsdi (rtx [2], enum machine_mode); -extern void sparc_emit_fixunsdi (rtx [2], enum machine_mode); +extern void sparc_emit_floatunsdi (rtx [2], machine_mode); +extern void sparc_emit_fixunsdi (rtx [2], machine_mode); extern void emit_tfmode_binop (enum rtx_code, rtx *); extern void emit_tfmode_unop (enum rtx_code, rtx *); extern void emit_tfmode_cvt (enum rtx_code, rtx *); extern bool constant_address_p (rtx); extern bool legitimate_pic_operand_p (rtx); -extern rtx sparc_legitimize_reload_address (rtx, enum machine_mode, int, int, +extern rtx sparc_legitimize_reload_address (rtx, machine_mode, int, int, int, int *win); extern void load_got_register (void); extern void sparc_emit_call_insn (rtx, rtx); extern void sparc_defer_case_vector (rtx, rtx, int); -extern bool sparc_expand_move (enum machine_mode, rtx *); +extern bool sparc_expand_move (machine_mode, rtx *); extern void sparc_emit_set_symbolic_const64 (rtx, rtx, rtx); extern int sparc_splitdi_legitimate (rtx, rtx); extern int sparc_split_regreg_legitimate (rtx, rtx); -extern int sparc_absnegfloat_split_legitimate (rtx, rtx); -extern const char *output_ubranch (rtx, rtx); -extern const char *output_cbranch (rtx, rtx, int, int, int, rtx); -extern const char *output_return (rtx); -extern const char *output_sibcall (rtx, rtx); -extern const char *output_v8plus_shift (rtx, rtx *, const char *); -extern const char *output_v8plus_mult (rtx, rtx *, const char *); -extern const char *output_v9branch (rtx, rtx, int, int, int, int, rtx); +extern const char *output_ubranch (rtx, rtx_insn *); +extern const char *output_cbranch (rtx, rtx, int, int, int, rtx_insn *); +extern const char *output_return (rtx_insn *); +extern const char *output_sibcall (rtx_insn *, rtx); +extern const char *output_v8plus_shift (rtx_insn *, rtx *, const char *); +extern const char *output_v8plus_mult (rtx_insn *, rtx *, const char *); +extern const char *output_v9branch (rtx, rtx, int, int, int, int, rtx_insn *); extern const char *output_probe_stack_range (rtx, rtx); -extern const char *output_cbcond (rtx, rtx, rtx); +extern const char *output_cbcond (rtx, rtx, rtx_insn *); extern bool emit_scc_insn (rtx []); extern void emit_conditional_branch_insn (rtx []); extern int registers_ok_for_ldd_peep (rtx, rtx); extern int mems_ok_for_ldd_peep (rtx, rtx, rtx); -extern rtx widen_mem_for_ldd_peep (rtx, rtx, enum machine_mode); -extern int empty_delay_slot (rtx); +extern rtx widen_mem_for_ldd_peep (rtx, rtx, machine_mode); +extern int empty_delay_slot (rtx_insn *); extern int emit_cbcond_nop (rtx); -extern int eligible_for_call_delay (rtx); -extern int eligible_for_return_delay (rtx); -extern int eligible_for_sibcall_delay (rtx); -extern int emit_move_sequence (rtx, enum machine_mode); +extern int eligible_for_call_delay (rtx_insn *); +extern int eligible_for_return_delay (rtx_insn *); +extern int eligible_for_sibcall_delay (rtx_insn *); +extern int emit_move_sequence (rtx, machine_mode); extern int fp_sethi_p (rtx); extern int fp_mov_p (rtx); extern int fp_high_losum_p (rtx); @@ -100,15 +99,15 @@ extern int memory_ok_for_ldd (rtx); extern int v9_regcmp_p (enum rtx_code); /* Function used for V8+ code generation. Returns 1 if the high 32 bits of REG are 0 before INSN. */ -extern int sparc_check_64 (rtx, rtx); +extern int sparc_check_64 (rtx, rtx_insn *); extern rtx gen_df_reg (rtx, int); extern void sparc_expand_compare_and_swap (rtx op[]); extern void sparc_expand_vector_init (rtx, rtx); -extern void sparc_expand_vec_perm_bmask(enum machine_mode, rtx); -extern bool sparc_expand_conditional_move (enum machine_mode, rtx *); -extern void sparc_expand_vcond (enum machine_mode, rtx *, int, int); -unsigned int sparc_regmode_natural_size (enum machine_mode); -bool sparc_modes_tieable_p (enum machine_mode, enum machine_mode); +extern void sparc_expand_vec_perm_bmask(machine_mode, rtx); +extern bool sparc_expand_conditional_move (machine_mode, rtx *); +extern void sparc_expand_vcond (machine_mode, rtx *, int, int); +unsigned int sparc_regmode_natural_size (machine_mode); +bool sparc_modes_tieable_p (machine_mode, machine_mode); #endif /* RTX_CODE */ extern void sparc_emit_membar_for_model (enum memmodel, int, int); diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index f52b9761a1a..19e45c23fca 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for SPARC. - Copyright (C) 1987-2014 Free Software Foundation, Inc. + Copyright (C) 1987-2015 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com) 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, at Cygnus Support. @@ -24,7 +24,17 @@ along with GCC; see the file COPYING3. If not see #include "system.h" #include "coretypes.h" #include "tm.h" +#include "hash-set.h" +#include "machmode.h" +#include "vec.h" +#include "double-int.h" +#include "input.h" +#include "alias.h" +#include "symtab.h" +#include "wide-int.h" +#include "inchash.h" #include "tree.h" +#include "fold-const.h" #include "stringpool.h" #include "stor-layout.h" #include "calls.h" @@ -40,6 +50,15 @@ along with GCC; see the file COPYING3. If not see #include "flags.h" #include "function.h" #include "except.h" +#include "hashtab.h" +#include "statistics.h" +#include "real.h" +#include "fixed-value.h" +#include "expmed.h" +#include "dojump.h" +#include "explow.h" +#include "emit-rtl.h" +#include "stmt.h" #include "expr.h" #include "optabs.h" #include "recog.h" @@ -50,9 +69,15 @@ along with GCC; see the file COPYING3. If not see #include "target.h" #include "target-def.h" #include "common/common-target.h" -#include "pointer-set.h" #include "hash-table.h" -#include "vec.h" +#include "predict.h" +#include "dominance.h" +#include "cfg.h" +#include "cfgrtl.h" +#include "cfganal.h" +#include "lcm.h" +#include "cfgbuild.h" +#include "cfgcleanup.h" #include "basic-block.h" #include "tree-ssa-alias.h" #include "internal-fn.h" @@ -69,6 +94,8 @@ along with GCC; see the file COPYING3. If not see #include "opts.h" #include "tree-pass.h" #include "context.h" +#include "builtins.h" +#include "rtl-iter.h" /* Processor costs */ @@ -499,9 +526,6 @@ struct GTY(()) machine_function rtx frame_base_reg; HOST_WIDE_INT frame_base_offset; - /* Some local-dynamic TLS symbol name. */ - const char *some_ld_name; - /* Number of global or FP registers to be saved (as 4-byte quantities). */ int n_global_fp_regs; @@ -533,30 +557,30 @@ int sparc_indent_opcode = 0; static void sparc_option_override (void); static void sparc_init_modes (void); static void scan_record_type (const_tree, int *, int *, int *); -static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode, +static int function_arg_slotno (const CUMULATIVE_ARGS *, machine_mode, const_tree, bool, bool, int *, int *); -static int supersparc_adjust_cost (rtx, rtx, rtx, int); -static int hypersparc_adjust_cost (rtx, rtx, rtx, int); +static int supersparc_adjust_cost (rtx_insn *, rtx, rtx_insn *, int); +static int hypersparc_adjust_cost (rtx_insn *, rtx, rtx_insn *, int); static void sparc_emit_set_const32 (rtx, rtx); static void sparc_emit_set_const64 (rtx, rtx); static void sparc_output_addr_vec (rtx); static void sparc_output_addr_diff_vec (rtx); static void sparc_output_deferred_case_vectors (void); -static bool sparc_legitimate_address_p (enum machine_mode, rtx, bool); -static bool sparc_legitimate_constant_p (enum machine_mode, rtx); +static bool sparc_legitimate_address_p (machine_mode, rtx, bool); +static bool sparc_legitimate_constant_p (machine_mode, rtx); static rtx sparc_builtin_saveregs (void); static int epilogue_renumber (rtx *, int); static bool sparc_assemble_integer (rtx, unsigned int, int); -static int set_extends (rtx); +static int set_extends (rtx_insn *); static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT); static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT); #ifdef TARGET_SOLARIS static void sparc_solaris_elf_asm_named_section (const char *, unsigned int, tree) ATTRIBUTE_UNUSED; #endif -static int sparc_adjust_cost (rtx, rtx, rtx, int); +static int sparc_adjust_cost (rtx_insn *, rtx, rtx_insn *, int); static int sparc_issue_rate (void); static void sparc_sched_init (FILE *, int, int); static int sparc_use_sched_lookahead (void); @@ -573,52 +597,50 @@ static void sparc_init_builtins (void); static void sparc_fpu_init_builtins (void); static void sparc_vis_init_builtins (void); static tree sparc_builtin_decl (unsigned, bool); -static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int); +static rtx sparc_expand_builtin (tree, rtx, rtx, machine_mode, int); static tree sparc_fold_builtin (tree, int, tree *, bool); static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT, const_tree); static struct machine_function * sparc_init_machine_status (void); -static bool sparc_cannot_force_const_mem (enum machine_mode, rtx); +static bool sparc_cannot_force_const_mem (machine_mode, rtx); static rtx sparc_tls_get_addr (void); static rtx sparc_tls_got (void); -static const char *get_some_local_dynamic_name (void); -static int get_some_local_dynamic_name_1 (rtx *, void *); -static int sparc_register_move_cost (enum machine_mode, +static int sparc_register_move_cost (machine_mode, reg_class_t, reg_class_t); static bool sparc_rtx_costs (rtx, int, int, int, int *, bool); static rtx sparc_function_value (const_tree, const_tree, bool); -static rtx sparc_libcall_value (enum machine_mode, const_rtx); +static rtx sparc_libcall_value (machine_mode, const_rtx); static bool sparc_function_value_regno_p (const unsigned int); static rtx sparc_struct_value_rtx (tree, int); -static enum machine_mode sparc_promote_function_mode (const_tree, enum machine_mode, +static machine_mode sparc_promote_function_mode (const_tree, machine_mode, int *, const_tree, int); static bool sparc_return_in_memory (const_tree, const_tree); static bool sparc_strict_argument_naming (cumulative_args_t); static void sparc_va_start (tree, rtx); static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *); -static bool sparc_vector_mode_supported_p (enum machine_mode); +static bool sparc_vector_mode_supported_p (machine_mode); static bool sparc_tls_referenced_p (rtx); static rtx sparc_legitimize_tls_address (rtx); static rtx sparc_legitimize_pic_address (rtx, rtx); -static rtx sparc_legitimize_address (rtx, rtx, enum machine_mode); +static rtx sparc_legitimize_address (rtx, rtx, machine_mode); static rtx sparc_delegitimize_address (rtx); static bool sparc_mode_dependent_address_p (const_rtx, addr_space_t); static bool sparc_pass_by_reference (cumulative_args_t, - enum machine_mode, const_tree, bool); + machine_mode, const_tree, bool); static void sparc_function_arg_advance (cumulative_args_t, - enum machine_mode, const_tree, bool); + machine_mode, const_tree, bool); static rtx sparc_function_arg_1 (cumulative_args_t, - enum machine_mode, const_tree, bool, bool); + machine_mode, const_tree, bool, bool); static rtx sparc_function_arg (cumulative_args_t, - enum machine_mode, const_tree, bool); + machine_mode, const_tree, bool); static rtx sparc_function_incoming_arg (cumulative_args_t, - enum machine_mode, const_tree, bool); -static unsigned int sparc_function_arg_boundary (enum machine_mode, + machine_mode, const_tree, bool); +static unsigned int sparc_function_arg_boundary (machine_mode, const_tree); static int sparc_arg_partial_bytes (cumulative_args_t, - enum machine_mode, tree, bool); + machine_mode, tree, bool); static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; static void sparc_file_end (void); static bool sparc_frame_pointer_required (void); @@ -629,15 +651,15 @@ static void sparc_conditional_register_usage (void); static const char *sparc_mangle_type (const_tree); #endif static void sparc_trampoline_init (rtx, tree, rtx); -static enum machine_mode sparc_preferred_simd_mode (enum machine_mode); +static machine_mode sparc_preferred_simd_mode (machine_mode); static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass); static bool sparc_print_operand_punct_valid_p (unsigned char); static void sparc_print_operand (FILE *, rtx, int); static void sparc_print_operand_address (FILE *, rtx); static reg_class_t sparc_secondary_reload (bool, rtx, reg_class_t, - enum machine_mode, + machine_mode, secondary_reload_info *); -static enum machine_mode sparc_cstore_mode (enum insn_code icode); +static machine_mode sparc_cstore_mode (enum insn_code icode); static void sparc_atomic_assign_expand_fenv (tree *, tree *, tree *); #ifdef SUBTARGET_ATTRIBUTE_TABLE @@ -871,17 +893,10 @@ mem_ref (rtx x) pass runs as late as possible. The pass is inserted in the pass pipeline at the end of sparc_option_override. */ -static bool -sparc_gate_work_around_errata (void) -{ - /* The only errata we handle are those of the AT697F and UT699. */ - return sparc_fix_at697f != 0 || sparc_fix_ut699 != 0; -} - static unsigned int sparc_do_work_around_errata (void) { - rtx insn, next; + rtx_insn *insn, *next; /* Force all instructions to be split into their final form. */ split_all_insns_noflow (); @@ -893,8 +908,9 @@ sparc_do_work_around_errata (void) rtx set; /* Look into the instruction in a delay slot. */ - if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) - insn = XVECEXP (PATTERN (insn), 0, 1); + if (NONJUMP_INSN_P (insn)) + if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) + insn = seq->insn (1); /* Look for a single-word load into an odd-numbered FP register. */ if (sparc_fix_at697f @@ -1025,7 +1041,7 @@ sparc_do_work_around_errata (void) /* The problematic combination is with the sibling FP register. */ const unsigned int x = REGNO (SET_DEST (set)); const unsigned int y = x ^ 1; - rtx after; + rtx_insn *after; int i; next = next_active_insn (insn); @@ -1059,15 +1075,16 @@ sparc_do_work_around_errata (void) if (++i == n_insns) break; branch_p = true; - after = NULL_RTX; + after = NULL; } /* This is a branch with a filled delay slot. */ - else if (GET_CODE (PATTERN (after)) == SEQUENCE) + else if (rtx_sequence *seq = + dyn_cast <rtx_sequence *> (PATTERN (after))) { if (++i == n_insns) break; branch_p = true; - after = XVECEXP (PATTERN (after), 0, 1); + after = seq->insn (1); } /* This is a regular instruction. */ else @@ -1129,14 +1146,12 @@ const pass_data pass_data_work_around_errata = RTL_PASS, /* type */ "errata", /* name */ OPTGROUP_NONE, /* optinfo_flags */ - true, /* has_gate */ - true, /* has_execute */ TV_MACH_DEP, /* tv_id */ 0, /* properties_required */ 0, /* properties_provided */ 0, /* properties_destroyed */ 0, /* todo_flags_start */ - TODO_verify_rtl_sharing, /* todo_flags_finish */ + 0, /* todo_flags_finish */ }; class pass_work_around_errata : public rtl_opt_pass @@ -1147,8 +1162,16 @@ public: {} /* opt_pass methods: */ - bool gate () { return sparc_gate_work_around_errata (); } - unsigned int execute () { return sparc_do_work_around_errata (); } + virtual bool gate (function *) + { + /* The only errata we handle are those of the AT697F and UT699. */ + return sparc_fix_at697f != 0 || sparc_fix_ut699 != 0; + } + + virtual unsigned int execute (function *) + { + return sparc_do_work_around_errata (); + } }; // class pass_work_around_errata @@ -1246,6 +1269,7 @@ sparc_option_override (void) { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC }, { TARGET_CPU_leon, PROCESSOR_LEON }, { TARGET_CPU_leon3, PROCESSOR_LEON3 }, + { TARGET_CPU_leon3v7, PROCESSOR_LEON3V7 }, { TARGET_CPU_sparclite, PROCESSOR_F930 }, { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X }, { TARGET_CPU_sparclet, PROCESSOR_TSC701 }, @@ -1274,6 +1298,7 @@ sparc_option_override (void) { "hypersparc", MASK_ISA, MASK_V8|MASK_FPU }, { "leon", MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU }, { "leon3", MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU }, + { "leon3v7", MASK_ISA, MASK_LEON3|MASK_FPU }, { "sparclite", MASK_ISA, MASK_SPARCLITE }, /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */ { "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE }, @@ -1526,6 +1551,7 @@ sparc_option_override (void) sparc_costs = &leon_costs; break; case PROCESSOR_LEON3: + case PROCESSOR_LEON3V7: sparc_costs = &leon3_costs; break; case PROCESSOR_SPARCLET: @@ -1734,7 +1760,7 @@ can_use_mov_pic_label_ref (rtx label) /* Expand a move instruction. Return true if all work is done. */ bool -sparc_expand_move (enum machine_mode mode, rtx *operands) +sparc_expand_move (machine_mode mode, rtx *operands) { /* Handle sets of MEM first. */ if (GET_CODE (operands[0]) == MEM) @@ -1877,7 +1903,7 @@ sparc_expand_move (enum machine_mode mode, rtx *operands) static void sparc_emit_set_const32 (rtx op0, rtx op1) { - enum machine_mode mode = GET_MODE (op0); + machine_mode mode = GET_MODE (op0); rtx temp = op0; if (can_create_pseudo_p ()) @@ -2705,7 +2731,7 @@ sparc_emit_set_const64 (rtx op0, rtx op1) is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special processing is needed. */ -enum machine_mode +machine_mode select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED) { if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) @@ -2757,7 +2783,7 @@ select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED) static rtx gen_compare_reg_1 (enum rtx_code code, rtx x, rtx y) { - enum machine_mode mode; + machine_mode mode; rtx cc_reg; if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) @@ -3425,7 +3451,7 @@ emit_tfmode_cvt (enum rtx_code code, rtx *operands) nop into its delay slot. */ int -empty_delay_slot (rtx insn) +empty_delay_slot (rtx_insn *insn) { rtx seq; @@ -3481,7 +3507,7 @@ emit_cbcond_nop (rtx insn) /* Return nonzero if TRIAL can go into the call delay slot. */ int -eligible_for_call_delay (rtx trial) +eligible_for_call_delay (rtx_insn *trial) { rtx pat; @@ -3607,7 +3633,7 @@ eligible_for_restore_insn (rtx trial, bool return_p) /* Return nonzero if TRIAL can go into the function return's delay slot. */ int -eligible_for_return_delay (rtx trial) +eligible_for_return_delay (rtx_insn *trial) { int regno; rtx pat; @@ -3673,7 +3699,7 @@ eligible_for_return_delay (rtx trial) /* Return nonzero if TRIAL can go into the sibling call's delay slot. */ int -eligible_for_sibcall_delay (rtx trial) +eligible_for_sibcall_delay (rtx_insn *trial) { rtx pat; @@ -3722,7 +3748,7 @@ eligible_for_sibcall_delay (rtx trial) not constant (TLS) or not known at final link time (PIC). */ static bool -sparc_cannot_force_const_mem (enum machine_mode mode, rtx x) +sparc_cannot_force_const_mem (machine_mode mode, rtx x) { switch (GET_CODE (x)) { @@ -3816,7 +3842,7 @@ pic_address_needs_scratch (rtx x) satisfies CONSTANT_P. */ static bool -sparc_legitimate_constant_p (enum machine_mode mode, rtx x) +sparc_legitimate_constant_p (machine_mode mode, rtx x) { switch (GET_CODE (x)) { @@ -3912,7 +3938,7 @@ legitimate_pic_operand_p (rtx x) ordinarily. This changes a bit when generating PIC. */ static bool -sparc_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict) +sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict) { rtx rs1 = NULL, rs2 = NULL, imm1 = NULL; @@ -4103,7 +4129,8 @@ sparc_tls_referenced_p (rtx x) static rtx sparc_legitimize_tls_address (rtx addr) { - rtx temp1, temp2, temp3, ret, o0, got, insn; + rtx temp1, temp2, temp3, ret, o0, got; + rtx_insn *insn; gcc_assert (can_create_pseudo_p ()); @@ -4256,7 +4283,7 @@ sparc_legitimize_pic_address (rtx orig, rtx reg) || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig))) { rtx pic_ref, address; - rtx insn; + rtx_insn *insn; if (reg == 0) { @@ -4369,7 +4396,7 @@ sparc_legitimize_pic_address (rtx orig, rtx reg) static rtx sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, - enum machine_mode mode) + machine_mode mode) { rtx orig_x = x; @@ -4454,7 +4481,7 @@ sparc_delegitimize_address (rtx x) operand or requires a scratch register. */ rtx -sparc_legitimize_reload_address (rtx x, enum machine_mode mode, +sparc_legitimize_reload_address (rtx x, machine_mode mode, int opnum, int type, int ind_levels ATTRIBUTE_UNUSED, int *win) { @@ -4600,7 +4627,7 @@ load_got_register (void) void sparc_emit_call_insn (rtx pat, rtx addr) { - rtx insn; + rtx_insn *insn; insn = emit_call_insn (pat); @@ -4821,47 +4848,50 @@ sparc_init_modes (void) for (i = 0; i < NUM_MACHINE_MODES; i++) { - switch (GET_MODE_CLASS (i)) + machine_mode m = (machine_mode) i; + unsigned int size = GET_MODE_SIZE (m); + + switch (GET_MODE_CLASS (m)) { case MODE_INT: case MODE_PARTIAL_INT: case MODE_COMPLEX_INT: - if (GET_MODE_SIZE (i) < 4) + if (size < 4) sparc_mode_class[i] = 1 << (int) H_MODE; - else if (GET_MODE_SIZE (i) == 4) + else if (size == 4) sparc_mode_class[i] = 1 << (int) S_MODE; - else if (GET_MODE_SIZE (i) == 8) + else if (size == 8) sparc_mode_class[i] = 1 << (int) D_MODE; - else if (GET_MODE_SIZE (i) == 16) + else if (size == 16) sparc_mode_class[i] = 1 << (int) T_MODE; - else if (GET_MODE_SIZE (i) == 32) + else if (size == 32) sparc_mode_class[i] = 1 << (int) O_MODE; else sparc_mode_class[i] = 0; break; case MODE_VECTOR_INT: - if (GET_MODE_SIZE (i) == 4) + if (size == 4) sparc_mode_class[i] = 1 << (int) SF_MODE; - else if (GET_MODE_SIZE (i) == 8) + else if (size == 8) sparc_mode_class[i] = 1 << (int) DF_MODE; else sparc_mode_class[i] = 0; break; case MODE_FLOAT: case MODE_COMPLEX_FLOAT: - if (GET_MODE_SIZE (i) == 4) + if (size == 4) sparc_mode_class[i] = 1 << (int) SF_MODE; - else if (GET_MODE_SIZE (i) == 8) + else if (size == 8) sparc_mode_class[i] = 1 << (int) DF_MODE; - else if (GET_MODE_SIZE (i) == 16) + else if (size == 16) sparc_mode_class[i] = 1 << (int) TF_MODE; - else if (GET_MODE_SIZE (i) == 32) + else if (size == 32) sparc_mode_class[i] = 1 << (int) OF_MODE; else sparc_mode_class[i] = 0; break; case MODE_CC: - if (i == (int) CCFPmode || i == (int) CCFPEmode) + if (m == CCFPmode || m == CCFPEmode) sparc_mode_class[i] = 1 << (int) CCFP_MODE; else sparc_mode_class[i] = 1 << (int) CC_MODE; @@ -5244,7 +5274,8 @@ emit_save_or_restore_regs (unsigned int low, unsigned int high, rtx base, sorr_act_t action_true, sorr_act_t action_false) { unsigned int i; - rtx mem, insn; + rtx mem; + rtx_insn *insn; if (TARGET_ARCH64 && high <= 32) { @@ -5290,7 +5321,7 @@ emit_save_or_restore_regs (unsigned int low, unsigned int high, rtx base, { bool reg0 = save_p (i, leaf_function); bool reg1 = save_p (i + 1, leaf_function); - enum machine_mode mode; + machine_mode mode; int regno; if (reg0 && reg1) @@ -5403,10 +5434,10 @@ emit_save_or_restore_local_in_regs (rtx base, int offset, sorr_act_t action) /* Emit a window_save insn. */ -static rtx +static rtx_insn * emit_window_save (rtx increment) { - rtx insn = emit_insn (gen_window_save (increment)); + rtx_insn *insn = emit_insn (gen_window_save (increment)); RTX_FRAME_RELATED_P (insn) = 1; /* The incoming return address (%o7) is saved in %i7. */ @@ -5447,7 +5478,7 @@ void sparc_expand_prologue (void) { HOST_WIDE_INT size; - rtx insn; + rtx_insn *insn; /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying on the final value of the flag means deferring the prologue/epilogue @@ -5581,7 +5612,7 @@ void sparc_flat_expand_prologue (void) { HOST_WIDE_INT size; - rtx insn; + rtx_insn *insn; sparc_leaf_function_p = optimize > 0 && crtl->is_leaf; @@ -5889,7 +5920,7 @@ output_restore (rtx pat) /* Output a return. */ const char * -output_return (rtx insn) +output_return (rtx_insn *insn) { if (crtl->calls_eh_return) { @@ -5976,7 +6007,7 @@ output_return (rtx insn) /* Output a sibling call. */ const char * -output_sibcall (rtx insn, rtx call_operand) +output_sibcall (rtx_insn *insn, rtx call_operand) { rtx operands[1]; @@ -6011,7 +6042,7 @@ output_sibcall (rtx insn, rtx call_operand) if (final_sequence) { - rtx delay = NEXT_INSN (insn); + rtx_insn *delay = NEXT_INSN (insn); gcc_assert (delay); output_restore (PATTERN (delay)); @@ -6173,9 +6204,9 @@ init_cumulative_args (struct sparc_args *cum, tree fntype, /* Handle promotion of pointer and integer arguments. */ -static enum machine_mode +static machine_mode sparc_promote_function_mode (const_tree type, - enum machine_mode mode, + machine_mode mode, int *punsignedp, const_tree fntype ATTRIBUTE_UNUSED, int for_return ATTRIBUTE_UNUSED) @@ -6252,7 +6283,7 @@ scan_record_type (const_tree type, int *intregs_p, int *fpregs_p, *PPADDING records the amount of padding needed in words. */ static int -function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode, +function_arg_slotno (const struct sparc_args *cum, machine_mode mode, const_tree type, bool named, bool incoming_p, int *pregno, int *ppadding) { @@ -6406,8 +6437,8 @@ static void function_arg_record_value_2 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool); static void function_arg_record_value_1 (const_tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool); -static rtx function_arg_record_value (const_tree, enum machine_mode, int, int, int); -static rtx function_arg_union_value (int, enum machine_mode, int, int); +static rtx function_arg_record_value (const_tree, machine_mode, int, int, int); +static rtx function_arg_union_value (int, machine_mode, int, int); /* A subroutine of function_arg_record_value. Traverse the structure recursively and determine how many registers will be required. */ @@ -6514,7 +6545,7 @@ static void function_arg_record_value_3 (HOST_WIDE_INT bitpos, struct function_arg_record_value_parms *parms) { - enum machine_mode mode; + machine_mode mode; unsigned int regno; unsigned int startbit, endbit; int this_slotno, intslots, intoffset; @@ -6615,7 +6646,7 @@ function_arg_record_value_2 (const_tree type, HOST_WIDE_INT startbitpos, { int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; int regno, nregs, pos; - enum machine_mode mode = DECL_MODE (field); + machine_mode mode = DECL_MODE (field); rtx reg; function_arg_record_value_3 (bitpos, parms); @@ -6676,7 +6707,7 @@ function_arg_record_value_2 (const_tree type, HOST_WIDE_INT startbitpos, REGBASE is the regno of the base register for the parameter array. */ static rtx -function_arg_record_value (const_tree type, enum machine_mode mode, +function_arg_record_value (const_tree type, machine_mode mode, int slotno, int named, int regbase) { HOST_WIDE_INT typesize = int_size_in_bytes (type); @@ -6772,7 +6803,7 @@ function_arg_record_value (const_tree type, enum machine_mode mode, REGNO is the hard register the union will be passed in. */ static rtx -function_arg_union_value (int size, enum machine_mode mode, int slotno, +function_arg_union_value (int size, machine_mode mode, int slotno, int regno) { int nwords = ROUND_ADVANCE (size), i; @@ -6801,28 +6832,30 @@ function_arg_union_value (int size, enum machine_mode mode, int slotno, } /* Used by function_arg and sparc_function_value_1 to implement the conventions - for passing and returning large (BLKmode) vectors. + for passing and returning BLKmode vectors. Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE. - SIZE is the size in bytes of the vector (at least 8 bytes). + SIZE is the size in bytes of the vector. REGNO is the FP hard register the vector will be passed in. */ static rtx function_arg_vector_value (int size, int regno) { - int i, nregs = size / 8; - rtx regs; + const int nregs = MAX (1, size / 8); + rtx regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs)); - regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs)); - - for (i = 0; i < nregs; i++) - { + if (size < 8) + XVECEXP (regs, 0, 0) + = gen_rtx_EXPR_LIST (VOIDmode, + gen_rtx_REG (SImode, regno), + const0_rtx); + else + for (int i = 0; i < nregs; i++) XVECEXP (regs, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (DImode, regno + 2*i), GEN_INT (i*8)); - } return regs; } @@ -6843,7 +6876,7 @@ function_arg_vector_value (int size, int regno) TARGET_FUNCTION_INCOMING_ARG. */ static rtx -sparc_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode, +sparc_function_arg_1 (cumulative_args_t cum_v, machine_mode mode, const_tree type, bool named, bool incoming_p) { const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); @@ -6868,10 +6901,9 @@ sparc_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode, || (TARGET_ARCH64 && size <= 16)); if (mode == BLKmode) - return function_arg_vector_value (size, - SPARC_FP_ARG_FIRST + 2*slotno); - else - mclass = MODE_FLOAT; + return function_arg_vector_value (size, SPARC_FP_ARG_FIRST + 2*slotno); + + mclass = MODE_FLOAT; } if (TARGET_ARCH32) @@ -6981,7 +7013,7 @@ sparc_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode, /* Handle the TARGET_FUNCTION_ARG target hook. */ static rtx -sparc_function_arg (cumulative_args_t cum, enum machine_mode mode, +sparc_function_arg (cumulative_args_t cum, machine_mode mode, const_tree type, bool named) { return sparc_function_arg_1 (cum, mode, type, named, false); @@ -6990,7 +7022,7 @@ sparc_function_arg (cumulative_args_t cum, enum machine_mode mode, /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */ static rtx -sparc_function_incoming_arg (cumulative_args_t cum, enum machine_mode mode, +sparc_function_incoming_arg (cumulative_args_t cum, machine_mode mode, const_tree type, bool named) { return sparc_function_arg_1 (cum, mode, type, named, true); @@ -6999,7 +7031,7 @@ sparc_function_incoming_arg (cumulative_args_t cum, enum machine_mode mode, /* For sparc64, objects requiring 16 byte alignment are passed that way. */ static unsigned int -sparc_function_arg_boundary (enum machine_mode mode, const_tree type) +sparc_function_arg_boundary (machine_mode mode, const_tree type) { return ((TARGET_ARCH64 && (GET_MODE_ALIGNMENT (mode) == 128 @@ -7019,7 +7051,7 @@ sparc_function_arg_boundary (enum machine_mode mode, const_tree type) mode] will be split between that reg and memory. */ static int -sparc_arg_partial_bytes (cumulative_args_t cum, enum machine_mode mode, +sparc_arg_partial_bytes (cumulative_args_t cum, machine_mode mode, tree type, bool named) { int slotno, regno, padding; @@ -7078,7 +7110,7 @@ sparc_arg_partial_bytes (cumulative_args_t cum, enum machine_mode mode, static bool sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED, - enum machine_mode mode, const_tree type, + machine_mode mode, const_tree type, bool named ATTRIBUTE_UNUSED) { if (TARGET_ARCH32) @@ -7130,7 +7162,7 @@ sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED, TYPE is null for libcalls where that information may not be available. */ static void -sparc_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, +sparc_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, const_tree type, bool named) { CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); @@ -7175,7 +7207,7 @@ sparc_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, argument slot. */ enum direction -function_arg_padding (enum machine_mode mode, const_tree type) +function_arg_padding (machine_mode mode, const_tree type) { if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) return upward; @@ -7259,7 +7291,7 @@ sparc_struct_value_rtx (tree fndecl, int incoming) provided. */ rtx ret_reg = gen_rtx_REG (Pmode, 31); rtx scratch = gen_reg_rtx (SImode); - rtx endlab = gen_label_rtx (); + rtx_code_label *endlab = gen_label_rtx (); /* Calculate the return object size */ tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl)); @@ -7296,7 +7328,7 @@ sparc_struct_value_rtx (tree fndecl, int incoming) except that up to 32 bytes may be returned in registers. */ static rtx -sparc_function_value_1 (const_tree type, enum machine_mode mode, +sparc_function_value_1 (const_tree type, machine_mode mode, bool outgoing) { /* Beware that the two values are swapped here wrt function_arg. */ @@ -7315,10 +7347,9 @@ sparc_function_value_1 (const_tree type, enum machine_mode mode, || (TARGET_ARCH64 && size <= 32)); if (mode == BLKmode) - return function_arg_vector_value (size, - SPARC_FP_ARG_FIRST); - else - mclass = MODE_FLOAT; + return function_arg_vector_value (size, SPARC_FP_ARG_FIRST); + + mclass = MODE_FLOAT; } if (TARGET_ARCH64 && type) @@ -7407,7 +7438,7 @@ sparc_function_value (const_tree valtype, /* Handle TARGET_LIBCALL_VALUE. */ static rtx -sparc_libcall_value (enum machine_mode mode, +sparc_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) { return sparc_function_value_1 (NULL_TREE, mode, false); @@ -7551,15 +7582,15 @@ sparc_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, Specify whether the vector mode is supported by the hardware. */ static bool -sparc_vector_mode_supported_p (enum machine_mode mode) +sparc_vector_mode_supported_p (machine_mode mode) { return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false; } /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */ -static enum machine_mode -sparc_preferred_simd_mode (enum machine_mode mode) +static machine_mode +sparc_preferred_simd_mode (machine_mode mode) { if (TARGET_VIS) switch (mode) @@ -7583,7 +7614,7 @@ sparc_preferred_simd_mode (enum machine_mode mode) DEST is the destination insn (i.e. the label), INSN is the source. */ const char * -output_ubranch (rtx dest, rtx insn) +output_ubranch (rtx dest, rtx_insn *insn) { static char string[64]; bool v9_form = false; @@ -7657,12 +7688,12 @@ output_ubranch (rtx dest, rtx insn) const char * output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, - rtx insn) + rtx_insn *insn) { static char string[64]; enum rtx_code code = GET_CODE (op); rtx cc_reg = XEXP (op, 0); - enum machine_mode mode = GET_MODE (cc_reg); + machine_mode mode = GET_MODE (cc_reg); const char *labelno, *branch; int spaces = 8, far; char *p; @@ -7906,7 +7937,7 @@ sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison) { const char *qpfunc; rtx slot0, slot1, result, tem, tem2, libfunc; - enum machine_mode mode; + machine_mode mode; enum rtx_code new_comparison; switch (comparison) @@ -8045,14 +8076,14 @@ sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison) optabs would emit if we didn't have TFmode patterns. */ void -sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode) +sparc_emit_floatunsdi (rtx *operands, machine_mode mode) { - rtx neglab, donelab, i0, i1, f0, in, out; + rtx i0, i1, f0, in, out; out = operands[0]; in = force_reg (DImode, operands[1]); - neglab = gen_label_rtx (); - donelab = gen_label_rtx (); + rtx_code_label *neglab = gen_label_rtx (); + rtx_code_label *donelab = gen_label_rtx (); i0 = gen_reg_rtx (DImode); i1 = gen_reg_rtx (DImode); f0 = gen_reg_rtx (mode); @@ -8078,14 +8109,14 @@ sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode) optabs would emit if we didn't have TFmode patterns. */ void -sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode) +sparc_emit_fixunsdi (rtx *operands, machine_mode mode) { - rtx neglab, donelab, i0, i1, f0, in, out, limit; + rtx i0, i1, f0, in, out, limit; out = operands[0]; in = force_reg (mode, operands[1]); - neglab = gen_label_rtx (); - donelab = gen_label_rtx (); + rtx_code_label *neglab = gen_label_rtx (); + rtx_code_label *donelab = gen_label_rtx (); i0 = gen_reg_rtx (DImode); i1 = gen_reg_rtx (DImode); limit = gen_reg_rtx (mode); @@ -8120,9 +8151,9 @@ sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode) and OP is the conditional expression. */ const char * -output_cbcond (rtx op, rtx dest, rtx insn) +output_cbcond (rtx op, rtx dest, rtx_insn *insn) { - enum machine_mode mode = GET_MODE (XEXP (op, 0)); + machine_mode mode = GET_MODE (XEXP (op, 0)); enum rtx_code code = GET_CODE (op); const char *cond_str, *tmpl; int far, emit_nop, len; @@ -8247,11 +8278,11 @@ output_cbcond (rtx op, rtx dest, rtx insn) const char * output_v9branch (rtx op, rtx dest, int reg, int label, int reversed, - int annul, rtx insn) + int annul, rtx_insn *insn) { static char string[64]; enum rtx_code code = GET_CODE (op); - enum machine_mode mode = GET_MODE (XEXP (op, 0)); + machine_mode mode = GET_MODE (XEXP (op, 0)); rtx note; int far; char *p; @@ -8539,22 +8570,6 @@ sparc_split_regreg_legitimate (rtx reg1, rtx reg2) return 0; } -/* Return 1 if x and y are some kind of REG and they refer to - different hard registers. This test is guaranteed to be - run after reload. */ - -int -sparc_absnegfloat_split_legitimate (rtx x, rtx y) -{ - if (GET_CODE (x) != REG) - return 0; - if (GET_CODE (y) != REG) - return 0; - if (REGNO (x) == REGNO (y)) - return 0; - return 1; -} - /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. This makes them candidates for using ldd and std insns. @@ -8681,7 +8696,7 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx) /* Return the widened memory access made of MEM1 and MEM2 in MODE. */ rtx -widen_mem_for_ldd_peep (rtx mem1, rtx mem2, enum machine_mode mode) +widen_mem_for_ldd_peep (rtx mem1, rtx mem2, machine_mode mode) { rtx x = widen_memory_access (mem1, mode, 0); MEM_NOTRAP_P (x) = MEM_NOTRAP_P (mem1) && MEM_NOTRAP_P (mem2); @@ -8800,7 +8815,11 @@ sparc_print_operand (FILE *file, rtx x, int code) return; case '&': /* Print some local dynamic TLS name. */ - assemble_name (file, get_some_local_dynamic_name ()); + if (const char *name = get_some_local_dynamic_name ()) + assemble_name (file, name); + else + output_operand_lossage ("'%%&' used without any " + "local dynamic TLS references"); return; case 'Y': @@ -9418,7 +9437,7 @@ sparc_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ static int -supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) +supersparc_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn, int cost) { enum attr_type insn_type; @@ -9479,7 +9498,7 @@ supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) } static int -hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) +hypersparc_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn, int cost) { enum attr_type insn_type, dep_type; rtx pat = PATTERN(insn); @@ -9556,7 +9575,7 @@ hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) } static int -sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost) +sparc_adjust_cost(rtx_insn *insn, rtx link, rtx_insn *dep, int cost) { switch (sparc_cpu) { @@ -9624,7 +9643,7 @@ sparc_issue_rate (void) } static int -set_extends (rtx insn) +set_extends (rtx_insn *insn) { register rtx pat = PATTERN (insn); @@ -9790,7 +9809,7 @@ sparc_output_deferred_case_vectors (void) unknown. Return 1 if the high bits are zero, -1 if the register is sign extended. */ int -sparc_check_64 (rtx x, rtx insn) +sparc_check_64 (rtx x, rtx_insn *insn) { /* If a register is set only once it is safe to ignore insns this code does not know how to handle. The loop will either recognize @@ -9850,7 +9869,7 @@ sparc_check_64 (rtx x, rtx insn) OPERANDS are its operands and OPCODE is the mnemonic to be used. */ const char * -output_v8plus_shift (rtx insn, rtx *operands, const char *opcode) +output_v8plus_shift (rtx_insn *insn, rtx *operands, const char *opcode) { static char asm_code[60]; @@ -10672,7 +10691,7 @@ sparc_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) static rtx sparc_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, - enum machine_mode tmode ATTRIBUTE_UNUSED, + machine_mode tmode ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED) { tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); @@ -10686,7 +10705,7 @@ sparc_expand_builtin (tree exp, rtx target, if (nonvoid) { - enum machine_mode tmode = insn_data[icode].operand[0].mode; + machine_mode tmode = insn_data[icode].operand[0].mode; if (!target || GET_MODE (target) != tmode || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) @@ -10927,30 +10946,30 @@ sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, && TREE_CODE (arg2) == INTEGER_CST) { bool overflow = false; - double_int result = TREE_INT_CST (arg2); - double_int tmp; + widest_int result = wi::to_widest (arg2); + widest_int tmp; unsigned i; for (i = 0; i < VECTOR_CST_NELTS (arg0); ++i) { - double_int e0 = TREE_INT_CST (VECTOR_CST_ELT (arg0, i)); - double_int e1 = TREE_INT_CST (VECTOR_CST_ELT (arg1, i)); + tree e0 = VECTOR_CST_ELT (arg0, i); + tree e1 = VECTOR_CST_ELT (arg1, i); bool neg1_ovf, neg2_ovf, add1_ovf, add2_ovf; - tmp = e1.neg_with_overflow (&neg1_ovf); - tmp = e0.add_with_sign (tmp, false, &add1_ovf); - if (tmp.is_negative ()) - tmp = tmp.neg_with_overflow (&neg2_ovf); + tmp = wi::neg (wi::to_widest (e1), &neg1_ovf); + tmp = wi::add (wi::to_widest (e0), tmp, SIGNED, &add1_ovf); + if (wi::neg_p (tmp)) + tmp = wi::neg (tmp, &neg2_ovf); else neg2_ovf = false; - result = result.add_with_sign (tmp, false, &add2_ovf); + result = wi::add (result, tmp, SIGNED, &add2_ovf); overflow |= neg1_ovf | neg2_ovf | add1_ovf | add2_ovf; } gcc_assert (!overflow); - return build_int_cst_wide (rtype, result.low, result.high); + return wide_int_to_tree (rtype, result); } default: @@ -10968,7 +10987,7 @@ static bool sparc_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, int *total, bool speed ATTRIBUTE_UNUSED) { - enum machine_mode mode = GET_MODE (x); + machine_mode mode = GET_MODE (x); bool float_mode_p = FLOAT_MODE_P (mode); switch (code) @@ -11194,7 +11213,7 @@ general_or_i64_p (reg_class_t rclass) /* Implement TARGET_REGISTER_MOVE_COST. */ static int -sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, +sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, reg_class_t from, reg_class_t to) { bool need_memory = false; @@ -11277,7 +11296,8 @@ sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, tree function) { - rtx this_rtx, insn, funexp; + rtx this_rtx, funexp; + rtx_insn *insn; unsigned int int_arg_first; reload_completed = 1; @@ -11490,42 +11510,7 @@ sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED, static struct machine_function * sparc_init_machine_status (void) { - return ggc_alloc_cleared_machine_function (); -} - -/* Locate some local-dynamic symbol still in use by this function - so that we can print its name in local-dynamic base patterns. */ - -static const char * -get_some_local_dynamic_name (void) -{ - rtx insn; - - if (cfun->machine->some_ld_name) - return cfun->machine->some_ld_name; - - for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) - if (INSN_P (insn) - && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0)) - return cfun->machine->some_ld_name; - - gcc_unreachable (); -} - -static int -get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) -{ - rtx x = *px; - - if (x - && GET_CODE (x) == SYMBOL_REF - && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) - { - cfun->machine->some_ld_name = XSTR (x, 0); - return 1; - } - - return 0; + return ggc_cleared_alloc<machine_function> (); } /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. @@ -11737,7 +11722,7 @@ sparc_expand_compare_and_swap_12 (rtx bool_result, rtx result, rtx mem, rtx newvalue = gen_reg_rtx (SImode); rtx res = gen_reg_rtx (SImode); rtx resv = gen_reg_rtx (SImode); - rtx memsi, val, mask, end_label, loop_label, cc; + rtx memsi, val, mask, cc; emit_insn (gen_rtx_SET (VOIDmode, addr, gen_rtx_AND (Pmode, addr1, GEN_INT (-4)))); @@ -11787,8 +11772,8 @@ sparc_expand_compare_and_swap_12 (rtx bool_result, rtx result, rtx mem, emit_insn (gen_rtx_SET (VOIDmode, newv, gen_rtx_AND (SImode, newv, mask))); - end_label = gen_label_rtx (); - loop_label = gen_label_rtx (); + rtx_code_label *end_label = gen_label_rtx (); + rtx_code_label *loop_label = gen_label_rtx (); emit_label (loop_label); emit_insn (gen_rtx_SET (VOIDmode, oldvalue, @@ -11833,7 +11818,7 @@ void sparc_expand_compare_and_swap (rtx operands[]) { rtx bval, retval, mem, oldval, newval; - enum machine_mode mode; + machine_mode mode; enum memmodel model; bval = operands[0]; @@ -11871,7 +11856,7 @@ sparc_expand_compare_and_swap (rtx operands[]) } void -sparc_expand_vec_perm_bmask (enum machine_mode vmode, rtx sel) +sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel) { rtx t_1, t_2, t_3; @@ -12092,7 +12077,7 @@ sparc_conditional_register_usage (void) static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass) { - enum machine_mode mode = GET_MODE (x); + machine_mode mode = GET_MODE (x); if (CONSTANT_P (x)) { if (FP_REG_CLASS_P (rclass) @@ -12133,7 +12118,7 @@ sparc_preferred_reload_class (rtx x, reg_class_t rclass) OPERANDS are its operands and OPCODE is the mnemonic to be used. */ const char * -output_v8plus_mult (rtx insn, rtx *operands, const char *opcode) +output_v8plus_mult (rtx_insn *insn, rtx *operands, const char *opcode) { char mulstr[32]; @@ -12210,8 +12195,8 @@ output_v8plus_mult (rtx insn, rtx *operands, const char *opcode) and INNER_MODE are the modes describing TARGET. */ static void -vector_init_bshuffle (rtx target, rtx elt, enum machine_mode mode, - enum machine_mode inner_mode) +vector_init_bshuffle (rtx target, rtx elt, machine_mode mode, + machine_mode inner_mode) { rtx t1, final_insn, sel; int bmask; @@ -12292,8 +12277,8 @@ vector_init_faligndata (rtx target, rtx elt) void sparc_expand_vector_init (rtx target, rtx vals) { - const enum machine_mode mode = GET_MODE (target); - const enum machine_mode inner_mode = GET_MODE_INNER (mode); + const machine_mode mode = GET_MODE (target); + const machine_mode inner_mode = GET_MODE_INNER (mode); const int n_elts = GET_MODE_NUNITS (mode); int i, n_var = 0; bool all_same; @@ -12372,7 +12357,7 @@ sparc_expand_vector_init (rtx target, rtx vals) static reg_class_t sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, - enum machine_mode mode, secondary_reload_info *sri) + machine_mode mode, secondary_reload_info *sri) { enum reg_class rclass = (enum reg_class) rclass_i; @@ -12437,10 +12422,10 @@ sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */ bool -sparc_expand_conditional_move (enum machine_mode mode, rtx *operands) +sparc_expand_conditional_move (machine_mode mode, rtx *operands) { enum rtx_code rc = GET_CODE (operands[1]); - enum machine_mode cmp_mode; + machine_mode cmp_mode; rtx cc_reg, dst, cmp; cmp = operands[1]; @@ -12498,7 +12483,7 @@ sparc_expand_conditional_move (enum machine_mode mode, rtx *operands) code to be used for the condition mask. */ void -sparc_expand_vcond (enum machine_mode mode, rtx *operands, int ccode, int fcode) +sparc_expand_vcond (machine_mode mode, rtx *operands, int ccode, int fcode) { rtx mask, cop0, cop1, fcmp, cmask, bshuf, gsr; enum rtx_code code = GET_CODE (operands[3]); @@ -12538,7 +12523,7 @@ sparc_expand_vcond (enum machine_mode mode, rtx *operands, int ccode, int fcode) registers should return 4 here. */ unsigned int -sparc_regmode_natural_size (enum machine_mode mode) +sparc_regmode_natural_size (machine_mode mode) { int size = UNITS_PER_WORD; @@ -12562,7 +12547,7 @@ sparc_regmode_natural_size (enum machine_mode mode) point registers are 32-bit addressable. */ bool -sparc_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2) +sparc_modes_tieable_p (machine_mode mode1, machine_mode mode2) { enum mode_class mclass1, mclass2; unsigned short size1, size2; @@ -12601,7 +12586,7 @@ sparc_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2) /* Implement TARGET_CSTORE_MODE. */ -static enum machine_mode +static machine_mode sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED) { return (TARGET_ARCH64 ? DImode : SImode); @@ -12636,13 +12621,13 @@ sparc_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) __builtin_load_fsr (&tmp1_var); */ - tree fenv_var = create_tmp_var (unsigned_type_node, NULL); + tree fenv_var = create_tmp_var (unsigned_type_node); mark_addressable (fenv_var); tree fenv_addr = build_fold_addr_expr (fenv_var); tree stfsr = sparc_builtins[SPARC_BUILTIN_STFSR]; tree hold_stfsr = build_call_expr (stfsr, 1, fenv_addr); - tree tmp1_var = create_tmp_var (unsigned_type_node, NULL); + tree tmp1_var = create_tmp_var (unsigned_type_node); mark_addressable (tmp1_var); tree masked_fenv_var = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, @@ -12674,7 +12659,7 @@ sparc_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) tmp2_var >>= 5; __atomic_feraiseexcept ((int) tmp2_var); */ - tree tmp2_var = create_tmp_var (unsigned_type_node, NULL); + tree tmp2_var = create_tmp_var (unsigned_type_node); mark_addressable (tmp2_var); tree tmp3_addr = build_fold_addr_expr (tmp2_var); tree update_stfsr = build_call_expr (stfsr, 1, tmp3_addr); diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index dd2b5ad9cf0..48f3f6d9ced 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for Sun SPARC. - Copyright (C) 1987-2014 Free Software Foundation, Inc. + Copyright (C) 1987-2015 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com). 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, at Cygnus Support. @@ -137,21 +137,22 @@ extern enum cmodel sparc_cmodel; #define TARGET_CPU_hypersparc 3 #define TARGET_CPU_leon 4 #define TARGET_CPU_leon3 5 -#define TARGET_CPU_sparclite 6 -#define TARGET_CPU_f930 6 /* alias */ -#define TARGET_CPU_f934 6 /* alias */ -#define TARGET_CPU_sparclite86x 7 -#define TARGET_CPU_sparclet 8 -#define TARGET_CPU_tsc701 8 /* alias */ -#define TARGET_CPU_v9 9 /* generic v9 implementation */ -#define TARGET_CPU_sparcv9 9 /* alias */ -#define TARGET_CPU_sparc64 9 /* alias */ -#define TARGET_CPU_ultrasparc 10 -#define TARGET_CPU_ultrasparc3 11 -#define TARGET_CPU_niagara 12 -#define TARGET_CPU_niagara2 13 -#define TARGET_CPU_niagara3 14 -#define TARGET_CPU_niagara4 15 +#define TARGET_CPU_leon3v7 6 +#define TARGET_CPU_sparclite 7 +#define TARGET_CPU_f930 7 /* alias */ +#define TARGET_CPU_f934 7 /* alias */ +#define TARGET_CPU_sparclite86x 8 +#define TARGET_CPU_sparclet 9 +#define TARGET_CPU_tsc701 9 /* alias */ +#define TARGET_CPU_v9 10 /* generic v9 implementation */ +#define TARGET_CPU_sparcv9 10 /* alias */ +#define TARGET_CPU_sparc64 10 /* alias */ +#define TARGET_CPU_ultrasparc 11 +#define TARGET_CPU_ultrasparc3 12 +#define TARGET_CPU_niagara 13 +#define TARGET_CPU_niagara2 14 +#define TARGET_CPU_niagara3 15 +#define TARGET_CPU_niagara4 16 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ @@ -239,6 +240,11 @@ extern enum cmodel sparc_cmodel; #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG #endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7 +#define CPP_CPU32_DEFAULT_SPEC "-D__leon__" +#define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG +#endif + #endif #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) @@ -285,6 +291,7 @@ extern enum cmodel sparc_cmodel; %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ %{mcpu=leon:-D__leon__ -D__sparc_v8__} \ %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \ +%{mcpu=leon3v7:-D__leon__} \ %{mcpu=v9:-D__sparc_v9__} \ %{mcpu=ultrasparc:-D__sparc_v9__} \ %{mcpu=ultrasparc3:-D__sparc_v9__} \ @@ -334,6 +341,7 @@ extern enum cmodel sparc_cmodel; %{mcpu=hypersparc:-Av8} \ %{mcpu=leon:" AS_LEON_FLAG "} \ %{mcpu=leon3:" AS_LEON_FLAG "} \ +%{mcpu=leon3v7:" AS_LEONV7_FLAG "} \ %{mv8plus:-Av8plus} \ %{mcpu=v9:-Av9} \ %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ @@ -1760,8 +1768,10 @@ extern int sparc_indent_opcode; #ifdef HAVE_AS_LEON #define AS_LEON_FLAG "-Aleon" +#define AS_LEONV7_FLAG "-Aleon" #else #define AS_LEON_FLAG "-Av8" +#define AS_LEONV7_FLAG "-Av7" #endif /* We use gcc _mcount for profiling. */ diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 8b6c647fc00..5ec0bf1777d 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -1,5 +1,5 @@ ;; Machine description for SPARC chip for GCC -;; Copyright (C) 1987-2014 Free Software Foundation, Inc. +;; Copyright (C) 1987-2015 Free Software Foundation, Inc. ;; Contributed by Michael Tiemann (tiemann@cygnus.com) ;; 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, ;; at Cygnus Support. @@ -221,6 +221,7 @@ hypersparc, leon, leon3, + leon3v7, sparclite, f930, f934, @@ -424,6 +425,10 @@ (define_attr "fptype" "single,double" (const_string "single")) +;; FP precision specific to the UT699. +(define_attr "fptype_ut699" "none,single" + (const_string "none")) + ;; UltraSPARC-III integer load type. (define_attr "us3load_type" "2cycle,3cycle" (const_string "2cycle")) @@ -464,7 +469,8 @@ (const_string "false") (and (eq_attr "fix_ut699" "true") (and (eq_attr "type" "fpload,fp,fpmove,fpmul,fpdivs,fpsqrts") - (eq_attr "fptype" "single"))) + (ior (eq_attr "fptype" "single") + (eq_attr "fptype_ut699" "single")))) (const_string "false") (eq_attr "length" "1") (const_string "true") @@ -1886,7 +1892,7 @@ emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), operands[1])); #else - unsigned int low, high; + HOST_WIDE_INT low, high; low = trunc_int_for_mode (INTVAL (operands[1]), SImode); high = trunc_int_for_mode (INTVAL (operands[1]) >> 32, SImode); @@ -2365,14 +2371,14 @@ #if HOST_BITS_PER_WIDE_INT == 32 gcc_unreachable (); #else - enum machine_mode mode = GET_MODE (operands[1]); + machine_mode mode = GET_MODE (operands[1]); rtx tem = simplify_subreg (DImode, operands[1], mode, 0); emit_insn (gen_movdi (operands[0], tem)); #endif } else { - enum machine_mode mode = GET_MODE (operands[1]); + machine_mode mode = GET_MODE (operands[1]); rtx hi = simplify_subreg (SImode, operands[1], mode, 0); rtx lo = simplify_subreg (SImode, operands[1], mode, 4); @@ -3455,7 +3461,8 @@ "TARGET_FPU" "fdtos\t%1, %0" [(set_attr "type" "fp") - (set_attr "fptype" "double")]) + (set_attr "fptype" "double") + (set_attr "fptype_ut699" "single")]) (define_expand "trunctfsf2" [(set (match_operand:SF 0 "register_operand" "") @@ -3496,7 +3503,7 @@ "TARGET_FPU" "fitos\t%1, %0" [(set_attr "type" "fp") - (set_attr "fptype" "double")]) + (set_attr "fptype" "single")]) (define_insn "floatsidf2" [(set (match_operand:DF 0 "register_operand" "=e") @@ -3583,7 +3590,7 @@ "TARGET_FPU" "fstoi\t%1, %0" [(set_attr "type" "fp") - (set_attr "fptype" "double")]) + (set_attr "fptype" "single")]) (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "register_operand" "=f") @@ -3591,7 +3598,8 @@ "TARGET_FPU" "fdtoi\t%1, %0" [(set_attr "type" "fp") - (set_attr "fptype" "double")]) + (set_attr "fptype" "double") + (set_attr "fptype_ut699" "single")]) (define_expand "fix_trunctfsi2" [(set (match_operand:SI 0 "register_operand" "") @@ -4822,7 +4830,7 @@ [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))] { - operands[4] = GEN_INT (~INTVAL (operands[2])); + operands[4] = gen_int_mode (~INTVAL (operands[2]), SImode); }) (define_insn_and_split "*or_not_di_sp32" @@ -4899,7 +4907,7 @@ [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))] { - operands[4] = GEN_INT (~INTVAL (operands[2])); + operands[4] = gen_int_mode (~INTVAL (operands[2]), SImode); }) (define_split @@ -4911,7 +4919,7 @@ [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))] { - operands[4] = GEN_INT (~INTVAL (operands[2])); + operands[4] = gen_int_mode (~INTVAL (operands[2]), SImode); }) ;; Split DImode logical operations requiring two instructions. @@ -5554,53 +5562,52 @@ [(set_attr "type" "fpdivs")]) (define_expand "negtf2" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] + [(set (match_operand:TF 0 "register_operand" "") + (neg:TF (match_operand:TF 1 "register_operand" "")))] "TARGET_FPU" "") -(define_insn_and_split "*negtf2_notv9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] - ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. - "TARGET_FPU - && ! TARGET_V9" - "@ - fnegs\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (neg:SF (match_dup 3))) - (set (match_dup 4) (match_dup 5)) - (set (match_dup 6) (match_dup 7))] - "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1); - operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) - -(define_insn_and_split "*negtf2_v9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] - ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. - "TARGET_FPU && TARGET_V9" - "@ - fnegd\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (neg:DF (match_dup 3))) - (set (match_dup 4) (match_dup 5))] - "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2") - (set_attr "fptype" "double")]) +(define_insn "*negtf2_hq" + [(set (match_operand:TF 0 "register_operand" "=e") + (neg:TF (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fnegq\t%1, %0" + [(set_attr "type" "fpmove")]) + +(define_insn_and_split "*negtf2" + [(set (match_operand:TF 0 "register_operand" "=e") + (neg:TF (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && !TARGET_HARD_QUAD" + "#" + "&& reload_completed" + [(clobber (const_int 0))] +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + dest1 = gen_df_reg (set_dest, 0); + dest2 = gen_df_reg (set_dest, 1); + src1 = gen_df_reg (set_src, 0); + src2 = gen_df_reg (set_src, 1); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movdf (dest2, src2)); + emit_insn (gen_negdf2 (dest1, src1)); + } + else + { + emit_insn (gen_negdf2 (dest1, src1)); + if (REGNO (dest2) != REGNO (src2)) + emit_insn (gen_movdf (dest2, src2)); + } + DONE; +} + [(set_attr "length" "2")]) (define_expand "negdf2" [(set (match_operand:DF 0 "register_operand" "") @@ -5609,22 +5616,39 @@ "") (define_insn_and_split "*negdf2_notv9" - [(set (match_operand:DF 0 "register_operand" "=e,e") - (neg:DF (match_operand:DF 1 "register_operand" "0,e")))] - "TARGET_FPU && ! TARGET_V9" - "@ - fnegs\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (neg:SF (match_dup 3))) - (set (match_dup 4) (match_dup 5))] - "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) + [(set (match_operand:DF 0 "register_operand" "=e") + (neg:DF (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU && !TARGET_V9" + "#" + "&& reload_completed" + [(clobber (const_int 0))] +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + dest1 = gen_highpart (SFmode, set_dest); + dest2 = gen_lowpart (SFmode, set_dest); + src1 = gen_highpart (SFmode, set_src); + src2 = gen_lowpart (SFmode, set_src); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movsf (dest2, src2)); + emit_insn (gen_negsf2 (dest1, src1)); + } + else + { + emit_insn (gen_negsf2 (dest1, src1)); + if (REGNO (dest2) != REGNO (src2)) + emit_insn (gen_movsf (dest2, src2)); + } + DONE; +} + [(set_attr "length" "2")]) (define_insn "*negdf2_v9" [(set (match_operand:DF 0 "register_operand" "=e") @@ -5647,56 +5671,47 @@ "TARGET_FPU" "") -(define_insn_and_split "*abstf2_notv9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] - ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. - "TARGET_FPU && ! TARGET_V9" - "@ - fabss\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (abs:SF (match_dup 3))) - (set (match_dup 4) (match_dup 5)) - (set (match_dup 6) (match_dup 7))] - "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1); - operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) - -(define_insn "*abstf2_hq_v9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] - "TARGET_FPU && TARGET_V9 && TARGET_HARD_QUAD" - "@ - fabsd\t%0, %0 - fabsq\t%1, %0" - [(set_attr "type" "fpmove") - (set_attr "fptype" "double,*")]) +(define_insn "*abstf2_hq" + [(set (match_operand:TF 0 "register_operand" "=e") + (abs:TF (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fabsq\t%1, %0" + [(set_attr "type" "fpmove")]) -(define_insn_and_split "*abstf2_v9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] - "TARGET_FPU && TARGET_V9 && !TARGET_HARD_QUAD" - "@ - fabsd\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (abs:DF (match_dup 3))) - (set (match_dup 4) (match_dup 5))] - "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2") - (set_attr "fptype" "double,*")]) +(define_insn_and_split "*abstf2" + [(set (match_operand:TF 0 "register_operand" "=e") + (abs:TF (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && !TARGET_HARD_QUAD" + "#" + "&& reload_completed" + [(clobber (const_int 0))] +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + dest1 = gen_df_reg (set_dest, 0); + dest2 = gen_df_reg (set_dest, 1); + src1 = gen_df_reg (set_src, 0); + src2 = gen_df_reg (set_src, 1); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movdf (dest2, src2)); + emit_insn (gen_absdf2 (dest1, src1)); + } + else + { + emit_insn (gen_absdf2 (dest1, src1)); + if (REGNO (dest2) != REGNO (src2)) + emit_insn (gen_movdf (dest2, src2)); + } + DONE; +} + [(set_attr "length" "2")]) (define_expand "absdf2" [(set (match_operand:DF 0 "register_operand" "") @@ -5705,22 +5720,39 @@ "") (define_insn_and_split "*absdf2_notv9" - [(set (match_operand:DF 0 "register_operand" "=e,e") - (abs:DF (match_operand:DF 1 "register_operand" "0,e")))] - "TARGET_FPU && ! TARGET_V9" - "@ - fabss\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (abs:SF (match_dup 3))) - (set (match_dup 4) (match_dup 5))] - "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) + [(set (match_operand:DF 0 "register_operand" "=e") + (abs:DF (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU && !TARGET_V9" + "#" + "&& reload_completed" + [(clobber (const_int 0))] +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + dest1 = gen_highpart (SFmode, set_dest); + dest2 = gen_lowpart (SFmode, set_dest); + src1 = gen_highpart (SFmode, set_src); + src2 = gen_lowpart (SFmode, set_src); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movsf (dest2, src2)); + emit_insn (gen_abssf2 (dest1, src1)); + } + else + { + emit_insn (gen_abssf2 (dest1, src1)); + if (REGNO (dest2) != REGNO (src2)) + emit_insn (gen_movsf (dest2, src2)); + } + DONE; +} + [(set_attr "length" "2")]) (define_insn "*absdf2_v9" [(set (match_operand:DF 0 "register_operand" "=e") @@ -5795,19 +5827,6 @@ } [(set_attr "type" "shift")]) -(define_insn "*ashlsi3_extend" - [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI - (ashift:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "arith_operand" "rI"))))] - "TARGET_ARCH64" -{ - if (GET_CODE (operands[2]) == CONST_INT) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - return "sll\t%1, %2, %0"; -} - [(set_attr "type" "shift")]) - (define_expand "ashldi3" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (match_operand:DI 1 "register_operand" "r") diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt index c02aec59f06..93d24a69be3 100644 --- a/gcc/config/sparc/sparc.opt +++ b/gcc/config/sparc/sparc.opt @@ -1,6 +1,6 @@ ; Options for the SPARC port of the compiler ; -; Copyright (C) 2005-2014 Free Software Foundation, Inc. +; Copyright (C) 2005-2015 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -113,6 +113,10 @@ mrelax Target Optimize tail call instructions in assembler and linker +muser-mode +Target Report Mask(USER_MODE) +Do not generate code that can only run in supervisor mode + mcpu= Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7) Use features of and schedule code for given CPU @@ -149,6 +153,9 @@ EnumValue Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3) EnumValue +Enum(sparc_processor_type) String(leon3v7) Value(PROCESSOR_LEON3V7) + +EnumValue Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE) EnumValue diff --git a/gcc/config/sparc/sparclet.md b/gcc/config/sparc/sparclet.md index 2ee3be6950f..8a2fe7c023b 100644 --- a/gcc/config/sparc/sparclet.md +++ b/gcc/config/sparc/sparclet.md @@ -1,5 +1,5 @@ ;; Scheduling description for SPARClet. -;; Copyright (C) 2002-2014 Free Software Foundation, Inc. +;; Copyright (C) 2002-2015 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/supersparc.md b/gcc/config/sparc/supersparc.md index 2825d55b859..7cf7793217f 100644 --- a/gcc/config/sparc/supersparc.md +++ b/gcc/config/sparc/supersparc.md @@ -1,5 +1,5 @@ ;; Scheduling description for SuperSPARC. -;; Copyright (C) 2002-2014 Free Software Foundation, Inc. +;; Copyright (C) 2002-2015 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md index fd5691f73be..7d00b1080b4 100644 --- a/gcc/config/sparc/sync.md +++ b/gcc/config/sparc/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for SPARC synchronization instructions. -;; Copyright (C) 2005-2014 Free Software Foundation, Inc. +;; Copyright (C) 2005-2015 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -64,11 +64,19 @@ "stbar" [(set_attr "type" "multi")]) +;; For LEON3, STB has the effect of membar #StoreLoad. +(define_insn "*membar_storeload_leon3" + [(set (match_operand:BLK 0 "" "") + (unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))] + "TARGET_LEON3" + "stb\t%%g0, [%%sp-1]" + [(set_attr "type" "store")]) + ;; For V8, LDSTUB has the effect of membar #StoreLoad. (define_insn "*membar_storeload" [(set (match_operand:BLK 0 "" "") (unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))] - "TARGET_V8" + "TARGET_V8 && !TARGET_LEON3" "ldstub\t[%%sp-1], %%g0" [(set_attr "type" "multi")]) @@ -200,10 +208,27 @@ [(match_operand:I48MODE 2 "register_operand" "r") (match_operand:I48MODE 3 "register_operand" "0")] UNSPECV_CAS))] - "(TARGET_V9 || TARGET_LEON3) && (<MODE>mode != DImode || TARGET_ARCH64)" + "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64)" "cas<modesuffix>\t%1, %2, %0" [(set_attr "type" "multi")]) +(define_insn "*atomic_compare_and_swap_leon3_1" + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "mem_noofs_operand" "+w")) + (set (match_dup 1) + (unspec_volatile:SI + [(match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPECV_CAS))] + "TARGET_LEON3" +{ + if (TARGET_USER_MODE) + return "casa\t%1 0xa, %2, %0"; /* ASI for user data space. */ + else + return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space. */ +} + [(set_attr "type" "multi")]) + (define_insn "*atomic_compare_and_swapdi_v8plus" [(set (match_operand:DI 0 "register_operand" "=h") (match_operand:DI 1 "mem_noofs_operand" "+w")) diff --git a/gcc/config/sparc/sysv4.h b/gcc/config/sparc/sysv4.h index 413d1fc150b..ff886b1d195 100644 --- a/gcc/config/sparc/sysv4.h +++ b/gcc/config/sparc/sysv4.h @@ -1,5 +1,5 @@ /* Target definitions for GNU compiler for SPARC running System V.4 - Copyright (C) 1991-2014 Free Software Foundation, Inc. + Copyright (C) 1991-2015 Free Software Foundation, Inc. Contributed by Ron Guilmette (rfg@monkeys.com). This file is part of GCC. diff --git a/gcc/config/sparc/t-elf b/gcc/config/sparc/t-elf index 9234a60adc1..4d7355f6857 100644 --- a/gcc/config/sparc/t-elf +++ b/gcc/config/sparc/t-elf @@ -1,4 +1,4 @@ -# Copyright (C) 1997-2014 Free Software Foundation, Inc. +# Copyright (C) 1997-2015 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-leon b/gcc/config/sparc/t-leon index 16b3450fd6b..1b203f6bc3c 100644 --- a/gcc/config/sparc/t-leon +++ b/gcc/config/sparc/t-leon @@ -1,4 +1,4 @@ -# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Copyright (C) 2010-2015 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-leon3 b/gcc/config/sparc/t-leon3 index ca34ed20ce9..a5edd4b3e2b 100644 --- a/gcc/config/sparc/t-leon3 +++ b/gcc/config/sparc/t-leon3 @@ -1,4 +1,4 @@ -# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Copyright (C) 2010-2015 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-linux64 b/gcc/config/sparc/t-linux64 index cb2bce9cde5..6467c31e1a0 100644 --- a/gcc/config/sparc/t-linux64 +++ b/gcc/config/sparc/t-linux64 @@ -1,4 +1,4 @@ -# Copyright (C) 1998-2014 Free Software Foundation, Inc. +# Copyright (C) 1998-2015 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-rtems b/gcc/config/sparc/t-rtems index 86a2302614c..adb6dcbaacc 100644 --- a/gcc/config/sparc/t-rtems +++ b/gcc/config/sparc/t-rtems @@ -1,4 +1,4 @@ -# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# Copyright (C) 2012-2015 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -17,6 +17,15 @@ # <http://www.gnu.org/licenses/>. # -MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3 -MULTILIB_DIRNAMES = soft v8 leon3 +MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3/mcpu=leon3v7 muser-mode +MULTILIB_DIRNAMES = soft v8 leon3 leon3v7 user-mode MULTILIB_MATCHES = msoft-float=mno-fpu + +MULTILIB_EXCEPTIONS = muser-mode +MULTILIB_EXCEPTIONS += mcpu=leon3 +MULTILIB_EXCEPTIONS += mcpu=leon3v7 +MULTILIB_EXCEPTIONS += msoft-float/mcpu=leon3 +MULTILIB_EXCEPTIONS += msoft-float/mcpu=leon3v7 +MULTILIB_EXCEPTIONS += msoft-float/muser-mode +MULTILIB_EXCEPTIONS += msoft-float/mcpu=v8/muser-mode +MULTILIB_EXCEPTIONS += mcpu=v8/muser-mode diff --git a/gcc/config/sparc/t-rtems-64 b/gcc/config/sparc/t-rtems-64 index b094546fc5a..af5cbabd1ce 100644 --- a/gcc/config/sparc/t-rtems-64 +++ b/gcc/config/sparc/t-rtems-64 @@ -1,4 +1,4 @@ -# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# Copyright (C) 2012-2015 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-sol2-64 b/gcc/config/sparc/t-sol2 index ec7e4eba6fd..ec7e4eba6fd 100644 --- a/gcc/config/sparc/t-sol2-64 +++ b/gcc/config/sparc/t-sol2 diff --git a/gcc/config/sparc/t-sparc b/gcc/config/sparc/t-sparc index 828f9f733d2..7968d921d36 100644 --- a/gcc/config/sparc/t-sparc +++ b/gcc/config/sparc/t-sparc @@ -1,6 +1,6 @@ # General rules that all sparc/ targets must have. # -# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# Copyright (C) 2011-2015 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/tso.h b/gcc/config/sparc/tso.h index f496f0329d3..5aaf97623c9 100644 --- a/gcc/config/sparc/tso.h +++ b/gcc/config/sparc/tso.h @@ -1,5 +1,5 @@ /* Include fragment for Sparc TSO operating systems. - Copyright (C) 2011-2014 Free Software Foundation, Inc. + Copyright (C) 2011-2015 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/ultra1_2.md b/gcc/config/sparc/ultra1_2.md index 0635d4ecbcb..72f2281be35 100644 --- a/gcc/config/sparc/ultra1_2.md +++ b/gcc/config/sparc/ultra1_2.md @@ -1,5 +1,5 @@ ;; Scheduling description for UltraSPARC-I/II. -;; Copyright (C) 2002-2014 Free Software Foundation, Inc. +;; Copyright (C) 2002-2015 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/ultra3.md b/gcc/config/sparc/ultra3.md index f3c8eb69014..c4426a30e9f 100644 --- a/gcc/config/sparc/ultra3.md +++ b/gcc/config/sparc/ultra3.md @@ -1,5 +1,5 @@ ;; Scheduling description for UltraSPARC-III. -;; Copyright (C) 2002-2014 Free Software Foundation, Inc. +;; Copyright (C) 2002-2015 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/visintrin.h b/gcc/config/sparc/visintrin.h index 7f881f7cc83..e655e378d9a 100644 --- a/gcc/config/sparc/visintrin.h +++ b/gcc/config/sparc/visintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2014 Free Software Foundation, Inc. +/* Copyright (C) 2011-2015 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/vxworks.h b/gcc/config/sparc/vxworks.h index 9e093a66485..c66dba8f5a4 100644 --- a/gcc/config/sparc/vxworks.h +++ b/gcc/config/sparc/vxworks.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for SPARC targeting the VxWorks run time environment. - Copyright (C) 2007-2014 Free Software Foundation, Inc. + Copyright (C) 2007-2015 Free Software Foundation, Inc. This file is part of GCC. |