* Merge from gcc2 June 9, 1998 snapshot. See ChangeLog.13 for

        details.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@20808 138bc75d-0d04-0410-961f-82ee72b054a4

22 files changed, 106 insertions, 92 deletions

diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index 0a0c4f116cb..5bcb1fb3abe 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -2808,6 +2808,51 @@ print_operand (file, x, code)
     }
 }
 
+/* Emit RTL insns to initialize the variable parts of a trampoline at
+   TRAMP. FNADDR is an RTX for the address of the function's pure
+   code.  CXT is an RTX for the static chain value for the function.
+   We assume here that a function will be called many more times than
+   its address is taken (e.g., it might be passed to qsort), so we
+   take the trouble to initialize the "hint" field in the JMP insn.
+   Note that the hint field is PC (new) + 4 * bits 13:0.  */
+
+void
+alpha_initialize_trampoline (tramp, fnaddr, cxt)
+     rtx tramp;
+     rtx fnaddr;
+     rtx cxt;
+{
+  rtx temp, temp1, addr;
+
+  /* Store function address and CXT.  */
+  addr = memory_address (Pmode, plus_constant (tramp, 16));
+  emit_move_insn (gen_rtx (MEM, Pmode, addr), fnaddr);
+  addr = memory_address (Pmode, plus_constant (tramp, 24));
+  emit_move_insn (gen_rtx (MEM, Pmode, addr), cxt);
+
+  /* Compute hint value.  */
+  temp = force_operand (plus_constant (tramp, 12), NULL_RTX);
+  temp = expand_binop (DImode, sub_optab, fnaddr, temp, temp, 1, OPTAB_WIDEN);
+  temp = expand_shift (RSHIFT_EXPR, Pmode, temp,
+		       build_int_2 (2, 0), NULL_RTX, 1);
+  temp = expand_and (gen_lowpart (SImode, temp), GEN_INT (0x3fff), 0);
+
+  /* Merge in the hint.  */
+  addr = memory_address (SImode, plus_constant (tramp, 8));
+  temp1 = force_reg (SImode, gen_rtx (MEM, SImode, addr));
+  temp1 = expand_and (temp1, GEN_INT (0xffffc000), NULL_RTX);
+  temp1 = expand_binop (SImode, ior_optab, temp1, temp, temp1, 1, OPTAB_WIDEN);
+  emit_move_insn (gen_rtx (MEM, SImode, addr), temp1);
+
+#ifdef TRANSFER_FROM_TRAMPOLINE
+  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
+		     0, VOIDmode, 1, addr, Pmode);
+#endif
+
+  emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode,
+		      gen_rtvec (1, const0_rtx), 0));
+}
+
 /* Do what is necessary for `va_start'.  The argument is ignored;
    We look at the current function to determine if stdarg or varargs
    is used and fill in an initial va_list.  A pointer to this constructor
diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h
index 00e5c915f8a..d7bb2d16887 100644
--- a/gcc/config/alpha/alpha.h
+++ b/gcc/config/alpha/alpha.h
@@ -676,12 +676,17 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
 
    For the Alpha, `Q' means that this is a memory operand but not a
    reference to an unaligned location.
+
    `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
-   function.  */
+   function.
+
+   'S' is a 6-bit constant (valid for a shift insn).  */
 
 #define EXTRA_CONSTRAINT(OP, C)				\
-  ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) != AND \
-   : (C) == 'R' ? current_file_function_operand (OP, Pmode)	\
+  ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) != AND	\
+   : (C) == 'R' ? current_file_function_operand (OP, Pmode)		\
+   : (C) == 'S' ? (GET_CODE (OP) == CONST_INT				\
+		   && (unsigned HOST_WIDE_INT) INTVAL (OP) < 64)	\
    : 0)
 
 /* Given an rtx X being reloaded into a reg required to be
@@ -1202,38 +1207,8 @@ extern void output_end_prologue ();
    to initialize the "hint" field in the JMP insn.  Note that the hint
    field is PC (new) + 4 * bits 13:0.  */
 
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  rtx _temp, _temp1, _addr;						\
-									\
-  _addr = memory_address (Pmode, plus_constant ((TRAMP), 16));		\
-  emit_move_insn (gen_rtx (MEM, Pmode, _addr), (FNADDR));		\
-  _addr = memory_address (Pmode, plus_constant ((TRAMP), 24));		\
-  emit_move_insn (gen_rtx (MEM, Pmode, _addr), (CXT));			\
-									\
-  _temp = force_operand (plus_constant ((TRAMP), 12), NULL_RTX);	\
-  _temp = expand_binop (DImode, sub_optab, (FNADDR), _temp, _temp, 1,	\
-			OPTAB_WIDEN);					\
-  _temp = expand_shift (RSHIFT_EXPR, Pmode, _temp,			\
-			build_int_2 (2, 0), NULL_RTX, 1);		\
-  _temp = expand_and (gen_lowpart (SImode, _temp),			\
-		      GEN_INT (0x3fff), 0); 				\
-									\
-  _addr = memory_address (SImode, plus_constant ((TRAMP), 8));		\
-  _temp1 = force_reg (SImode, gen_rtx (MEM, SImode, _addr));		\
-  _temp1 = expand_and (_temp1, GEN_INT (0xffffc000), NULL_RTX);		\
-  _temp1 = expand_binop (SImode, ior_optab, _temp1, _temp, _temp1, 1,	\
-			 OPTAB_WIDEN);					\
-									\
-  emit_move_insn (gen_rtx (MEM, SImode, _addr), _temp1);		\
-									\
-  emit_library_call (gen_rtx (SYMBOL_REF, Pmode,			\
-			      "__enable_execute_stack"),		\
-		     0, VOIDmode, 1,_addr, Pmode);			\
-									\
-  emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode,			\
-		      gen_rtvec (1, const0_rtx), 0));			\
-}
+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
+  alpha_initialize_trampoline (TRAMP, FNADDR, CXT)
 
 /* Attempt to turn on access permissions for the stack.  */
 
@@ -2127,6 +2102,7 @@ do {									\
     }									\
 } while (0)
 
+
 /* Define results of standard character escape sequences.  */
 #define TARGET_BELL 007
 #define TARGET_BS 010
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 6e280cbd178..a8e5c8eb34d 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -1177,7 +1177,7 @@
 (define_insn "ashldi3"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
-		   (match_operand:DI 2 "reg_or_6bit_operand" "P,rI")))]
+		   (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
   ""
   "*
 {
@@ -1218,7 +1218,7 @@
 (define_insn "lshrdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-		     (match_operand:DI 2 "reg_or_6bit_operand" "rI")))]
+		     (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
   ""
   "srl %r1,%2,%0"
   [(set_attr "type" "shift")])
@@ -1226,7 +1226,7 @@
 (define_insn "ashrdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-		     (match_operand:DI 2 "reg_or_6bit_operand" "rI")))]
+		     (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
   ""
   "sra %r1,%2,%0"
   [(set_attr "type" "shift")])
diff --git a/gcc/config/alpha/linux.h b/gcc/config/alpha/linux.h
index 47e06c62aa4..aa43450fe98 100644
--- a/gcc/config/alpha/linux.h
+++ b/gcc/config/alpha/linux.h
@@ -1,7 +1,7 @@
-/* Definitions of target machine for GNU compiler,
-   for Alpha Linux-based GNU systems.
-   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
-   Contributed by Richard Henderson.
+/* Definitions of target machine for GNU compiler, for Alpha Linux-based GNU
+   systems using ECOFF.
+   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+   Contributed by Bob Manson.
 
 This file is part of GNU CC.
 
@@ -44,28 +44,4 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
 #undef TARGET_CAN_FAULT_IN_PROLOGUE
 #define TARGET_CAN_FAULT_IN_PROLOGUE 1
 
-/* Emit RTL insns to initialize the variable parts of a trampoline.
-   FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function. 
-
-   This differs from the standard version in that:
-
-   We do not initialize the "hint" field because it only has an 8k
-   range and so the target is in range of something on the stack. 
-   Omitting the hint saves a bogus branch-prediction cache line load.
-
-   GNU/Linux always has an executable stack -- no need for a system call. */
-
-#undef INITIALIZE_TRAMPOLINE
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)                       \
-{                                                                       \
-  rtx _addr;                                             		\
-                                                                        \
-  _addr = memory_address (Pmode, plus_constant ((TRAMP), 16));          \
-  emit_move_insn (gen_rtx (MEM, Pmode, _addr), (FNADDR));               \
-  _addr = memory_address (Pmode, plus_constant ((TRAMP), 24));          \
-  emit_move_insn (gen_rtx (MEM, Pmode, _addr), (CXT));                  \
-                                                                        \
-  emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode,                        \
-                      gen_rtvec (1, const0_rtx), 0));                   \
-}
+#undef ASM_FINAL_SPEC
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 7272cc927c8..e2f46e7c965 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -1910,7 +1910,7 @@ arc_final_prescan_insn (insn, opvec, noperands)
   record_cc_ref (insn);
 
   /* Allow -mdebug-ccfsm to turn this off so we can see how well it does.
-     We can't do this in macro FINAL_PRESCAN_INSN because it's called from
+     We can't do this in macro FINAL_PRESCAN_INSN because its called from
      final_scan_insn which has `optimize' as a local.  */
   if (optimize < 2 || TARGET_NO_COND_EXEC)
     return;
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 0ddc91afb89..61ca39f5311 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -1583,7 +1583,7 @@ do { if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); } while (0)
    After generation of rtl, the compiler makes no further distinction
    between pointers and any other objects of this machine mode.  */
 /* ??? The arc doesn't have full 32 bit pointers, but making this PSImode has
-   it's own problems (you have to add extendpsisi2 and trucnsipsi2 but how does
+   its own problems (you have to add extendpsisi2 and trucnsipsi2 but how does
    one do it without getting excess code?).  Try to avoid it.  */
 #define Pmode SImode
 
diff --git a/gcc/config/dsp16xx/dsp16xx.h b/gcc/config/dsp16xx/dsp16xx.h
index 785e8ca983b..b01db107849 100644
--- a/gcc/config/dsp16xx/dsp16xx.h
+++ b/gcc/config/dsp16xx/dsp16xx.h
@@ -138,7 +138,7 @@ extern char *output_block_move();
 /* Tell gcc where to look for the startfile */
 #define STANDARD_STARTFILE_PREFIX   "/d1600/lib"
 
-/* Tell gcc where to look for it's executables */
+/* Tell gcc where to look for its executables */
 #define STANDARD_EXEC_PREFIX  "/d1600/bin"
 
 /* Command line options to the AT&T assembler */
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index a3af135f426..560a20bb599 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -3037,7 +3037,7 @@ output_simode_bld (bild, log2, operands)
   return "";
 }
 
-/* Given INSN and it's current length LENGTH, return the adjustment
+/* Given INSN and its current length LENGTH, return the adjustment
    (in bytes) to correctly compute INSN's length.
 
    We use this to get the lengths of various memory references correct.  */
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 4d7e79eecfa..423a249dafe 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -439,8 +439,8 @@
   [(set (cc0)
 	(match_operator 2 "VOIDmode_compare_op"
 			[(float_extend:XF
-			  (match_operand:DF 1 "nonimmediate_operand" "fm"))
-			 (match_operand:XF 0 "register_operand" "f")]))
+			  (match_operand:DF 0 "nonimmediate_operand" "fm"))
+			 (match_operand:XF 1 "register_operand" "f")]))
    (clobber (match_scratch:HI 3 "=a"))]
   "TARGET_80387"
   "* return output_float_compare (insn, operands);")
@@ -457,6 +457,16 @@
 
 (define_insn ""
   [(set (cc0)
+	(match_operator 2 "VOIDmode_compare_op"
+			[(float_extend:XF
+			  (match_operand:SF 0 "nonimmediate_operand" "fm"))
+			 (match_operand:XF 1 "register_operand" "f")]))
+   (clobber (match_scratch:HI 3 "=a"))]
+  "TARGET_80387"
+  "* return output_float_compare (insn, operands);")
+
+(define_insn ""
+  [(set (cc0)
 	(compare:CCFPEQ (match_operand:XF 0 "register_operand" "f")
 			(match_operand:XF 1 "register_operand" "f")))
    (clobber (match_scratch:HI 2 "=a"))]
diff --git a/gcc/config/i386/linux-aout.h b/gcc/config/i386/linux-aout.h
index 349642fa7c7..98cf55e7830 100644
--- a/gcc/config/i386/linux-aout.h
+++ b/gcc/config/i386/linux-aout.h
@@ -1,5 +1,5 @@
 /* Definitions for Intel 386 running Linux-based GNU systems using a.out.
-   Copyright (C) 1992, 1994, 1995, 1997 Free Software Foundation, Inc.
+   Copyright (C) 1992, 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
    Contributed by H.J. Lu (hjl@nynexst.com)
 
 This file is part of GNU CC.
diff --git a/gcc/config/i386/linux-oldld.h b/gcc/config/i386/linux-oldld.h
index 116a5bf4b30..a67fd0f8535 100644
--- a/gcc/config/i386/linux-oldld.h
+++ b/gcc/config/i386/linux-oldld.h
@@ -1,6 +1,6 @@
 /* Definitions for Intel 386 running Linux-based GNU systems with pre-BFD
    a.out linkers.
-   Copyright (C) 1995, 1997 Free Software Foundation, Inc.
+   Copyright (C) 1995, 1997, 1998 Free Software Foundation, Inc.
    Contributed by Michael Meissner (meissner@cygnus.com)
 
 This file is part of GNU CC.
diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h
index 649c29e2625..e435f803172 100644
--- a/gcc/config/i386/linux.h
+++ b/gcc/config/i386/linux.h
@@ -1,5 +1,5 @@
-/* Definitions for Intel 386 running Linux with ELF format
-   Copyright (C) 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
+/* Definitions for Intel 386 running Linux-based GNU systems with ELF format.
+   Copyright (C) 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
    Contributed by Eric Youngdale.
    Modified for stabs-in-ELF by H.J. Lu.
 
diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h
index dff81720328..1503bdfcdd7 100644
--- a/gcc/config/m32r/m32r.h
+++ b/gcc/config/m32r/m32r.h
@@ -1910,7 +1910,7 @@ do {									\
    After generation of rtl, the compiler makes no further distinction
    between pointers and any other objects of this machine mode.  */
 /* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
-   it's own problems (you have to add extendpsisi2 and truncsipsi2).
+   its own problems (you have to add extendpsisi2 and truncsipsi2).
    Try to avoid it.  */
 #define Pmode SImode
 
diff --git a/gcc/config/m68k/lb1sf68.asm b/gcc/config/m68k/lb1sf68.asm
index 7d6dba32d1e..9e33ccb4b2f 100644
--- a/gcc/config/m68k/lb1sf68.asm
+++ b/gcc/config/m68k/lb1sf68.asm
@@ -1,5 +1,5 @@
 /* libgcc1 routines for 68000 w/o floating-point hardware.
-   Copyright (C) 1994, 1996, 1997 Free Software Foundation, Inc.
+   Copyright (C) 1994, 1996, 1997, 1998 Free Software Foundation, Inc.
 
 This file is part of GNU CC.
 
diff --git a/gcc/config/m88k/m88k.h b/gcc/config/m88k/m88k.h
index 441674c08de..b74ae45064d 100644
--- a/gcc/config/m88k/m88k.h
+++ b/gcc/config/m88k/m88k.h
@@ -2079,7 +2079,7 @@ do {									 \
   sprintf (LABEL, TARGET_SVR4 ? "*.%s%d" : "*@%s%d", PREFIX, NUM)
 
 /* Internal macro to get a single precision floating point value into
-   an int, so we can print it's value in hex.  */
+   an int, so we can print its value in hex.  */
 #define FLOAT_TO_INT_INTERNAL( FVALUE, IVALUE )				\
   { union {								\
       REAL_VALUE_TYPE d;						\
diff --git a/gcc/config/m88k/m88k.md b/gcc/config/m88k/m88k.md
index c94e6fd82ae..118ebe366da 100644
--- a/gcc/config/m88k/m88k.md
+++ b/gcc/config/m88k/m88k.md
@@ -1125,7 +1125,7 @@
 ;; The comparison operations store the comparison into a register and
 ;; record that register.  The following Bxx or Sxx insn uses that
 ;; register as an input.  To facilitate use of bcnd instead of cmp/bb1,
-;; cmpsi records it's operands and produces no code when any operand
+;; cmpsi records its operands and produces no code when any operand
 ;; is constant.  In this case, the Bxx insns use gen_bcnd and the
 ;; Sxx insns use gen_test to ensure a cmp has been emitted.
 ;;
@@ -3972,7 +3972,7 @@
 ;; This insn is used for some loop tests, typically loops reversed when
 ;; strength reduction is used.  It is actually created when the instruction
 ;; combination phase combines the special loop test.  Since this insn
-;; is both a jump insn and has an output, it must deal with it's own
+;; is both a jump insn and has an output, it must deal with its own
 ;; reloads, hence the `m' constraints.  The `!' constraints direct reload
 ;; to not choose the register alternatives in the event a reload is needed.
 
diff --git a/gcc/config/mips/iris6.h b/gcc/config/mips/iris6.h
index 536ceee95d0..2eda40ab978 100644
--- a/gcc/config/mips/iris6.h
+++ b/gcc/config/mips/iris6.h
@@ -96,6 +96,9 @@ Boston, MA 02111-1307, USA.  */
 #undef PREFERRED_DEBUGGING_TYPE
 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 
+/* Force the generation of dwarf .debug_frame sections even if not
+   compiling -g.  This guarantees that we can unwind the stack. */
+#define DWARF2_FRAME_INFO 1
 /* The size in bytes of a DWARF field indicating an offset or length
    relative to a debug info section, specified to be 4 bytes in the DWARF-2
    specification.  The SGI/MIPS ABI defines it to be the same as PTR_SIZE.  */
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 590895936b5..52b8c8e25ea 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -3992,7 +3992,7 @@ while (0)
 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE)				\
   mips_output_lineno (STREAM, LINE)
 
-/* The MIPS implementation uses some labels for it's own purpose.  The
+/* The MIPS implementation uses some labels for its own purpose.  The
    following lists what labels are created, and are all formed by the
    pattern $L[a-z].*.  The machine independent portion of GCC creates
    labels matching:  $L[A-Z][0-9]+ and $L[0-9]+.
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 50ff6407e11..fae82e54fab 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -4626,7 +4626,7 @@ move\\t%0,%z4\\n\\
 
 (define_expand "reload_indi"
   [(set (match_operand:DI 0 "register_operand" "=b")
-	(match_operand:DI 1 "movdi_operand" "b"))
+	(match_operand:DI 1 "" "b"))
    (clobber (match_operand:TI 2 "register_operand" "=&d"))]
   "TARGET_64BIT"
   "
@@ -4641,10 +4641,12 @@ move\\t%0,%z4\\n\\
       if (GET_CODE (operands[1]) == MEM)
 	{
 	  rtx memword, offword, hiword, loword;
+	  rtx addr = find_replacement (&XEXP (operands[1], 0));
+	  rtx op1 = change_address (operands[1], VOIDmode, addr);
 
 	  scratch = gen_rtx (REG, SImode, REGNO (scratch));
-	  memword = change_address (operands[1], SImode, NULL_RTX);
-	  offword = change_address (adj_offsettable_operand (operands[1], 4),
+	  memword = change_address (op1, SImode, NULL_RTX);
+	  offword = change_address (adj_offsettable_operand (op1, 4),
 				    SImode, NULL_RTX);
 	  if (BYTES_BIG_ENDIAN)
 	    {
@@ -4693,7 +4695,7 @@ move\\t%0,%z4\\n\\
 ;; use a TImode scratch reg.
 
 (define_expand "reload_outdi"
-  [(set (match_operand:DI 0 "general_operand" "=b")
+  [(set (match_operand:DI 0 "" "=b")
 	(match_operand:DI 1 "se_register_operand" "b"))
    (clobber (match_operand:TI 2 "register_operand" "=&d"))]
   "TARGET_64BIT"
@@ -4715,10 +4717,12 @@ move\\t%0,%z4\\n\\
       if (GET_CODE (operands[0]) == MEM)
 	{
 	  rtx scratch, memword, offword, hiword, loword;
+	  rtx addr = find_replacement (&XEXP (operands[0], 0));
+	  rtx op0 = change_address (operands[0], VOIDmode, addr);
 
 	  scratch = gen_rtx (REG, SImode, REGNO (operands[2]));
-	  memword = change_address (operands[0], SImode, NULL_RTX);
-	  offword = change_address (adj_offsettable_operand (operands[0], 4),
+	  memword = change_address (op0, SImode, NULL_RTX);
+	  offword = change_address (adj_offsettable_operand (op0, 4),
 				    SImode, NULL_RTX);
 	  if (BYTES_BIG_ENDIAN)
 	    {
diff --git a/gcc/config/ns32k/ns32k.c b/gcc/config/ns32k/ns32k.c
index 1c759aed060..8c2fb1f784b 100644
--- a/gcc/config/ns32k/ns32k.c
+++ b/gcc/config/ns32k/ns32k.c
@@ -495,7 +495,7 @@ print_operand (file, x, code)
 	  u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
 	  PUT_IMMEDIATE_PREFIX(file);
 #ifdef SEQUENT_ASM
-	  /* Sequent likes it's floating point constants as integers */
+	  /* Sequent likes its floating point constants as integers */
 	  fprintf (file, "0Dx%08x%08x", u.i[1], u.i[0]);
 #else
 #ifdef ENCORE_ASM
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 5d2059c561c..77bae75405b 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -1390,7 +1390,7 @@ extern char leaf_reg_remap[];
    : gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, frame_pointer_rtx,	\
 				  GEN_INT (STARTING_FRAME_OFFSET))))
 
-/* Get_secondary_mem widens it's argument to BITS_PER_WORD which loses on v9
+/* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
    because the movsi and movsf patterns don't handle r/f moves.
    For v8 we copy the default definition.  */
 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index a8fb8f82d93..ff77c99a4a4 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -5614,7 +5614,7 @@ if (! TARGET_ARCH64)
   if (GET_CODE (XEXP (operands[0], 0)) == LABEL_REF)
     {
       /* This is really a PIC sequence.  We want to represent
-	 it as a funny jump so it's delay slots can be filled. 
+	 it as a funny jump so its delay slots can be filled. 
 
 	 ??? But if this really *is* a CALL, will not it clobber the
 	 call-clobbered registers?  We lose this if it is a JUMP_INSN.