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author | law <law@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-01-30 13:50:10 +0000 |
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committer | law <law@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-01-30 13:50:10 +0000 |
commit | 51a37ccae91f4e77ae0a34c5828413c4f2938a28 (patch) | |
tree | 38ce516e6258bbf3412b44284c428c6d19a85d67 /gcc/config | |
parent | ecfe64e715427b09de5d98f13d842885edbdeec5 (diff) | |
download | gcc-51a37ccae91f4e77ae0a34c5828413c4f2938a28.tar.gz |
* pa.md (parallel shift and shiftadd): Mark output of shift as an
earlyclobber.
Fixes -O1 bootstrap problem.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@24922 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
-rw-r--r-- | gcc/config/pa/pa.md | 51 |
1 files changed, 27 insertions, 24 deletions
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index ada7553d99f..5775e201624 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -3627,6 +3627,28 @@ [(set_attr "type" "binary") (set_attr "length" "4")]) +;; This variant of the above insn can occur if the first operand +;; is the frame pointer. This is a kludge, but there doesn't +;; seem to be a way around it. Only recognize it while reloading. +;; Note how operand 3 uses a predicate of "const_int_operand", but +;; has constraints allowing a register. I don't know how this works, +;; but it somehow makes sure that out-of-range constants are placed +;; in a register which somehow magically is a "const_int_operand". +;; (this was stolen from alpha.md, I'm not going to try and change it. + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=&r,r") + (plus:SI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r") + (match_operand:SI 4 "shadd_operand" "")) + (match_operand:SI 1 "register_operand" "r,r")) + (match_operand:SI 3 "const_int_operand" "r,J")))] + "reload_in_progress" + "@ + sh%O4addl %2,%1,%0\;addl %3,%0,%0 + sh%O4addl %2,%1,%0\;ldo %3(%0),%0" + [(set_attr "type" "multi") + (set_attr "length" "8")]) + ;; This anonymous pattern and splitter wins because it reduces the latency ;; of the shadd sequence without increasing the latency of the shift. ;; @@ -3636,12 +3658,15 @@ ;; It would be clearer if combine used the same operator for both expressions, ;; it's somewhat confusing to have a mult in ine operation and an ashift ;; in the other. +;; +;; If this pattern is not split before register allocation, then we must expose +;; the fact that operand 4 is set before operands 1, 2 and 3 have been read. (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r") (match_operand:SI 3 "shadd_operand" "")) (match_operand:SI 1 "register_operand" "r"))) - (set (match_operand:SI 4 "register_operand" "=r") + (set (match_operand:SI 4 "register_operand" "=&r") (ashift:SI (match_dup 2) (match_operand:SI 5 "const_int_operand" "i")))] "INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))" @@ -3654,7 +3679,7 @@ (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r") (match_operand:SI 3 "shadd_operand" "")) (match_operand:SI 1 "register_operand" "r"))) - (set (match_operand:SI 4 "register_operand" "=r") + (set (match_operand:SI 4 "register_operand" "=&r") (ashift:SI (match_dup 2) (match_operand:SI 5 "const_int_operand" "i")))] "INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))" @@ -3663,28 +3688,6 @@ (match_dup 1)))] "") -;; This variant of the above insn can occur if the first operand -;; is the frame pointer. This is a kludge, but there doesn't -;; seem to be a way around it. Only recognize it while reloading. -;; Note how operand 3 uses a predicate of "const_int_operand", but -;; has constraints allowing a register. I don't know how this works, -;; but it somehow makes sure that out-of-range constants are placed -;; in a register which somehow magically is a "const_int_operand". -;; (this was stolen from alpha.md, I'm not going to try and change it. - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=&r,r") - (plus:SI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r,r") - (match_operand:SI 4 "shadd_operand" "")) - (match_operand:SI 1 "register_operand" "r,r")) - (match_operand:SI 3 "const_int_operand" "r,J")))] - "reload_in_progress" - "@ - sh%O4addl %2,%1,%0\;addl %3,%0,%0 - sh%O4addl %2,%1,%0\;ldo %3(%0),%0" - [(set_attr "type" "multi") - (set_attr "length" "8")]) - (define_expand "ashlsi3" [(set (match_operand:SI 0 "register_operand" "") (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "") |