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| author | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-11-20 13:32:32 +0000 |
|---|---|---|
| committer | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-11-20 13:32:32 +0000 |
| commit | fe5ad9266cba2cbb611a831aaac450d3f6decd0c (patch) | |
| tree | a1dce161550e71aa81d0af00e118e4f68d907995 /gcc/config | |
| parent | 6715fbd40b05c43941c4d4e093cceb5345a695e7 (diff) | |
| parent | 8c53c46cebf42cb4f4ac125ca6428c5e9b519f66 (diff) | |
| download | gcc-fe5ad9266cba2cbb611a831aaac450d3f6decd0c.tar.gz | |
Merge from trunk.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/wide-int@205111 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
79 files changed, 1083 insertions, 1463 deletions
diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 2f1a8d03cb1..fec7b222529 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -24,6 +24,9 @@ #include "tm.h" #include "rtl.h" #include "tree.h" +#include "stor-layout.h" +#include "stringpool.h" +#include "calls.h" #include "expr.h" #include "tm_p.h" #include "recog.h" @@ -81,57 +84,101 @@ enum aarch64_simd_builtin_type_mode #define UP(X) X##_UP -typedef enum +#define SIMD_MAX_BUILTIN_ARGS 5 + +enum aarch64_type_qualifiers { - AARCH64_SIMD_BINOP, - AARCH64_SIMD_TERNOP, - AARCH64_SIMD_QUADOP, - AARCH64_SIMD_UNOP, - AARCH64_SIMD_GETLANE, - AARCH64_SIMD_SETLANE, - AARCH64_SIMD_CREATE, - AARCH64_SIMD_DUP, - AARCH64_SIMD_DUPLANE, - AARCH64_SIMD_COMBINE, - AARCH64_SIMD_SPLIT, - AARCH64_SIMD_LANEMUL, - AARCH64_SIMD_LANEMULL, - AARCH64_SIMD_LANEMULH, - AARCH64_SIMD_LANEMAC, - AARCH64_SIMD_SCALARMUL, - AARCH64_SIMD_SCALARMULL, - AARCH64_SIMD_SCALARMULH, - AARCH64_SIMD_SCALARMAC, - AARCH64_SIMD_CONVERT, - AARCH64_SIMD_FIXCONV, - AARCH64_SIMD_SELECT, - AARCH64_SIMD_RESULTPAIR, - AARCH64_SIMD_REINTERP, - AARCH64_SIMD_VTBL, - AARCH64_SIMD_VTBX, - AARCH64_SIMD_LOAD1, - AARCH64_SIMD_LOAD1LANE, - AARCH64_SIMD_STORE1, - AARCH64_SIMD_STORE1LANE, - AARCH64_SIMD_LOADSTRUCT, - AARCH64_SIMD_LOADSTRUCTLANE, - AARCH64_SIMD_STORESTRUCT, - AARCH64_SIMD_STORESTRUCTLANE, - AARCH64_SIMD_LOGICBINOP, - AARCH64_SIMD_SHIFTINSERT, - AARCH64_SIMD_SHIFTIMM, - AARCH64_SIMD_SHIFTACC -} aarch64_simd_itype; + /* T foo. */ + qualifier_none = 0x0, + /* unsigned T foo. */ + qualifier_unsigned = 0x1, /* 1 << 0 */ + /* const T foo. */ + qualifier_const = 0x2, /* 1 << 1 */ + /* T *foo. */ + qualifier_pointer = 0x4, /* 1 << 2 */ + /* const T *foo. */ + qualifier_const_pointer = 0x6, /* qualifier_const | qualifier_pointer */ + /* Used when expanding arguments if an operand could + be an immediate. */ + qualifier_immediate = 0x8, /* 1 << 3 */ + qualifier_maybe_immediate = 0x10, /* 1 << 4 */ + /* void foo (...). */ + qualifier_void = 0x20, /* 1 << 5 */ + /* Some patterns may have internal operands, this qualifier is an + instruction to the initialisation code to skip this operand. */ + qualifier_internal = 0x40, /* 1 << 6 */ + /* Some builtins should use the T_*mode* encoded in a simd_builtin_datum + rather than using the type of the operand. */ + qualifier_map_mode = 0x80, /* 1 << 7 */ + /* qualifier_pointer | qualifier_map_mode */ + qualifier_pointer_map_mode = 0x84, + /* qualifier_const_pointer | qualifier_map_mode */ + qualifier_const_pointer_map_mode = 0x86 +}; typedef struct { const char *name; - const aarch64_simd_itype itype; enum aarch64_simd_builtin_type_mode mode; const enum insn_code code; unsigned int fcode; + enum aarch64_type_qualifiers *qualifiers; } aarch64_simd_builtin_datum; +static enum aarch64_type_qualifiers +aarch64_types_unop_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none }; +#define TYPES_UNOP (aarch64_types_unop_qualifiers) +#define TYPES_CREATE (aarch64_types_unop_qualifiers) +#define TYPES_REINTERP (aarch64_types_unop_qualifiers) +static enum aarch64_type_qualifiers +aarch64_types_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_maybe_immediate }; +#define TYPES_BINOP (aarch64_types_binop_qualifiers) +static enum aarch64_type_qualifiers +aarch64_types_ternop_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none, qualifier_none }; +#define TYPES_TERNOP (aarch64_types_ternop_qualifiers) +static enum aarch64_type_qualifiers +aarch64_types_quadop_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none, + qualifier_none, qualifier_none }; +#define TYPES_QUADOP (aarch64_types_quadop_qualifiers) + +static enum aarch64_type_qualifiers +aarch64_types_getlane_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_immediate }; +#define TYPES_GETLANE (aarch64_types_getlane_qualifiers) +#define TYPES_SHIFTIMM (aarch64_types_getlane_qualifiers) +static enum aarch64_type_qualifiers +aarch64_types_setlane_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate }; +#define TYPES_SETLANE (aarch64_types_setlane_qualifiers) +#define TYPES_SHIFTINSERT (aarch64_types_setlane_qualifiers) +#define TYPES_SHIFTACC (aarch64_types_setlane_qualifiers) + +static enum aarch64_type_qualifiers +aarch64_types_combine_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none }; +#define TYPES_COMBINE (aarch64_types_combine_qualifiers) + +static enum aarch64_type_qualifiers +aarch64_types_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_const_pointer_map_mode }; +#define TYPES_LOAD1 (aarch64_types_load1_qualifiers) +#define TYPES_LOADSTRUCT (aarch64_types_load1_qualifiers) + +/* The first argument (return type) of a store should be void type, + which we represent with qualifier_void. Their first operand will be + a DImode pointer to the location to store to, so we must use + qualifier_map_mode | qualifier_pointer to build a pointer to the + element type of the vector. */ +static enum aarch64_type_qualifiers +aarch64_types_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_void, qualifier_pointer_map_mode, qualifier_none }; +#define TYPES_STORE1 (aarch64_types_store1_qualifiers) +#define TYPES_STORESTRUCT (aarch64_types_store1_qualifiers) + #define CF0(N, X) CODE_FOR_aarch64_##N##X #define CF1(N, X) CODE_FOR_##N##X##1 #define CF2(N, X) CODE_FOR_##N##X##2 @@ -140,7 +187,7 @@ typedef struct #define CF10(N, X) CODE_FOR_##N##X #define VAR1(T, N, MAP, A) \ - {#N, AARCH64_SIMD_##T, UP (A), CF##MAP (N, A), 0}, + {#N, UP (A), CF##MAP (N, A), 0, TYPES_##T}, #define VAR2(T, N, MAP, A, B) \ VAR1 (T, N, MAP, A) \ VAR1 (T, N, MAP, B) @@ -279,118 +326,175 @@ static GTY(()) tree aarch64_builtin_decls[AARCH64_BUILTIN_MAX]; #define NUM_DREG_TYPES 6 #define NUM_QREG_TYPES 6 +/* Return a tree for a signed or unsigned argument of either + the mode specified by MODE, or the inner mode of MODE. */ +tree +aarch64_build_scalar_type (enum machine_mode mode, bool unsigned_p) +{ +#undef INT_TYPES +#define INT_TYPES \ + AARCH64_TYPE_BUILDER (QI) \ + AARCH64_TYPE_BUILDER (HI) \ + AARCH64_TYPE_BUILDER (SI) \ + AARCH64_TYPE_BUILDER (DI) \ + AARCH64_TYPE_BUILDER (EI) \ + AARCH64_TYPE_BUILDER (OI) \ + AARCH64_TYPE_BUILDER (CI) \ + AARCH64_TYPE_BUILDER (XI) \ + AARCH64_TYPE_BUILDER (TI) \ + +/* Statically declare all the possible types we might need. */ +#undef AARCH64_TYPE_BUILDER +#define AARCH64_TYPE_BUILDER(X) \ + static tree X##_aarch64_type_node_s = NULL; \ + static tree X##_aarch64_type_node_u = NULL; + + INT_TYPES + + static tree float_aarch64_type_node = NULL; + static tree double_aarch64_type_node = NULL; + + gcc_assert (!VECTOR_MODE_P (mode)); + +/* If we've already initialised this type, don't initialise it again, + otherwise ask for a new type of the correct size. */ +#undef AARCH64_TYPE_BUILDER +#define AARCH64_TYPE_BUILDER(X) \ + case X##mode: \ + if (unsigned_p) \ + return (X##_aarch64_type_node_u \ + ? X##_aarch64_type_node_u \ + : X##_aarch64_type_node_u \ + = make_unsigned_type (GET_MODE_PRECISION (mode))); \ + else \ + return (X##_aarch64_type_node_s \ + ? X##_aarch64_type_node_s \ + : X##_aarch64_type_node_s \ + = make_signed_type (GET_MODE_PRECISION (mode))); \ + break; + + switch (mode) + { + INT_TYPES + case SFmode: + if (!float_aarch64_type_node) + { + float_aarch64_type_node = make_node (REAL_TYPE); + TYPE_PRECISION (float_aarch64_type_node) = FLOAT_TYPE_SIZE; + layout_type (float_aarch64_type_node); + } + return float_aarch64_type_node; + break; + case DFmode: + if (!double_aarch64_type_node) + { + double_aarch64_type_node = make_node (REAL_TYPE); + TYPE_PRECISION (double_aarch64_type_node) = DOUBLE_TYPE_SIZE; + layout_type (double_aarch64_type_node); + } + return double_aarch64_type_node; + break; + default: + gcc_unreachable (); + } +} + +tree +aarch64_build_vector_type (enum machine_mode mode, bool unsigned_p) +{ + tree eltype; + +#define VECTOR_TYPES \ + AARCH64_TYPE_BUILDER (V16QI) \ + AARCH64_TYPE_BUILDER (V8HI) \ + AARCH64_TYPE_BUILDER (V4SI) \ + AARCH64_TYPE_BUILDER (V2DI) \ + AARCH64_TYPE_BUILDER (V8QI) \ + AARCH64_TYPE_BUILDER (V4HI) \ + AARCH64_TYPE_BUILDER (V2SI) \ + \ + AARCH64_TYPE_BUILDER (V4SF) \ + AARCH64_TYPE_BUILDER (V2DF) \ + AARCH64_TYPE_BUILDER (V2SF) \ +/* Declare our "cache" of values. */ +#undef AARCH64_TYPE_BUILDER +#define AARCH64_TYPE_BUILDER(X) \ + static tree X##_aarch64_type_node_s = NULL; \ + static tree X##_aarch64_type_node_u = NULL; + + VECTOR_TYPES + + gcc_assert (VECTOR_MODE_P (mode)); + +#undef AARCH64_TYPE_BUILDER +#define AARCH64_TYPE_BUILDER(X) \ + case X##mode: \ + if (unsigned_p) \ + return X##_aarch64_type_node_u \ + ? X##_aarch64_type_node_u \ + : X##_aarch64_type_node_u \ + = build_vector_type_for_mode (aarch64_build_scalar_type \ + (GET_MODE_INNER (mode), \ + unsigned_p), mode); \ + else \ + return X##_aarch64_type_node_s \ + ? X##_aarch64_type_node_s \ + : X##_aarch64_type_node_s \ + = build_vector_type_for_mode (aarch64_build_scalar_type \ + (GET_MODE_INNER (mode), \ + unsigned_p), mode); \ + break; + + switch (mode) + { + default: + eltype = aarch64_build_scalar_type (GET_MODE_INNER (mode), unsigned_p); + return build_vector_type_for_mode (eltype, mode); + break; + VECTOR_TYPES + } +} + +tree +aarch64_build_type (enum machine_mode mode, bool unsigned_p) +{ + if (VECTOR_MODE_P (mode)) + return aarch64_build_vector_type (mode, unsigned_p); + else + return aarch64_build_scalar_type (mode, unsigned_p); +} + static void aarch64_init_simd_builtins (void) { unsigned int i, fcode = AARCH64_SIMD_BUILTIN_BASE + 1; - /* Scalar type nodes. */ - tree aarch64_simd_intQI_type_node; - tree aarch64_simd_intHI_type_node; - tree aarch64_simd_polyQI_type_node; - tree aarch64_simd_polyHI_type_node; - tree aarch64_simd_intSI_type_node; - tree aarch64_simd_intDI_type_node; - tree aarch64_simd_float_type_node; - tree aarch64_simd_double_type_node; - - /* Pointer to scalar type nodes. */ - tree intQI_pointer_node; - tree intHI_pointer_node; - tree intSI_pointer_node; - tree intDI_pointer_node; - tree float_pointer_node; - tree double_pointer_node; - - /* Const scalar type nodes. */ - tree const_intQI_node; - tree const_intHI_node; - tree const_intSI_node; - tree const_intDI_node; - tree const_float_node; - tree const_double_node; - - /* Pointer to const scalar type nodes. */ - tree const_intQI_pointer_node; - tree const_intHI_pointer_node; - tree const_intSI_pointer_node; - tree const_intDI_pointer_node; - tree const_float_pointer_node; - tree const_double_pointer_node; - - /* Vector type nodes. */ - tree V8QI_type_node; - tree V4HI_type_node; - tree V2SI_type_node; - tree V2SF_type_node; - tree V16QI_type_node; - tree V8HI_type_node; - tree V4SI_type_node; - tree V4SF_type_node; - tree V2DI_type_node; - tree V2DF_type_node; - - /* Scalar unsigned type nodes. */ - tree intUQI_type_node; - tree intUHI_type_node; - tree intUSI_type_node; - tree intUDI_type_node; - - /* Opaque integer types for structures of vectors. */ - tree intEI_type_node; - tree intOI_type_node; - tree intCI_type_node; - tree intXI_type_node; - - /* Pointer to vector type nodes. */ - tree V8QI_pointer_node; - tree V4HI_pointer_node; - tree V2SI_pointer_node; - tree V2SF_pointer_node; - tree V16QI_pointer_node; - tree V8HI_pointer_node; - tree V4SI_pointer_node; - tree V4SF_pointer_node; - tree V2DI_pointer_node; - tree V2DF_pointer_node; - - /* Operations which return results as pairs. */ - tree void_ftype_pv8qi_v8qi_v8qi; - tree void_ftype_pv4hi_v4hi_v4hi; - tree void_ftype_pv2si_v2si_v2si; - tree void_ftype_pv2sf_v2sf_v2sf; - tree void_ftype_pdi_di_di; - tree void_ftype_pv16qi_v16qi_v16qi; - tree void_ftype_pv8hi_v8hi_v8hi; - tree void_ftype_pv4si_v4si_v4si; - tree void_ftype_pv4sf_v4sf_v4sf; - tree void_ftype_pv2di_v2di_v2di; - tree void_ftype_pv2df_v2df_v2df; - - tree reinterp_ftype_dreg[NUM_DREG_TYPES][NUM_DREG_TYPES]; - tree reinterp_ftype_qreg[NUM_QREG_TYPES][NUM_QREG_TYPES]; - tree dreg_types[NUM_DREG_TYPES], qreg_types[NUM_QREG_TYPES]; - - /* Create distinguished type nodes for AARCH64_SIMD vector element types, - and pointers to values of such types, so we can detect them later. */ - aarch64_simd_intQI_type_node = - make_signed_type (GET_MODE_PRECISION (QImode)); - aarch64_simd_intHI_type_node = - make_signed_type (GET_MODE_PRECISION (HImode)); - aarch64_simd_polyQI_type_node = + /* In order that 'poly' types mangle correctly they must not share + a base tree with the other scalar types, thus we must generate them + as a special case. */ + tree aarch64_simd_polyQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode)); - aarch64_simd_polyHI_type_node = + tree aarch64_simd_polyHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode)); - aarch64_simd_intSI_type_node = - make_signed_type (GET_MODE_PRECISION (SImode)); - aarch64_simd_intDI_type_node = - make_signed_type (GET_MODE_PRECISION (DImode)); - aarch64_simd_float_type_node = make_node (REAL_TYPE); - aarch64_simd_double_type_node = make_node (REAL_TYPE); - TYPE_PRECISION (aarch64_simd_float_type_node) = FLOAT_TYPE_SIZE; - TYPE_PRECISION (aarch64_simd_double_type_node) = DOUBLE_TYPE_SIZE; - layout_type (aarch64_simd_float_type_node); - layout_type (aarch64_simd_double_type_node); + + /* Scalar type nodes. */ + tree aarch64_simd_intQI_type_node = aarch64_build_type (QImode, false); + tree aarch64_simd_intHI_type_node = aarch64_build_type (HImode, false); + tree aarch64_simd_intSI_type_node = aarch64_build_type (SImode, false); + tree aarch64_simd_intDI_type_node = aarch64_build_type (DImode, false); + tree aarch64_simd_intTI_type_node = aarch64_build_type (TImode, false); + tree aarch64_simd_intEI_type_node = aarch64_build_type (EImode, false); + tree aarch64_simd_intOI_type_node = aarch64_build_type (OImode, false); + tree aarch64_simd_intCI_type_node = aarch64_build_type (CImode, false); + tree aarch64_simd_intXI_type_node = aarch64_build_type (XImode, false); + tree aarch64_simd_intUQI_type_node = aarch64_build_type (QImode, true); + tree aarch64_simd_intUHI_type_node = aarch64_build_type (HImode, true); + tree aarch64_simd_intUSI_type_node = aarch64_build_type (SImode, true); + tree aarch64_simd_intUDI_type_node = aarch64_build_type (DImode, true); + + /* Float type nodes. */ + tree aarch64_simd_float_type_node = aarch64_build_type (SFmode, false); + tree aarch64_simd_double_type_node = aarch64_build_type (DFmode, false); /* Define typedefs which exactly correspond to the modes we are basing vector types on. If you change these names you'll need to change @@ -411,518 +515,129 @@ aarch64_init_simd_builtins (void) "__builtin_aarch64_simd_poly8"); (*lang_hooks.types.register_builtin_type) (aarch64_simd_polyHI_type_node, "__builtin_aarch64_simd_poly16"); - - intQI_pointer_node = build_pointer_type (aarch64_simd_intQI_type_node); - intHI_pointer_node = build_pointer_type (aarch64_simd_intHI_type_node); - intSI_pointer_node = build_pointer_type (aarch64_simd_intSI_type_node); - intDI_pointer_node = build_pointer_type (aarch64_simd_intDI_type_node); - float_pointer_node = build_pointer_type (aarch64_simd_float_type_node); - double_pointer_node = build_pointer_type (aarch64_simd_double_type_node); - - /* Next create constant-qualified versions of the above types. */ - const_intQI_node = build_qualified_type (aarch64_simd_intQI_type_node, - TYPE_QUAL_CONST); - const_intHI_node = build_qualified_type (aarch64_simd_intHI_type_node, - TYPE_QUAL_CONST); - const_intSI_node = build_qualified_type (aarch64_simd_intSI_type_node, - TYPE_QUAL_CONST); - const_intDI_node = build_qualified_type (aarch64_simd_intDI_type_node, - TYPE_QUAL_CONST); - const_float_node = build_qualified_type (aarch64_simd_float_type_node, - TYPE_QUAL_CONST); - const_double_node = build_qualified_type (aarch64_simd_double_type_node, - TYPE_QUAL_CONST); - - const_intQI_pointer_node = build_pointer_type (const_intQI_node); - const_intHI_pointer_node = build_pointer_type (const_intHI_node); - const_intSI_pointer_node = build_pointer_type (const_intSI_node); - const_intDI_pointer_node = build_pointer_type (const_intDI_node); - const_float_pointer_node = build_pointer_type (const_float_node); - const_double_pointer_node = build_pointer_type (const_double_node); - - /* Now create vector types based on our AARCH64 SIMD element types. */ - /* 64-bit vectors. */ - V8QI_type_node = - build_vector_type_for_mode (aarch64_simd_intQI_type_node, V8QImode); - V4HI_type_node = - build_vector_type_for_mode (aarch64_simd_intHI_type_node, V4HImode); - V2SI_type_node = - build_vector_type_for_mode (aarch64_simd_intSI_type_node, V2SImode); - V2SF_type_node = - build_vector_type_for_mode (aarch64_simd_float_type_node, V2SFmode); - /* 128-bit vectors. */ - V16QI_type_node = - build_vector_type_for_mode (aarch64_simd_intQI_type_node, V16QImode); - V8HI_type_node = - build_vector_type_for_mode (aarch64_simd_intHI_type_node, V8HImode); - V4SI_type_node = - build_vector_type_for_mode (aarch64_simd_intSI_type_node, V4SImode); - V4SF_type_node = - build_vector_type_for_mode (aarch64_simd_float_type_node, V4SFmode); - V2DI_type_node = - build_vector_type_for_mode (aarch64_simd_intDI_type_node, V2DImode); - V2DF_type_node = - build_vector_type_for_mode (aarch64_simd_double_type_node, V2DFmode); - - /* Unsigned integer types for various mode sizes. */ - intUQI_type_node = make_unsigned_type (GET_MODE_PRECISION (QImode)); - intUHI_type_node = make_unsigned_type (GET_MODE_PRECISION (HImode)); - intUSI_type_node = make_unsigned_type (GET_MODE_PRECISION (SImode)); - intUDI_type_node = make_unsigned_type (GET_MODE_PRECISION (DImode)); - - (*lang_hooks.types.register_builtin_type) (intUQI_type_node, - "__builtin_aarch64_simd_uqi"); - (*lang_hooks.types.register_builtin_type) (intUHI_type_node, - "__builtin_aarch64_simd_uhi"); - (*lang_hooks.types.register_builtin_type) (intUSI_type_node, - "__builtin_aarch64_simd_usi"); - (*lang_hooks.types.register_builtin_type) (intUDI_type_node, - "__builtin_aarch64_simd_udi"); - - /* Opaque integer types for structures of vectors. */ - intEI_type_node = make_signed_type (GET_MODE_PRECISION (EImode)); - intOI_type_node = make_signed_type (GET_MODE_PRECISION (OImode)); - intCI_type_node = make_signed_type (GET_MODE_PRECISION (CImode)); - intXI_type_node = make_signed_type (GET_MODE_PRECISION (XImode)); - - (*lang_hooks.types.register_builtin_type) (intTI_type_node, + (*lang_hooks.types.register_builtin_type) (aarch64_simd_intTI_type_node, "__builtin_aarch64_simd_ti"); - (*lang_hooks.types.register_builtin_type) (intEI_type_node, + (*lang_hooks.types.register_builtin_type) (aarch64_simd_intEI_type_node, "__builtin_aarch64_simd_ei"); - (*lang_hooks.types.register_builtin_type) (intOI_type_node, + (*lang_hooks.types.register_builtin_type) (aarch64_simd_intOI_type_node, "__builtin_aarch64_simd_oi"); - (*lang_hooks.types.register_builtin_type) (intCI_type_node, + (*lang_hooks.types.register_builtin_type) (aarch64_simd_intCI_type_node, "__builtin_aarch64_simd_ci"); - (*lang_hooks.types.register_builtin_type) (intXI_type_node, + (*lang_hooks.types.register_builtin_type) (aarch64_simd_intXI_type_node, "__builtin_aarch64_simd_xi"); - /* Pointers to vector types. */ - V8QI_pointer_node = build_pointer_type (V8QI_type_node); - V4HI_pointer_node = build_pointer_type (V4HI_type_node); - V2SI_pointer_node = build_pointer_type (V2SI_type_node); - V2SF_pointer_node = build_pointer_type (V2SF_type_node); - V16QI_pointer_node = build_pointer_type (V16QI_type_node); - V8HI_pointer_node = build_pointer_type (V8HI_type_node); - V4SI_pointer_node = build_pointer_type (V4SI_type_node); - V4SF_pointer_node = build_pointer_type (V4SF_type_node); - V2DI_pointer_node = build_pointer_type (V2DI_type_node); - V2DF_pointer_node = build_pointer_type (V2DF_type_node); - - /* Operations which return results as pairs. */ - void_ftype_pv8qi_v8qi_v8qi = - build_function_type_list (void_type_node, V8QI_pointer_node, - V8QI_type_node, V8QI_type_node, NULL); - void_ftype_pv4hi_v4hi_v4hi = - build_function_type_list (void_type_node, V4HI_pointer_node, - V4HI_type_node, V4HI_type_node, NULL); - void_ftype_pv2si_v2si_v2si = - build_function_type_list (void_type_node, V2SI_pointer_node, - V2SI_type_node, V2SI_type_node, NULL); - void_ftype_pv2sf_v2sf_v2sf = - build_function_type_list (void_type_node, V2SF_pointer_node, - V2SF_type_node, V2SF_type_node, NULL); - void_ftype_pdi_di_di = - build_function_type_list (void_type_node, intDI_pointer_node, - aarch64_simd_intDI_type_node, - aarch64_simd_intDI_type_node, NULL); - void_ftype_pv16qi_v16qi_v16qi = - build_function_type_list (void_type_node, V16QI_pointer_node, - V16QI_type_node, V16QI_type_node, NULL); - void_ftype_pv8hi_v8hi_v8hi = - build_function_type_list (void_type_node, V8HI_pointer_node, - V8HI_type_node, V8HI_type_node, NULL); - void_ftype_pv4si_v4si_v4si = - build_function_type_list (void_type_node, V4SI_pointer_node, - V4SI_type_node, V4SI_type_node, NULL); - void_ftype_pv4sf_v4sf_v4sf = - build_function_type_list (void_type_node, V4SF_pointer_node, - V4SF_type_node, V4SF_type_node, NULL); - void_ftype_pv2di_v2di_v2di = - build_function_type_list (void_type_node, V2DI_pointer_node, - V2DI_type_node, V2DI_type_node, NULL); - void_ftype_pv2df_v2df_v2df = - build_function_type_list (void_type_node, V2DF_pointer_node, - V2DF_type_node, V2DF_type_node, NULL); - - dreg_types[0] = V8QI_type_node; - dreg_types[1] = V4HI_type_node; - dreg_types[2] = V2SI_type_node; - dreg_types[3] = V2SF_type_node; - dreg_types[4] = aarch64_simd_intDI_type_node; - dreg_types[5] = aarch64_simd_double_type_node; - - qreg_types[0] = V16QI_type_node; - qreg_types[1] = V8HI_type_node; - qreg_types[2] = V4SI_type_node; - qreg_types[3] = V4SF_type_node; - qreg_types[4] = V2DI_type_node; - qreg_types[5] = V2DF_type_node; - - /* If NUM_DREG_TYPES != NUM_QREG_TYPES, we will need separate nested loops - for qreg and dreg reinterp inits. */ - for (i = 0; i < NUM_DREG_TYPES; i++) - { - int j; - for (j = 0; j < NUM_DREG_TYPES; j++) - { - reinterp_ftype_dreg[i][j] - = build_function_type_list (dreg_types[i], dreg_types[j], NULL); - reinterp_ftype_qreg[i][j] - = build_function_type_list (qreg_types[i], qreg_types[j], NULL); - } - } + /* Unsigned integer types for various mode sizes. */ + (*lang_hooks.types.register_builtin_type) (aarch64_simd_intUQI_type_node, + "__builtin_aarch64_simd_uqi"); + (*lang_hooks.types.register_builtin_type) (aarch64_simd_intUHI_type_node, + "__builtin_aarch64_simd_uhi"); + (*lang_hooks.types.register_builtin_type) (aarch64_simd_intUSI_type_node, + "__builtin_aarch64_simd_usi"); + (*lang_hooks.types.register_builtin_type) (aarch64_simd_intUDI_type_node, + "__builtin_aarch64_simd_udi"); for (i = 0; i < ARRAY_SIZE (aarch64_simd_builtin_data); i++, fcode++) { + bool print_type_signature_p = false; + char type_signature[SIMD_MAX_BUILTIN_ARGS] = { 0 }; aarch64_simd_builtin_datum *d = &aarch64_simd_builtin_data[i]; const char *const modenames[] = - { - "v8qi", "v4hi", "v2si", "v2sf", "di", "df", - "v16qi", "v8hi", "v4si", "v4sf", "v2di", "v2df", - "ti", "ei", "oi", "xi", "si", "sf", "hi", "qi" - }; + { + "v8qi", "v4hi", "v2si", "v2sf", "di", "df", + "v16qi", "v8hi", "v4si", "v4sf", "v2di", "v2df", + "ti", "ei", "oi", "xi", "si", "sf", "hi", "qi" + }; + const enum machine_mode modes[] = + { + V8QImode, V4HImode, V2SImode, V2SFmode, DImode, DFmode, + V16QImode, V8HImode, V4SImode, V4SFmode, V2DImode, + V2DFmode, TImode, EImode, OImode, XImode, SImode, + SFmode, HImode, QImode + }; char namebuf[60]; tree ftype = NULL; tree fndecl = NULL; - int is_load = 0; - int is_store = 0; gcc_assert (ARRAY_SIZE (modenames) == T_MAX); d->fcode = fcode; - switch (d->itype) + /* We must track two variables here. op_num is + the operand number as in the RTL pattern. This is + required to access the mode (e.g. V4SF mode) of the + argument, from which the base type can be derived. + arg_num is an index in to the qualifiers data, which + gives qualifiers to the type (e.g. const unsigned). + The reason these two variables may differ by one is the + void return type. While all return types take the 0th entry + in the qualifiers array, there is no operand for them in the + RTL pattern. */ + int op_num = insn_data[d->code].n_operands - 1; + int arg_num = d->qualifiers[0] & qualifier_void + ? op_num + 1 + : op_num; + tree return_type = void_type_node, args = void_list_node; + tree eltype; + + /* Build a function type directly from the insn_data for this + builtin. The build_function_type () function takes care of + removing duplicates for us. */ + for (; op_num >= 0; arg_num--, op_num--) { - case AARCH64_SIMD_LOAD1: - case AARCH64_SIMD_LOAD1LANE: - case AARCH64_SIMD_LOADSTRUCT: - case AARCH64_SIMD_LOADSTRUCTLANE: - is_load = 1; - /* Fall through. */ - case AARCH64_SIMD_STORE1: - case AARCH64_SIMD_STORE1LANE: - case AARCH64_SIMD_STORESTRUCT: - case AARCH64_SIMD_STORESTRUCTLANE: - if (!is_load) - is_store = 1; - /* Fall through. */ - case AARCH64_SIMD_UNOP: - case AARCH64_SIMD_BINOP: - case AARCH64_SIMD_TERNOP: - case AARCH64_SIMD_QUADOP: - case AARCH64_SIMD_COMBINE: - case AARCH64_SIMD_CONVERT: - case AARCH64_SIMD_CREATE: - case AARCH64_SIMD_DUP: - case AARCH64_SIMD_DUPLANE: - case AARCH64_SIMD_FIXCONV: - case AARCH64_SIMD_GETLANE: - case AARCH64_SIMD_LANEMAC: - case AARCH64_SIMD_LANEMUL: - case AARCH64_SIMD_LANEMULH: - case AARCH64_SIMD_LANEMULL: - case AARCH64_SIMD_LOGICBINOP: - case AARCH64_SIMD_SCALARMAC: - case AARCH64_SIMD_SCALARMUL: - case AARCH64_SIMD_SCALARMULH: - case AARCH64_SIMD_SCALARMULL: - case AARCH64_SIMD_SELECT: - case AARCH64_SIMD_SETLANE: - case AARCH64_SIMD_SHIFTACC: - case AARCH64_SIMD_SHIFTIMM: - case AARCH64_SIMD_SHIFTINSERT: - case AARCH64_SIMD_SPLIT: - case AARCH64_SIMD_VTBL: - case AARCH64_SIMD_VTBX: - { - int k; - tree return_type = void_type_node, args = void_list_node; - tree eltype; - /* Build a function type directly from the insn_data for this - builtin. The build_function_type () function takes care of - removing duplicates for us. */ - - for (k = insn_data[d->code].n_operands -1; k >= 0; k--) - { - /* Skip an internal operand for vget_{low, high}. */ - if (k == 2 && d->itype == AARCH64_SIMD_SPLIT) - continue; - - if (is_load && k == 1) - { - /* AdvSIMD load patterns always have the memory operand - (a DImode pointer) in the operand 1 position. We - want a const pointer to the element type in that - position. */ - gcc_assert (insn_data[d->code].operand[k].mode == DImode); - - switch (d->mode) - { - case T_V8QI: - case T_V16QI: - eltype = const_intQI_pointer_node; - break; - - case T_V4HI: - case T_V8HI: - eltype = const_intHI_pointer_node; - break; - - case T_V2SI: - case T_V4SI: - eltype = const_intSI_pointer_node; - break; - - case T_V2SF: - case T_V4SF: - eltype = const_float_pointer_node; - break; - - case T_DI: - case T_V2DI: - eltype = const_intDI_pointer_node; - break; - - case T_DF: - case T_V2DF: - eltype = const_double_pointer_node; - break; - - default: - gcc_unreachable (); - } - } - else if (is_store && k == 0) - { - /* Similarly, AdvSIMD store patterns use operand 0 as - the memory location to store to (a DImode pointer). - Use a pointer to the element type of the store in - that position. */ - gcc_assert (insn_data[d->code].operand[k].mode == DImode); - - switch (d->mode) - { - case T_V8QI: - case T_V16QI: - eltype = intQI_pointer_node; - break; - - case T_V4HI: - case T_V8HI: - eltype = intHI_pointer_node; - break; - - case T_V2SI: - case T_V4SI: - eltype = intSI_pointer_node; - break; - - case T_V2SF: - case T_V4SF: - eltype = float_pointer_node; - break; - - case T_DI: - case T_V2DI: - eltype = intDI_pointer_node; - break; - - case T_DF: - case T_V2DF: - eltype = double_pointer_node; - break; - - default: - gcc_unreachable (); - } - } - else - { - switch (insn_data[d->code].operand[k].mode) - { - case VOIDmode: - eltype = void_type_node; - break; - /* Scalars. */ - case QImode: - eltype = aarch64_simd_intQI_type_node; - break; - case HImode: - eltype = aarch64_simd_intHI_type_node; - break; - case SImode: - eltype = aarch64_simd_intSI_type_node; - break; - case SFmode: - eltype = aarch64_simd_float_type_node; - break; - case DFmode: - eltype = aarch64_simd_double_type_node; - break; - case DImode: - eltype = aarch64_simd_intDI_type_node; - break; - case TImode: - eltype = intTI_type_node; - break; - case EImode: - eltype = intEI_type_node; - break; - case OImode: - eltype = intOI_type_node; - break; - case CImode: - eltype = intCI_type_node; - break; - case XImode: - eltype = intXI_type_node; - break; - /* 64-bit vectors. */ - case V8QImode: - eltype = V8QI_type_node; - break; - case V4HImode: - eltype = V4HI_type_node; - break; - case V2SImode: - eltype = V2SI_type_node; - break; - case V2SFmode: - eltype = V2SF_type_node; - break; - /* 128-bit vectors. */ - case V16QImode: - eltype = V16QI_type_node; - break; - case V8HImode: - eltype = V8HI_type_node; - break; - case V4SImode: - eltype = V4SI_type_node; - break; - case V4SFmode: - eltype = V4SF_type_node; - break; - case V2DImode: - eltype = V2DI_type_node; - break; - case V2DFmode: - eltype = V2DF_type_node; - break; - default: - gcc_unreachable (); - } - } - - if (k == 0 && !is_store) - return_type = eltype; - else - args = tree_cons (NULL_TREE, eltype, args); - } - ftype = build_function_type (return_type, args); - } - break; + enum machine_mode op_mode = insn_data[d->code].operand[op_num].mode; + enum aarch64_type_qualifiers qualifiers = d->qualifiers[arg_num]; - case AARCH64_SIMD_RESULTPAIR: - { - switch (insn_data[d->code].operand[1].mode) - { - case V8QImode: - ftype = void_ftype_pv8qi_v8qi_v8qi; - break; - case V4HImode: - ftype = void_ftype_pv4hi_v4hi_v4hi; - break; - case V2SImode: - ftype = void_ftype_pv2si_v2si_v2si; - break; - case V2SFmode: - ftype = void_ftype_pv2sf_v2sf_v2sf; - break; - case DImode: - ftype = void_ftype_pdi_di_di; - break; - case V16QImode: - ftype = void_ftype_pv16qi_v16qi_v16qi; - break; - case V8HImode: - ftype = void_ftype_pv8hi_v8hi_v8hi; - break; - case V4SImode: - ftype = void_ftype_pv4si_v4si_v4si; - break; - case V4SFmode: - ftype = void_ftype_pv4sf_v4sf_v4sf; - break; - case V2DImode: - ftype = void_ftype_pv2di_v2di_v2di; - break; - case V2DFmode: - ftype = void_ftype_pv2df_v2df_v2df; - break; - default: - gcc_unreachable (); - } - } - break; + if (qualifiers & qualifier_unsigned) + { + type_signature[arg_num] = 'u'; + print_type_signature_p = true; + } + else + type_signature[arg_num] = 's'; + + /* Skip an internal operand for vget_{low, high}. */ + if (qualifiers & qualifier_internal) + continue; + + /* Some builtins have different user-facing types + for certain arguments, encoded in d->mode. */ + if (qualifiers & qualifier_map_mode) + op_mode = modes[d->mode]; + + /* For pointers, we want a pointer to the basic type + of the vector. */ + if (qualifiers & qualifier_pointer && VECTOR_MODE_P (op_mode)) + op_mode = GET_MODE_INNER (op_mode); + + eltype = aarch64_build_type (op_mode, + qualifiers & qualifier_unsigned); + + /* Add qualifiers. */ + if (qualifiers & qualifier_const) + eltype = build_qualified_type (eltype, TYPE_QUAL_CONST); + + if (qualifiers & qualifier_pointer) + eltype = build_pointer_type (eltype); + + /* If we have reached arg_num == 0, we are at a non-void + return type. Otherwise, we are still processing + arguments. */ + if (arg_num == 0) + return_type = eltype; + else + args = tree_cons (NULL_TREE, eltype, args); + } - case AARCH64_SIMD_REINTERP: - { - /* We iterate over 6 doubleword types, then 6 quadword - types. */ - int rhs_d = d->mode % NUM_DREG_TYPES; - int rhs_q = (d->mode - NUM_DREG_TYPES) % NUM_QREG_TYPES; - switch (insn_data[d->code].operand[0].mode) - { - case V8QImode: - ftype = reinterp_ftype_dreg[0][rhs_d]; - break; - case V4HImode: - ftype = reinterp_ftype_dreg[1][rhs_d]; - break; - case V2SImode: - ftype = reinterp_ftype_dreg[2][rhs_d]; - break; - case V2SFmode: - ftype = reinterp_ftype_dreg[3][rhs_d]; - break; - case DImode: - ftype = reinterp_ftype_dreg[4][rhs_d]; - break; - case DFmode: - ftype = reinterp_ftype_dreg[5][rhs_d]; - break; - case V16QImode: - ftype = reinterp_ftype_qreg[0][rhs_q]; - break; - case V8HImode: - ftype = reinterp_ftype_qreg[1][rhs_q]; - break; - case V4SImode: - ftype = reinterp_ftype_qreg[2][rhs_q]; - break; - case V4SFmode: - ftype = reinterp_ftype_qreg[3][rhs_q]; - break; - case V2DImode: - ftype = reinterp_ftype_qreg[4][rhs_q]; - break; - case V2DFmode: - ftype = reinterp_ftype_qreg[5][rhs_q]; - break; - default: - gcc_unreachable (); - } - } - break; + ftype = build_function_type (return_type, args); - default: - gcc_unreachable (); - } gcc_assert (ftype != NULL); - snprintf (namebuf, sizeof (namebuf), "__builtin_aarch64_%s%s", - d->name, modenames[d->mode]); + if (print_type_signature_p) + snprintf (namebuf, sizeof (namebuf), "__builtin_aarch64_%s%s_%s", + d->name, modenames[d->mode], type_signature); + else + snprintf (namebuf, sizeof (namebuf), "__builtin_aarch64_%s%s", + d->name, modenames[d->mode]); fndecl = add_builtin_function (namebuf, ftype, fcode, BUILT_IN_MD, NULL, NULL_TREE); @@ -953,8 +668,6 @@ typedef enum SIMD_ARG_STOP } builtin_simd_arg; -#define SIMD_MAX_BUILTIN_ARGS 5 - static rtx aarch64_simd_expand_args (rtx target, int icode, int have_retval, tree exp, ...) @@ -1082,99 +795,58 @@ aarch64_simd_expand_builtin (int fcode, tree exp, rtx target) { aarch64_simd_builtin_datum *d = &aarch64_simd_builtin_data[fcode - (AARCH64_SIMD_BUILTIN_BASE + 1)]; - aarch64_simd_itype itype = d->itype; enum insn_code icode = d->code; + builtin_simd_arg args[SIMD_MAX_BUILTIN_ARGS]; + int num_args = insn_data[d->code].n_operands; + int is_void = 0; + int k; - switch (itype) - { - case AARCH64_SIMD_UNOP: - return aarch64_simd_expand_args (target, icode, 1, exp, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_STOP); + is_void = !!(d->qualifiers[0] & qualifier_void); - case AARCH64_SIMD_BINOP: - { - rtx arg2 = expand_normal (CALL_EXPR_ARG (exp, 1)); - /* Handle constants only if the predicate allows it. */ - bool op1_const_int_p = - (CONST_INT_P (arg2) - && (*insn_data[icode].operand[2].predicate) - (arg2, insn_data[icode].operand[2].mode)); - return aarch64_simd_expand_args - (target, icode, 1, exp, - SIMD_ARG_COPY_TO_REG, - op1_const_int_p ? SIMD_ARG_CONSTANT : SIMD_ARG_COPY_TO_REG, - SIMD_ARG_STOP); - } + num_args += is_void; + + for (k = 1; k < num_args; k++) + { + /* We have four arrays of data, each indexed in a different fashion. + qualifiers - element 0 always describes the function return type. + operands - element 0 is either the operand for return value (if + the function has a non-void return type) or the operand for the + first argument. + expr_args - element 0 always holds the first argument. + args - element 0 is always used for the return type. */ + int qualifiers_k = k; + int operands_k = k - is_void; + int expr_args_k = k - 1; + + if (d->qualifiers[qualifiers_k] & qualifier_immediate) + args[k] = SIMD_ARG_CONSTANT; + else if (d->qualifiers[qualifiers_k] & qualifier_maybe_immediate) + { + rtx arg + = expand_normal (CALL_EXPR_ARG (exp, + (expr_args_k))); + /* Handle constants only if the predicate allows it. */ + bool op_const_int_p = + (CONST_INT_P (arg) + && (*insn_data[icode].operand[operands_k].predicate) + (arg, insn_data[icode].operand[operands_k].mode)); + args[k] = op_const_int_p ? SIMD_ARG_CONSTANT : SIMD_ARG_COPY_TO_REG; + } + else + args[k] = SIMD_ARG_COPY_TO_REG; - case AARCH64_SIMD_TERNOP: - return aarch64_simd_expand_args (target, icode, 1, exp, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_STOP); - - case AARCH64_SIMD_QUADOP: - return aarch64_simd_expand_args (target, icode, 1, exp, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_STOP); - case AARCH64_SIMD_LOAD1: - case AARCH64_SIMD_LOADSTRUCT: - return aarch64_simd_expand_args (target, icode, 1, exp, - SIMD_ARG_COPY_TO_REG, SIMD_ARG_STOP); - - case AARCH64_SIMD_STORE1: - case AARCH64_SIMD_STORESTRUCT: - return aarch64_simd_expand_args (target, icode, 0, exp, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_COPY_TO_REG, SIMD_ARG_STOP); - - case AARCH64_SIMD_REINTERP: - return aarch64_simd_expand_args (target, icode, 1, exp, - SIMD_ARG_COPY_TO_REG, SIMD_ARG_STOP); - - case AARCH64_SIMD_CREATE: - return aarch64_simd_expand_args (target, icode, 1, exp, - SIMD_ARG_COPY_TO_REG, SIMD_ARG_STOP); - - case AARCH64_SIMD_COMBINE: - return aarch64_simd_expand_args (target, icode, 1, exp, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_COPY_TO_REG, SIMD_ARG_STOP); - - case AARCH64_SIMD_GETLANE: - return aarch64_simd_expand_args (target, icode, 1, exp, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_CONSTANT, - SIMD_ARG_STOP); - - case AARCH64_SIMD_SETLANE: - return aarch64_simd_expand_args (target, icode, 1, exp, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_CONSTANT, - SIMD_ARG_STOP); - - case AARCH64_SIMD_SHIFTIMM: - return aarch64_simd_expand_args (target, icode, 1, exp, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_CONSTANT, - SIMD_ARG_STOP); - - case AARCH64_SIMD_SHIFTACC: - case AARCH64_SIMD_SHIFTINSERT: - return aarch64_simd_expand_args (target, icode, 1, exp, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_COPY_TO_REG, - SIMD_ARG_CONSTANT, - SIMD_ARG_STOP); - - default: - gcc_unreachable (); } + args[k] = SIMD_ARG_STOP; + + /* The interface to aarch64_simd_expand_args expects a 0 if + the function is void, and a 1 if it is not. */ + return aarch64_simd_expand_args + (target, icode, !is_void, exp, + args[1], + args[2], + args[3], + args[4], + SIMD_ARG_STOP); } /* Expand an expression EXP that calls a built-in function, diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index f9eb975a559..b175e6c4d9d 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -26,6 +26,10 @@ #include "rtl.h" #include "insn-attr.h" #include "tree.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "calls.h" +#include "varasm.h" #include "regs.h" #include "df.h" #include "hard-reg-set.h" @@ -1796,7 +1800,8 @@ aarch64_save_or_restore_fprs (int start_offset, int increment, unsigned regno; unsigned regno2; rtx insn; - rtx (*gen_mem_ref)(enum machine_mode, rtx) = (frame_pointer_needed)? gen_frame_mem : gen_rtx_MEM; + rtx (*gen_mem_ref)(enum machine_mode, rtx) + = (frame_pointer_needed)? gen_frame_mem : gen_rtx_MEM; for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++) @@ -1839,16 +1844,17 @@ aarch64_save_or_restore_fprs (int start_offset, int increment, ( gen_load_pairdf (gen_rtx_REG (DFmode, regno), mem, gen_rtx_REG (DFmode, regno2), mem2)); - add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DFmode, regno)); - add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DFmode, regno2)); + add_reg_note (insn, REG_CFA_RESTORE, + gen_rtx_REG (DFmode, regno)); + add_reg_note (insn, REG_CFA_RESTORE, + gen_rtx_REG (DFmode, regno2)); } /* The first part of a frame-related parallel insn is always assumed to be relevant to the frame calculations; subsequent parts, are only frame-related if explicitly marked. */ - RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, - 1)) = 1; + RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1; regno = regno2; start_offset += increment * 2; } @@ -1859,7 +1865,8 @@ aarch64_save_or_restore_fprs (int start_offset, int increment, else { insn = emit_move_insn (gen_rtx_REG (DFmode, regno), mem); - add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno)); + add_reg_note (insn, REG_CFA_RESTORE, + gen_rtx_REG (DImode, regno)); } start_offset += increment; } diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 8b55a7bb7b5..228115f50fc 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -789,13 +789,13 @@ do { \ /* Emit rtl for profiling. Output assembler code to FILE to call "_mcount" for profiling a function entry. */ -#define PROFILE_HOOK(LABEL) \ -{ \ - rtx fun,lr; \ - lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \ - fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ - emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lr, Pmode); \ -} +#define PROFILE_HOOK(LABEL) \ + { \ + rtx fun, lr; \ + lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \ + fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ + emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lr, Pmode); \ + } /* All the work done in PROFILE_HOOK, but still required. */ #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 47f3eb3f653..22051ec27e6 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -125,155 +125,6 @@ (define_attr "mode2" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF" (const_string "unknown")) -; The "v8type" attribute is used to for fine grained classification of -; AArch64 instructions. This table briefly explains the meaning of each type. - -; adc add/subtract with carry. -; adcs add/subtract with carry (setting condition flags). -; adr calculate address. -; alu simple alu instruction (no memory or fp regs access). -; alu_ext simple alu instruction (sign/zero-extended register). -; alu_shift simple alu instruction, with a source operand shifted by a constant. -; alus simple alu instruction (setting condition flags). -; alus_ext simple alu instruction (sign/zero-extended register, setting condition flags). -; alus_shift simple alu instruction, with a source operand shifted by a constant (setting condition flags). -; bfm bitfield move operation. -; branch branch. -; call subroutine call. -; ccmp conditional compare. -; clz count leading zeros/sign bits. -; csel conditional select. -; dmb data memory barrier. -; extend sign/zero-extend (specialised bitfield move). -; extr extract register-sized bitfield encoding. -; fpsimd_load load single floating point / simd scalar register from memory. -; fpsimd_load2 load pair of floating point / simd scalar registers from memory. -; fpsimd_store store single floating point / simd scalar register to memory. -; fpsimd_store2 store pair floating point / simd scalar registers to memory. -; fadd floating point add/sub. -; fccmp floating point conditional compare. -; fcmp floating point comparison. -; fconst floating point load immediate. -; fcsel floating point conditional select. -; fcvt floating point convert (float to float). -; fcvtf2i floating point convert (float to integer). -; fcvti2f floating point convert (integer to float). -; fdiv floating point division operation. -; ffarith floating point abs, neg or cpy. -; fmadd floating point multiply-add/sub. -; fminmax floating point min/max. -; fmov floating point move (float to float). -; fmovf2i floating point move (float to integer). -; fmovi2f floating point move (integer to float). -; fmul floating point multiply. -; frint floating point round to integral. -; fsqrt floating point square root. -; load_acq load-acquire. -; load load single general register from memory -; load2 load pair of general registers from memory -; logic logical operation (register). -; logic_imm and/or/xor operation (immediate). -; logic_shift logical operation with shift. -; logics logical operation (register, setting condition flags). -; logics_imm and/or/xor operation (immediate, setting condition flags). -; logics_shift logical operation with shift (setting condition flags). -; madd integer multiply-add/sub. -; maddl widening integer multiply-add/sub. -; misc miscellaneous - any type that doesn't fit into the rest. -; move integer move operation. -; move2 double integer move operation. -; movk move 16-bit immediate with keep. -; movz move 16-bit immmediate with zero/one. -; mrs system/special register move. -; mulh 64x64 to 128-bit multiply (high part). -; mull widening multiply. -; mult integer multiply instruction. -; prefetch memory prefetch. -; rbit reverse bits. -; rev reverse bytes. -; sdiv integer division operation (signed). -; shift variable shift operation. -; shift_imm immediate shift operation (specialised bitfield move). -; store_rel store-release. -; store store single general register to memory. -; store2 store pair of general registers to memory. -; udiv integer division operation (unsigned). - -(define_attr "v8type" - "adc,\ - adcs,\ - adr,\ - alu,\ - alu_ext,\ - alu_shift,\ - alus,\ - alus_ext,\ - alus_shift,\ - bfm,\ - branch,\ - call,\ - ccmp,\ - clz,\ - csel,\ - dmb,\ - div,\ - div64,\ - extend,\ - extr,\ - fpsimd_load,\ - fpsimd_load2,\ - fpsimd_store2,\ - fpsimd_store,\ - fadd,\ - fccmp,\ - fcvt,\ - fcvtf2i,\ - fcvti2f,\ - fcmp,\ - fconst,\ - fcsel,\ - fdiv,\ - ffarith,\ - fmadd,\ - fminmax,\ - fmov,\ - fmovf2i,\ - fmovi2f,\ - fmul,\ - frint,\ - fsqrt,\ - load_acq,\ - load1,\ - load2,\ - logic,\ - logic_imm,\ - logic_shift,\ - logics,\ - logics_imm,\ - logics_shift,\ - madd,\ - maddl,\ - misc,\ - move,\ - move2,\ - movk,\ - movz,\ - mrs,\ - mulh,\ - mull,\ - mult,\ - prefetch,\ - rbit,\ - rev,\ - sdiv,\ - shift,\ - shift_imm,\ - store_rel,\ - store1,\ - store2,\ - udiv" - (const_string "alu")) - ; The "type" attribute is is included here from AArch32 backend to be able ; to share pipeline descriptions. (include "../arm/types.md") @@ -328,16 +179,14 @@ [(set (pc) (match_operand:DI 0 "register_operand" "r"))] "" "br\\t%0" - [(set_attr "v8type" "branch") - (set_attr "type" "branch")] + [(set_attr "type" "branch")] ) (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "b\\t%l0" - [(set_attr "v8type" "branch") - (set_attr "type" "branch")] + [(set_attr "type" "branch")] ) (define_expand "cbranch<mode>4" @@ -375,8 +224,7 @@ (pc)))] "" "b%m0\\t%l2" - [(set_attr "v8type" "branch") - (set_attr "type" "branch")] + [(set_attr "type" "branch")] ) (define_expand "casesi" @@ -440,7 +288,6 @@ return aarch64_output_casesi (operands); " [(set_attr "length" "16") - (set_attr "v8type" "branch") (set_attr "type" "branch")] ) @@ -448,7 +295,7 @@ [(unspec[(const_int 0)] UNSPEC_NOP)] "" "nop" - [(set_attr "v8type" "misc")] + [(set_attr "type" "no_insn")] ) (define_expand "prologue" @@ -482,8 +329,7 @@ [(return)] "" "ret" - [(set_attr "v8type" "branch") - (set_attr "type" "branch")] + [(set_attr "type" "branch")] ) (define_insn "eh_return" @@ -491,8 +337,7 @@ UNSPECV_EH_RETURN)] "" "#" - [(set_attr "v8type" "branch") - (set_attr "type" "branch")] + [(set_attr "type" "branch")] ) @@ -513,8 +358,7 @@ (pc)))] "" "<cbz>\\t%<w>0, %l1" - [(set_attr "v8type" "branch") - (set_attr "type" "branch")] + [(set_attr "type" "branch")] ) @@ -533,8 +377,7 @@ return \"ubfx\\t%<w>3, %<w>0, %1, #1\;<cbz>\\t%<w>3, %l2\"; return \"<tbz>\\t%<w>0, %1, %l2\"; " - [(set_attr "v8type" "branch") - (set_attr "type" "branch") + [(set_attr "type" "branch") (set_attr "mode" "<MODE>") (set (attr "length") (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -32768)) @@ -555,8 +398,7 @@ return \"ubfx\\t%<w>2, %<w>0, <sizem1>, #1\;<cbz>\\t%<w>2, %l1\"; return \"<tbz>\\t%<w>0, <sizem1>, %l1\"; " - [(set_attr "v8type" "branch") - (set_attr "type" "branch") + [(set_attr "type" "branch") (set_attr "mode" "<MODE>") (set (attr "length") (if_then_else (and (ge (minus (match_dup 1) (pc)) (const_int -32768)) @@ -601,8 +443,7 @@ (clobber (reg:DI LR_REGNUM))] "" "blr\\t%0" - [(set_attr "v8type" "call") - (set_attr "type" "call")] + [(set_attr "type" "call")] ) (define_insn "*call_symbol" @@ -613,8 +454,7 @@ "GET_CODE (operands[0]) == SYMBOL_REF && !aarch64_is_long_call_p (operands[0])" "bl\\t%a0" - [(set_attr "v8type" "call") - (set_attr "type" "call")] + [(set_attr "type" "call")] ) (define_expand "call_value" @@ -651,8 +491,7 @@ (clobber (reg:DI LR_REGNUM))] "" "blr\\t%1" - [(set_attr "v8type" "call") - (set_attr "type" "call")] + [(set_attr "type" "call")] ) @@ -665,8 +504,7 @@ "GET_CODE (operands[1]) == SYMBOL_REF && !aarch64_is_long_call_p (operands[1])" "bl\\t%a1" - [(set_attr "v8type" "call") - (set_attr "type" "call")] + [(set_attr "type" "call")] ) (define_expand "sibcall" @@ -701,8 +539,7 @@ (use (match_operand 2 "" ""))] "GET_CODE (operands[0]) == SYMBOL_REF" "b\\t%a0" - [(set_attr "v8type" "branch") - (set_attr "type" "branch")] + [(set_attr "type" "branch")] ) @@ -714,8 +551,7 @@ (use (match_operand 3 "" ""))] "GET_CODE (operands[1]) == SYMBOL_REF" "b\\t%a1" - [(set_attr "v8type" "branch") - (set_attr "type" "branch")] + [(set_attr "type" "branch")] ) ;; Call subroutine returning any type. @@ -792,8 +628,7 @@ gcc_unreachable (); } } - [(set_attr "v8type" "move,alu,alu,load1,load1,store1,store1,*,*,*") - (set_attr "type" "mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\ + [(set_attr "type" "mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\ neon_from_gp<q>,neon_from_gp<q>, neon_dup") (set_attr "simd" "*,*,yes,*,*,*,*,yes,yes,yes") (set_attr "mode" "<MODE>")] @@ -834,8 +669,7 @@ fmov\\t%s0, %w1 fmov\\t%w0, %s1 fmov\\t%s0, %s1" - [(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov") - (set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\ + [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\ adr,adr,fmov,fmov,fmov") (set_attr "mode" "SI") (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")] @@ -861,8 +695,7 @@ fmov\\t%x0, %d1 fmov\\t%d0, %d1 movi\\t%d0, %1" - [(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov,fmov") - (set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\ + [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\ adr,adr,fmov,fmov,fmov,fmov") (set_attr "mode" "DI") (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") @@ -877,8 +710,7 @@ "UINTVAL (operands[1]) < GET_MODE_BITSIZE (<MODE>mode) && UINTVAL (operands[1]) % 16 == 0" "movk\\t%<w>0, %X2, lsl %1" - [(set_attr "v8type" "movk") - (set_attr "type" "mov_imm") + [(set_attr "type" "mov_imm") (set_attr "mode" "<MODE>")] ) @@ -909,9 +741,7 @@ stp\\txzr, xzr, %0 ldr\\t%q0, %1 str\\t%q1, %0" - [(set_attr "v8type" "move2,fmovi2f,fmovf2i,*, \ - load2,store2,store2,fpsimd_load,fpsimd_store") - (set_attr "type" "multiple,f_mcr,f_mrc,neon_logic_q, \ + [(set_attr "type" "multiple,f_mcr,f_mrc,neon_logic_q, \ load2,store2,store2,f_loadd,f_stored") (set_attr "mode" "DI,DI,DI,TI,DI,DI,DI,TI,TI") (set_attr "length" "8,8,8,4,4,4,4,4,4") @@ -963,10 +793,7 @@ ldr\\t%w0, %1 str\\t%w1, %0 mov\\t%w0, %w1" - [(set_attr "v8type" "fmovi2f,fmovf2i,\ - fmov,fconst,fpsimd_load,\ - fpsimd_store,fpsimd_load,fpsimd_store,fmov") - (set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\ + [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\ f_loads,f_stores,f_loads,f_stores,fmov") (set_attr "mode" "SF")] ) @@ -986,10 +813,7 @@ ldr\\t%x0, %1 str\\t%x1, %0 mov\\t%x0, %x1" - [(set_attr "v8type" "fmovi2f,fmovf2i,\ - fmov,fconst,fpsimd_load,\ - fpsimd_store,fpsimd_load,fpsimd_store,move") - (set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\ + [(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\ f_loadd,f_stored,f_loadd,f_stored,mov_reg") (set_attr "mode" "DF")] ) @@ -1028,8 +852,7 @@ str\\t%q1, %0 ldp\\t%0, %H0, %1 stp\\t%1, %H1, %0" - [(set_attr "v8type" "logic,move2,fmovi2f,fmovf2i,fconst,fconst,fpsimd_load,fpsimd_store,fpsimd_load2,fpsimd_store2") - (set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,fconstd,fconstd,\ + [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,fconstd,fconstd,\ f_loadd,f_stored,neon_load1_2reg,neon_store1_2reg") (set_attr "mode" "DF,DF,DF,DF,DF,DF,TF,TF,DF,DF") (set_attr "length" "4,8,8,8,4,4,4,4,4,4") @@ -1060,8 +883,7 @@ XEXP (operands[1], 0), GET_MODE_SIZE (<MODE>mode)))" "ldp\\t%<w>0, %<w>2, %1" - [(set_attr "v8type" "load2") - (set_attr "type" "load2") + [(set_attr "type" "load2") (set_attr "mode" "<MODE>")] ) @@ -1077,8 +899,7 @@ XEXP (operands[0], 0), GET_MODE_SIZE (<MODE>mode)))" "stp\\t%<w>1, %<w>3, %0" - [(set_attr "v8type" "store2") - (set_attr "type" "store2") + [(set_attr "type" "store2") (set_attr "mode" "<MODE>")] ) @@ -1094,8 +915,7 @@ XEXP (operands[1], 0), GET_MODE_SIZE (<MODE>mode)))" "ldp\\t%<w>0, %<w>2, %1" - [(set_attr "v8type" "fpsimd_load2") - (set_attr "type" "neon_load1_2reg<q>") + [(set_attr "type" "neon_load1_2reg<q>") (set_attr "mode" "<MODE>")] ) @@ -1111,8 +931,7 @@ XEXP (operands[0], 0), GET_MODE_SIZE (<MODE>mode)))" "stp\\t%<w>1, %<w>3, %0" - [(set_attr "v8type" "fpsimd_store2") - (set_attr "type" "neon_store1_2reg<q>") + [(set_attr "type" "neon_store1_2reg<q>") (set_attr "mode" "<MODE>")] ) @@ -1131,8 +950,7 @@ (match_operand:P 5 "const_int_operand" "n"))))])] "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPI:MODE>mode)" "ldp\\t%<w>2, %<w>3, [%1], %4" - [(set_attr "v8type" "load2") - (set_attr "type" "load2") + [(set_attr "type" "load2") (set_attr "mode" "<GPI:MODE>")] ) @@ -1151,8 +969,7 @@ (match_operand:GPI 3 "register_operand" "r"))])] "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPI:MODE>mode)" "stp\\t%<w>2, %<w>3, [%0, %4]!" - [(set_attr "v8type" "store2") - (set_attr "type" "store2") + [(set_attr "type" "store2") (set_attr "mode" "<GPI:MODE>")] ) @@ -1173,8 +990,7 @@ "@ sxtw\t%0, %w1 ldrsw\t%0, %1" - [(set_attr "v8type" "extend,load1") - (set_attr "type" "extend,load1") + [(set_attr "type" "extend,load1") (set_attr "mode" "DI")] ) @@ -1185,8 +1001,7 @@ "@ uxtw\t%0, %w1 ldr\t%w0, %1" - [(set_attr "v8type" "extend,load1") - (set_attr "type" "extend,load1") + [(set_attr "type" "extend,load1") (set_attr "mode" "DI")] ) @@ -1203,8 +1018,7 @@ "@ sxt<SHORT:size>\t%<GPI:w>0, %w1 ldrs<SHORT:size>\t%<GPI:w>0, %1" - [(set_attr "v8type" "extend,load1") - (set_attr "type" "extend,load1") + [(set_attr "type" "extend,load1") (set_attr "mode" "<GPI:MODE>")] ) @@ -1216,8 +1030,7 @@ uxt<SHORT:size>\t%<GPI:w>0, %w1 ldr<SHORT:size>\t%w0, %1 ldr\t%<SHORT:size>0, %1" - [(set_attr "v8type" "extend,load1,load1") - (set_attr "type" "extend,load1,load1") + [(set_attr "type" "extend,load1,load1") (set_attr "mode" "<GPI:MODE>")] ) @@ -1234,8 +1047,7 @@ "@ <su>xtb\t%w0, %w1 <ldrxt>b\t%w0, %1" - [(set_attr "v8type" "extend,load1") - (set_attr "type" "extend,load1") + [(set_attr "type" "extend,load1") (set_attr "mode" "HI")] ) @@ -1279,8 +1091,7 @@ add\\t%w0, %w1, %2 add\\t%w0, %w1, %w2 sub\\t%w0, %w1, #%n2" - [(set_attr "v8type" "alu") - (set_attr "type" "alu_imm,alu_reg,alu_imm") + [(set_attr "type" "alu_imm,alu_reg,alu_imm") (set_attr "mode" "SI")] ) @@ -1296,8 +1107,7 @@ add\\t%w0, %w1, %2 add\\t%w0, %w1, %w2 sub\\t%w0, %w1, #%n2" - [(set_attr "v8type" "alu") - (set_attr "type" "alu_imm,alu_reg,alu_imm") + [(set_attr "type" "alu_imm,alu_reg,alu_imm") (set_attr "mode" "SI")] ) @@ -1313,8 +1123,7 @@ add\\t%x0, %x1, %x2 sub\\t%x0, %x1, #%n2 add\\t%d0, %d1, %d2" - [(set_attr "v8type" "alu") - (set_attr "type" "alu_imm,alu_reg,alu_imm,alu_reg") + [(set_attr "type" "alu_imm,alu_reg,alu_imm,alu_reg") (set_attr "mode" "DI") (set_attr "simd" "*,*,*,yes")] ) @@ -1332,8 +1141,7 @@ adds\\t%<w>0, %<w>1, %<w>2 adds\\t%<w>0, %<w>1, %<w>2 subs\\t%<w>0, %<w>1, #%n2" - [(set_attr "v8type" "alus") - (set_attr "type" "alus_reg,alus_imm,alus_imm") + [(set_attr "type" "alus_reg,alus_imm,alus_imm") (set_attr "mode" "<MODE>")] ) @@ -1351,8 +1159,7 @@ adds\\t%w0, %w1, %w2 adds\\t%w0, %w1, %w2 subs\\t%w0, %w1, #%n2" - [(set_attr "v8type" "alus") - (set_attr "type" "alus_reg,alus_imm,alus_imm") + [(set_attr "type" "alus_reg,alus_imm,alus_imm") (set_attr "mode" "SI")] ) @@ -1369,8 +1176,7 @@ (match_dup 3)))] "" "adds\\t%<w>0, %<w>3, %<w>1, lsl %p2" - [(set_attr "v8type" "alus_shift") - (set_attr "type" "alus_shift_imm") + [(set_attr "type" "alus_shift_imm") (set_attr "mode" "<MODE>")] ) @@ -1387,8 +1193,7 @@ (mult:GPI (match_dup 2) (match_dup 3))))] "" "subs\\t%<w>0, %<w>1, %<w>2, lsl %p3" - [(set_attr "v8type" "alus_shift") - (set_attr "type" "alus_shift_imm") + [(set_attr "type" "alus_shift_imm") (set_attr "mode" "<MODE>")] ) @@ -1403,8 +1208,7 @@ (plus:GPI (ANY_EXTEND:GPI (match_dup 1)) (match_dup 2)))] "" "adds\\t%<GPI:w>0, %<GPI:w>2, %<GPI:w>1, <su>xt<ALLX:size>" - [(set_attr "v8type" "alus_ext") - (set_attr "type" "alus_ext") + [(set_attr "type" "alus_ext") (set_attr "mode" "<GPI:MODE>")] ) @@ -1419,8 +1223,7 @@ (minus:GPI (match_dup 1) (ANY_EXTEND:GPI (match_dup 2))))] "" "subs\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size>" - [(set_attr "v8type" "alus_ext") - (set_attr "type" "alus_ext") + [(set_attr "type" "alus_ext") (set_attr "mode" "<GPI:MODE>")] ) @@ -1441,8 +1244,7 @@ (match_dup 4)))] "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])" "adds\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2" - [(set_attr "v8type" "alus_ext") - (set_attr "type" "alus_ext") + [(set_attr "type" "alus_ext") (set_attr "mode" "<MODE>")] ) @@ -1463,8 +1265,7 @@ (const_int 0))))] "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])" "subs\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2" - [(set_attr "v8type" "alus_ext") - (set_attr "type" "alus_ext") + [(set_attr "type" "alus_ext") (set_attr "mode" "<MODE>")] ) @@ -1479,8 +1280,7 @@ cmn\\t%<w>0, %<w>1 cmn\\t%<w>0, %<w>1 cmp\\t%<w>0, #%n1" - [(set_attr "v8type" "alus") - (set_attr "type" "alus_reg,alus_imm,alus_imm") + [(set_attr "type" "alus_reg,alus_imm,alus_imm") (set_attr "mode" "<MODE>")] ) @@ -1491,8 +1291,7 @@ (match_operand:GPI 1 "register_operand" "r")))] "" "cmn\\t%<w>1, %<w>0" - [(set_attr "v8type" "alus") - (set_attr "type" "alus_reg") + [(set_attr "type" "alus_reg") (set_attr "mode" "<MODE>")] ) @@ -1503,8 +1302,7 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "add\\t%<w>0, %<w>3, %<w>1, <shift> %2" - [(set_attr "v8type" "alu_shift") - (set_attr "type" "alu_shift_imm") + [(set_attr "type" "alu_shift_imm") (set_attr "mode" "<MODE>")] ) @@ -1513,12 +1311,11 @@ [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (plus:SI (ASHIFT:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_shift_imm_si" "n")) - (match_operand:SI 3 "register_operand" "r"))))] + (match_operand:QI 2 "aarch64_shift_imm_si" "n")) + (match_operand:SI 3 "register_operand" "r"))))] "" "add\\t%w0, %w3, %w1, <shift> %2" - [(set_attr "v8type" "alu_shift") - (set_attr "type" "alu_shift_imm") + [(set_attr "type" "alu_shift_imm") (set_attr "mode" "SI")] ) @@ -1529,8 +1326,7 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "add\\t%<w>0, %<w>3, %<w>1, lsl %p2" - [(set_attr "v8type" "alu_shift") - (set_attr "type" "alu_shift_imm") + [(set_attr "type" "alu_shift_imm") (set_attr "mode" "<MODE>")] ) @@ -1540,8 +1336,7 @@ (match_operand:GPI 2 "register_operand" "r")))] "" "add\\t%<GPI:w>0, %<GPI:w>2, %<GPI:w>1, <su>xt<ALLX:size>" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "<GPI:MODE>")] ) @@ -1553,8 +1348,7 @@ (match_operand:GPI 2 "register_operand" "r"))))] "" "add\\t%w0, %w2, %w1, <su>xt<SHORT:size>" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "SI")] ) @@ -1566,8 +1360,7 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "add\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %2" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "<GPI:MODE>")] ) @@ -1581,8 +1374,7 @@ (match_operand:SI 3 "register_operand" "r"))))] "" "add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %2" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "SI")] ) @@ -1594,8 +1386,7 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "add\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %p2" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "<GPI:MODE>")] ) @@ -1608,8 +1399,7 @@ (match_operand:SI 3 "register_operand" "r"))))] "" "add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %p2" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "SI")] ) @@ -1623,8 +1413,7 @@ (match_operand:GPI 4 "register_operand" "r")))] "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])" "add\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "<MODE>")] ) @@ -1640,8 +1429,7 @@ (match_operand:SI 4 "register_operand" "r"))))] "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])" "add\\t%w0, %w4, %w1, <su>xt%e3 %p2" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "SI")] ) @@ -1654,8 +1442,7 @@ (match_operand:GPI 2 "register_operand" "r"))))] "" "adc\\t%<w>0, %<w>1, %<w>2" - [(set_attr "v8type" "adc") - (set_attr "type" "adc_reg") + [(set_attr "type" "adc_reg") (set_attr "mode" "<MODE>")] ) @@ -1670,8 +1457,7 @@ (match_operand:SI 2 "register_operand" "r")))))] "" "adc\\t%w0, %w1, %w2" - [(set_attr "v8type" "adc") - (set_attr "type" "adc_reg") + [(set_attr "type" "adc_reg") (set_attr "mode" "SI")] ) @@ -1684,8 +1470,7 @@ (geu:GPI (reg:CC CC_REGNUM) (const_int 0))))] "" "adc\\t%<w>0, %<w>1, %<w>2" - [(set_attr "v8type" "adc") - (set_attr "type" "adc_reg") + [(set_attr "type" "adc_reg") (set_attr "mode" "<MODE>")] ) @@ -1700,8 +1485,7 @@ (geu:SI (reg:CC CC_REGNUM) (const_int 0)))))] "" "adc\\t%w0, %w1, %w2" - [(set_attr "v8type" "adc") - (set_attr "type" "adc_reg") + [(set_attr "type" "adc_reg") (set_attr "mode" "SI")] ) @@ -1714,8 +1498,7 @@ (match_operand:GPI 2 "register_operand" "r")))] "" "adc\\t%<w>0, %<w>1, %<w>2" - [(set_attr "v8type" "adc") - (set_attr "type" "adc_reg") + [(set_attr "type" "adc_reg") (set_attr "mode" "<MODE>")] ) @@ -1730,8 +1513,7 @@ (match_operand:SI 2 "register_operand" "r"))))] "" "adc\\t%w0, %w1, %w2" - [(set_attr "v8type" "adc") - (set_attr "type" "adc_reg") + [(set_attr "type" "adc_reg") (set_attr "mode" "SI")] ) @@ -1744,8 +1526,7 @@ (match_operand:GPI 1 "register_operand" "r")))] "" "adc\\t%<w>0, %<w>1, %<w>2" - [(set_attr "v8type" "adc") - (set_attr "type" "adc_reg") + [(set_attr "type" "adc_reg") (set_attr "mode" "<MODE>")] ) @@ -1760,8 +1541,7 @@ (match_operand:SI 1 "register_operand" "r"))))] "" "adc\\t%w0, %w1, %w2" - [(set_attr "v8type" "adc") - (set_attr "type" "adc_reg") + [(set_attr "type" "adc_reg") (set_attr "mode" "SI")] ) @@ -1777,8 +1557,7 @@ operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3]))); return \"add\t%<w>0, %<w>4, %<w>1, uxt%e3 %p2\";" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "<MODE>")] ) @@ -1796,8 +1575,7 @@ operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3]))); return \"add\t%w0, %w4, %w1, uxt%e3 %p2\";" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "SI")] ) @@ -1807,8 +1585,7 @@ (match_operand:SI 2 "register_operand" "r")))] "" "sub\\t%w0, %w1, %w2" - [(set_attr "v8type" "alu") - (set_attr "type" "alu_reg") + [(set_attr "type" "alu_reg") (set_attr "mode" "SI")] ) @@ -1820,8 +1597,7 @@ (match_operand:SI 2 "register_operand" "r"))))] "" "sub\\t%w0, %w1, %w2" - [(set_attr "v8type" "alu") - (set_attr "type" "alu_reg") + [(set_attr "type" "alu_reg") (set_attr "mode" "SI")] ) @@ -1833,8 +1609,7 @@ "@ sub\\t%x0, %x1, %x2 sub\\t%d0, %d1, %d2" - [(set_attr "v8type" "alu") - (set_attr "type" "alu_reg") + [(set_attr "type" "alu_reg, neon_sub") (set_attr "mode" "DI") (set_attr "simd" "*,yes")] ) @@ -1849,8 +1624,7 @@ (minus:GPI (match_dup 1) (match_dup 2)))] "" "subs\\t%<w>0, %<w>1, %<w>2" - [(set_attr "v8type" "alus") - (set_attr "type" "alus_reg") + [(set_attr "type" "alus_reg") (set_attr "mode" "<MODE>")] ) @@ -1864,8 +1638,7 @@ (zero_extend:DI (minus:SI (match_dup 1) (match_dup 2))))] "" "subs\\t%w0, %w1, %w2" - [(set_attr "v8type" "alus") - (set_attr "type" "alus_reg") + [(set_attr "type" "alus_reg") (set_attr "mode" "SI")] ) @@ -1877,8 +1650,7 @@ (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))))] "" "sub\\t%<w>0, %<w>3, %<w>1, <shift> %2" - [(set_attr "v8type" "alu_shift") - (set_attr "type" "alu_shift_imm") + [(set_attr "type" "alu_shift_imm") (set_attr "mode" "<MODE>")] ) @@ -1892,8 +1664,7 @@ (match_operand:QI 2 "aarch64_shift_imm_si" "n")))))] "" "sub\\t%w0, %w3, %w1, <shift> %2" - [(set_attr "v8type" "alu_shift") - (set_attr "type" "alu_shift_imm") + [(set_attr "type" "alu_shift_imm") (set_attr "mode" "SI")] ) @@ -1905,8 +1676,7 @@ (match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))))] "" "sub\\t%<w>0, %<w>3, %<w>1, lsl %p2" - [(set_attr "v8type" "alu_shift") - (set_attr "type" "alu_shift_imm") + [(set_attr "type" "alu_shift_imm") (set_attr "mode" "<MODE>")] ) @@ -1920,8 +1690,7 @@ (match_operand:QI 2 "aarch64_pwr_2_si" "n")))))] "" "sub\\t%w0, %w3, %w1, lsl %p2" - [(set_attr "v8type" "alu_shift") - (set_attr "type" "alu_shift_imm") + [(set_attr "type" "alu_shift_imm") (set_attr "mode" "SI")] ) @@ -1932,8 +1701,7 @@ (match_operand:ALLX 2 "register_operand" "r"))))] "" "sub\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size>" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "<GPI:MODE>")] ) @@ -1946,8 +1714,7 @@ (match_operand:SHORT 2 "register_operand" "r")))))] "" "sub\\t%w0, %w1, %w2, <su>xt<SHORT:size>" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "SI")] ) @@ -1959,8 +1726,7 @@ (match_operand 3 "aarch64_imm3" "Ui3"))))] "" "sub\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size> %3" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "<GPI:MODE>")] ) @@ -1974,8 +1740,7 @@ (match_operand 3 "aarch64_imm3" "Ui3")))))] "" "sub\\t%w0, %w1, %w2, <su>xt<SHORT:size> %3" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "SI")] ) @@ -1989,8 +1754,7 @@ (const_int 0))))] "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])" "sub\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "<MODE>")] ) @@ -2006,8 +1770,7 @@ (const_int 0)))))] "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])" "sub\\t%w0, %w4, %w1, <su>xt%e3 %p2" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "SI")] ) @@ -2020,8 +1783,7 @@ (match_operand:GPI 2 "register_operand" "r")))] "" "sbc\\t%<w>0, %<w>1, %<w>2" - [(set_attr "v8type" "adc") - (set_attr "type" "adc_reg") + [(set_attr "type" "adc_reg") (set_attr "mode" "<MODE>")] ) @@ -2036,8 +1798,7 @@ (match_operand:SI 2 "register_operand" "r"))))] "" "sbc\\t%w0, %w1, %w2" - [(set_attr "v8type" "adc") - (set_attr "type" "adc_reg") + [(set_attr "type" "adc_reg") (set_attr "mode" "SI")] ) @@ -2053,8 +1814,7 @@ operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3]))); return \"sub\t%<w>0, %<w>4, %<w>1, uxt%e3 %p2\";" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "<MODE>")] ) @@ -2072,8 +1832,7 @@ operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3]))); return \"sub\t%w0, %w4, %w1, uxt%e3 %p2\";" - [(set_attr "v8type" "alu_ext") - (set_attr "type" "alu_ext") + [(set_attr "type" "alu_ext") (set_attr "mode" "SI")] ) @@ -2105,8 +1864,7 @@ GEN_INT (63))))); DONE; } - [(set_attr "v8type" "alu") - (set_attr "type" "alu_reg") + [(set_attr "type" "alu_reg") (set_attr "mode" "DI")] ) @@ -2117,8 +1875,7 @@ "@ neg\\t%<w>0, %<w>1 neg\\t%<rtn>0<vas>, %<rtn>1<vas>" - [(set_attr "v8type" "alu") - (set_attr "type" "alu_reg, neon_neg<q>") + [(set_attr "type" "alu_reg, neon_neg<q>") (set_attr "simd" "*,yes") (set_attr "mode" "<MODE>")] ) @@ -2129,8 +1886,7 @@ (zero_extend:DI (neg:SI (match_operand:SI 1 "register_operand" "r"))))] "" "neg\\t%w0, %w1" - [(set_attr "v8type" "alu") - (set_attr "type" "alu_reg") + [(set_attr "type" "alu_reg") (set_attr "mode" "SI")] ) @@ -2140,8 +1896,7 @@ (match_operand:GPI 1 "register_operand" "r")))] "" "ngc\\t%<w>0, %<w>1" - [(set_attr "v8type" "adc") - (set_attr "type" "adc_reg") + [(set_attr "type" "adc_reg") (set_attr "mode" "<MODE>")] ) @@ -2152,8 +1907,7 @@ (match_operand:SI 1 "register_operand" "r"))))] "" "ngc\\t%w0, %w1" - [(set_attr "v8type" "adc") - (set_attr "type" "adc_reg") + [(set_attr "type" "adc_reg") (set_attr "mode" "SI")] ) @@ -2165,8 +1919,7 @@ (neg:GPI (match_dup 1)))] "" "negs\\t%<w>0, %<w>1" - [(set_attr "v8type" "alus") - (set_attr "type" "alus_reg") + [(set_attr "type" "alus_reg") (set_attr "mode" "<MODE>")] ) @@ -2179,8 +1932,7 @@ (zero_extend:DI (neg:SI (match_dup 1))))] "" "negs\\t%w0, %w1" - [(set_attr "v8type" "alus") - (set_attr "type" "alus_reg") + [(set_attr "type" "alus_reg") (set_attr "mode" "SI")] ) @@ -2195,8 +1947,7 @@ (neg:GPI (ASHIFT:GPI (match_dup 1) (match_dup 2))))] "" "negs\\t%<w>0, %<w>1, <shift> %2" - [(set_attr "v8type" "alus_shift") - (set_attr "type" "alus_shift_imm") + [(set_attr "type" "alus_shift_imm") (set_attr "mode" "<MODE>")] ) @@ -2207,8 +1958,7 @@ (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))))] "" "neg\\t%<w>0, %<w>1, <shift> %2" - [(set_attr "v8type" "alu_shift") - (set_attr "type" "alu_shift_imm") + [(set_attr "type" "alu_shift_imm") (set_attr "mode" "<MODE>")] ) @@ -2221,8 +1971,7 @@ (match_operand:QI 2 "aarch64_shift_imm_si" "n")))))] "" "neg\\t%w0, %w1, <shift> %2" - [(set_attr "v8type" "alu_shift") - (set_attr "type" "alu_shift_imm") + [(set_attr "type" "alu_shift_imm") (set_attr "mode" "SI")] ) @@ -2233,8 +1982,7 @@ (match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))))] "" "neg\\t%<w>0, %<w>1, lsl %p2" - [(set_attr "v8type" "alu_shift") - (set_attr "type" "alu_shift_imm") + [(set_attr "type" "alu_shift_imm") (set_attr "mode" "<MODE>")] ) @@ -2247,8 +1995,7 @@ (match_operand:QI 2 "aarch64_pwr_2_si" "n")))))] "" "neg\\t%w0, %w1, lsl %p2" - [(set_attr "v8type" "alu_shift") - (set_attr "type" "alu_shift_imm") + [(set_attr "type" "alu_shift_imm") (set_attr "mode" "SI")] ) @@ -2258,8 +2005,7 @@ (match_operand:GPI 2 "register_operand" "r")))] "" "mul\\t%<w>0, %<w>1, %<w>2" - [(set_attr "v8type" "mult") - (set_attr "type" "mul") + [(set_attr "type" "mul") (set_attr "mode" "<MODE>")] ) @@ -2271,8 +2017,7 @@ (match_operand:SI 2 "register_operand" "r"))))] "" "mul\\t%w0, %w1, %w2" - [(set_attr "v8type" "mult") - (set_attr "type" "mul") + [(set_attr "type" "mul") (set_attr "mode" "SI")] ) @@ -2283,8 +2028,7 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "madd\\t%<w>0, %<w>1, %<w>2, %<w>3" - [(set_attr "v8type" "madd") - (set_attr "type" "mla") + [(set_attr "type" "mla") (set_attr "mode" "<MODE>")] ) @@ -2297,8 +2041,7 @@ (match_operand:SI 3 "register_operand" "r"))))] "" "madd\\t%w0, %w1, %w2, %w3" - [(set_attr "v8type" "madd") - (set_attr "type" "mla") + [(set_attr "type" "mla") (set_attr "mode" "SI")] ) @@ -2310,8 +2053,7 @@ "" "msub\\t%<w>0, %<w>1, %<w>2, %<w>3" - [(set_attr "v8type" "madd") - (set_attr "type" "mla") + [(set_attr "type" "mla") (set_attr "mode" "<MODE>")] ) @@ -2325,8 +2067,7 @@ "" "msub\\t%w0, %w1, %w2, %w3" - [(set_attr "v8type" "madd") - (set_attr "type" "mla") + [(set_attr "type" "mla") (set_attr "mode" "SI")] ) @@ -2337,8 +2078,7 @@ "" "mneg\\t%<w>0, %<w>1, %<w>2" - [(set_attr "v8type" "mult") - (set_attr "type" "mul") + [(set_attr "type" "mul") (set_attr "mode" "<MODE>")] ) @@ -2351,8 +2091,7 @@ "" "mneg\\t%w0, %w1, %w2" - [(set_attr "v8type" "mult") - (set_attr "type" "mul") + [(set_attr "type" "mul") (set_attr "mode" "SI")] ) @@ -2362,8 +2101,7 @@ (ANY_EXTEND:DI (match_operand:SI 2 "register_operand" "r"))))] "" "<su>mull\\t%0, %w1, %w2" - [(set_attr "v8type" "mull") - (set_attr "type" "<su>mull") + [(set_attr "type" "<su>mull") (set_attr "mode" "DI")] ) @@ -2375,8 +2113,7 @@ (match_operand:DI 3 "register_operand" "r")))] "" "<su>maddl\\t%0, %w1, %w2, %3" - [(set_attr "v8type" "maddl") - (set_attr "type" "<su>mlal") + [(set_attr "type" "<su>mlal") (set_attr "mode" "DI")] ) @@ -2389,8 +2126,7 @@ (match_operand:SI 2 "register_operand" "r")))))] "" "<su>msubl\\t%0, %w1, %w2, %3" - [(set_attr "v8type" "maddl") - (set_attr "type" "<su>mlal") + [(set_attr "type" "<su>mlal") (set_attr "mode" "DI")] ) @@ -2401,8 +2137,7 @@ (ANY_EXTEND:DI (match_operand:SI 2 "register_operand" "r"))))] "" "<su>mnegl\\t%0, %w1, %w2" - [(set_attr "v8type" "mull") - (set_attr "type" "<su>mull") + [(set_attr "type" "<su>mull") (set_attr "mode" "DI")] ) @@ -2416,8 +2151,7 @@ (const_int 64))))] "" "<su>mulh\\t%0, %1, %2" - [(set_attr "v8type" "mulh") - (set_attr "type" "<su>mull") + [(set_attr "type" "<su>mull") (set_attr "mode" "DI")] ) @@ -2427,8 +2161,7 @@ (match_operand:GPI 2 "register_operand" "r")))] "" "<su>div\\t%<w>0, %<w>1, %<w>2" - [(set_attr "v8type" "<su>div") - (set_attr "type" "<su>div") + [(set_attr "type" "<su>div") (set_attr "mode" "<MODE>")] ) @@ -2440,8 +2173,7 @@ (match_operand:SI 2 "register_operand" "r"))))] "" "<su>div\\t%w0, %w1, %w2" - [(set_attr "v8type" "<su>div") - (set_attr "type" "<su>div") + [(set_attr "type" "<su>div") (set_attr "mode" "SI")] ) @@ -2458,8 +2190,7 @@ cmp\\t%<w>0, %<w>1 cmp\\t%<w>0, %<w>1 cmn\\t%<w>0, #%n1" - [(set_attr "v8type" "alus") - (set_attr "type" "alus_reg,alus_imm,alus_imm") + [(set_attr "type" "alus_reg,alus_imm,alus_imm") (set_attr "mode" "<MODE>")] ) @@ -2471,8 +2202,7 @@ "@ fcmp\\t%<s>0, #0.0 fcmp\\t%<s>0, %<s>1" - [(set_attr "v8type" "fcmp") - (set_attr "type" "fcmp<s>") + [(set_attr "type" "fcmp<s>") (set_attr "mode" "<MODE>")] ) @@ -2484,8 +2214,7 @@ "@ fcmpe\\t%<s>0, #0.0 fcmpe\\t%<s>0, %<s>1" - [(set_attr "v8type" "fcmp") - (set_attr "type" "fcmp<s>") + [(set_attr "type" "fcmp<s>") (set_attr "mode" "<MODE>")] ) @@ -2497,8 +2226,7 @@ (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")))] "" "cmp\\t%<w>2, %<w>0, <shift> %1" - [(set_attr "v8type" "alus_shift") - (set_attr "type" "alus_shift_imm") + [(set_attr "type" "alus_shift_imm") (set_attr "mode" "<MODE>")] ) @@ -2509,8 +2237,7 @@ (match_operand:GPI 1 "register_operand" "r")))] "" "cmp\\t%<GPI:w>1, %<GPI:w>0, <su>xt<ALLX:size>" - [(set_attr "v8type" "alus_ext") - (set_attr "type" "alus_ext") + [(set_attr "type" "alus_ext") (set_attr "mode" "<GPI:MODE>")] ) @@ -2523,8 +2250,7 @@ (match_operand:GPI 2 "register_operand" "r")))] "" "cmp\\t%<GPI:w>2, %<GPI:w>0, <su>xt<ALLX:size> %1" - [(set_attr "v8type" "alus_ext") - (set_attr "type" "alus_ext") + [(set_attr "type" "alus_ext") (set_attr "mode" "<GPI:MODE>")] ) @@ -2564,8 +2290,7 @@ [(match_operand 2 "cc_register" "") (const_int 0)]))] "" "cset\\t%<w>0, %m1" - [(set_attr "v8type" "csel") - (set_attr "type" "csel") + [(set_attr "type" "csel") (set_attr "mode" "<MODE>")] ) @@ -2577,8 +2302,7 @@ [(match_operand 2 "cc_register" "") (const_int 0)])))] "" "cset\\t%w0, %m1" - [(set_attr "v8type" "csel") - (set_attr "type" "csel") + [(set_attr "type" "csel") (set_attr "mode" "SI")] ) @@ -2588,8 +2312,7 @@ [(match_operand 2 "cc_register" "") (const_int 0)])))] "" "csetm\\t%<w>0, %m1" - [(set_attr "v8type" "csel") - (set_attr "type" "csel") + [(set_attr "type" "csel") (set_attr "mode" "<MODE>")] ) @@ -2601,8 +2324,7 @@ [(match_operand 2 "cc_register" "") (const_int 0)]))))] "" "csetm\\t%w0, %m1" - [(set_attr "v8type" "csel") - (set_attr "type" "csel") + [(set_attr "type" "csel") (set_attr "mode" "SI")] ) @@ -2656,8 +2378,7 @@ csinc\\t%<w>0, %<w>4, <w>zr, %M1 mov\\t%<w>0, -1 mov\\t%<w>0, 1" - [(set_attr "v8type" "csel") - (set_attr "type" "csel") + [(set_attr "type" "csel") (set_attr "mode" "<MODE>")] ) @@ -2681,8 +2402,7 @@ csinc\\t%w0, %w4, wzr, %M1 mov\\t%w0, -1 mov\\t%w0, 1" - [(set_attr "v8type" "csel") - (set_attr "type" "csel") + [(set_attr "type" "csel") (set_attr "mode" "SI")] ) @@ -2695,8 +2415,7 @@ (match_operand:GPF 4 "register_operand" "w")))] "TARGET_FLOAT" "fcsel\\t%<s>0, %<s>3, %<s>4, %m1" - [(set_attr "v8type" "fcsel") - (set_attr "type" "fcsel") + [(set_attr "type" "fcsel") (set_attr "mode" "<MODE>")] ) @@ -2745,8 +2464,7 @@ (match_operand:GPI 1 "register_operand" "r")))] "" "csinc\\t%<w>0, %<w>1, %<w>1, %M2" - [(set_attr "v8type" "csel") - (set_attr "type" "csel") + [(set_attr "type" "csel") (set_attr "mode" "<MODE>")]) (define_insn "csinc3<mode>_insn" @@ -2759,8 +2477,7 @@ (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))] "" "csinc\\t%<w>0, %<w>4, %<w>3, %M1" - [(set_attr "v8type" "csel") - (set_attr "type" "csel") + [(set_attr "type" "csel") (set_attr "mode" "<MODE>")] ) @@ -2773,8 +2490,7 @@ (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))] "" "csinv\\t%<w>0, %<w>4, %<w>3, %M1" - [(set_attr "v8type" "csel") - (set_attr "type" "csel") + [(set_attr "type" "csel") (set_attr "mode" "<MODE>")]) (define_insn "*csneg3<mode>_insn" @@ -2786,8 +2502,7 @@ (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))] "" "csneg\\t%<w>0, %<w>4, %<w>3, %M1" - [(set_attr "v8type" "csel") - (set_attr "type" "csel") + [(set_attr "type" "csel") (set_attr "mode" "<MODE>")]) ;; ------------------------------------------------------------------- @@ -2800,8 +2515,7 @@ (match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>")))] "" "<logical>\\t%<w>0, %<w>1, %<w>2" - [(set_attr "v8type" "logic,logic_imm") - (set_attr "type" "logic_reg,logic_imm") + [(set_attr "type" "logic_reg,logic_imm") (set_attr "mode" "<MODE>")]) ;; zero_extend version of above @@ -2812,8 +2526,7 @@ (match_operand:SI 2 "aarch64_logical_operand" "r,K"))))] "" "<logical>\\t%w0, %w1, %w2" - [(set_attr "v8type" "logic,logic_imm") - (set_attr "type" "logic_reg,logic_imm") + [(set_attr "type" "logic_reg,logic_imm") (set_attr "mode" "SI")]) (define_insn "*and<mode>3_compare0" @@ -2826,8 +2539,7 @@ (and:GPI (match_dup 1) (match_dup 2)))] "" "ands\\t%<w>0, %<w>1, %<w>2" - [(set_attr "v8type" "logics,logics_imm") - (set_attr "type" "logics_reg,logics_imm") + [(set_attr "type" "logics_reg,logics_imm") (set_attr "mode" "<MODE>")] ) @@ -2842,8 +2554,7 @@ (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))] "" "ands\\t%w0, %w1, %w2" - [(set_attr "v8type" "logics,logics_imm") - (set_attr "type" "logics_reg,logics_imm") + [(set_attr "type" "logics_reg,logics_imm") (set_attr "mode" "SI")] ) @@ -2859,8 +2570,7 @@ (and:GPI (SHIFT:GPI (match_dup 1) (match_dup 2)) (match_dup 3)))] "" "ands\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2" - [(set_attr "v8type" "logics_shift") - (set_attr "type" "logics_shift_imm") + [(set_attr "type" "logics_shift_imm") (set_attr "mode" "<MODE>")] ) @@ -2878,8 +2588,7 @@ (match_dup 3))))] "" "ands\\t%w0, %w3, %w1, <SHIFT:shift> %2" - [(set_attr "v8type" "logics_shift") - (set_attr "type" "logics_shift_imm") + [(set_attr "type" "logics_shift_imm") (set_attr "mode" "SI")] ) @@ -2891,8 +2600,7 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "<LOGICAL:logical>\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2" - [(set_attr "v8type" "logic_shift") - (set_attr "type" "logic_shift_imm") + [(set_attr "type" "logic_shift_imm") (set_attr "mode" "<MODE>")]) ;; zero_extend version of above @@ -2905,8 +2613,7 @@ (match_operand:SI 3 "register_operand" "r"))))] "" "<LOGICAL:logical>\\t%w0, %w3, %w1, <SHIFT:shift> %2" - [(set_attr "v8type" "logic_shift") - (set_attr "type" "logic_shift_imm") + [(set_attr "type" "logic_shift_imm") (set_attr "mode" "SI")]) (define_insn "one_cmpl<mode>2" @@ -2914,8 +2621,7 @@ (not:GPI (match_operand:GPI 1 "register_operand" "r")))] "" "mvn\\t%<w>0, %<w>1" - [(set_attr "v8type" "logic") - (set_attr "type" "logic_reg") + [(set_attr "type" "logic_reg") (set_attr "mode" "<MODE>")]) (define_insn "*one_cmpl_<optab><mode>2" @@ -2924,8 +2630,7 @@ (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))))] "" "mvn\\t%<w>0, %<w>1, <shift> %2" - [(set_attr "v8type" "logic_shift") - (set_attr "type" "logic_shift_imm") + [(set_attr "type" "logic_shift_imm") (set_attr "mode" "<MODE>")]) (define_insn "*<LOGICAL:optab>_one_cmpl<mode>3" @@ -2935,8 +2640,7 @@ (match_operand:GPI 2 "register_operand" "r")))] "" "<LOGICAL:nlogical>\\t%<w>0, %<w>2, %<w>1" - [(set_attr "v8type" "logic") - (set_attr "type" "logic_reg") + [(set_attr "type" "logic_reg") (set_attr "mode" "<MODE>")]) (define_insn "*and_one_cmpl<mode>3_compare0" @@ -2950,8 +2654,7 @@ (and:GPI (not:GPI (match_dup 1)) (match_dup 2)))] "" "bics\\t%<w>0, %<w>2, %<w>1" - [(set_attr "v8type" "logics") - (set_attr "type" "logics_reg") + [(set_attr "type" "logics_reg") (set_attr "mode" "<MODE>")]) ;; zero_extend version of above @@ -2966,8 +2669,7 @@ (zero_extend:DI (and:SI (not:SI (match_dup 1)) (match_dup 2))))] "" "bics\\t%w0, %w2, %w1" - [(set_attr "v8type" "logics") - (set_attr "type" "logics_reg") + [(set_attr "type" "logics_reg") (set_attr "mode" "SI")]) (define_insn "*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3" @@ -2979,8 +2681,7 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "<LOGICAL:nlogical>\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2" - [(set_attr "v8type" "logic_shift") - (set_attr "type" "logics_shift_imm") + [(set_attr "type" "logics_shift_imm") (set_attr "mode" "<MODE>")]) (define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0" @@ -2998,8 +2699,7 @@ (match_dup 1) (match_dup 2))) (match_dup 3)))] "" "bics\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2" - [(set_attr "v8type" "logics_shift") - (set_attr "type" "logics_shift_imm") + [(set_attr "type" "logics_shift_imm") (set_attr "mode" "<MODE>")]) ;; zero_extend version of above @@ -3018,8 +2718,7 @@ (SHIFT:SI (match_dup 1) (match_dup 2))) (match_dup 3))))] "" "bics\\t%w0, %w3, %w1, <SHIFT:shift> %2" - [(set_attr "v8type" "logics_shift") - (set_attr "type" "logics_shift_imm") + [(set_attr "type" "logics_shift_imm") (set_attr "mode" "SI")]) (define_insn "clz<mode>2" @@ -3027,8 +2726,7 @@ (clz:GPI (match_operand:GPI 1 "register_operand" "r")))] "" "clz\\t%<w>0, %<w>1" - [(set_attr "v8type" "clz") - (set_attr "type" "clz") + [(set_attr "type" "clz") (set_attr "mode" "<MODE>")]) (define_expand "ffs<mode>2" @@ -3051,8 +2749,7 @@ (unspec:GPI [(match_operand:GPI 1 "register_operand" "r")] UNSPEC_CLS))] "" "cls\\t%<w>0, %<w>1" - [(set_attr "v8type" "clz") - (set_attr "type" "clz") + [(set_attr "type" "clz") (set_attr "mode" "<MODE>")]) (define_insn "rbit<mode>2" @@ -3060,8 +2757,7 @@ (unspec:GPI [(match_operand:GPI 1 "register_operand" "r")] UNSPEC_RBIT))] "" "rbit\\t%<w>0, %<w>1" - [(set_attr "v8type" "rbit") - (set_attr "type" "rbit") + [(set_attr "type" "rbit") (set_attr "mode" "<MODE>")]) (define_expand "ctz<mode>2" @@ -3083,8 +2779,7 @@ (const_int 0)))] "" "tst\\t%<w>0, %<w>1" - [(set_attr "v8type" "logics") - (set_attr "type" "logics_reg") + [(set_attr "type" "logics_reg") (set_attr "mode" "<MODE>")]) (define_insn "*and_<SHIFT:optab><mode>3nr_compare0" @@ -3097,8 +2792,7 @@ (const_int 0)))] "" "tst\\t%<w>2, %<w>0, <SHIFT:shift> %1" - [(set_attr "v8type" "logics_shift") - (set_attr "type" "logics_shift_imm") + [(set_attr "type" "logics_shift_imm") (set_attr "mode" "<MODE>")]) ;; ------------------------------------------------------------------- @@ -3200,7 +2894,6 @@ ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas> lsl\t%<w>0, %<w>1, %<w>2" [(set_attr "simd" "yes,yes,no") - (set_attr "v8type" "*,*,shift") (set_attr "type" "neon_shift_imm<q>, neon_shift_reg<q>,shift_reg") (set_attr "mode" "*,*,<MODE>")] ) @@ -3217,7 +2910,6 @@ # lsr\t%<w>0, %<w>1, %<w>2" [(set_attr "simd" "yes,yes,no") - (set_attr "v8type" "*,*,shift") (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg") (set_attr "mode" "*,*,<MODE>")] ) @@ -3260,7 +2952,6 @@ # asr\t%<w>0, %<w>1, %<w>2" [(set_attr "simd" "yes,yes,no") - (set_attr "v8type" "*,*,shift") (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg") (set_attr "mode" "*,*,<MODE>")] ) @@ -3353,8 +3044,7 @@ (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>")))] "" "ror\\t%<w>0, %<w>1, %<w>2" - [(set_attr "v8type" "shift") - (set_attr "type" "shift_reg") + [(set_attr "type" "shift_reg") (set_attr "mode" "<MODE>")] ) @@ -3366,8 +3056,7 @@ (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss"))))] "" "<shift>\\t%w0, %w1, %w2" - [(set_attr "v8type" "shift") - (set_attr "type" "shift_reg") + [(set_attr "type" "shift_reg") (set_attr "mode" "SI")] ) @@ -3377,8 +3066,7 @@ (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss")))] "" "lsl\\t%<w>0, %<w>1, %<w>2" - [(set_attr "v8type" "shift") - (set_attr "type" "shift_reg") + [(set_attr "type" "shift_reg") (set_attr "mode" "<MODE>")] ) @@ -3391,8 +3079,7 @@ operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2])); return "<bfshift>\t%w0, %w1, %2, %3"; } - [(set_attr "v8type" "bfm") - (set_attr "type" "bfm") + [(set_attr "type" "bfm") (set_attr "mode" "<MODE>")] ) @@ -3405,8 +3092,7 @@ "UINTVAL (operands[3]) < GET_MODE_BITSIZE (<MODE>mode) && (UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (<MODE>mode))" "extr\\t%<w>0, %<w>1, %<w>2, %4" - [(set_attr "v8type" "shift") - (set_attr "type" "shift_imm") + [(set_attr "type" "shift_imm") (set_attr "mode" "<MODE>")] ) @@ -3421,8 +3107,7 @@ "UINTVAL (operands[3]) < 32 && (UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)" "extr\\t%w0, %w1, %w2, %4" - [(set_attr "v8type" "shift") - (set_attr "type" "shift_imm") + [(set_attr "type" "shift_imm") (set_attr "mode" "SI")] ) @@ -3435,8 +3120,7 @@ operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2])); return "ror\\t%<w>0, %<w>1, %3"; } - [(set_attr "v8type" "shift") - (set_attr "type" "shift_imm") + [(set_attr "type" "shift_imm") (set_attr "mode" "<MODE>")] ) @@ -3451,8 +3135,7 @@ operands[3] = GEN_INT (32 - UINTVAL (operands[2])); return "ror\\t%w0, %w1, %3"; } - [(set_attr "v8type" "shift") - (set_attr "type" "shift_imm") + [(set_attr "type" "shift_imm") (set_attr "mode" "SI")] ) @@ -3466,8 +3149,7 @@ operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2])); return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3"; } - [(set_attr "v8type" "bfm") - (set_attr "type" "bfm") + [(set_attr "type" "bfm") (set_attr "mode" "<GPI:MODE>")] ) @@ -3481,8 +3163,7 @@ operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2])); return "ubfx\t%<GPI:w>0, %<GPI:w>1, %2, %3"; } - [(set_attr "v8type" "bfm") - (set_attr "type" "bfm") + [(set_attr "type" "bfm") (set_attr "mode" "<GPI:MODE>")] ) @@ -3496,8 +3177,7 @@ operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2])); return "sbfx\\t%<GPI:w>0, %<GPI:w>1, %2, %3"; } - [(set_attr "v8type" "bfm") - (set_attr "type" "bfm") + [(set_attr "type" "bfm") (set_attr "mode" "<GPI:MODE>")] ) @@ -3521,8 +3201,7 @@ (match_operand 3 "const_int_operand" "n")))] "" "<su>bfx\\t%<w>0, %<w>1, %3, %2" - [(set_attr "v8type" "bfm") - (set_attr "type" "bfm") + [(set_attr "type" "bfm") (set_attr "mode" "<MODE>")] ) @@ -3566,8 +3245,7 @@ || (UINTVAL (operands[2]) + UINTVAL (operands[1]) > GET_MODE_BITSIZE (<MODE>mode)))" "bfi\\t%<w>0, %<w>3, %2, %1" - [(set_attr "v8type" "bfm") - (set_attr "type" "bfm") + [(set_attr "type" "bfm") (set_attr "mode" "<MODE>")] ) @@ -3582,8 +3260,7 @@ || (UINTVAL (operands[3]) + UINTVAL (operands[1]) > GET_MODE_BITSIZE (<MODE>mode)))" "bfxil\\t%<w>0, %<w>2, %3, %1" - [(set_attr "v8type" "bfm") - (set_attr "type" "bfm") + [(set_attr "type" "bfm") (set_attr "mode" "<MODE>")] ) @@ -3599,8 +3276,7 @@ : GEN_INT (<GPI:sizen> - UINTVAL (operands[2])); return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3"; } - [(set_attr "v8type" "bfm") - (set_attr "type" "bfm") + [(set_attr "type" "bfm") (set_attr "mode" "<GPI:MODE>")] ) @@ -3614,8 +3290,7 @@ "exact_log2 ((INTVAL (operands[3]) >> INTVAL (operands[2])) + 1) >= 0 && (INTVAL (operands[3]) & ((1 << INTVAL (operands[2])) - 1)) == 0" "ubfiz\\t%<w>0, %<w>1, %2, %P3" - [(set_attr "v8type" "bfm") - (set_attr "type" "bfm") + [(set_attr "type" "bfm") (set_attr "mode" "<MODE>")] ) @@ -3624,8 +3299,7 @@ (bswap:GPI (match_operand:GPI 1 "register_operand" "r")))] "" "rev\\t%<w>0, %<w>1" - [(set_attr "v8type" "rev") - (set_attr "type" "rev") + [(set_attr "type" "rev") (set_attr "mode" "<MODE>")] ) @@ -3634,8 +3308,7 @@ (bswap:HI (match_operand:HI 1 "register_operand" "r")))] "" "rev16\\t%w0, %w1" - [(set_attr "v8type" "rev") - (set_attr "type" "rev") + [(set_attr "type" "rev") (set_attr "mode" "HI")] ) @@ -3645,8 +3318,7 @@ (zero_extend:DI (bswap:SI (match_operand:SI 1 "register_operand" "r"))))] "" "rev\\t%w0, %w1" - [(set_attr "v8type" "rev") - (set_attr "type" "rev") + [(set_attr "type" "rev") (set_attr "mode" "SI")] ) @@ -3663,8 +3335,7 @@ FRINT))] "TARGET_FLOAT" "frint<frint_suffix>\\t%<s>0, %<s>1" - [(set_attr "v8type" "frint") - (set_attr "type" "f_rint<s>") + [(set_attr "type" "f_rint<s>") (set_attr "mode" "<MODE>")] ) @@ -3676,8 +3347,7 @@ FCVT)))] "TARGET_FLOAT" "fcvt<frint_suffix><su>\\t%<GPI:w>0, %<GPF:s>1" - [(set_attr "v8type" "fcvtf2i") - (set_attr "type" "f_cvtf2i") + [(set_attr "type" "f_cvtf2i") (set_attr "mode" "<GPF:MODE>") (set_attr "mode2" "<GPI:MODE>")] ) @@ -3691,8 +3361,7 @@ (match_operand:GPF 3 "register_operand" "w")))] "TARGET_FLOAT" "fmadd\\t%<s>0, %<s>1, %<s>2, %<s>3" - [(set_attr "v8type" "fmadd") - (set_attr "type" "fmac<s>") + [(set_attr "type" "fmac<s>") (set_attr "mode" "<MODE>")] ) @@ -3703,8 +3372,7 @@ (match_operand:GPF 3 "register_operand" "w")))] "TARGET_FLOAT" "fmsub\\t%<s>0, %<s>1, %<s>2, %<s>3" - [(set_attr "v8type" "fmadd") - (set_attr "type" "fmac<s>") + [(set_attr "type" "fmac<s>") (set_attr "mode" "<MODE>")] ) @@ -3715,8 +3383,7 @@ (neg:GPF (match_operand:GPF 3 "register_operand" "w"))))] "TARGET_FLOAT" "fnmsub\\t%<s>0, %<s>1, %<s>2, %<s>3" - [(set_attr "v8type" "fmadd") - (set_attr "type" "fmac<s>") + [(set_attr "type" "fmac<s>") (set_attr "mode" "<MODE>")] ) @@ -3727,8 +3394,7 @@ (neg:GPF (match_operand:GPF 3 "register_operand" "w"))))] "TARGET_FLOAT" "fnmadd\\t%<s>0, %<s>1, %<s>2, %<s>3" - [(set_attr "v8type" "fmadd") - (set_attr "type" "fmac<s>") + [(set_attr "type" "fmac<s>") (set_attr "mode" "<MODE>")] ) @@ -3740,8 +3406,7 @@ (match_operand:GPF 3 "register_operand" "w"))))] "!HONOR_SIGNED_ZEROS (<MODE>mode) && TARGET_FLOAT" "fnmadd\\t%<s>0, %<s>1, %<s>2, %<s>3" - [(set_attr "v8type" "fmadd") - (set_attr "type" "fmac<s>") + [(set_attr "type" "fmac<s>") (set_attr "mode" "<MODE>")] ) @@ -3754,8 +3419,7 @@ (float_extend:DF (match_operand:SF 1 "register_operand" "w")))] "TARGET_FLOAT" "fcvt\\t%d0, %s1" - [(set_attr "v8type" "fcvt") - (set_attr "type" "f_cvt") + [(set_attr "type" "f_cvt") (set_attr "mode" "DF") (set_attr "mode2" "SF")] ) @@ -3765,8 +3429,7 @@ (float_truncate:SF (match_operand:DF 1 "register_operand" "w")))] "TARGET_FLOAT" "fcvt\\t%s0, %d1" - [(set_attr "v8type" "fcvt") - (set_attr "type" "f_cvt") + [(set_attr "type" "f_cvt") (set_attr "mode" "SF") (set_attr "mode2" "DF")] ) @@ -3776,8 +3439,7 @@ (fix:GPI (match_operand:GPF 1 "register_operand" "w")))] "TARGET_FLOAT" "fcvtzs\\t%<GPI:w>0, %<GPF:s>1" - [(set_attr "v8type" "fcvtf2i") - (set_attr "type" "f_cvtf2i") + [(set_attr "type" "f_cvtf2i") (set_attr "mode" "<GPF:MODE>") (set_attr "mode2" "<GPI:MODE>")] ) @@ -3787,8 +3449,7 @@ (unsigned_fix:GPI (match_operand:GPF 1 "register_operand" "w")))] "TARGET_FLOAT" "fcvtzu\\t%<GPI:w>0, %<GPF:s>1" - [(set_attr "v8type" "fcvtf2i") - (set_attr "type" "f_cvtf2i") + [(set_attr "type" "f_cvtf2i") (set_attr "mode" "<GPF:MODE>") (set_attr "mode2" "<GPI:MODE>")] ) @@ -3798,8 +3459,7 @@ (float:GPF (match_operand:GPI 1 "register_operand" "r")))] "TARGET_FLOAT" "scvtf\\t%<GPF:s>0, %<GPI:w>1" - [(set_attr "v8type" "fcvti2f") - (set_attr "type" "f_cvti2f") + [(set_attr "type" "f_cvti2f") (set_attr "mode" "<GPF:MODE>") (set_attr "mode2" "<GPI:MODE>")] ) @@ -3809,8 +3469,7 @@ (unsigned_float:GPF (match_operand:GPI 1 "register_operand" "r")))] "TARGET_FLOAT" "ucvtf\\t%<GPF:s>0, %<GPI:w>1" - [(set_attr "v8type" "fcvt") - (set_attr "type" "f_cvt") + [(set_attr "type" "f_cvt") (set_attr "mode" "<GPF:MODE>") (set_attr "mode2" "<GPI:MODE>")] ) @@ -3826,8 +3485,7 @@ (match_operand:GPF 2 "register_operand" "w")))] "TARGET_FLOAT" "fadd\\t%<s>0, %<s>1, %<s>2" - [(set_attr "v8type" "fadd") - (set_attr "type" "fadd<s>") + [(set_attr "type" "fadd<s>") (set_attr "mode" "<MODE>")] ) @@ -3838,8 +3496,7 @@ (match_operand:GPF 2 "register_operand" "w")))] "TARGET_FLOAT" "fsub\\t%<s>0, %<s>1, %<s>2" - [(set_attr "v8type" "fadd") - (set_attr "type" "fadd<s>") + [(set_attr "type" "fadd<s>") (set_attr "mode" "<MODE>")] ) @@ -3850,8 +3507,7 @@ (match_operand:GPF 2 "register_operand" "w")))] "TARGET_FLOAT" "fmul\\t%<s>0, %<s>1, %<s>2" - [(set_attr "v8type" "fmul") - (set_attr "type" "fmul<s>") + [(set_attr "type" "fmul<s>") (set_attr "mode" "<MODE>")] ) @@ -3862,8 +3518,7 @@ (match_operand:GPF 2 "register_operand" "w")))] "TARGET_FLOAT" "fnmul\\t%<s>0, %<s>1, %<s>2" - [(set_attr "v8type" "fmul") - (set_attr "type" "fmul<s>") + [(set_attr "type" "fmul<s>") (set_attr "mode" "<MODE>")] ) @@ -3874,8 +3529,7 @@ (match_operand:GPF 2 "register_operand" "w")))] "TARGET_FLOAT" "fdiv\\t%<s>0, %<s>1, %<s>2" - [(set_attr "v8type" "fdiv") - (set_attr "type" "fdiv<s>") + [(set_attr "type" "fdiv<s>") (set_attr "mode" "<MODE>")] ) @@ -3884,8 +3538,7 @@ (neg:GPF (match_operand:GPF 1 "register_operand" "w")))] "TARGET_FLOAT" "fneg\\t%<s>0, %<s>1" - [(set_attr "v8type" "ffarith") - (set_attr "type" "ffarith<s>") + [(set_attr "type" "ffarith<s>") (set_attr "mode" "<MODE>")] ) @@ -3894,8 +3547,7 @@ (sqrt:GPF (match_operand:GPF 1 "register_operand" "w")))] "TARGET_FLOAT" "fsqrt\\t%<s>0, %<s>1" - [(set_attr "v8type" "fsqrt") - (set_attr "type" "fsqrt<s>") + [(set_attr "type" "fsqrt<s>") (set_attr "mode" "<MODE>")] ) @@ -3904,8 +3556,7 @@ (abs:GPF (match_operand:GPF 1 "register_operand" "w")))] "TARGET_FLOAT" "fabs\\t%<s>0, %<s>1" - [(set_attr "v8type" "ffarith") - (set_attr "type" "ffarith<s>") + [(set_attr "type" "ffarith<s>") (set_attr "mode" "<MODE>")] ) @@ -3919,8 +3570,7 @@ (match_operand:GPF 2 "register_operand" "w")))] "TARGET_FLOAT" "fmaxnm\\t%<s>0, %<s>1, %<s>2" - [(set_attr "v8type" "fminmax") - (set_attr "type" "f_minmax<s>") + [(set_attr "type" "f_minmax<s>") (set_attr "mode" "<MODE>")] ) @@ -3930,8 +3580,7 @@ (match_operand:GPF 2 "register_operand" "w")))] "TARGET_FLOAT" "fminnm\\t%<s>0, %<s>1, %<s>2" - [(set_attr "v8type" "fminmax") - (set_attr "type" "f_minmax<s>") + [(set_attr "type" "f_minmax<s>") (set_attr "mode" "<MODE>")] ) @@ -3958,14 +3607,13 @@ ;; The following secondary reload helpers patterns are invoked ;; after or during reload as we don't want these patterns to start ;; kicking in during the combiner. - + (define_insn "aarch64_movdi_<mode>low" [(set (match_operand:DI 0 "register_operand" "=r") (truncate:DI (match_operand:TX 1 "register_operand" "w")))] "reload_completed || reload_in_progress" "fmov\\t%x0, %d1" - [(set_attr "v8type" "fmovf2i") - (set_attr "type" "f_mrc") + [(set_attr "type" "f_mrc") (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -3977,8 +3625,7 @@ (const_int 64))))] "reload_completed || reload_in_progress" "fmov\\t%x0, %1.d[1]" - [(set_attr "v8type" "fmovf2i") - (set_attr "type" "f_mrc") + [(set_attr "type" "f_mrc") (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -3989,8 +3636,7 @@ (zero_extend:TX (match_operand:DI 1 "register_operand" "r")))] "reload_completed || reload_in_progress" "fmov\\t%0.d[1], %x1" - [(set_attr "v8type" "fmovi2f") - (set_attr "type" "f_mcr") + [(set_attr "type" "f_mcr") (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -4000,8 +3646,7 @@ (zero_extend:TX (match_operand:DI 1 "register_operand" "r")))] "reload_completed || reload_in_progress" "fmov\\t%d0, %x1" - [(set_attr "v8type" "fmovi2f") - (set_attr "type" "f_mcr") + [(set_attr "type" "f_mcr") (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -4012,8 +3657,7 @@ (truncate:DI (match_operand:TI 1 "register_operand" "w"))))] "reload_completed || reload_in_progress" "fmov\\t%d0, %d1" - [(set_attr "v8type" "fmovi2f") - (set_attr "type" "f_mcr") + [(set_attr "type" "f_mcr") (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -4045,8 +3689,7 @@ (match_operand 2 "aarch64_valid_symref" "S")))] "" "add\\t%<w>0, %<w>1, :lo12:%a2" - [(set_attr "v8type" "alu") - (set_attr "type" "alu_reg") + [(set_attr "type" "alu_reg") (set_attr "mode" "<MODE>")] ) @@ -4058,8 +3701,7 @@ UNSPEC_GOTSMALLPIC))] "" "ldr\\t%<w>0, [%1, #:got_lo12:%a2]" - [(set_attr "v8type" "load1") - (set_attr "type" "load1") + [(set_attr "type" "load1") (set_attr "mode" "<MODE>")] ) @@ -4072,8 +3714,7 @@ UNSPEC_GOTSMALLPIC)))] "TARGET_ILP32" "ldr\\t%w0, [%1, #:got_lo12:%a2]" - [(set_attr "v8type" "load1") - (set_attr "type" "load1") + [(set_attr "type" "load1") (set_attr "mode" "DI")] ) @@ -4083,8 +3724,7 @@ UNSPEC_GOTTINYPIC))] "" "ldr\\t%0, %L1" - [(set_attr "v8type" "load1") - (set_attr "type" "load1") + [(set_attr "type" "load1") (set_attr "mode" "DI")] ) @@ -4093,8 +3733,7 @@ (unspec:DI [(const_int 0)] UNSPEC_TLS))] "" "mrs\\t%0, tpidr_el0" - [(set_attr "v8type" "mrs") - (set_attr "type" "mrs") + [(set_attr "type" "mrs") (set_attr "mode" "DI")] ) @@ -4119,8 +3758,7 @@ ] "" "adrp\\tx0, %A1\;add\\tx0, x0, %L1\;bl\\t%2\;nop" - [(set_attr "v8type" "call") - (set_attr "type" "call") + [(set_attr "type" "call") (set_attr "length" "16")]) (define_insn "tlsie_small" @@ -4129,8 +3767,7 @@ UNSPEC_GOTSMALLTLS))] "" "adrp\\t%0, %A1\;ldr\\t%0, [%0, #%L1]" - [(set_attr "v8type" "load1") - (set_attr "type" "load1") + [(set_attr "type" "load1") (set_attr "mode" "DI") (set_attr "length" "8")] ) @@ -4142,8 +3779,7 @@ UNSPEC_GOTSMALLTLS))] "" "add\\t%0, %1, #%G2\;add\\t%0, %0, #%L2" - [(set_attr "v8type" "alu") - (set_attr "type" "alu_reg") + [(set_attr "type" "alu_reg") (set_attr "mode" "DI") (set_attr "length" "8")] ) @@ -4156,8 +3792,7 @@ (clobber (match_scratch:DI 1 "=r"))] "TARGET_TLS_DESC" "adrp\\tx0, %A0\;ldr\\t%1, [x0, #%L0]\;add\\tx0, x0, %L0\;.tlsdesccall\\t%0\;blr\\t%1" - [(set_attr "v8type" "call") - (set_attr "type" "call") + [(set_attr "type" "call") (set_attr "length" "16")]) (define_insn "stack_tie" diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index e710b0c3717..c55835e7fe1 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -25,6 +25,9 @@ along with GCC; see the file COPYING3. If not see #include "tm.h" #include "rtl.h" #include "tree.h" +#include "stor-layout.h" +#include "calls.h" +#include "varasm.h" #include "regs.h" #include "hard-reg-set.h" #include "insn-config.h" @@ -51,6 +54,7 @@ along with GCC; see the file COPYING3. If not see #include "gimple.h" #include "gimplify.h" #include "gimple-ssa.h" +#include "stringpool.h" #include "tree-ssanames.h" #include "tree-stdarg.h" #include "tm-constrs.h" @@ -4831,7 +4835,8 @@ alpha_gp_save_rtx (void) label. Emit the sequence properly on the edge. We are only invoked from dw2_build_landing_pads and finish_eh_generation will call commit_edge_insertions thanks to a kludge. */ - insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR)); + insert_insn_on_edge (seq, + single_succ_edge (ENTRY_BLOCK_PTR_FOR_FN (cfun))); cfun->machine->gp_save_rtx = m; } diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index e9a0d24b973..5ad807e996e 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -34,6 +34,10 @@ along with GCC; see the file COPYING3. If not see #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "varasm.h" +#include "stor-layout.h" +#include "stringpool.h" +#include "calls.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h index 841f544e83d..c3652a72c81 100644 --- a/gcc/config/arm/aarch-common-protos.h +++ b/gcc/config/arm/aarch-common-protos.h @@ -31,6 +31,7 @@ extern int arm_no_early_alu_shift_dep (rtx, rtx); extern int arm_no_early_alu_shift_value_dep (rtx, rtx); extern int arm_no_early_mul_dep (rtx, rtx); extern int arm_no_early_store_addr_dep (rtx, rtx); +extern bool arm_rtx_shift_left_p (rtx); /* RTX cost table definitions. These are used when tuning for speed rather than for size and should reflect the _additional_ cost over the cost diff --git a/gcc/config/arm/aarch-common.c b/gcc/config/arm/aarch-common.c index 201e581a4a6..a46e6751a7b 100644 --- a/gcc/config/arm/aarch-common.c +++ b/gcc/config/arm/aarch-common.c @@ -40,7 +40,7 @@ typedef struct /* Return TRUE if X is either an arithmetic shift left, or is a multiplication by a power of two. */ -static bool +bool arm_rtx_shift_left_p (rtx x) { enum rtx_code code = GET_CODE (x); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 8957309ad1d..12934233a48 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -27,6 +27,10 @@ #include "tm.h" #include "rtl.h" #include "tree.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "calls.h" +#include "varasm.h" #include "obstack.h" #include "regs.h" #include "hard-reg-set.h" @@ -2449,6 +2453,10 @@ arm_option_override (void) arm_pic_register = pic_register; } + if (TARGET_VXWORKS_RTP + && !global_options_set.x_arm_pic_data_is_text_relative) + arm_pic_data_is_text_relative = 0; + /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */ if (fix_cm3_ldrd == 2) { @@ -5929,7 +5937,8 @@ require_pic_register (void) we can't yet emit instructions directly in the final insn stream. Queue the insns on the entry edge, they will be committed after everything else is expanded. */ - insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR)); + insert_insn_on_edge (seq, + single_succ_edge (ENTRY_BLOCK_PTR_FOR_FN (cfun))); } } } @@ -5959,7 +5968,7 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig))) && NEED_GOT_RELOC - && !TARGET_VXWORKS_RTP) + && arm_pic_data_is_text_relative) insn = arm_pic_static_addr (orig, reg); else { @@ -8752,6 +8761,30 @@ arm_unspec_cost (rtx x, enum rtx_code /* outer_code */, bool speed_p, int *cost) call (one insn for -Os) and then one for processing the result. */ #define LIBCALL_COST(N) COSTS_N_INSNS (N + (speed_p ? 18 : 2)) +#define HANDLE_NARROW_SHIFT_ARITH(OP, IDX) \ + do \ + { \ + shift_op = shifter_op_p (XEXP (x, IDX), &shift_reg); \ + if (shift_op != NULL \ + && arm_rtx_shift_left_p (XEXP (x, IDX))) \ + { \ + if (shift_reg) \ + { \ + if (speed_p) \ + *cost += extra_cost->alu.arith_shift_reg; \ + *cost += rtx_cost (shift_reg, ASHIFT, 1, speed_p); \ + } \ + else if (speed_p) \ + *cost += extra_cost->alu.arith_shift; \ + \ + *cost += (rtx_cost (shift_op, ASHIFT, 0, speed_p) \ + + rtx_cost (XEXP (x, 1 - IDX), \ + OP, 1, speed_p)); \ + return true; \ + } \ + } \ + while (0); + /* RTX costs. Make an estimate of the cost of executing the operation X, which is contained with an operation with code OUTER_CODE. SPEED_P indicates whether the cost desired is the performance cost, @@ -9108,6 +9141,15 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, if (GET_MODE_CLASS (mode) == MODE_INT && GET_MODE_SIZE (mode) < 4) { + rtx shift_op, shift_reg; + shift_reg = NULL; + + /* We check both sides of the MINUS for shifter operands since, + unlike PLUS, it's not commutative. */ + + HANDLE_NARROW_SHIFT_ARITH (MINUS, 0) + HANDLE_NARROW_SHIFT_ARITH (MINUS, 1) + /* Slightly disparage, as we might need to widen the result. */ *cost = 1 + COSTS_N_INSNS (1); if (speed_p) @@ -9207,11 +9249,18 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, return false; } + /* Narrow modes can be synthesized in SImode, but the range + of useful sub-operations is limited. Check for shift operations + on one of the operands. Only left shifts can be used in the + narrow modes. */ if (GET_MODE_CLASS (mode) == MODE_INT && GET_MODE_SIZE (mode) < 4) { - /* Narrow modes can be synthesized in SImode, but the range - of useful sub-operations is limited. */ + rtx shift_op, shift_reg; + shift_reg = NULL; + + HANDLE_NARROW_SHIFT_ARITH (PLUS, 0) + if (CONST_INT_P (XEXP (x, 1))) { int insns = arm_gen_constant (PLUS, SImode, NULL_RTX, @@ -10330,6 +10379,8 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, } } +#undef HANDLE_NARROW_SHIFT_ARITH + /* RTX costs when optimizing for size. */ static bool arm_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, @@ -18330,7 +18381,8 @@ arm_r3_live_at_start_p (void) /* Just look at cfg info, which is still close enough to correct at this point. This gives false positives for broken functions that might use uninitialized data that happens to be allocated in r3, but who cares? */ - return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 3); + return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR_FOR_FN (cfun)), + 3); } /* Compute the number of bytes used to store the static chain register on the @@ -19863,7 +19915,7 @@ any_sibcall_could_use_r3 (void) if (!crtl->tail_call_emit) return false; - FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) + FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) if (e->flags & EDGE_SIBCALL) { rtx call = BB_END (e->src); @@ -21452,7 +21504,7 @@ arm_assemble_integer (rtx x, unsigned int size, int aligned_p) { /* See legitimize_pic_address for an explanation of the TARGET_VXWORKS_RTP check. */ - if (TARGET_VXWORKS_RTP + if (!arm_pic_data_is_text_relative || (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x))) fputs ("(GOT)", asm_out_file); else diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 1781b75b34b..dbd841ec842 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -568,6 +568,10 @@ extern int prefer_neon_for_64bits; #define NEED_PLT_RELOC 0 #endif +#ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE +#define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 +#endif + /* Nonzero if we need to refer to the GOT with a PC-relative offset. In other words, generate diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 3726201dd4f..a26550a476a 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -5170,7 +5170,8 @@ [(set_attr "length" "8,4,8,8") (set_attr "arch" "neon_for_64bits,*,*,avoid_neon_for_64bits") (set_attr "ce_count" "2") - (set_attr "predicable" "yes")] + (set_attr "predicable" "yes") + (set_attr "type" "multiple,mov_reg,multiple,multiple")] ) (define_insn "extend<mode>di2" diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index 9b740386ca3..fa0839a9e12 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -158,6 +158,10 @@ mlong-calls Target Report Mask(LONG_CALLS) Generate call insns as indirect calls, if necessary +mpic-data-is-text-relative +Target Report Var(arm_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE) +Assume data segments are relative to text segment. + mpic-register= Target RejectNegative Joined Var(arm_pic_register_string) Specify the register to be used for PIC addressing diff --git a/gcc/config/avr/avr-c.c b/gcc/config/avr/avr-c.c index 4e64405a351..2cfb264ad20 100644 --- a/gcc/config/avr/avr-c.c +++ b/gcc/config/avr/avr-c.c @@ -26,6 +26,7 @@ #include "tm_p.h" #include "cpplib.h" #include "tree.h" +#include "stor-layout.h" #include "target.h" #include "c-family/c-common.h" #include "langhooks.h" diff --git a/gcc/config/avr/avr-log.c b/gcc/config/avr/avr-log.c index 87fa14d7006..3d2f54d9707 100644 --- a/gcc/config/avr/avr-log.c +++ b/gcc/config/avr/avr-log.c @@ -24,6 +24,7 @@ #include "tm.h" #include "rtl.h" #include "tree.h" +#include "print-tree.h" #include "output.h" #include "input.h" #include "function.h" diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c index f0383a7b314..f1241f4e0f2 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -32,6 +32,10 @@ #include "flags.h" #include "reload.h" #include "tree.h" +#include "print-tree.h" +#include "calls.h" +#include "stor-layout.h" +#include "stringpool.h" #include "output.h" #include "expr.h" #include "c-family/c-common.h" diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c index 5a9f27dc4cf..88fe426dd43 100644 --- a/gcc/config/bfin/bfin.c +++ b/gcc/config/bfin/bfin.c @@ -32,6 +32,8 @@ #include "output.h" #include "insn-attr.h" #include "tree.h" +#include "varasm.h" +#include "calls.h" #include "flags.h" #include "except.h" #include "function.h" @@ -3597,7 +3599,7 @@ hwloop_optimize (hwloop_info loop) if (single_pred_p (bb) && single_pred_edge (bb)->flags & EDGE_FALLTHRU - && single_pred (bb) != ENTRY_BLOCK_PTR) + && single_pred (bb) != ENTRY_BLOCK_PTR_FOR_FN (cfun)) { bb = single_pred (bb); last_insn = BB_END (bb); diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c index a37e02ff834..af310bac8dc 100644 --- a/gcc/config/c6x/c6x.c +++ b/gcc/config/c6x/c6x.c @@ -25,6 +25,10 @@ #include "tm.h" #include "rtl.h" #include "tree.h" +#include "stor-layout.h" +#include "varasm.h" +#include "calls.h" +#include "stringpool.h" #include "insn-flags.h" #include "output.h" #include "insn-attr.h" diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c index 1ac29cc800a..b3972766d5b 100644 --- a/gcc/config/cr16/cr16.c +++ b/gcc/config/cr16/cr16.c @@ -24,6 +24,8 @@ #include "tm.h" #include "rtl.h" #include "tree.h" +#include "stor-layout.h" +#include "calls.h" #include "tm_p.h" #include "regs.h" #include "hard-reg-set.h" diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c index 7432251b950..2d2a108031d 100644 --- a/gcc/config/cris/cris.c +++ b/gcc/config/cris/cris.c @@ -30,6 +30,10 @@ along with GCC; see the file COPYING3. If not see #include "insn-attr.h" #include "flags.h" #include "tree.h" +#include "varasm.h" +#include "stor-layout.h" +#include "calls.h" +#include "stmt.h" #include "expr.h" #include "except.h" #include "function.h" diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c index 81e18dfb969..50fb3f05f1f 100644 --- a/gcc/config/darwin.c +++ b/gcc/config/darwin.c @@ -32,6 +32,9 @@ along with GCC; see the file COPYING3. If not see #include "insn-attr.h" #include "flags.h" #include "tree.h" +#include "stringpool.h" +#include "varasm.h" +#include "stor-layout.h" #include "expr.h" #include "reload.h" #include "function.h" diff --git a/gcc/config/epiphany/epiphany.c b/gcc/config/epiphany/epiphany.c index c3200250c06..c264cdaee78 100644 --- a/gcc/config/epiphany/epiphany.c +++ b/gcc/config/epiphany/epiphany.c @@ -23,6 +23,10 @@ along with GCC; see the file COPYING3. If not see #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "stor-layout.h" +#include "varasm.h" +#include "calls.h" +#include "stringpool.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" @@ -2762,7 +2766,7 @@ epiphany_special_round_type_align (tree type, unsigned computed, || tree_to_uhwi (offset) >= try_align || tree_to_uhwi (size) >= try_align) return try_align; - total = TREE_INT_CST_LOW (offset) + TREE_INT_CST_LOW (size); + total = tree_to_uhwi (offset) + tree_to_uhwi (size); if (total > max) max = total; } diff --git a/gcc/config/fr30/fr30.c b/gcc/config/fr30/fr30.c index 4a45feafd04..caa50d9e691 100644 --- a/gcc/config/fr30/fr30.c +++ b/gcc/config/fr30/fr30.c @@ -33,6 +33,8 @@ #include "flags.h" #include "recog.h" #include "tree.h" +#include "stor-layout.h" +#include "varasm.h" #include "output.h" #include "expr.h" #include "obstack.h" diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c index bcd55111434..a5eb2c1c844 100644 --- a/gcc/config/frv/frv.c +++ b/gcc/config/frv/frv.c @@ -23,6 +23,9 @@ along with GCC; see the file COPYING3. If not see #include "tm.h" #include "rtl.h" #include "tree.h" +#include "varasm.h" +#include "stor-layout.h" +#include "stringpool.h" #include "regs.h" #include "hard-reg-set.h" #include "insn-config.h" @@ -8024,7 +8027,7 @@ frv_optimize_membar_global (basic_block bb, struct frv_io *first_io, /* We need to keep the membar if there is an edge to the exit block. */ FOR_EACH_EDGE (succ, ei, bb->succs) /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */ - if (succ->dest == EXIT_BLOCK_PTR) + if (succ->dest == EXIT_BLOCK_PTR_FOR_FN (cfun)) return; /* Work out the union of all successor blocks. */ diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c index 69f37fd02d6..f0ebca30f2c 100644 --- a/gcc/config/h8300/h8300.c +++ b/gcc/config/h8300/h8300.c @@ -25,6 +25,10 @@ along with GCC; see the file COPYING3. If not see #include "tm.h" #include "rtl.h" #include "tree.h" +#include "stor-layout.h" +#include "varasm.h" +#include "calls.h" +#include "stringpool.h" #include "regs.h" #include "hard-reg-set.h" #include "insn-config.h" diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index 85ed7a20034..bceb8f2ef6d 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -60,7 +60,7 @@ extern int avx_vperm2f128_parallel (rtx par, enum machine_mode mode); extern bool ix86_expand_strlen (rtx, rtx, rtx, rtx); extern bool ix86_expand_set_or_movmem (rtx, rtx, rtx, rtx, rtx, rtx, - rtx, rtx, rtx, bool); + rtx, rtx, rtx, rtx, bool); extern bool constant_address_p (rtx); extern bool legitimate_pic_operand_p (rtx); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index d332b5bc80e..8e6bbd14dff 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -23,6 +23,11 @@ along with GCC; see the file COPYING3. If not see #include "tm.h" #include "rtl.h" #include "tree.h" +#include "stringpool.h" +#include "attribs.h" +#include "calls.h" +#include "stor-layout.h" +#include "varasm.h" #include "tm_p.h" #include "regs.h" #include "hard-reg-set.h" @@ -5589,7 +5594,7 @@ ix86_eax_live_at_start_p (void) to correct at this point. This gives false positives for broken functions that might use uninitialized data that happens to be allocated in eax, but who cares? */ - return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0); + return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR_FOR_FN (cfun)), 0); } static bool @@ -9297,7 +9302,7 @@ ix86_compute_frame_layout (struct ix86_frame *frame) Recompute the value as needed. Do not recompute when amount of registers didn't change as reload does multiple calls to the function and does not expect the decision to change within single iteration. */ - else if (!optimize_bb_for_size_p (ENTRY_BLOCK_PTR) + else if (!optimize_bb_for_size_p (ENTRY_BLOCK_PTR_FOR_FN (cfun)) && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs) { int count = frame->nregs; @@ -11386,7 +11391,7 @@ ix86_expand_epilogue (int style) /* Leave results in shorter dependency chains on CPUs that are able to grok it fast. */ else if (TARGET_USE_LEAVE - || optimize_bb_for_size_p (EXIT_BLOCK_PTR) + || optimize_bb_for_size_p (EXIT_BLOCK_PTR_FOR_FN (cfun)) || !cfun->machine->use_fast_prologue_epilogue) ix86_emit_leave (); else @@ -11870,27 +11875,6 @@ ix86_live_on_entry (bitmap regs) } } -/* Determine if op is suitable SUBREG RTX for address. */ - -static bool -ix86_address_subreg_operand (rtx op) -{ - enum machine_mode mode; - - if (!REG_P (op)) - return false; - - mode = GET_MODE (op); - - /* Don't allow SUBREGs that span more than a word. It can lead to spill - failures when the register is one word out of a two word structure. */ - if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) - return false; - - /* Allow only SUBREGs of non-eliminable hard registers. */ - return register_no_elim_operand (op, mode); -} - /* Extract the parts of an RTL expression that is a valid memory address for an instruction. Return 0 if the structure of the address is grossly off. Return -1 if the address contains ASHIFT, so it is not @@ -11947,7 +11931,7 @@ ix86_decompose_address (rtx addr, struct ix86_address *out) base = addr; else if (GET_CODE (addr) == SUBREG) { - if (ix86_address_subreg_operand (SUBREG_REG (addr))) + if (REG_P (SUBREG_REG (addr))) base = addr; else return 0; @@ -12011,7 +11995,7 @@ ix86_decompose_address (rtx addr, struct ix86_address *out) break; case SUBREG: - if (!ix86_address_subreg_operand (SUBREG_REG (op))) + if (!REG_P (SUBREG_REG (op))) return 0; /* FALLTHRU */ @@ -12064,18 +12048,12 @@ ix86_decompose_address (rtx addr, struct ix86_address *out) if (REG_P (index)) ; else if (GET_CODE (index) == SUBREG - && ix86_address_subreg_operand (SUBREG_REG (index))) + && REG_P (SUBREG_REG (index))) ; else return 0; } -/* Address override works only on the (%reg) part of %fs:(%reg). */ - if (seg != SEG_DEFAULT - && ((base && GET_MODE (base) != word_mode) - || (index && GET_MODE (index) != word_mode))) - return 0; - /* Extract the integral value of scale. */ if (scale_rtx) { @@ -12592,6 +12570,45 @@ ix86_legitimize_reload_address (rtx x, return false; } +/* Determine if op is suitable RTX for an address register. + Return naked register if a register or a register subreg is + found, otherwise return NULL_RTX. */ + +static rtx +ix86_validate_address_register (rtx op) +{ + enum machine_mode mode = GET_MODE (op); + + /* Only SImode or DImode registers can form the address. */ + if (mode != SImode && mode != DImode) + return NULL_RTX; + + if (REG_P (op)) + return op; + else if (GET_CODE (op) == SUBREG) + { + rtx reg = SUBREG_REG (op); + + if (!REG_P (reg)) + return NULL_RTX; + + mode = GET_MODE (reg); + + /* Don't allow SUBREGs that span more than a word. It can + lead to spill failures when the register is one word out + of a two word structure. */ + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) + return NULL_RTX; + + /* Allow only SUBREGs of non-eliminable hard registers. */ + if (register_no_elim_operand (reg, mode)) + return reg; + } + + /* Op is not a register. */ + return NULL_RTX; +} + /* Recognizes RTL expressions that are valid memory addresses for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. @@ -12607,6 +12624,7 @@ ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, struct ix86_address parts; rtx base, index, disp; HOST_WIDE_INT scale; + enum ix86_address_seg seg; if (ix86_decompose_address (addr, &parts) <= 0) /* Decomposition failed. */ @@ -12616,21 +12634,14 @@ ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, index = parts.index; disp = parts.disp; scale = parts.scale; + seg = parts.seg; /* Validate base register. */ if (base) { - rtx reg; - - if (REG_P (base)) - reg = base; - else if (GET_CODE (base) == SUBREG && REG_P (SUBREG_REG (base))) - reg = SUBREG_REG (base); - else - /* Base is not a register. */ - return false; + rtx reg = ix86_validate_address_register (base); - if (GET_MODE (base) != SImode && GET_MODE (base) != DImode) + if (reg == NULL_RTX) return false; if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg)) @@ -12642,17 +12653,9 @@ ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, /* Validate index register. */ if (index) { - rtx reg; + rtx reg = ix86_validate_address_register (index); - if (REG_P (index)) - reg = index; - else if (GET_CODE (index) == SUBREG && REG_P (SUBREG_REG (index))) - reg = SUBREG_REG (index); - else - /* Index is not a register. */ - return false; - - if (GET_MODE (index) != SImode && GET_MODE (index) != DImode) + if (reg == NULL_RTX) return false; if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg)) @@ -12666,6 +12669,12 @@ ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, && GET_MODE (base) != GET_MODE (index)) return false; + /* Address override works only on the (%reg) part of %fs:(%reg). */ + if (seg != SEG_DEFAULT + && ((base && GET_MODE (base) != word_mode) + || (index && GET_MODE (index) != word_mode))) + return false; + /* Validate scale factor. */ if (scale != 1) { @@ -23712,7 +23721,8 @@ bool ix86_expand_set_or_movmem (rtx dst, rtx src, rtx count_exp, rtx val_exp, rtx align_exp, rtx expected_align_exp, rtx expected_size_exp, rtx min_size_exp, - rtx max_size_exp, bool issetmem) + rtx max_size_exp, rtx probable_max_size_exp, + bool issetmem) { rtx destreg; rtx srcreg = NULL; @@ -23736,6 +23746,7 @@ ix86_expand_set_or_movmem (rtx dst, rtx src, rtx count_exp, rtx val_exp, /* TODO: Once vlaue ranges are available, fill in proper data. */ unsigned HOST_WIDE_INT min_size = 0; unsigned HOST_WIDE_INT max_size = -1; + unsigned HOST_WIDE_INT probable_max_size = -1; bool misaligned_prologue_used = false; if (CONST_INT_P (align_exp)) @@ -23751,13 +23762,19 @@ ix86_expand_set_or_movmem (rtx dst, rtx src, rtx count_exp, rtx val_exp, align = MEM_ALIGN (dst) / BITS_PER_UNIT; if (CONST_INT_P (count_exp)) - min_size = max_size = count = expected_size = INTVAL (count_exp); - if (min_size_exp) - min_size = INTVAL (min_size_exp); - if (max_size_exp) - max_size = INTVAL (max_size_exp); - if (CONST_INT_P (expected_size_exp) && count == 0) - expected_size = INTVAL (expected_size_exp); + min_size = max_size = probable_max_size = count = expected_size + = INTVAL (count_exp); + else + { + if (min_size_exp) + min_size = INTVAL (min_size_exp); + if (max_size_exp) + max_size = INTVAL (max_size_exp); + if (probable_max_size_exp) + probable_max_size = INTVAL (probable_max_size_exp); + if (CONST_INT_P (expected_size_exp) && count == 0) + expected_size = INTVAL (expected_size_exp); + } /* Make sure we don't need to care about overflow later on. */ if (count > ((unsigned HOST_WIDE_INT) 1 << 30)) @@ -23765,7 +23782,8 @@ ix86_expand_set_or_movmem (rtx dst, rtx src, rtx count_exp, rtx val_exp, /* Step 0: Decide on preferred algorithm, desired alignment and size of chunks to be copied by main loop. */ - alg = decide_alg (count, expected_size, min_size, max_size, issetmem, + alg = decide_alg (count, expected_size, min_size, probable_max_size, + issetmem, issetmem && val_exp == const0_rtx, &dynamic_check, &noalign); if (alg == libcall) @@ -29820,7 +29838,7 @@ add_condition_to_bb (tree function_decl, tree version_decl, make_edge (bb1, bb3, EDGE_FALSE_VALUE); remove_edge (e23); - make_edge (bb2, EXIT_BLOCK_PTR, 0); + make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0); pop_cfun (); @@ -36555,7 +36573,7 @@ ix86_pad_returns (void) edge e; edge_iterator ei; - FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) + FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) { basic_block bb = e->src; rtx ret = BB_END (bb); @@ -36655,14 +36673,14 @@ ix86_count_insn (basic_block bb) edge prev_e; edge_iterator prev_ei; - if (e->src == ENTRY_BLOCK_PTR) + if (e->src == ENTRY_BLOCK_PTR_FOR_FN (cfun)) { min_prev_count = 0; break; } FOR_EACH_EDGE (prev_e, prev_ei, e->src->preds) { - if (prev_e->src == ENTRY_BLOCK_PTR) + if (prev_e->src == ENTRY_BLOCK_PTR_FOR_FN (cfun)) { int count = ix86_count_insn_bb (e->src); if (count < min_prev_count) @@ -36686,7 +36704,7 @@ ix86_pad_short_function (void) edge e; edge_iterator ei; - FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) + FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) { rtx ret = BB_END (e->src); if (JUMP_P (ret) && ANY_RETURN_P (PATTERN (ret))) @@ -36726,7 +36744,7 @@ ix86_seh_fixup_eh_fallthru (void) edge e; edge_iterator ei; - FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) + FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) { rtx insn, next; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 045d4ae8eb7..8178f9b9ab0 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -15506,13 +15506,15 @@ (use (match_operand:SI 4 "const_int_operand")) (use (match_operand:SI 5 "const_int_operand")) (use (match_operand:SI 6 "")) - (use (match_operand:SI 7 ""))] + (use (match_operand:SI 7 "")) + (use (match_operand:SI 8 ""))] "" { if (ix86_expand_set_or_movmem (operands[0], operands[1], operands[2], NULL, operands[3], operands[4], operands[5], - operands[6], operands[7], false)) + operands[6], operands[7], + operands[8], false)) DONE; else FAIL; @@ -15702,14 +15704,15 @@ (use (match_operand:SI 4 "const_int_operand")) (use (match_operand:SI 5 "const_int_operand")) (use (match_operand:SI 6 "")) - (use (match_operand:SI 7 ""))] + (use (match_operand:SI 7 "")) + (use (match_operand:SI 8 ""))] "" { if (ix86_expand_set_or_movmem (operands[0], NULL, operands[1], operands[2], operands[3], operands[4], operands[5], operands[6], - operands[7], true)) + operands[7], operands[8], true)) DONE; else FAIL; diff --git a/gcc/config/i386/winnt-cxx.c b/gcc/config/i386/winnt-cxx.c index 92de46abd59..d466299abed 100644 --- a/gcc/config/i386/winnt-cxx.c +++ b/gcc/config/i386/winnt-cxx.c @@ -23,6 +23,8 @@ along with GCC; see the file COPYING3. If not see #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "stringpool.h" +#include "attribs.h" #include "cp/cp-tree.h" /* This is why we're a separate module. */ #include "flags.h" #include "tm_p.h" diff --git a/gcc/config/i386/winnt.c b/gcc/config/i386/winnt.c index 94155d89a7f..2c1677eec88 100644 --- a/gcc/config/i386/winnt.c +++ b/gcc/config/i386/winnt.c @@ -27,6 +27,8 @@ along with GCC; see the file COPYING3. If not see #include "hard-reg-set.h" #include "output.h" #include "tree.h" +#include "stringpool.h" +#include "varasm.h" #include "flags.h" #include "tm_p.h" #include "diagnostic-core.h" diff --git a/gcc/config/ia64/ia64-c.c b/gcc/config/ia64/ia64-c.c index 4d4dbc84369..6489668b7d9 100644 --- a/gcc/config/ia64/ia64-c.c +++ b/gcc/config/ia64/ia64-c.c @@ -23,6 +23,7 @@ along with GCC; see the file COPYING3. If not see #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "stringpool.h" #include "cpplib.h" #include "c-family/c-common.h" #include "c-family/c-pragma.h" diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index 4fde7aab43e..71bc666b685 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -25,6 +25,10 @@ along with GCC; see the file COPYING3. If not see #include "tm.h" #include "rtl.h" #include "tree.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "calls.h" +#include "varasm.h" #include "regs.h" #include "hard-reg-set.h" #include "insn-config.h" @@ -3488,7 +3492,7 @@ ia64_expand_prologue (void) edge e; edge_iterator ei; - FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) + FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) if ((e->flags & EDGE_FAKE) == 0 && (e->flags & EDGE_FALLTHRU) != 0) break; @@ -10183,7 +10187,8 @@ ia64_asm_unwind_emit (FILE *asm_out_file, rtx insn) if (NOTE_INSN_BASIC_BLOCK_P (insn)) { - last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR; + last_block = NOTE_BASIC_BLOCK (insn)->next_bb + == EXIT_BLOCK_PTR_FOR_FN (cfun); /* Restore unwind state from immediately before the epilogue. */ if (need_copy_state) diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c index e65d0ccdc03..e6d1171ca85 100644 --- a/gcc/config/iq2000/iq2000.c +++ b/gcc/config/iq2000/iq2000.c @@ -22,6 +22,9 @@ along with GCC; see the file COPYING3. If not see #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "stor-layout.h" +#include "calls.h" +#include "varasm.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" diff --git a/gcc/config/lm32/lm32.c b/gcc/config/lm32/lm32.c index 6483a03e57d..6bddc488727 100644 --- a/gcc/config/lm32/lm32.c +++ b/gcc/config/lm32/lm32.c @@ -35,6 +35,7 @@ #include "recog.h" #include "output.h" #include "tree.h" +#include "calls.h" #include "expr.h" #include "flags.h" #include "reload.h" diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c index deac40c228f..ec30b8d7f9b 100644 --- a/gcc/config/m32c/m32c.c +++ b/gcc/config/m32c/m32c.c @@ -36,6 +36,9 @@ #include "diagnostic-core.h" #include "obstack.h" #include "tree.h" +#include "stor-layout.h" +#include "varasm.h" +#include "calls.h" #include "expr.h" #include "optabs.h" #include "except.h" diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c index c94da538fcf..6cee5d728b3 100644 --- a/gcc/config/m32r/m32r.c +++ b/gcc/config/m32r/m32r.c @@ -22,6 +22,10 @@ #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "stor-layout.h" +#include "varasm.h" +#include "stringpool.h" +#include "calls.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index 7035504bfe3..2b5bc22ecb2 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -22,6 +22,9 @@ along with GCC; see the file COPYING3. If not see #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "calls.h" +#include "stor-layout.h" +#include "varasm.h" #include "rtl.h" #include "function.h" #include "regs.h" @@ -514,7 +517,7 @@ m68k_option_override (void) { enum target_device dev; dev = all_microarchs[M68K_DEFAULT_TUNE].device; - m68k_tune_flags = all_devices[dev]->flags; + m68k_tune_flags = all_devices[dev].flags; } #endif else diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c index 6550b6905f0..6bd60702fa2 100644 --- a/gcc/config/mcore/mcore.c +++ b/gcc/config/mcore/mcore.c @@ -23,6 +23,10 @@ #include "tm.h" #include "rtl.h" #include "tree.h" +#include "stor-layout.h" +#include "varasm.h" +#include "stringpool.h" +#include "calls.h" #include "tm_p.h" #include "mcore.h" #include "regs.h" diff --git a/gcc/config/mep/mep.c b/gcc/config/mep/mep.c index 489bef9c2d3..6ce6c530077 100644 --- a/gcc/config/mep/mep.c +++ b/gcc/config/mep/mep.c @@ -24,6 +24,10 @@ along with GCC; see the file COPYING3. If not see #include "tm.h" #include "rtl.h" #include "tree.h" +#include "varasm.h" +#include "calls.h" +#include "stringpool.h" +#include "stor-layout.h" #include "regs.h" #include "hard-reg-set.h" #include "insn-config.h" diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c index 3258a95ef3a..93dede4d189 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c @@ -33,6 +33,9 @@ #include "insn-attr.h" #include "recog.h" #include "tree.h" +#include "varasm.h" +#include "stor-layout.h" +#include "calls.h" #include "function.h" #include "expr.h" #include "flags.h" diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 80bbb00c2c8..d06d5747081 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -34,6 +34,10 @@ along with GCC; see the file COPYING3. If not see #include "recog.h" #include "output.h" #include "tree.h" +#include "varasm.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "calls.h" #include "function.h" #include "expr.h" #include "optabs.h" @@ -14838,7 +14842,7 @@ r10k_simplify_address (rtx x, rtx insn) /* Replace the incoming value of $sp with virtual_incoming_args_rtx. */ if (x == stack_pointer_rtx - && DF_REF_BB (def) == ENTRY_BLOCK_PTR) + && DF_REF_BB (def) == ENTRY_BLOCK_PTR_FOR_FN (cfun)) newx = virtual_incoming_args_rtx; } else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use), @@ -16072,10 +16076,13 @@ mips_reorg_process_insns (void) if (crtl->profile) cfun->machine->all_noreorder_p = false; - /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder - because we rely on the assembler to work around some errata. - The r5900 too has several bugs. */ - if (TARGET_FIX_VR4120 || TARGET_FIX_24K || TARGET_MIPS5900) + /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be + all noreorder because we rely on the assembler to work around some + errata. The R5900 too has several bugs. */ + if (TARGET_FIX_VR4120 + || TARGET_FIX_RM7000 + || TARGET_FIX_24K + || TARGET_MIPS5900) cfun->machine->all_noreorder_p = false; /* The same is true for -mfix-vr4130 if we might generate MFLO or diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index c4a2a4a6862..11687b8a053 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1167,6 +1167,7 @@ struct mips_cpu_info { %{meva} %{mno-eva} \ %{msmartmips} %{mno-smartmips} \ %{mmt} %{mno-mt} \ +%{mfix-rm7000} %{mno-fix-rm7000} \ %{mfix-vr4120} %{mfix-vr4130} \ %{mfix-24k} \ %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 3554beb3033..6991f203df4 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -6776,7 +6776,7 @@ (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>" [(set (match_operand:GPR 0 "register_operand" "=d,d") (if_then_else:GPR - (match_operator:MOVECC 4 "equality_operator" + (match_operator 4 "equality_operator" [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>") (const_int 0)]) (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") @@ -6788,10 +6788,23 @@ [(set_attr "type" "condmove") (set_attr "mode" "<GPR:MODE>")]) +(define_insn "*mov<GPR:mode>_on_<GPR2:mode>_ne" + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (if_then_else:GPR + (match_operand:GPR2 1 "register_operand" "<GPR2:reg>,<GPR2:reg>") + (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") + (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))] + "ISA_HAS_CONDMOVE" + "@ + movn\t%0,%z2,%1 + movz\t%0,%z3,%1" + [(set_attr "type" "condmove") + (set_attr "mode" "<GPR:MODE>")]) + (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>" [(set (match_operand:SCALARF 0 "register_operand" "=f,f") (if_then_else:SCALARF - (match_operator:MOVECC 4 "equality_operator" + (match_operator 4 "equality_operator" [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>") (const_int 0)]) (match_operand:SCALARF 2 "register_operand" "f,0") diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 0324041dbea..10faf4216a5 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -165,6 +165,10 @@ mfix-r4400 Target Report Mask(FIX_R4400) Work around certain R4400 errata +mfix-rm7000 +Target Report Var(TARGET_FIX_RM7000) +Work around certain RM7000 errata + mfix-r10000 Target Report Mask(FIX_R10000) Work around certain R10000 errata diff --git a/gcc/config/mmix/mmix.c b/gcc/config/mmix/mmix.c index 34b4fea7503..eb43af71d08 100644 --- a/gcc/config/mmix/mmix.c +++ b/gcc/config/mmix/mmix.c @@ -31,6 +31,9 @@ along with GCC; see the file COPYING3. If not see #include "basic-block.h" #include "flags.h" #include "tree.h" +#include "varasm.h" +#include "stor-layout.h" +#include "calls.h" #include "function.h" #include "expr.h" #include "diagnostic-core.h" diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c index df563d03eac..7304e8638c7 100644 --- a/gcc/config/mn10300/mn10300.c +++ b/gcc/config/mn10300/mn10300.c @@ -24,6 +24,9 @@ #include "tm.h" #include "rtl.h" #include "tree.h" +#include "stor-layout.h" +#include "varasm.h" +#include "calls.h" #include "regs.h" #include "hard-reg-set.h" #include "insn-config.h" @@ -3226,7 +3229,6 @@ mn10300_loop_contains_call_insn (loop_p loop) static void mn10300_scan_for_setlb_lcc (void) { - loop_iterator liter; loop_p loop; DUMP ("Looking for loops that can use the SETLB insn", NULL_RTX); @@ -3241,7 +3243,7 @@ mn10300_scan_for_setlb_lcc (void) if an inner loop is not suitable for use with the SETLB/Lcc insns, it may be the case that its parent loop is suitable. Thus we should check all loops, but work from the innermost outwards. */ - FOR_EACH_LOOP (liter, loop, LI_ONLY_INNERMOST) + FOR_EACH_LOOP (loop, LI_ONLY_INNERMOST) { const char * reason = NULL; diff --git a/gcc/config/moxie/moxie.c b/gcc/config/moxie/moxie.c index d4f7d6d9d68..abba0aebd2d 100644 --- a/gcc/config/moxie/moxie.c +++ b/gcc/config/moxie/moxie.c @@ -36,6 +36,9 @@ #include "diagnostic-core.h" #include "obstack.h" #include "tree.h" +#include "stor-layout.h" +#include "varasm.h" +#include "calls.h" #include "expr.h" #include "optabs.h" #include "except.h" diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c index 8721f3a8229..e3f6712596a 100644 --- a/gcc/config/msp430/msp430.c +++ b/gcc/config/msp430/msp430.c @@ -23,6 +23,8 @@ #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "stor-layout.h" +#include "calls.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c index 7dfcdc7366d..80ca1f647b7 100644 --- a/gcc/config/nds32/nds32.c +++ b/gcc/config/nds32/nds32.c @@ -25,6 +25,9 @@ #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "stor-layout.h" +#include "varasm.h" +#include "calls.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" @@ -4563,7 +4566,7 @@ nds32_fp_as_gp_check_available (void) || frame_pointer_needed || NDS32_REQUIRED_CALLEE_SAVED_P (FP_REGNUM) || (cfun->stdarg == 1) - || (find_fallthru_edge (EXIT_BLOCK_PTR->preds) == NULL)) + || (find_fallthru_edge (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) == NULL)) return 0; /* Now we can check the possibility of using fp_as_gp optimization. */ diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 260830f00d7..2aa63c6bd0c 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -30,6 +30,10 @@ along with GCC; see the file COPYING3. If not see #include "insn-attr.h" #include "flags.h" #include "tree.h" +#include "stor-layout.h" +#include "stringpool.h" +#include "varasm.h" +#include "calls.h" #include "output.h" #include "dbxout.h" #include "except.h" diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c index 0a310c50d79..42237b5d798 100644 --- a/gcc/config/pdp11/pdp11.c +++ b/gcc/config/pdp11/pdp11.c @@ -33,6 +33,9 @@ along with GCC; see the file COPYING3. If not see #include "flags.h" #include "recog.h" #include "tree.h" +#include "stor-layout.h" +#include "varasm.h" +#include "calls.h" #include "expr.h" #include "diagnostic-core.h" #include "tm_p.h" diff --git a/gcc/config/picochip/picochip.c b/gcc/config/picochip/picochip.c index 641bccb81f6..4756cb78b72 100644 --- a/gcc/config/picochip/picochip.c +++ b/gcc/config/picochip/picochip.c @@ -34,6 +34,10 @@ along with GCC; see the file COPYING3. If not, see #include "recog.h" #include "obstack.h" #include "tree.h" +#include "calls.h" +#include "stor-layout.h" +#include "stringpool.h" +#include "varasm.h" #include "expr.h" #include "optabs.h" #include "except.h" diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c index f071e31daf2..72aefc205a1 100644 --- a/gcc/config/rl78/rl78.c +++ b/gcc/config/rl78/rl78.c @@ -23,6 +23,9 @@ #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "varasm.h" +#include "stor-layout.h" +#include "calls.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h index 78e84531300..66b483ec116 100644 --- a/gcc/config/rs6000/linux64.h +++ b/gcc/config/rs6000/linux64.h @@ -71,7 +71,11 @@ extern int dot_symbols; #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_POWER7 #undef PROCESSOR_DEFAULT64 +#ifdef LINUX64_DEFAULT_ABI_ELFv2 +#define PROCESSOR_DEFAULT64 PROCESSOR_POWER8 +#else #define PROCESSOR_DEFAULT64 PROCESSOR_POWER7 +#endif /* We don't need to generate entries in .fixup, except when -mrelocatable or -mrelocatable-lib is given. */ diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index e2e5409d998..8cc0dc691cf 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -26,6 +26,8 @@ #include "tm.h" #include "cpplib.h" #include "tree.h" +#include "stor-layout.h" +#include "stringpool.h" #include "wide-int.h" #include "c-family/c-common.h" #include "c-family/c-pragma.h" diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index c530ccde536..df2ca2440b3 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -32,6 +32,11 @@ #include "recog.h" #include "obstack.h" #include "tree.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "calls.h" +#include "print-tree.h" +#include "varasm.h" #include "expr.h" #include "optabs.h" #include "except.h" @@ -3217,6 +3222,12 @@ rs6000_option_override_internal (bool global_init_p) } } + /* If little-endian, default to -mstrict-align on older processors. + Testing for htm matches power8 and later. */ + if (!BYTES_BIG_ENDIAN + && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM)) + rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN; + /* Add some warnings for VSX. */ if (TARGET_VSX) { @@ -7984,6 +7995,7 @@ rs6000_emit_le_vsx_move (rtx dest, rtx source, enum machine_mode mode) gcc_assert (!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode) && mode != TImode + && !gpr_or_gpr_p (dest, source) && (MEM_P (source) ^ MEM_P (dest))); if (MEM_P (source)) @@ -22938,7 +22950,7 @@ rs6000_emit_prologue (void) && DEFAULT_ABI == ABI_V4 && flag_pic && ! info->lr_save_p - && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0); + && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0); if (save_LR_around_toc_setup) { rtx lr = gen_rtx_REG (Pmode, LR_REGNO); @@ -29801,6 +29813,8 @@ altivec_expand_vec_perm_const (rtx operands[4]) break; if (i == 16) { + if (!BYTES_BIG_ENDIAN) + elt = 15 - elt; emit_insn (gen_altivec_vspltb (target, op0, GEN_INT (elt))); return true; } diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h index ba4ceb3ff2e..73c3ec16c2c 100644 --- a/gcc/config/rs6000/sysv4.h +++ b/gcc/config/rs6000/sysv4.h @@ -538,12 +538,7 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN) #define CC1_ENDIAN_BIG_SPEC "" -#define CC1_ENDIAN_LITTLE_SPEC "\ -%{!mstrict-align: %{!mno-strict-align: \ - %{!mcall-i960-old: \ - -mstrict-align \ - } \ -}}" +#define CC1_ENDIAN_LITTLE_SPEC "" #define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_big)" diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 10a401813d1..650fbddc2bb 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -108,6 +108,7 @@ if (!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode) && <MODE>mode != TImode + && !gpr_or_gpr_p (operands[0], operands[1]) && (memory_operand (operands[0], <MODE>mode) ^ memory_operand (operands[1], <MODE>mode))) { diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c index 89860927a82..662ab9b72cc 100644 --- a/gcc/config/rx/rx.c +++ b/gcc/config/rx/rx.c @@ -27,6 +27,9 @@ #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "varasm.h" +#include "stor-layout.h" +#include "calls.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" diff --git a/gcc/config/s390/htmxlintrin.h b/gcc/config/s390/htmxlintrin.h index 800d5f0aa0c..d1c7ec566e1 100644 --- a/gcc/config/s390/htmxlintrin.h +++ b/gcc/config/s390/htmxlintrin.h @@ -33,13 +33,20 @@ extern "C" { the IBM XL compiler. For documentation please see the "z/OS XL C/C++ Programming Guide" publicly available on the web. */ -extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +/* FIXME: __TM_simple_begin and __TM_begin should be marked + __always_inline__ as well but this currently produces an error + since the tbegin builtins are "returns_twice" and setjmp_call_p + (calls.c) therefore identifies the functions as calling setjmp. + The tree inliner currently refuses to inline functions calling + setjmp. */ + +long __TM_simple_begin () { return __builtin_tbegin_nofloat (0); } -extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +long __TM_begin (void* const tdb) { return __builtin_tbegin_nofloat (tdb); @@ -78,7 +85,7 @@ __TM_nesting_depth (void* const tdb_ptr) if (depth != 0) return depth; - if (tdb->format == 0) + if (tdb->format != 1) return 0; return tdb->nesting_depth; } @@ -90,7 +97,7 @@ __TM_is_user_abort (void* const tdb_ptr) { struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr; - if (tdb->format == 0) + if (tdb->format != 1) return 0; return !!(tdb->abort_code >= _HTM_FIRST_USER_ABORT_CODE); @@ -101,7 +108,7 @@ __TM_is_named_user_abort (void* const tdb_ptr, unsigned char* code) { struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr; - if (tdb->format == 0) + if (tdb->format != 1) return 0; if (tdb->abort_code >= _HTM_FIRST_USER_ABORT_CODE) @@ -117,7 +124,7 @@ __TM_is_illegal (void* const tdb_ptr) { struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr; - return (tdb->format == 0 + return (tdb->format == 1 && (tdb->abort_code == 4 /* unfiltered program interruption */ || tdb->abort_code == 11 /* restricted instruction */)); } @@ -127,7 +134,7 @@ __TM_is_footprint_exceeded (void* const tdb_ptr) { struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr; - return (tdb->format == 0 + return (tdb->format == 1 && (tdb->abort_code == 7 /* fetch overflow */ || tdb->abort_code == 8 /* store overflow */)); } @@ -137,7 +144,7 @@ __TM_is_nested_too_deep (void* const tdb_ptr) { struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr; - return tdb->format == 0 && tdb->abort_code == 13; /* depth exceeded */ + return tdb->format == 1 && tdb->abort_code == 13; /* depth exceeded */ } extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -145,7 +152,7 @@ __TM_is_conflict (void* const tdb_ptr) { struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr; - return (tdb->format == 0 + return (tdb->format == 1 && (tdb->abort_code == 9 /* fetch conflict */ || tdb->abort_code == 10 /* store conflict */)); } diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 39453038fe7..62d162ab087 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -26,6 +26,11 @@ along with GCC; see the file COPYING3. If not see #include "tm.h" #include "rtl.h" #include "tree.h" +#include "print-tree.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "varasm.h" +#include "calls.h" #include "tm_p.h" #include "regs.h" #include "hard-reg-set.h" @@ -895,7 +900,8 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1, { /* For CCRAWmode put the required cc mask into the second operand. */ - if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode) + if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode + && INTVAL (*op1) >= 0 && INTVAL (*op1) <= 3) *op1 = gen_rtx_CONST_INT (VOIDmode, 1 << (3 - INTVAL (*op1))); *op0 = XVECEXP (*op0, 0, 0); *code = new_code; @@ -7964,10 +7970,13 @@ s390_optimize_nonescaping_tx (void) if (!cfun->machine->tbegin_p) return; - for (bb_index = 0; bb_index < n_basic_blocks; bb_index++) + for (bb_index = 0; bb_index < n_basic_blocks_for_fn (cfun); bb_index++) { bb = BASIC_BLOCK (bb_index); + if (!bb) + continue; + FOR_BB_INSNS (bb, insn) { rtx ite, cc, pat, target; @@ -8081,7 +8090,10 @@ s390_optimize_nonescaping_tx (void) if (!result) return; - PATTERN (tbegin_insn) = XVECEXP (PATTERN (tbegin_insn), 0, 0); + PATTERN (tbegin_insn) = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (2, + XVECEXP (PATTERN (tbegin_insn), 0, 0), + XVECEXP (PATTERN (tbegin_insn), 0, 1))); INSN_CODE (tbegin_insn) = -1; df_insn_rescan (tbegin_insn); @@ -9793,6 +9805,7 @@ s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) const int CC3 = 1 << 0; rtx abort_label = gen_label_rtx (); rtx leave_label = gen_label_rtx (); + rtx retry_plus_two = gen_reg_rtx (SImode); rtx retry_reg = gen_reg_rtx (SImode); rtx retry_label = NULL_RTX; rtx jump; @@ -9801,16 +9814,17 @@ s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) if (retry != NULL_RTX) { emit_move_insn (retry_reg, retry); + emit_insn (gen_addsi3 (retry_plus_two, retry_reg, const2_rtx)); + emit_insn (gen_addsi3 (retry_reg, retry_reg, const1_rtx)); retry_label = gen_label_rtx (); emit_label (retry_label); } if (clobber_fprs_p) - emit_insn (gen_tbegin_1 (tdb, - gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK))); + emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb)); else - emit_insn (gen_tbegin_nofloat_1 (tdb, - gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK))); + emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), + tdb)); jump = s390_emit_jump (abort_label, gen_rtx_NE (VOIDmode, @@ -9831,6 +9845,10 @@ s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) /* Abort handler code. */ emit_label (abort_label); + emit_move_insn (dest, gen_rtx_UNSPEC (SImode, + gen_rtvec (1, gen_rtx_REG (CCRAWmode, + CC_REGNUM)), + UNSPEC_CC_TO_INT)); if (retry != NULL_RTX) { rtx count = gen_reg_rtx (SImode); @@ -9842,7 +9860,7 @@ s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) add_int_reg_note (jump, REG_BR_PROB, very_unlikely); /* CC2 - transient failure. Perform retry with ppa. */ - emit_move_insn (count, retry); + emit_move_insn (count, retry_plus_two); emit_insn (gen_subsi3 (count, count, retry_reg)); emit_insn (gen_tx_assist (count)); jump = emit_jump_insn (gen_doloop_si64 (retry_label, @@ -9852,10 +9870,6 @@ s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) LABEL_NUSES (retry_label) = 1; } - emit_move_insn (dest, gen_rtx_UNSPEC (SImode, - gen_rtvec (1, gen_rtx_REG (CCRAWmode, - CC_REGNUM)), - UNSPEC_CC_TO_INT)); emit_label (leave_label); } @@ -9894,6 +9908,9 @@ static void s390_init_builtins (void) { tree ftype, uint64_type; + tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"), + NULL, NULL); + tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL); /* void foo (void) */ ftype = build_function_type_list (void_type_node, NULL_TREE); @@ -9904,17 +9921,17 @@ s390_init_builtins (void) ftype = build_function_type_list (void_type_node, integer_type_node, NULL_TREE); add_builtin_function ("__builtin_tabort", ftype, - S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, NULL_TREE); + S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, noreturn_attr); add_builtin_function ("__builtin_tx_assist", ftype, S390_BUILTIN_TX_ASSIST, BUILT_IN_MD, NULL, NULL_TREE); /* int foo (void *) */ ftype = build_function_type_list (integer_type_node, ptr_type_node, NULL_TREE); add_builtin_function ("__builtin_tbegin", ftype, S390_BUILTIN_TBEGIN, - BUILT_IN_MD, NULL, NULL_TREE); + BUILT_IN_MD, NULL, returns_twice_attr); add_builtin_function ("__builtin_tbegin_nofloat", ftype, S390_BUILTIN_TBEGIN_NOFLOAT, - BUILT_IN_MD, NULL, NULL_TREE); + BUILT_IN_MD, NULL, returns_twice_attr); /* int foo (void *, int) */ ftype = build_function_type_list (integer_type_node, ptr_type_node, @@ -9922,11 +9939,11 @@ s390_init_builtins (void) add_builtin_function ("__builtin_tbegin_retry", ftype, S390_BUILTIN_TBEGIN_RETRY, BUILT_IN_MD, - NULL, NULL_TREE); + NULL, returns_twice_attr); add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype, S390_BUILTIN_TBEGIN_RETRY_NOFLOAT, BUILT_IN_MD, - NULL, NULL_TREE); + NULL, returns_twice_attr); /* int foo (void) */ ftype = build_function_type_list (integer_type_node, NULL_TREE); diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 8354e263892..d537d29d24f 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -155,6 +155,7 @@ ; Transactional Execution support UNSPECV_TBEGIN + UNSPECV_TBEGIN_TDB UNSPECV_TBEGINC UNSPECV_TEND UNSPECV_TABORT @@ -9997,9 +9998,10 @@ (define_insn "tbegin_1" [(set (reg:CCRAW CC_REGNUM) - (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q") - (match_operand 1 "const_int_operand" " D")] + (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] UNSPECV_TBEGIN)) + (set (match_operand:BLK 1 "memory_operand" "=Q") + (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) (clobber (reg:DF 16)) (clobber (reg:DF 17)) (clobber (reg:DF 18)) @@ -10018,18 +10020,19 @@ (clobber (reg:DF 31))] ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is ; not supposed to be used for immediates (see genpreds.c). - "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff" - "tbegin\t%0,%x1" + "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" + "tbegin\t%1,%x0" [(set_attr "op_type" "SIL")]) ; Same as above but without the FPR clobbers (define_insn "tbegin_nofloat_1" [(set (reg:CCRAW CC_REGNUM) - (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q") - (match_operand 1 "const_int_operand" " D")] - UNSPECV_TBEGIN))] - "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff" - "tbegin\t%0,%x1" + (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] + UNSPECV_TBEGIN)) + (set (match_operand:BLK 1 "memory_operand" "=Q") + (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] + "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" + "tbegin\t%1,%x0" [(set_attr "op_type" "SIL")]) @@ -10113,15 +10116,12 @@ ; Transaction perform processor assist (define_expand "tx_assist" - [(set (match_dup 1) (const_int 0)) - (unspec_volatile [(match_operand:SI 0 "register_operand" "") - (match_dup 1) + [(unspec_volatile [(match_operand:SI 0 "register_operand" "") + (reg:SI GPR0_REGNUM) (const_int 1)] UNSPECV_PPA)] "TARGET_HTM" -{ - operands[1] = gen_reg_rtx (SImode); -}) + "") (define_insn "*ppa" [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") @@ -10129,5 +10129,5 @@ (match_operand 2 "const_int_operand" "I")] UNSPECV_PPA)] "TARGET_HTM && INTVAL (operands[2]) < 16" - "ppa\t%0,%1,1" + "ppa\t%0,%1,%2" [(set_attr "op_type" "RRF")]) diff --git a/gcc/config/score/score.c b/gcc/config/score/score.c index c25aaa2da93..3fdf2ea9050 100644 --- a/gcc/config/score/score.c +++ b/gcc/config/score/score.c @@ -32,6 +32,10 @@ #include "diagnostic-core.h" #include "output.h" #include "tree.h" +#include "stringpool.h" +#include "calls.h" +#include "varasm.h" +#include "stor-layout.h" #include "function.h" #include "expr.h" #include "optabs.h" diff --git a/gcc/config/sh/sh-c.c b/gcc/config/sh/sh-c.c index 4f3a41a46e7..0d7937f4822 100644 --- a/gcc/config/sh/sh-c.c +++ b/gcc/config/sh/sh-c.c @@ -23,6 +23,8 @@ along with GCC; see the file COPYING3. If not see #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "stringpool.h" +#include "attribs.h" #include "tm_p.h" #include "cpplib.h" #include "c-family/c-common.h" diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 088ef396313..d5f7f15c1cc 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -26,6 +26,10 @@ along with GCC; see the file COPYING3. If not see #include "insn-config.h" #include "rtl.h" #include "tree.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "calls.h" +#include "varasm.h" #include "flags.h" #include "expr.h" #include "optabs.h" diff --git a/gcc/config/sol2-c.c b/gcc/config/sol2-c.c index 0accac40020..1a47e39e9cf 100644 --- a/gcc/config/sol2-c.c +++ b/gcc/config/sol2-c.c @@ -22,6 +22,8 @@ along with GCC; see the file COPYING3. If not see #include "system.h" #include "coretypes.h" #include "tree.h" +#include "stringpool.h" +#include "attribs.h" #include "tm.h" #include "tm_p.h" diff --git a/gcc/config/sol2-cxx.c b/gcc/config/sol2-cxx.c index e1b450d759b..d3d79554b96 100644 --- a/gcc/config/sol2-cxx.c +++ b/gcc/config/sol2-cxx.c @@ -21,6 +21,7 @@ along with GCC; see the file COPYING3. If not see #include "system.h" #include "coretypes.h" #include "tree.h" +#include "stringpool.h" #include "cp/cp-tree.h" #include "tm.h" #include "tm_p.h" diff --git a/gcc/config/sol2.c b/gcc/config/sol2.c index 7c7c429db3d..4200e620e16 100644 --- a/gcc/config/sol2.c +++ b/gcc/config/sol2.c @@ -22,6 +22,8 @@ along with GCC; see the file COPYING3. If not see #include "system.h" #include "coretypes.h" #include "tree.h" +#include "stringpool.h" +#include "varasm.h" #include "output.h" #include "tm.h" #include "rtl.h" diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index ab8f501e4fa..13192c0aa21 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -25,6 +25,10 @@ along with GCC; see the file COPYING3. If not see #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "calls.h" +#include "varasm.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" diff --git a/gcc/config/spu/spu-c.c b/gcc/config/spu/spu-c.c index 215962fa7c9..7632ec1462c 100644 --- a/gcc/config/spu/spu-c.c +++ b/gcc/config/spu/spu-c.c @@ -20,6 +20,7 @@ #include "tm.h" #include "cpplib.h" #include "tree.h" +#include "stringpool.h" #include "c-family/c-common.h" #include "c-family/c-pragma.h" #include "tm_p.h" diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c index e344b73fce6..315f1b3617f 100644 --- a/gcc/config/spu/spu.c +++ b/gcc/config/spu/spu.c @@ -28,6 +28,10 @@ #include "recog.h" #include "obstack.h" #include "tree.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "calls.h" +#include "varasm.h" #include "expr.h" #include "optabs.h" #include "except.h" @@ -2470,13 +2474,13 @@ spu_machine_dependent_reorg (void) compact_blocks (); spu_bb_info = - (struct spu_bb_info *) xcalloc (n_basic_blocks, + (struct spu_bb_info *) xcalloc (n_basic_blocks_for_fn (cfun), sizeof (struct spu_bb_info)); /* We need exact insn addresses and lengths. */ shorten_branches (get_insns ()); - for (i = n_basic_blocks - 1; i >= 0; i--) + for (i = n_basic_blocks_for_fn (cfun) - 1; i >= 0; i--) { bb = BASIC_BLOCK (i); branch = 0; diff --git a/gcc/config/stormy16/stormy16.c b/gcc/config/stormy16/stormy16.c index 3a08534be51..d5a1fc6ad86 100644 --- a/gcc/config/stormy16/stormy16.c +++ b/gcc/config/stormy16/stormy16.c @@ -35,6 +35,10 @@ #include "diagnostic-core.h" #include "obstack.h" #include "tree.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "varasm.h" +#include "calls.h" #include "expr.h" #include "optabs.h" #include "except.h" diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c index bf13d11b820..809beefa305 100644 --- a/gcc/config/tilegx/tilegx.c +++ b/gcc/config/tilegx/tilegx.c @@ -41,6 +41,10 @@ #include "timevar.h" #include "tree.h" #include "gimple.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "varasm.h" +#include "calls.h" #include "gimplify.h" #include "cfgloop.h" #include "tilegx-builtins.h" diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c index d497f64125f..9fe1b104f57 100644 --- a/gcc/config/tilepro/tilepro.c +++ b/gcc/config/tilepro/tilepro.c @@ -42,6 +42,10 @@ #include "timevar.h" #include "tree.h" #include "gimple.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "varasm.h" +#include "calls.h" #include "gimplify.h" #include "cfgloop.h" #include "tilepro-builtins.h" diff --git a/gcc/config/v850/v850-c.c b/gcc/config/v850/v850-c.c index 63ef368afc4..25158d50e09 100644 --- a/gcc/config/v850/v850-c.c +++ b/gcc/config/v850/v850-c.c @@ -24,6 +24,8 @@ along with GCC; see the file COPYING3. If not see #include "tm.h" #include "cpplib.h" #include "tree.h" +#include "stringpool.h" +#include "attribs.h" #include "c-family/c-pragma.h" #include "diagnostic-core.h" #include "ggc.h" diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c index 006cff4bcdf..32fe73b1fa6 100644 --- a/gcc/config/v850/v850.c +++ b/gcc/config/v850/v850.c @@ -23,6 +23,10 @@ #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "varasm.h" +#include "calls.h" #include "rtl.h" #include "regs.h" #include "hard-reg-set.h" diff --git a/gcc/config/vax/vax.c b/gcc/config/vax/vax.c index 2b6fd9aaa6e..90da3b9c2b8 100644 --- a/gcc/config/vax/vax.c +++ b/gcc/config/vax/vax.c @@ -24,6 +24,8 @@ along with GCC; see the file COPYING3. If not see #include "rtl.h" #include "df.h" #include "tree.h" +#include "calls.h" +#include "varasm.h" #include "regs.h" #include "hard-reg-set.h" #include "insn-config.h" diff --git a/gcc/config/vms/vms.c b/gcc/config/vms/vms.c index ba1e2a69798..3047cfde9fe 100644 --- a/gcc/config/vms/vms.c +++ b/gcc/config/vms/vms.c @@ -22,6 +22,7 @@ along with GCC; see the file COPYING3. If not see #include "system.h" #include "coretypes.h" #include "tree.h" +#include "stringpool.h" #include "vms-protos.h" #include "ggc.h" #include "target.h" diff --git a/gcc/config/vxworks.c b/gcc/config/vxworks.c index 2900d9785ea..2940ea11933 100644 --- a/gcc/config/vxworks.c +++ b/gcc/config/vxworks.c @@ -26,6 +26,7 @@ along with GCC; see the file COPYING3. If not see #include "output.h" #include "tm.h" #include "tree.h" +#include "stringpool.h" /* Like default_named_section_asm_out_constructor, except that even constructors with DEFAULT_INIT_PRIORITY must go in a numbered diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c index 6385c5df555..9e6bb23818f 100644 --- a/gcc/config/xtensa/xtensa.c +++ b/gcc/config/xtensa/xtensa.c @@ -34,6 +34,10 @@ along with GCC; see the file COPYING3. If not see #include "recog.h" #include "output.h" #include "tree.h" +#include "stringpool.h" +#include "stor-layout.h" +#include "calls.h" +#include "varasm.h" #include "expr.h" #include "flags.h" #include "reload.h" |