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| author | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-04-13 14:02:26 +0000 |
|---|---|---|
| committer | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-04-13 14:02:26 +0000 |
| commit | 00daaa9c6f433dff1959f2faa393fbb253e79977 (patch) | |
| tree | d5e36d64e7245343bd311224f37c23c3580f9c06 /gcc/config | |
| parent | db48deb0c084bb3a81a406248fb028d86a2d32d4 (diff) | |
| download | gcc-00daaa9c6f433dff1959f2faa393fbb253e79977.tar.gz | |
* config/i386/i386.md (*bmi2_umul<mode><dwi>3_1): Merge from
*bmi2_umulsidi3_1 and *bmi2_umulditi3_1 using DWIH mode iterator.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222052 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386.md | 46 |
1 files changed, 14 insertions, 32 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index e1c82fefc0d..729db75584e 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -6818,41 +6818,23 @@ (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH") -(define_insn "*bmi2_umulditi3_1" - [(set (match_operand:DI 0 "register_operand" "=r") - (mult:DI - (match_operand:DI 2 "nonimmediate_operand" "%d") - (match_operand:DI 3 "nonimmediate_operand" "rm"))) - (set (match_operand:DI 1 "register_operand" "=r") - (truncate:DI - (lshiftrt:TI - (mult:TI (zero_extend:TI (match_dup 2)) - (zero_extend:TI (match_dup 3))) - (const_int 64))))] - "TARGET_64BIT && TARGET_BMI2 - && !(MEM_P (operands[1]) && MEM_P (operands[2]))" - "mulx\t{%3, %0, %1|%1, %0, %3}" - [(set_attr "type" "imulx") - (set_attr "prefix" "vex") - (set_attr "mode" "DI")]) - -(define_insn "*bmi2_umulsidi3_1" - [(set (match_operand:SI 0 "register_operand" "=r") - (mult:SI - (match_operand:SI 2 "nonimmediate_operand" "%d") - (match_operand:SI 3 "nonimmediate_operand" "rm"))) - (set (match_operand:SI 1 "register_operand" "=r") - (truncate:SI - (lshiftrt:DI - (mult:DI (zero_extend:DI (match_dup 2)) - (zero_extend:DI (match_dup 3))) - (const_int 32))))] - "!TARGET_64BIT && TARGET_BMI2 +(define_insn "*bmi2_umul<mode><dwi>3_1" + [(set (match_operand:DWIH 0 "register_operand" "=r") + (mult:DWIH + (match_operand:DWIH 2 "nonimmediate_operand" "%d") + (match_operand:DWIH 3 "nonimmediate_operand" "rm"))) + (set (match_operand:DWIH 1 "register_operand" "=r") + (truncate:DWIH + (lshiftrt:<DWI> + (mult:<DWI> (zero_extend:<DWI> (match_dup 2)) + (zero_extend:<DWI> (match_dup 3))) + (match_operand:QI 4 "const_int_operand" "n"))))] + "TARGET_BMI2 && INTVAL (operands[4]) == <MODE_SIZE> * BITS_PER_UNIT && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "mulx\t{%3, %0, %1|%1, %0, %3}" [(set_attr "type" "imulx") (set_attr "prefix" "vex") - (set_attr "mode" "SI")]) + (set_attr "mode" "<MODE>")]) (define_insn "*umul<mode><dwi>3_1" [(set (match_operand:<DWI> 0 "register_operand" "=r,A") @@ -6902,7 +6884,7 @@ { split_double_mode (<DWI>mode, &operands[0], 1, &operands[3], &operands[4]); - operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)); + operands[5] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT); }) (define_insn "*mul<mode><dwi>3_1" |