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authorfjahanian <fjahanian@138bc75d-0d04-0410-961f-82ee72b054a4>2005-02-25 01:16:17 +0000
committerfjahanian <fjahanian@138bc75d-0d04-0410-961f-82ee72b054a4>2005-02-25 01:16:17 +0000
commit521f3adaa1baeaf00caf66ecb1761b845c1bcea7 (patch)
tree12ca1094d0607528e394f1a9cef736ad98176069 /gcc/config
parent57ccc2cd9054d617016d305b0f7a4b07b4a42d61 (diff)
downloadgcc-521f3adaa1baeaf00caf66ecb1761b845c1bcea7.tar.gz
config/rs6000/rs6000.c (rs6000_legitimize_reload_address): Check for
vector types if to use base reg for misaligned non-word ld/std. OKed by David Edelsohn. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@95529 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/rs6000/rs6000.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index ea5c0108413..e07ac501107 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -3881,6 +3881,7 @@ rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
&& REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& (INTVAL (XEXP (x, 1)) & 3) != 0
+ && !ALTIVEC_VECTOR_MODE (mode)
&& GET_MODE_SIZE (mode) >= UNITS_PER_WORD
&& TARGET_POWERPC64)
{