diff options
| author | jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-01-28 10:08:57 +0000 |
|---|---|---|
| committer | jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-01-28 10:08:57 +0000 |
| commit | 260d579bfd5550f6f48e118ef745bcf19cd5bcb5 (patch) | |
| tree | e9c6db6078e8cd30188cc138806e52646f4177e5 /gcc/config | |
| parent | ac64c2700c1327e13d6ba142b1a7bba466a4e280 (diff) | |
| download | gcc-260d579bfd5550f6f48e118ef745bcf19cd5bcb5.tar.gz | |
[Patch AArch64] Make integer vabs intrinsics UNSPECs
gcc/
* config/aarch64/aarch64-simd.md (aarch64_abs<mode>): New.
* config/aarch64/aarch64-simd-builtins.def (abs): Split by
integer and floating point variants.
* config/aarch64/iterators.md (unspec): Add UNSPEC_ABS.
gcc/testsuite/
* gcc.target/aarch64/abs_2.c: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@220202 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd-builtins.def | 3 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 13 | ||||
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 1 |
3 files changed, 16 insertions, 1 deletions
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 1a1520c465b..2c52b27be71 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -358,7 +358,8 @@ /* Implemented by a mixture of abs2 patterns. Note the DImode builtin is only ever used for the int64x1_t intrinsic, there is no scalar version. */ - BUILTIN_VALLDI (UNOP, abs, 2) + BUILTIN_VSDQ_I_DI (UNOP, abs, 0) + BUILTIN_VDQF (UNOP, abs, 2) VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf) VAR1 (BINOP, float_truncate_hi_, 0, v4sf) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 17ac56c010f..055757036d5 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -384,6 +384,19 @@ [(set_attr "type" "neon_abs<q>")] ) +;; The intrinsic version of integer ABS must not be allowed to +;; combine with any operation with an integerated ABS step, such +;; as SABD. +(define_insn "aarch64_abs<mode>" + [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w") + (unspec:VSDQ_I_DI + [(match_operand:VSDQ_I_DI 1 "register_operand" "w")] + UNSPEC_ABS))] + "TARGET_SIMD" + "abs\t%<v>0<Vmtype>, %<v>1<Vmtype>" + [(set_attr "type" "neon_abs<q>")] +) + (define_insn "abd<mode>_3" [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w") (abs:VDQ_BHSI (minus:VDQ_BHSI diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 65a2849155c..1fdff040d1a 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -184,6 +184,7 @@ [ UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md. UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md. + UNSPEC_ABS ; Used in aarch64-simd.md. UNSPEC_FMAX ; Used in aarch64-simd.md. UNSPEC_FMAXNMV ; Used in aarch64-simd.md. UNSPEC_FMAXV ; Used in aarch64-simd.md. |