* Makefile.in (BUILD_RTL): Replace $(BUILD_PREFIX)insn-modes.o

	with min-insn-modes.o.
	(STAGESTUFF): Add min-insn-modes.c.
	(genobjs): Add genmodes.o.
	(print-rtl.o, print-rtl1.o): Depend on $(TM_P_H).
	(insn-modes.o): Depend on $(TM_H) not $(GTM_H); also real.h.
	(min-insn-modes.c, min-insn-modes.o): New rules.
	(s-modes): Also generate min-insn-modes.c.
	($(BUILD_PREFIX_1)insn-modes.o): Kill.
	* genmodes.c (struct mode_data): Add format field.
	(blank_mode, validate_mode, complete_mode): Update to match.
	(make_scalar_mode): Separate into make_int_mode and make_float_mode.
	(_SCALAR_MODE): Kill.
	(FLOAT_MODE, FRACTIONAL_FLOAT_MODE): Add format argument.
	(emit_insn_modes_c_header): Adjust.
	(emit_min_insn_modes_c_header, emit_real_format_for_mode)
	(emit_min_insn_modes_c): New functions.
	(emit_insn_modes_c): Call emit_real_format_for_mode.
	(main): Add -m option to generate min-insn-modes.c.
	* machmode.h: Update documentation.  Add format argument to
	all uses of FLOAT_MODE.
	* real.c: Don't define real_format_for_mode here.

	* dwarfout.c: Move default definition of PRINT_REG...
	* defaults.h: ...here.
	* print-rtl.c: Include tm_p.h.
	(DEBUG_PRINT_REG, DEBUG_REGISTER_NAMES, debug_reg_names, reg_names):
	Kill.
	(print_rtx): Use PRINT_REG, not DEBUG_PRINT_REG.  But surround
	this entire block with #ifndef GENERATOR_FILE.
	* regclass.c: Unconditionally define reg_names.
	* config/mips/mips.h, config/rs6000/rs6000.h, config/sh/sh.h
	Don't define DEBUG_REGISTER_NAMES.
	* config/rs6000/darwin.h: Don't use DEBUG_REGISTER_NAMES in
	redefinition of REGISTER_NAMES.
	* config/i386/i386.h: Don't define DEBUG_PRINT_REG.

	* combine.c: Change all preprocessor conditionals on
	EXTRA_CC_MODES to use SELECT_CC_MODE instead; rearrange a bit
	for clarity.
	* genopinit.c: Remove mention of EXTRA_CC_MODES in comment.
	* configure.in: Don't define EXTRA_CC_MODES.
	* configure, config.in: Regenerate.
	* doc/tm.texi: Remove documentation of EXTRA_CC_MODES.

	* config/arc/arc.c, config/m32r/m32r.c, config/sparc/sparc.c:
	May assume that GET_MODE_CLASS is accurate for extra CC modes
	at all times.

	* config/i860/i860.h (INIT_CUMULATIVE_ARGS): Pass correct
	number of arguments to aggregate_value_p.

	* genmodes.c (RESET_FLOAT_FORMAT, reset_float_format): New.
	* machmode.def: Explain ARCH-modes.def.  Document
	RESET_FLOAT_FORMAT.  Improve commentary on various mode
	clusters.  Do not define OI, PQI, PHI, PSI, PDI, QF, HF, TQF,
	XF, or TF modes here.  Remove backward-compatibility
	definition of CC.

	* config/alpha/alpha-modes.def: New file; define TF mode.
	* config/arc/arm-modes.def: Define XF mode.
	* config/c4x/c4x-modes.def: Define QF and HF modes.  Unset
	float format for SF and DF modes.
	* config/dsp16xx/dsp16xx-modes.def: New file; define HF mode.
	* config/i386/i386-modes.def: Define XF and TF modes.
	* config/i960/i960-modes.def: Define TF mode.
	* config/ia64/ia64-modes.def: Define TF and OI modes.
	* config/m68k/m68k-modes.def: New file; define XF mode.
	* config/mips/mips-modes.def: New file; define TF mode, reset
	formats for SF and DF modes.
	* config/pa/pa-modes.def: Define TF mode.
	* config/rs6000/rs6000.c: Define TF and PSI modes.
	* config/s390/s390-modes.def: Define OI mode.
	* config/sh/sh-modes.def: New file; define PSI mode.
	* config/sparc/sparc-modes.def: Define TF mode.
	* config/vax/vax-modes.def: New file; reset formats for SF and
	DF modes.

	* config/c4x/c4x.c (c4x_override_options): No need to mess
	with real_format_for_mode or set REAL_MODE_FORMATs.
	(c4x_immed_int_constant): Don't apply GET_MODE_CLASS to rtx
	variable.
	* config/i386/i386.c (override_options): No need to set
	REAL_MODE_FORMATs here.
	* config/i960/i960.c (i960_initialize): Likewise.
	* config/m68k/m68k.c (m68k_override_options): Likewise.
	* config/ia64/ia64.c (ia64_override_options): Set REAL_MODE_FORMAT
	for TFmode only if not the default.
	* config/mips/mips.c (override_options): Likewise.
	* config/vax/vax.c (override_optionms): Set REAL_MODE_FORMAT for
	DFmode only if not the default.

	* config/i370/i370.h (RET_REG): Don't consider TFmode.
	* config/m68hc11/m68hc11.c (print_operand): Don't consider XFmode.
	* config/dsp16xx/dsp16xx.c (hard_regno_mode_ok): #if 0 out use
	of modes that don't appear anywhere in the machine description.

	* config/arc/arc-modes.def, config/arm/arm-modes.def
	* config/c4x/c4x-modes.def, config/frv/frv-modes.def
	* config/i386/i386-modes.def, config/i960/i960-modes.def
	* config/ia64/ia64-modes.def, config/mmix/mmix-modes.def
	* config/pa/pa-modes.def, config/pdp11/pdp11-modes.def
	* config/rs6000/rs6000-modes.def, config/s390/s390-modes.def
	* config/sparc/sparc-modes.def: Convert to new style for
	declaring extra CC modes.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@72440 138bc75d-0d04-0410-961f-82ee72b054a4

37 files changed, 292 insertions, 178 deletions

diff --git a/gcc/config/alpha/alpha-modes.def b/gcc/config/alpha/alpha-modes.def
new file mode 100644
index 00000000000..b3747a1dae8
--- /dev/null
+++ b/gcc/config/alpha/alpha-modes.def
@@ -0,0 +1,23 @@
+/* Alpha extra machine modes. 
+   Copyright (C) 2003 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* 128-bit floating point.  This gets reset in alpha_override_options
+   if VAX float format is in use. */
+FLOAT_MODE (TF, 16, ieee_quad_format);
diff --git a/gcc/config/arc/arc-modes.def b/gcc/config/arc/arc-modes.def
index 57624dc85b8..692a1e60fa5 100644
--- a/gcc/config/arc/arc-modes.def
+++ b/gcc/config/arc/arc-modes.def
@@ -21,5 +21,5 @@ Boston, MA 02111-1307, USA.  */
 /* Some insns set all condition code flags, some only set the ZNC flags, and
    some only set the ZN flags.  */
 
-CC (CCZNC)
-CC (CCZN)
+CC_MODE (CCZNC);
+CC_MODE (CCZN);
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index dae43e7c30f..4e2022e5111 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -320,13 +320,10 @@ arc_init_reg_tables ()
 	    arc_mode_class[i] = 0;
 	  break;
 	case MODE_CC:
+	  arc_mode_class[i] = 1 << (int) C_MODE;
+	  break;
 	default:
-	  /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
-	     we must explicitly check for them here.  */
-	  if (i == (int) CCmode || i == (int) CCZNmode || i == (int) CCZNCmode)
-	    arc_mode_class[i] = 1 << (int) C_MODE;
-	  else
-	    arc_mode_class[i] = 0;
+	  arc_mode_class[i] = 0;
 	  break;
 	}
     }
diff --git a/gcc/config/arm/arm-modes.def b/gcc/config/arm/arm-modes.def
index 6a32509e4cb..154d3220689 100644
--- a/gcc/config/arm/arm-modes.def
+++ b/gcc/config/arm/arm-modes.def
@@ -22,25 +22,29 @@
    the Free Software Foundation, 59 Temple Place - Suite 330,
    Boston, MA 02111-1307, USA.  */
 
+/* Extended precision floating point.
+   FIXME What format is this?  */
+FLOAT_MODE (XF, 12, 0);
+
 /* CCFPEmode should be used with floating inequalities,
    CCFPmode should be used with floating equalities.
    CC_NOOVmode should be used with SImode integer equalities.
    CC_Zmode should be used if only the Z flag is set correctly
    CCmode should be used otherwise. */
 
-CC (CC_NOOV)
-CC (CC_Z)
-CC (CC_SWP)
-CC (CCFP)
-CC (CCFPE)
-CC (CC_DNE)
-CC (CC_DEQ)
-CC (CC_DLE)
-CC (CC_DLT)
-CC (CC_DGE)
-CC (CC_DGT)
-CC (CC_DLEU)
-CC (CC_DLTU)
-CC (CC_DGEU)
-CC (CC_DGTU)
-CC (CC_C)
+CC_MODE (CC_NOOV);
+CC_MODE (CC_Z);
+CC_MODE (CC_SWP);
+CC_MODE (CCFP);
+CC_MODE (CCFPE);
+CC_MODE (CC_DNE);
+CC_MODE (CC_DEQ);
+CC_MODE (CC_DLE);
+CC_MODE (CC_DLT);
+CC_MODE (CC_DGE);
+CC_MODE (CC_DGT);
+CC_MODE (CC_DLEU);
+CC_MODE (CC_DLTU);
+CC_MODE (CC_DGEU);
+CC_MODE (CC_DGTU);
+CC_MODE (CC_C);
diff --git a/gcc/config/c4x/c4x-modes.def b/gcc/config/c4x/c4x-modes.def
index be536e05645..adf691a023a 100644
--- a/gcc/config/c4x/c4x-modes.def
+++ b/gcc/config/c4x/c4x-modes.def
@@ -21,6 +21,14 @@
    the Free Software Foundation, 59 Temple Place - Suite 330,
    Boston, MA 02111-1307, USA.  */
 
+/* C4x wants 1- and 2-word float modes, in its own peculiar format.
+   FIXME: Give this port a way to get rid of SFmode, DFmode, and all
+   the other modes it doesn't use.  */
+FLOAT_MODE (QF, 1, c4x_single_format);
+FLOAT_MODE (HF, 2, c4x_extended_format);
+RESET_FLOAT_FORMAT (SF, 0);  /* not used */
+RESET_FLOAT_FORMAT (DF, 0);  /* not used */
+
 /* Add any extra modes needed to represent the condition code.
 
    On the C4x, we have a "no-overflow" mode which is used when an ADD,
@@ -98,5 +106,4 @@
    load instructions after an add, subtract, neg, abs or multiply.
    We must emit a compare insn to check the result against 0.  */
 
-CC (CC_NOOV)
-
+CC_MODE (CC_NOOV);
diff --git a/gcc/config/c4x/c4x.c b/gcc/config/c4x/c4x.c
index a50cbb8a88c..7fb5a337b41 100644
--- a/gcc/config/c4x/c4x.c
+++ b/gcc/config/c4x/c4x.c
@@ -314,11 +314,6 @@ c4x_override_options (void)
      This provides compatibility with the old -mno-aliases option.  */
   if (! TARGET_ALIASES && ! flag_argument_noalias)
     flag_argument_noalias = 1;
-
-  /* We're C4X floating point, not IEEE floating point.  */
-  memset (real_format_for_mode, 0, sizeof real_format_for_mode);
-  REAL_MODE_FORMAT (QFmode) = &c4x_single_format;
-  REAL_MODE_FORMAT (HFmode) = &c4x_extended_format;
 }
 
 
@@ -2464,8 +2459,8 @@ c4x_immed_int_constant (rtx op)
     return 0;
 
   return GET_MODE (op) == VOIDmode
-    || GET_MODE_CLASS (op) == MODE_INT
-    || GET_MODE_CLASS (op) == MODE_PARTIAL_INT;
+    || GET_MODE_CLASS (GET_MODE (op)) == MODE_INT
+    || GET_MODE_CLASS (GET_MODE (op)) == MODE_PARTIAL_INT;
 }
 
 
diff --git a/gcc/config/dsp16xx/dsp16xx-modes.def b/gcc/config/dsp16xx/dsp16xx-modes.def
new file mode 100644
index 00000000000..968e271ff44
--- /dev/null
+++ b/gcc/config/dsp16xx/dsp16xx-modes.def
@@ -0,0 +1,23 @@
+/* DSP16xx extra modes.
+   Copyright (C) 2003 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* HFmode is the DSP16xx's equivalent of SFmode.
+   FIXME: What format is this anyway? */ 
+FLOAT_MODE (HF, 2, 0);
diff --git a/gcc/config/dsp16xx/dsp16xx.c b/gcc/config/dsp16xx/dsp16xx.c
index d858706149f..dcfbc7e6853 100644
--- a/gcc/config/dsp16xx/dsp16xx.c
+++ b/gcc/config/dsp16xx/dsp16xx.c
@@ -203,12 +203,15 @@ hard_regno_mode_ok (regno, mode)
 	 modes.  */
       
     case HFmode:
+    case HImode:
+#if 0 /* ??? These modes do not appear in the machine description nor
+         are there library routines for them.  */
     case SFmode:
     case DFmode:
     case XFmode:
-    case HImode:
     case SImode:
     case DImode:
+#endif
       if (regno == REG_A0 || regno == REG_A1 || regno == REG_Y || regno == REG_PROD
 	  || (IS_YBASE_REGISTER_WINDOW(regno) && ((regno & 1) == 0)))
 	return 1;
diff --git a/gcc/config/frv/frv-modes.def b/gcc/config/frv/frv-modes.def
index 1a8bd50c38a..3985099a91c 100644
--- a/gcc/config/frv/frv-modes.def
+++ b/gcc/config/frv/frv-modes.def
@@ -25,6 +25,6 @@ Boston, MA 02111-1307, USA.  */
    CC_FPmode	set FCC's from comparing floating point
    CC_CCRmode	set CCR's to do conditional execution */
 
-CC (CC_UNS)
-CC (CC_FP)
-CC (CC_CCR)
+CC_MODE (CC_UNS);
+CC_MODE (CC_FP);
+CC_MODE (CC_CCR);
diff --git a/gcc/config/i370/i370.h b/gcc/config/i370/i370.h
index f02d8735cf2..8109ddedc2e 100644
--- a/gcc/config/i370/i370.h
+++ b/gcc/config/i370/i370.h
@@ -570,7 +570,8 @@ enum reg_class
  */
 
 #define RET_REG(MODE)	\
-    (((MODE) == DCmode || (MODE) == SCmode || (MODE) == TFmode || (MODE) == DFmode || (MODE) == SFmode) ? 16 : 15)
+    (((MODE) == DCmode || (MODE) == SCmode \
+      || (MODE) == DFmode || (MODE) == SFmode) ? 16 : 15)
 
 #define FUNCTION_VALUE(VALTYPE, FUNC)  					\
   gen_rtx_REG (TYPE_MODE (VALTYPE), RET_REG (TYPE_MODE (VALTYPE)))
diff --git a/gcc/config/i386/i386-modes.def b/gcc/config/i386/i386-modes.def
index 485db6a86bb..ddfc5cfcf52 100644
--- a/gcc/config/i386/i386-modes.def
+++ b/gcc/config/i386/i386-modes.def
@@ -18,6 +18,12 @@ along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
+/* By default our XFmode is the 80-bit extended format.  If we use
+   TFmode instead, it's also the 80-bit format, but with padding. */
+
+FLOAT_MODE (XF, 12, ieee_extended_intel_96_format);
+FLOAT_MODE (TF, 16, ieee_extended_intel_128_format);
+
 /* Add any extra modes needed to represent the condition code.
 
    For the i386, we need separate modes when floating-point
@@ -38,9 +44,9 @@ Boston, MA 02111-1307, USA.  */
 
    Add CCZ to indicate that only the Zero flag is valid.  */
 
-CC (CCGC)
-CC (CCGOC)
-CC (CCNO)
-CC (CCZ)
-CC (CCFP)
-CC (CCFPU)
+CC_MODE (CCGC);
+CC_MODE (CCGOC);
+CC_MODE (CCNO);
+CC_MODE (CCZ);
+CC_MODE (CCFP);
+CC_MODE (CCFPU);
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 03f2be754ac..dbdb194fc74 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1111,11 +1111,6 @@ override_options (void)
 
   int const pta_size = ARRAY_SIZE (processor_alias_table);
 
-  /* By default our XFmode is the 80-bit extended format.  If we have
-     use TFmode instead, it's also the 80-bit format, but with padding.  */
-  REAL_MODE_FORMAT (XFmode) = &ieee_extended_intel_96_format;
-  REAL_MODE_FORMAT (TFmode) = &ieee_extended_intel_128_format;
-
   /* Set the default values for switches whose default depends on TARGET_64BIT
      in case they weren't overwritten by command line options.  */
   if (TARGET_64BIT)
diff --git a/gcc/config/i860/i860.h b/gcc/config/i860/i860.h
index 11aa529104e..b5575ec7f1c 100644
--- a/gcc/config/i860/i860.h
+++ b/gcc/config/i860/i860.h
@@ -465,7 +465,7 @@ struct cumulative_args { int ints, floats; };
    invisible first argument.  */
 
 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)	\
- ((CUM).ints = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE ((FNTYPE))) \
+ ((CUM).ints = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE ((FNTYPE)), 0) \
 		? 4 : 0),			\
   (CUM).floats = 0)
 
diff --git a/gcc/config/i960/i960-modes.def b/gcc/config/i960/i960-modes.def
index f42b7456ca1..e99939049c6 100644
--- a/gcc/config/i960/i960-modes.def
+++ b/gcc/config/i960/i960-modes.def
@@ -21,10 +21,13 @@ along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
+/* long double */
+FLOAT_MODE (TF, 16, ieee_extended_intel_128_format);
+
 /* Add any extra modes needed to represent the condition code.
 
    Also, signed and unsigned comparisons are distinguished, as
    are operations which are compatible with chkbit insns.  */
 
-CC (CC_UNS)
-CC (CC_CHK)
+CC_MODE (CC_UNS);
+CC_MODE (CC_CHK);
diff --git a/gcc/config/i960/i960.c b/gcc/config/i960/i960.c
index f62693a9176..c1284f48da3 100644
--- a/gcc/config/i960/i960.c
+++ b/gcc/config/i960/i960.c
@@ -167,9 +167,6 @@ i960_initialize ()
       i960_maxbitalignment = 128;
       i960_last_maxbitalignment = 8;
     }
-
-  /* Tell the compiler which flavor of TFmode we're using.  */
-  REAL_MODE_FORMAT (TFmode) = &ieee_extended_intel_128_format;
 }
 
 /* Return true if OP can be used as the source of an fp move insn.  */
diff --git a/gcc/config/ia64/ia64-modes.def b/gcc/config/ia64/ia64-modes.def
index b46303f9d59..f6d662fdd21 100644
--- a/gcc/config/ia64/ia64-modes.def
+++ b/gcc/config/ia64/ia64-modes.def
@@ -20,10 +20,16 @@ along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
+/* hpux will override this in ia64_override_options.  */
+FLOAT_MODE (TF, 16, ieee_extended_intel_128_format);
+
+/* 256-bit integer mode is needed for STACK_SAVEAREA_MODE.  */
+INT_MODE (OI, 32);
+
 /* Add any extra modes needed to represent the condition code.
 
    CCImode is used to mark a single predicate register instead
    of a register pair.  This is currently only used in reg_raw_mode
    so that flow doesn't do something stupid.  */
 
-CC (CCI)
+CC_MODE (CCI);
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 32e3c8b8e7b..b9a4537a301 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -4522,8 +4522,8 @@ ia64_override_options (void)
   init_machine_status = ia64_init_machine_status;
 
   /* Tell the compiler which flavor of TFmode we're using.  */
-  if (INTEL_EXTENDED_IEEE_FORMAT)
-    REAL_MODE_FORMAT (TFmode) = &ieee_extended_intel_128_format;
+  if (!INTEL_EXTENDED_IEEE_FORMAT)
+    REAL_MODE_FORMAT (TFmode) = &ieee_quad_format;
 }
 
 static enum attr_itanium_class ia64_safe_itanium_class (rtx);
diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c
index 1ce6b5b60c2..dfea2fc74be 100644
--- a/gcc/config/m32r/m32r.c
+++ b/gcc/config/m32r/m32r.c
@@ -249,13 +249,10 @@ init_reg_tables ()
 	    m32r_mode_class[i] = 0;
 	  break;
 	case MODE_CC:
+	  m32r_mode_class[i] = 1 << (int) C_MODE;
+	  break;
 	default:
-	  /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
-	     we must explicitly check for them here.  */
-	  if (i == (int) CCmode)
-	    m32r_mode_class[i] = 1 << (int) C_MODE;
-	  else
-	    m32r_mode_class[i] = 0;
+	  m32r_mode_class[i] = 0;
 	  break;
 	}
     }
diff --git a/gcc/config/m68hc11/m68hc11.c b/gcc/config/m68hc11/m68hc11.c
index 51267214a9e..3f1cb4f9941 100644
--- a/gcc/config/m68hc11/m68hc11.c
+++ b/gcc/config/m68hc11/m68hc11.c
@@ -2337,8 +2337,7 @@ print_operand (file, op, letter)
       REAL_VALUE_TO_TARGET_SINGLE (r, l);
       asm_fprintf (file, "%I0x%lx", l);
     }
-  else if (GET_CODE (op) == CONST_DOUBLE
-	   && (GET_MODE (op) == DFmode || GET_MODE (op) == XFmode))
+  else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
     {
       char dstr[30];
 
diff --git a/gcc/config/m68k/m68k-modes.def b/gcc/config/m68k/m68k-modes.def
new file mode 100644
index 00000000000..b0ee6208c37
--- /dev/null
+++ b/gcc/config/m68k/m68k-modes.def
@@ -0,0 +1,22 @@
+/* M68k extra machine modes. 
+   Copyright (C) 2003 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* 80-bit floating point (IEEE extended, in a 96-bit field) */
+FLOAT_MODE (XF, 12, ieee_extended_motorola_format);
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index e2215d17817..00fd0ea0851 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -290,9 +290,6 @@ override_options (void)
     flag_no_function_cse = 1;
 
   SUBTARGET_OVERRIDE_OPTIONS;
-
-  /* Tell the compiler which flavor of XFmode we're using.  */
-  REAL_MODE_FORMAT (XFmode) = &ieee_extended_motorola_format;
 }
 
 /* Return nonzero if FUNC is an interrupt function as specified by the
diff --git a/gcc/config/mips/mips-modes.def b/gcc/config/mips/mips-modes.def
new file mode 100644
index 00000000000..b74297124df
--- /dev/null
+++ b/gcc/config/mips/mips-modes.def
@@ -0,0 +1,27 @@
+/* MIPS extra machine modes. 
+   Copyright (C) 2003 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* MIPS has a quirky almost-IEEE format for all its
+   floating point.  */
+RESET_FLOAT_FORMAT (SF, mips_single_format);
+RESET_FLOAT_FORMAT (DF, mips_double_format);
+
+/* Irix6 will override this via MIPS_TFMODE_FORMAT.  */
+FLOAT_MODE (TF, 16, mips_quad_format);
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 06b40a3052c..71fd880ec6d 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -4856,12 +4856,8 @@ override_options (void)
       flag_delayed_branch = 0;
     }
 
-  REAL_MODE_FORMAT (SFmode) = &mips_single_format;
-  REAL_MODE_FORMAT (DFmode) = &mips_double_format;
 #ifdef MIPS_TFMODE_FORMAT
   REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
-#else
-  REAL_MODE_FORMAT (TFmode) = &mips_quad_format;
 #endif
 
   mips_print_operand_punct['?'] = 1;
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 5ea19a821a0..2e5fb7a39b3 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -3029,34 +3029,6 @@ typedef struct mips_args {
   &mips_reg_names[175][0]						\
 }
 
-/* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
-   So define this for it.  */
-#define DEBUG_REGISTER_NAMES						\
-{									\
-  "$0",   "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",		\
-  "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",		\
-  "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",		\
-  "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "$fp",  "ra",		\
-  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",	\
-  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",	\
-  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",	\
-  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",	\
-  "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",	\
-  "$fcc5","$fcc6","$fcc7","$rap", "",     "",     "",     "",		\
-  "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
-  "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
-  "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
-  "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
-  "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
-  "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
-  "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
-  "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
-  "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
-  "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
-  "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
-  "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
-}
-
 /* If defined, a C initializer for an array of structures
    containing a name and a register number.  This macro defines
    additional names for hard registers, thus allowing the `asm'
diff --git a/gcc/config/mmix/mmix-modes.def b/gcc/config/mmix/mmix-modes.def
index 001a04dce77..e4ebb30565e 100644
--- a/gcc/config/mmix/mmix-modes.def
+++ b/gcc/config/mmix/mmix-modes.def
@@ -32,19 +32,19 @@ Boston, MA 02111-1307, USA.  */
 
 /* The CC_UNS mode is for an unsigned operands integer comparison using
    the CMPU insn.  Result values correspond to those in CCmode.  */
-CC (CC_UNS)
+CC_MODE (CC_UNS);
 
 /* The CC_FP mode is for a non-equality floating-point comparison, using
    the FCMP or FCMPE insn.  The result is (integer) -1 or 1 for
    espectively a < b and a > b, otherwise 0.  */
-CC (CC_FP)
+CC_MODE (CC_FP);
 
 /* The CC_FPEQ mode is for an equality floating-point comparison, using
    the FEQL or FEQLE insn.  The result is (integer) 1 for a == b,
    otherwise 0 (including NaN:s).  */
-CC (CC_FPEQ)
+CC_MODE (CC_FPEQ);
 
 /* The CC_FUN mode is for an ordering comparison, using the FUN or FUNE
    insn.  The result is (integer) 1 if a is unordered to b, otherwise the
    result is 0.  */
-CC (CC_FUN)
+CC_MODE (CC_FUN);
diff --git a/gcc/config/pa/pa-modes.def b/gcc/config/pa/pa-modes.def
index c57c9bc4bc9..a68453df1f1 100644
--- a/gcc/config/pa/pa-modes.def
+++ b/gcc/config/pa/pa-modes.def
@@ -21,10 +21,8 @@ along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-/* Add any extra modes needed to represent the condition code.
-
-   HPPA floating comparisons produce condition codes.  */
-
-CC (CCFP)
-
+/* TFmode: IEEE quad floating point (software).  */
+FLOAT_MODE (TF, 16, ieee_quad_format);
 
+/* HPPA floating comparisons produce distinct condition codes.  */
+CC_MODE (CCFP);
diff --git a/gcc/config/pdp11/pdp11-modes.def b/gcc/config/pdp11/pdp11-modes.def
index 0071b0b5851..da083ad24a8 100644
--- a/gcc/config/pdp11/pdp11-modes.def
+++ b/gcc/config/pdp11/pdp11-modes.def
@@ -22,5 +22,4 @@ Boston, MA 02111-1307, USA.  */
 /* Add any extra modes needed to represent the condition code.
    CCFPmode is used for FPU, but should we use a separate reg? */
 
-CC (CCFP)
-
+CC_MODE (CCFP);
diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h
index 4722826d691..15e3f24c336 100644
--- a/gcc/config/rs6000/darwin.h
+++ b/gcc/config/rs6000/darwin.h
@@ -141,11 +141,29 @@ do {									\
 #undef	FP_SAVE_INLINE
 #define FP_SAVE_INLINE(FIRST_REG) ((FIRST_REG) < 64)
 
-/* Always use the "debug" register names, they're what the assembler
-   wants to see.  */
-
+/* The assembler wants the alternate register names, but without
+   leading percent sign.  */
 #undef REGISTER_NAMES
-#define REGISTER_NAMES DEBUG_REGISTER_NAMES
+#define REGISTER_NAMES							\
+{									\
+     "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",		\
+     "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15",		\
+    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",		\
+    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",		\
+     "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",		\
+     "f8",  "f9", "f10", "f11", "f12", "f13", "f14", "f15",		\
+    "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",		\
+    "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",		\
+     "mq",  "lr", "ctr",  "ap",						\
+    "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",		\
+    "xer",								\
+     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",             \
+     "v8",  "v9", "v10", "v11", "v12", "v13", "v14", "v15",             \
+    "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",             \
+    "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",             \
+    "vrsave", "vscr",							\
+    "spe_acc", "spefscr"                                                \
+}
 
 /* This outputs NAME to FILE.  */
 
diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def
index 5faa72671df..1b6aa481fee 100644
--- a/gcc/config/rs6000/rs6000-modes.def
+++ b/gcc/config/rs6000/rs6000-modes.def
@@ -19,6 +19,15 @@
    Free Software Foundation, 59 Temple Place - Suite 330, Boston,
    MA 02111-1307, USA.  */
 
+/* 128-bit floating point.  ABI_V4 uses IEEE quad, AIX/Darwin
+   adjust this in rs6000_override_options. */
+FLOAT_MODE (TF, 16, ieee_quad_format);
+
+/* PSImode is used for the XER register.  The XER register
+   is not used for anything; perhaps it should be deleted,
+   except that that would change register numbers.  */
+PARTIAL_INT_MODE (SI);
+
 /* Add any extra modes needed to represent the condition code.
 
    For the RS/6000, we need separate modes when unsigned (logical) comparisons
@@ -26,6 +35,6 @@
    use a mode for the case when we are comparing the results of two
    comparisons, as then only the EQ bit is valid in the register.  */
 
-CC (CCUNS)
-CC (CCFP)
-CC (CCEQ)
+CC_MODE (CCUNS);
+CC_MODE (CCFP);
+CC_MODE (CCEQ);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index fbdb6a5c06b..3aa2de340f5 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2550,31 +2550,6 @@ extern char rs6000_reg_names[][8];	/* register names (0 vs. %r0).  */
   &rs6000_reg_names[112][0],	/* spefscr */				\
 }
 
-/* print-rtl can't handle the above REGISTER_NAMES, so define the
-   following for it.  Switch to use the alternate names since
-   they are more mnemonic.  */
-
-#define DEBUG_REGISTER_NAMES						\
-{									\
-     "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",		\
-     "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15",		\
-    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",		\
-    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",		\
-     "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",		\
-     "f8",  "f9", "f10", "f11", "f12", "f13", "f14", "f15",		\
-    "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",		\
-    "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",		\
-     "mq",  "lr", "ctr",  "ap",						\
-    "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",		\
-    "xer",								\
-     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",             \
-     "v8",  "v9", "v10", "v11", "v12", "v13", "v14", "v15",             \
-    "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",             \
-    "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",             \
-    "vrsave", "vscr",							\
-    "spe_acc", "spefscr"                                                \
-}
-
 /* Table of additional register names to use in user input.  */
 
 #define ADDITIONAL_REGISTER_NAMES \
diff --git a/gcc/config/s390/s390-modes.def b/gcc/config/s390/s390-modes.def
index c3649fa304e..08759558871 100644
--- a/gcc/config/s390/s390-modes.def
+++ b/gcc/config/s390/s390-modes.def
@@ -20,20 +20,23 @@ along with GCC; see the file COPYING.  If not, write to the Free
 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 02111-1307, USA.  */
 
+/* 256-bit integer mode is needed for STACK_SAVEAREA_MODE.  */
+INT_MODE (OI, 32);
+
 /* Add any extra modes needed to represent the condition code.  */
 
-CC (CCZ)
-CC (CCA)
-CC (CCAP)
-CC (CCAN)
-CC (CCL)
-CC (CCL1)
-CC (CCL2)
-CC (CCU)
-CC (CCUR)
-CC (CCS)
-CC (CCSR)
-CC (CCT)
-CC (CCT1)
-CC (CCT2)
-CC (CCT3)
+CC_MODE (CCZ);
+CC_MODE (CCA);
+CC_MODE (CCAP);
+CC_MODE (CCAN);
+CC_MODE (CCL);
+CC_MODE (CCL1);
+CC_MODE (CCL2);
+CC_MODE (CCU);
+CC_MODE (CCUR);
+CC_MODE (CCS);
+CC_MODE (CCSR);
+CC_MODE (CCT);
+CC_MODE (CCT1);
+CC_MODE (CCT2);
+CC_MODE (CCT3);
diff --git a/gcc/config/sh/sh-modes.def b/gcc/config/sh/sh-modes.def
new file mode 100644
index 00000000000..3906b4354c2
--- /dev/null
+++ b/gcc/config/sh/sh-modes.def
@@ -0,0 +1,23 @@
+/* Alpha extra machine modes. 
+   Copyright (C) 2003 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* The SH uses a partial integer mode to represent the FPSCR register.  */
+PARTIAL_INT_MODE (SI);
+
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index acd9650b254..4ccff4b3531 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -743,8 +743,6 @@ extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
   "rap"									\
 }
 
-#define DEBUG_REGISTER_NAMES SH_REGISTER_NAMES_INITIALIZER
-
 #define REGNAMES_ARR_INDEX_1(index) \
   (sh_register_names[index])
 #define REGNAMES_ARR_INDEX_2(index) \
diff --git a/gcc/config/sparc/sparc-modes.def b/gcc/config/sparc/sparc-modes.def
index 612ff0dbf85..ea2a99d5ae1 100644
--- a/gcc/config/sparc/sparc-modes.def
+++ b/gcc/config/sparc/sparc-modes.def
@@ -21,6 +21,9 @@ along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
+/* 128-bit floating point */
+FLOAT_MODE (TF, 16, ieee_quad_format);
+
 /* Add any extra modes needed to represent the condition code.
 
    On the SPARC, we have a "no-overflow" mode which is used when an add or
@@ -34,9 +37,8 @@ Boston, MA 02111-1307, USA.  */
 
    CCXmode and CCX_NOOVmode are only used by v9.  */
 
-CC (CCX)
-CC (CC_NOOV)
-CC (CCX_NOOV)
-CC (CCFP)
-CC (CCFPE)
-
+CC_MODE (CCX);
+CC_MODE (CC_NOOV);
+CC_MODE (CCX_NOOV);
+CC_MODE (CCFP);
+CC_MODE (CCFPE);
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index aeb6709923e..1332817e0fa 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -3954,16 +3954,13 @@ sparc_init_modes (void)
 	    sparc_mode_class[i] = 0;
 	  break;
 	case MODE_CC:
-	default:
-	  /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
-	     we must explicitly check for them here.  */
 	  if (i == (int) CCFPmode || i == (int) CCFPEmode)
 	    sparc_mode_class[i] = 1 << (int) CCFP_MODE;
-	  else if (i == (int) CCmode || i == (int) CC_NOOVmode
-		   || i == (int) CCXmode || i == (int) CCX_NOOVmode)
-	    sparc_mode_class[i] = 1 << (int) CC_MODE;
 	  else
-	    sparc_mode_class[i] = 0;
+	    sparc_mode_class[i] = 1 << (int) CC_MODE;
+	  break;
+	default:
+	  sparc_mode_class[i] = 0;
 	  break;
 	}
     }
diff --git a/gcc/config/vax/vax-modes.def b/gcc/config/vax/vax-modes.def
new file mode 100644
index 00000000000..5f137f9aca9
--- /dev/null
+++ b/gcc/config/vax/vax-modes.def
@@ -0,0 +1,23 @@
+/* VAX extra machine modes. 
+   Copyright (C) 2003 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* We just need to reset the floating point formats.  */
+RESET_FLOAT_FORMAT (SF, vax_f_format);
+RESET_FLOAT_FORMAT (DF, vax_d_format);
diff --git a/gcc/config/vax/vax.c b/gcc/config/vax/vax.c
index a4ec09191e6..dd22e33bbf7 100644
--- a/gcc/config/vax/vax.c
+++ b/gcc/config/vax/vax.c
@@ -85,9 +85,8 @@ void
 override_options (void)
 {
   /* We're VAX floating point, not IEEE floating point.  */
-  memset (real_format_for_mode, 0, sizeof real_format_for_mode);
-  REAL_MODE_FORMAT (SFmode) = &vax_f_format;
-  REAL_MODE_FORMAT (DFmode) = (TARGET_G_FLOAT ? &vax_g_format : &vax_d_format);
+  if (TARGET_G_FLOAT)
+    REAL_MODE_FORMAT (DFmode) = &vax_g_format;
 }
 
 /* Generate the assembly code for function entry.  FILE is a stdio