diff options
| author | kyukhin <kyukhin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-10-14 08:42:02 +0000 |
|---|---|---|
| committer | kyukhin <kyukhin@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-10-14 08:42:02 +0000 |
| commit | 2014445687c56665cdb14ddf1a14f2a377c0abde (patch) | |
| tree | d247bf83a7306a213fc399261ed59b40964edeeb /gcc/config | |
| parent | 2d71b728a7eae7cef35f125640d13a13be6746e7 (diff) | |
| download | gcc-2014445687c56665cdb14ddf1a14f2a377c0abde.tar.gz | |
AVX-512. 69/n. Add vpmulhrsw insn support.
gcc/
* config/i386/sse.md
(define_insn "avx512bw_umulhrswv32hi3<mask_name>"): New.
(define_expand "<ssse3_avx2>_pmulhrsw<mode>3_mask"): Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@216186 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/sse.md | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index c9173934585..30fc1dc5fa1 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -13273,6 +13273,41 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) +(define_insn "avx512bw_umulhrswv32hi3<mask_name>" + [(set (match_operand:V32HI 0 "register_operand" "=v") + (truncate:V32HI + (lshiftrt:V32SI + (plus:V32SI + (lshiftrt:V32SI + (mult:V32SI + (sign_extend:V32SI + (match_operand:V32HI 1 "nonimmediate_operand" "%v")) + (sign_extend:V32SI + (match_operand:V32HI 2 "nonimmediate_operand" "vm"))) + (const_int 14)) + (const_vector:V32HI [(const_int 1) (const_int 1) + (const_int 1) (const_int 1) + (const_int 1) (const_int 1) + (const_int 1) (const_int 1) + (const_int 1) (const_int 1) + (const_int 1) (const_int 1) + (const_int 1) (const_int 1) + (const_int 1) (const_int 1) + (const_int 1) (const_int 1) + (const_int 1) (const_int 1) + (const_int 1) (const_int 1) + (const_int 1) (const_int 1) + (const_int 1) (const_int 1) + (const_int 1) (const_int 1) + (const_int 1) (const_int 1) + (const_int 1) (const_int 1)])) + (const_int 1))))] + "TARGET_AVX512BW" + "vpmulhrsw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}" + [(set_attr "type" "sseimul") + (set_attr "prefix" "evex") + (set_attr "mode" "XI")]) + (define_insn "ssse3_pmaddubsw128" [(set (match_operand:V8HI 0 "register_operand" "=x,x") (ss_plus:V8HI @@ -13350,6 +13385,29 @@ (define_mode_iterator PMULHRSW [V4HI V8HI (V16HI "TARGET_AVX2")]) +(define_expand "<ssse3_avx2>_pmulhrsw<mode>3_mask" + [(set (match_operand:PMULHRSW 0 "register_operand") + (vec_merge:PMULHRSW + (truncate:PMULHRSW + (lshiftrt:<ssedoublemode> + (plus:<ssedoublemode> + (lshiftrt:<ssedoublemode> + (mult:<ssedoublemode> + (sign_extend:<ssedoublemode> + (match_operand:PMULHRSW 1 "nonimmediate_operand")) + (sign_extend:<ssedoublemode> + (match_operand:PMULHRSW 2 "nonimmediate_operand"))) + (const_int 14)) + (match_dup 5)) + (const_int 1))) + (match_operand:PMULHRSW 3 "register_operand") + (match_operand:<avx512fmaskmode> 4 "register_operand")))] + "TARGET_AVX512BW && TARGET_AVX512VL" +{ + operands[5] = CONST1_RTX(<MODE>mode); + ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands); +}) + (define_expand "<ssse3_avx2>_pmulhrsw<mode>3" [(set (match_operand:PMULHRSW 0 "register_operand") (truncate:PMULHRSW |