2010-03-03 Basile Starynkevitch <basile@starynkevitch.net>

	MELT branch merged with trunk rev 157193



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@157194 138bc75d-0d04-0410-961f-82ee72b054a4

23 files changed, 302 insertions, 140 deletions

diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index 450300050ae..88cb97c5c46 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -388,7 +388,7 @@ override_options (void)
 	    break;
 	  }
       if (i == ct_size)
-	error ("bad value %qs for -mcpu switch", alpha_tune_string);
+	error ("bad value %qs for -mtune switch", alpha_tune_string);
     }
 
   /* Do some sanity checks on the above options.  */
diff --git a/gcc/config/host-solaris.c b/gcc/config/host-solaris.c
index 3a367051125..1d51a8d2127 100644
--- a/gcc/config/host-solaris.c
+++ b/gcc/config/host-solaris.c
@@ -1,5 +1,5 @@
 /* Solaris host-specific hook definitions.
-   Copyright (C) 2004, 2007, 2008 Free Software Foundation, Inc.
+   Copyright (C) 2004, 2007, 2008, 2010 Free Software Foundation, Inc.
 
    This file is part of GCC.
 
@@ -25,9 +25,48 @@
 #include "hosthooks-def.h"
 
 
+#undef HOST_HOOKS_GT_PCH_GET_ADDRESS
+#define HOST_HOOKS_GT_PCH_GET_ADDRESS sol_gt_pch_get_address
 #undef HOST_HOOKS_GT_PCH_USE_ADDRESS
 #define HOST_HOOKS_GT_PCH_USE_ADDRESS sol_gt_pch_use_address
 
+/* For various ports, try to guess a fixed spot in the vm space
+   that's probably free.  Based on McDougall, Mauro, Solaris Internals, 2nd
+   ed., p.460-461, fig. 9-3, 9-4, 9-5.  */
+#if defined(__sparcv9__)
+/* This low to avoid VA hole on UltraSPARC I/II.  */
+# define TRY_EMPTY_VM_SPACE	0x70000000000
+#elif defined(__sparc__)
+# define TRY_EMPTY_VM_SPACE	0x80000000
+#elif defined(__x86_64__)
+# define TRY_EMPTY_VM_SPACE	0x8000000000000000
+#elif defined(__i386__)
+# define TRY_EMPTY_VM_SPACE	0xB0000000
+#else
+# define TRY_EMPTY_VM_SPACE	0
+#endif
+
+/* Determine a location where we might be able to reliably allocate
+   SIZE bytes.  FD is the PCH file, though we should return with the
+   file unmapped.  */
+
+static void *
+sol_gt_pch_get_address (size_t size, int fd)
+{
+  void *addr;
+
+  addr = mmap ((caddr_t) TRY_EMPTY_VM_SPACE, size, PROT_READ | PROT_WRITE,
+	       MAP_PRIVATE, fd, 0);
+
+  /* If we failed the map, that means there's *no* free space.  */
+  if (addr == (void *) MAP_FAILED)
+    return NULL;
+  /* Unmap the area before returning.  */
+  munmap ((caddr_t) addr, size);
+
+  return addr;
+}
+
 /* Map SIZE bytes of FD+OFFSET at BASE.  Return 1 if we succeeded at 
    mapping the data at BASE, -1 if we couldn't.  */
 
diff --git a/gcc/config/i386/darwin.h b/gcc/config/i386/darwin.h
index eb9ee70a04d..49863a6bab7 100644
--- a/gcc/config/i386/darwin.h
+++ b/gcc/config/i386/darwin.h
@@ -162,14 +162,12 @@ extern void darwin_x86_file_end (void);
 #undef TARGET_SUBTARGET32_ISA_DEFAULT
 #define TARGET_SUBTARGET32_ISA_DEFAULT (OPTION_MASK_ISA_MMX		\
 					| OPTION_MASK_ISA_SSE		\
-					| OPTION_MASK_ISA_SSE2)
-
-#undef TARGET_SUBTARGET64_ISA_DEFAULT
-#define TARGET_SUBTARGET64_ISA_DEFAULT (OPTION_MASK_ISA_MMX		\
-					| OPTION_MASK_ISA_SSE		\
 					| OPTION_MASK_ISA_SSE2		\
 					| OPTION_MASK_ISA_SSE3)
 
+#undef TARGET_SUBTARGET64_ISA_DEFAULT
+#define TARGET_SUBTARGET64_ISA_DEFAULT TARGET_SUBTARGET32_ISA_DEFAULT
+
 /* For now, disable dynamic-no-pic.  We'll need to go through i386.c
    with a fine-tooth comb looking for refs to flag_pic!  */
 #define MASK_MACHO_DYNAMIC_NO_PIC 0
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index f87eefc1073..3a3b2ac943b 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2621,6 +2621,7 @@ override_options (bool main_args_p)
 {
   int i;
   unsigned int ix86_arch_mask, ix86_tune_mask;
+  const bool ix86_tune_specified = (ix86_tune_string != NULL); 
   const char *prefix;
   const char *suffix;
   const char *sw;
@@ -2821,8 +2822,12 @@ override_options (bool main_args_p)
 		   || !strcmp (ix86_tune_string, "generic64")))
 	;
       else if (!strncmp (ix86_tune_string, "generic", 7))
-	error ("bad value (%s) for %stune=%s %s",
+        error ("bad value (%s) for %stune=%s %s",
 	       ix86_tune_string, prefix, suffix, sw);
+      else if (!strcmp (ix86_tune_string, "x86-64"))
+        warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated.  Use "
+                 "%stune=k8%s or %stune=generic%s instead as appropriate.",
+                 prefix, suffix, prefix, suffix, prefix, suffix);
     }
   else
     {
@@ -2846,6 +2851,7 @@ override_options (bool main_args_p)
 	    ix86_tune_string = "generic32";
 	}
     }
+
   if (ix86_stringop_string)
     {
       if (!strcmp (ix86_stringop_string, "rep_byte"))
@@ -2868,23 +2874,12 @@ override_options (bool main_args_p)
 	error ("bad value (%s) for %sstringop-strategy=%s %s",
 	       ix86_stringop_string, prefix, suffix, sw);
     }
-  if (!strcmp (ix86_tune_string, "x86-64"))
-    warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated.  Use "
-	     "%stune=k8%s or %stune=generic%s instead as appropriate.",
-	     prefix, suffix, prefix, suffix, prefix, suffix);
 
   if (!ix86_arch_string)
     ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
   else
     ix86_arch_specified = 1;
 
-  if (!strcmp (ix86_arch_string, "generic"))
-    error ("generic CPU can be used only for %stune=%s %s",
-	   prefix, suffix, sw);
-  if (!strncmp (ix86_arch_string, "generic", 7))
-    error ("bad value (%s) for %sarch=%s %s",
-	   ix86_arch_string, prefix, suffix, sw);
-
   /* Validate -mabi= value.  */
   if (ix86_abi_string)
     {
@@ -3032,7 +3027,10 @@ override_options (bool main_args_p)
 	break;
       }
 
-  if (i == pta_size)
+  if (!strcmp (ix86_arch_string, "generic"))
+    error ("generic CPU can be used only for %stune=%s %s",
+	   prefix, suffix, sw);
+  else if (!strncmp (ix86_arch_string, "generic", 7) || i == pta_size)
     error ("bad value (%s) for %sarch=%s %s",
 	   ix86_arch_string, prefix, suffix, sw);
 
@@ -3071,7 +3069,8 @@ override_options (bool main_args_p)
 	  x86_prefetch_sse = true;
 	break;
       }
-  if (i == pta_size)
+
+  if (ix86_tune_specified && i == pta_size)
     error ("bad value (%s) for %stune=%s %s",
 	   ix86_tune_string, prefix, suffix, sw);
 
@@ -10884,6 +10883,9 @@ static rtx
 ix86_delegitimize_address (rtx x)
 {
   rtx orig_x = delegitimize_mem_from_attrs (x);
+  /* addend is NULL or some rtx if x is something+GOTOFF where
+     something doesn't include the PIC register.  */
+  rtx addend = NULL_RTX;
   /* reg_addend is NULL or a multiple of some register.  */
   rtx reg_addend = NULL_RTX;
   /* const_addend is NULL or a const_int.  */
@@ -10922,14 +10924,13 @@ ix86_delegitimize_address (rtx x)
       else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
 	reg_addend = XEXP (reg_addend, 0);
       else
-	return orig_x;
-      if (!REG_P (reg_addend)
-	  && GET_CODE (reg_addend) != MULT
-	  && GET_CODE (reg_addend) != ASHIFT)
-	return orig_x;
+	{
+	  reg_addend = NULL_RTX;
+	  addend = XEXP (x, 0);
+	}
     }
   else
-    return orig_x;
+    addend = XEXP (x, 0);
 
   x = XEXP (XEXP (x, 1), 0);
   if (GET_CODE (x) == PLUS
@@ -10940,7 +10941,7 @@ ix86_delegitimize_address (rtx x)
     }
 
   if (GET_CODE (x) == UNSPEC
-      && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
+      && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x) && !addend)
 	  || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
     result = XVECEXP (x, 0, 0);
 
@@ -10955,6 +10956,22 @@ ix86_delegitimize_address (rtx x)
     result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
   if (reg_addend)
     result = gen_rtx_PLUS (Pmode, reg_addend, result);
+  if (addend)
+    {
+      /* If the rest of original X doesn't involve the PIC register, add
+	 addend and subtract pic_offset_table_rtx.  This can happen e.g.
+	 for code like:
+	 leal (%ebx, %ecx, 4), %ecx
+	 ...
+	 movl foo@GOTOFF(%ecx), %edx
+	 in which case we return (%ecx - %ebx) + foo.  */
+      if (pic_offset_table_rtx)
+        result = gen_rtx_PLUS (Pmode, gen_rtx_MINUS (Pmode, copy_rtx (addend),
+						     pic_offset_table_rtx),
+			       result);
+      else
+	return orig_x;
+    }
   return result;
 }
 
@@ -24656,7 +24673,7 @@ avx_vpermilp_parallel (rtx par, enum machine_mode mode)
       if (!CONST_INT_P (er))
 	return 0;
       ei = INTVAL (er);
-      if (ei >= 2 * nelt)
+      if (ei >= nelt)
 	return 0;
       ipar[i] = ei;
     }
@@ -29127,8 +29144,8 @@ expand_vec_perm_blend (struct expand_vec_perm_d *d)
     do_subreg:
       vmode = V8HImode;
       target = gen_lowpart (vmode, target);
-      op0 = gen_lowpart (vmode, target);
-      op1 = gen_lowpart (vmode, target);
+      op0 = gen_lowpart (vmode, op0);
+      op1 = gen_lowpart (vmode, op1);
       break;
 
     default:
@@ -29136,7 +29153,7 @@ expand_vec_perm_blend (struct expand_vec_perm_d *d)
     }
 
   /* This matches five different patterns with the different modes.  */
-  x = gen_rtx_VEC_MERGE (vmode, op0, op1, GEN_INT (mask));
+  x = gen_rtx_VEC_MERGE (vmode, op1, op0, GEN_INT (mask));
   x = gen_rtx_SET (VOIDmode, target, x);
   emit_insn (x);
 
@@ -29248,7 +29265,12 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d)
      input where SEL+CONCAT may not.  */
   if (d->op0 == d->op1)
     {
-      if (expand_vselect (d->target, d->op0, d->perm, nelt))
+      int mask = nelt - 1;
+
+      for (i = 0; i < nelt; i++)
+	perm2[i] = d->perm[i] & mask;
+
+      if (expand_vselect (d->target, d->op0, perm2, nelt))
 	return true;
 
       /* There are plenty of patterns in sse.md that are written for
@@ -29259,8 +29281,8 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d)
 	 every other permutation operand.  */
       for (i = 0; i < nelt; i += 2)
 	{
-	  perm2[i] = d->perm[i];
-	  perm2[i+1] = d->perm[i+1] + nelt;
+	  perm2[i] = d->perm[i] & mask;
+	  perm2[i + 1] = (d->perm[i + 1] & mask) + nelt;
 	}
       if (expand_vselect_vconcat (d->target, d->op0, d->op0, perm2, nelt))
 	return true;
@@ -29268,11 +29290,12 @@ expand_vec_perm_1 (struct expand_vec_perm_d *d)
       /* Recognize shufps, which means adding {0, 0, nelt, nelt}.  */
       if (nelt >= 4)
 	{
-	  memcpy (perm2, d->perm, nelt);
-	  for (i = 2; i < nelt; i += 4)
+	  for (i = 0; i < nelt; i += 4)
 	    {
-	      perm2[i+0] += nelt;
-	      perm2[i+1] += nelt;
+	      perm2[i + 0] = d->perm[i + 0] & mask;
+	      perm2[i + 1] = d->perm[i + 1] & mask;
+	      perm2[i + 2] = (d->perm[i + 2] & mask) + nelt;
+	      perm2[i + 3] = (d->perm[i + 3] & mask) + nelt;
 	    }
 
 	  if (expand_vselect_vconcat (d->target, d->op0, d->op0, perm2, nelt))
diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h
index d07547a804f..8075df79282 100644
--- a/gcc/config/i386/linux64.h
+++ b/gcc/config/i386/linux64.h
@@ -61,11 +61,6 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
 #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
 
-#undef ASM_SPEC
-#define ASM_SPEC "%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} \
- %{Wa,*:%*} %{m32:--32} %{m64:--64} \
- %{!mno-sse2avx:%{mavx:-msse2avx}} %{msse2avx:%{!mavx:-msse2avx}}"
-
 #if TARGET_64BIT_DEFAULT
 #define SPEC_32 "m32"
 #define SPEC_64 "!m32"
@@ -74,6 +69,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define SPEC_64 "m64"
 #endif
 
+#undef ASM_SPEC
+#define ASM_SPEC "%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} \
+ %{Wa,*:%*} %{" SPEC_32 ":--32} %{" SPEC_64 ":--64} \
+ %{!mno-sse2avx:%{mavx:-msse2avx}} %{msse2avx:%{!mavx:-msse2avx}}"
+
 #undef	LINK_SPEC
 #define LINK_SPEC "%{" SPEC_64 ":-m elf_x86_64} %{" SPEC_32 ":-m elf_i386} \
   %{shared:-shared} \
diff --git a/gcc/config/i386/sol2-gas.h b/gcc/config/i386/sol2-gas.h
new file mode 100644
index 00000000000..c3573966ac8
--- /dev/null
+++ b/gcc/config/i386/sol2-gas.h
@@ -0,0 +1,28 @@
+/* Definitions of target machine for GCC, for x86 running Solaris 2
+   using the GNU assembler.
+
+Copyright (C) 2010 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+<http://www.gnu.org/licenses/>.  */
+
+/* Undefine this so that BNSYM/ENSYM pairs are emitted by STABS+.  */
+#undef NO_DBX_BNSYM_ENSYM
diff --git a/gcc/config/i386/sol2.h b/gcc/config/i386/sol2.h
index f062280fd18..00f1870801d 100644
--- a/gcc/config/i386/sol2.h
+++ b/gcc/config/i386/sol2.h
@@ -1,6 +1,6 @@
 /* Target definitions for GCC for Intel 80386 running Solaris 2
    Copyright (C) 1993, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004, 2007, 2008, 2009 Free Software Foundation, Inc.
+   2004, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
    Contributed by Fred Fish (fnf@cygnus.com).
 
 This file is part of GCC.
@@ -91,6 +91,10 @@ along with GCC; see the file COPYING3.  If not see
       }							\
   } while (0)
 
+/* The Solaris assembler cannot grok .stabd directives.  */
+#undef NO_DBX_BNSYM_ENSYM
+#define NO_DBX_BNSYM_ENSYM 1
+
 /* Solaris-specific #pragmas are implemented on top of attributes.  Hook in
    the bits from config/sol2.c.  */
 #define SUBTARGET_INSERT_ATTRIBUTES solaris_insert_attributes
diff --git a/gcc/config/i386/ssemath.h b/gcc/config/i386/ssemath.h
new file mode 100644
index 00000000000..357d6a378af
--- /dev/null
+++ b/gcc/config/i386/ssemath.h
@@ -0,0 +1,25 @@
+/* Copyright (C) 2010
+   Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+#undef TARGET_FPMATH_DEFAULT
+#define TARGET_FPMATH_DEFAULT (TARGET_SSE2 ? FPMATH_SSE : FPMATH_387)
+
+#undef TARGET_SUBTARGET32_ISA_DEFAULT
+#define TARGET_SUBTARGET32_ISA_DEFAULT \
+   (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2)
diff --git a/gcc/config/mep/mep.c b/gcc/config/mep/mep.c
index 54d21c8f1a0..e0fce28c084 100644
--- a/gcc/config/mep/mep.c
+++ b/gcc/config/mep/mep.c
@@ -50,6 +50,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "target-def.h"
 #include "langhooks.h"
 #include "df.h"
+#include "gimple.h"
 
 /* Structure of this file:
 
@@ -160,7 +161,6 @@ static bool mep_interrupt_saved_reg (int);
 static bool mep_call_saves_register (int);
 static rtx F (rtx);
 static void add_constant (int, int, int, int);
-static bool mep_function_uses_sp (void);
 static rtx maybe_dead_move (rtx, rtx, bool);
 static void mep_reload_pointer (int, const char *);
 static void mep_start_function (FILE *, HOST_WIDE_INT);
@@ -227,7 +227,7 @@ static bool mep_narrow_volatile_bitfield (void);
 static rtx mep_expand_builtin_saveregs (void);
 static tree mep_build_builtin_va_list (void);
 static void mep_expand_va_start (tree, rtx);
-static tree mep_gimplify_va_arg_expr (tree, tree, tree *, tree *);
+static tree mep_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
 static bool mep_can_eliminate (const int, const int);
 static void mep_trampoline_init (rtx, tree, rtx);
 
@@ -2757,27 +2757,6 @@ add_constant (int dest, int src, int value, int mark_frame)
     }
 }
 
-static bool
-mep_function_uses_sp (void)
-{
-  rtx insn;
-  struct sequence_stack *seq;
-  rtx sp = gen_rtx_REG (SImode, SP_REGNO);
-
-  insn = get_insns ();
-  for (seq = crtl->emit.sequence_stack;
-       seq;
-       insn = seq->first, seq = seq->next);
-
-  while (insn)
-    {
-      if (mep_mentioned_p (insn, sp, 0))
-	return true;
-      insn = NEXT_INSN (insn);
-    }
-  return false;
-}
-
 /* Move SRC to DEST.  Mark the move as being potentially dead if
    MAYBE_DEAD_P.  */
 
@@ -3699,7 +3678,8 @@ mep_expand_va_start (tree valist, rtx nextarg)
 
 static tree
 mep_gimplify_va_arg_expr (tree valist, tree type,
-			  tree *pre_p, tree *post_p ATTRIBUTE_UNUSED)
+			  gimple_seq *pre_p,
+			  gimple_seq *post_p ATTRIBUTE_UNUSED)
 {
   HOST_WIDE_INT size, rsize;
   bool by_reference, ivc2_vec;
@@ -6355,9 +6335,9 @@ mep_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
   tree fnname;
   const struct cgen_insn *cgen_insn;
   const struct insn_data *idata;
-  int first_arg = 0;
-  int return_type = void_type_node;
-  int builtin_n_args;
+  unsigned int first_arg = 0;
+  tree return_type = void_type_node;
+  unsigned int builtin_n_args;
 
   fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
   fnname = DECL_NAME (fndecl);
@@ -6367,7 +6347,7 @@ mep_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
   if (!mep_get_intrinsic_insn (DECL_FUNCTION_CODE (fndecl), &cgen_insn))
     {
       mep_intrinsic_unavailable (DECL_FUNCTION_CODE (fndecl));
-      return error_mark_node;
+      return NULL_RTX;
     }
   idata = &insn_data[cgen_insn->icode];
 
@@ -6388,19 +6368,19 @@ mep_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
   if (n_args < builtin_n_args)
     {
       error ("too few arguments to %qE", fnname);
-      return error_mark_node;
+      return NULL_RTX;
     }
   if (n_args > builtin_n_args)
     {
       error ("too many arguments to %qE", fnname);
-      return error_mark_node;
+      return NULL_RTX;
     }
 
-  for (a = first_arg; a < builtin_n_args+first_arg; a++)
+  for (a = first_arg; a < builtin_n_args + first_arg; a++)
     {
       tree value;
 
-      args = CALL_EXPR_ARG (exp, a-first_arg);
+      args = CALL_EXPR_ARG (exp, a - first_arg);
 
       value = args;
 
@@ -6411,7 +6391,7 @@ mep_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
 	    {
 	      debug_tree(value);
 	      error ("argument %d of %qE must be an address", a+1, fnname);
-	      return error_mark_node;
+	      return NULL_RTX;
 	    }
 	  value = TREE_OPERAND (value, 0);
 	}
@@ -6450,11 +6430,11 @@ mep_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
 	{
 	  error ("argument %d of %qE must be in the range %d...%d",
 		 a + 1, fnname, 0, cgen_insn->regnums[a].count - 1);
-	  return error_mark_node;
+	  return NULL_RTX;
 	}
     }
 
-  for (a=0; a<first_arg; a++)
+  for (a = 0; a < first_arg; a++)
     {
       if (a == 0 && target && GET_MODE (target) == idata->operand[0].mode)
 	arg[a] = target;
@@ -6473,7 +6453,7 @@ mep_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
 	{
 	  mep_incompatible_arg (&idata->operand[opindex],
 				arg[a], a + 1 - first_arg, fnname);
-	  return error_mark_node;
+	  return NULL_RTX;
 	}
     }
 
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index f5ad34882d4..e66e8c4318f 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -955,6 +955,10 @@ RS6000_BUILTIN(VSX_BUILTIN_VEC_SET_V2DF,		RS6000_BTC_CONST)
 RS6000_BUILTIN(VSX_BUILTIN_VEC_SET_V2DI,		RS6000_BTC_CONST)
 RS6000_BUILTIN(VSX_BUILTIN_VEC_EXT_V2DF,		RS6000_BTC_CONST)
 RS6000_BUILTIN(VSX_BUILTIN_VEC_EXT_V2DI,		RS6000_BTC_CONST)
+RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEL_V2DF,		RS6000_BTC_CONST)
+RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEL_V2DI,		RS6000_BTC_CONST)
+RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEH_V2DF,		RS6000_BTC_CONST)
+RS6000_BUILTIN(VSX_BUILTIN_VEC_MERGEH_V2DI,		RS6000_BTC_CONST)
 
 /* VSX overloaded builtins, add the overloaded functions not present in
    Altivec.  */
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index da5a360665a..3bb604998a9 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -1372,6 +1372,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+  { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF,
+    RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
+  { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI,
+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW,
@@ -1416,6 +1420,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
   { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW,
     RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+  { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF,
+    RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
+  { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI,
+    RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
     RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 },
   { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW,
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index af26bf165b7..7bcc0866887 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -8950,6 +8950,10 @@ static struct builtin_description bdesc_2arg[] =
   { MASK_VSX, CODE_FOR_vsx_xxmrghw_v4si, "__builtin_vsx_xxmrghw_4si", VSX_BUILTIN_XXMRGHW_4SI },
   { MASK_VSX, CODE_FOR_vsx_xxmrglw_v4sf, "__builtin_vsx_xxmrglw", VSX_BUILTIN_XXMRGLW_4SF },
   { MASK_VSX, CODE_FOR_vsx_xxmrglw_v4si, "__builtin_vsx_xxmrglw_4si", VSX_BUILTIN_XXMRGLW_4SI },
+  { MASK_VSX, CODE_FOR_vec_interleave_lowv2df, "__builtin_vsx_mergel_2df", VSX_BUILTIN_VEC_MERGEL_V2DF },
+  { MASK_VSX, CODE_FOR_vec_interleave_lowv2di, "__builtin_vsx_mergel_2di", VSX_BUILTIN_VEC_MERGEL_V2DI },
+  { MASK_VSX, CODE_FOR_vec_interleave_highv2df, "__builtin_vsx_mergeh_2df", VSX_BUILTIN_VEC_MERGEH_V2DF },
+  { MASK_VSX, CODE_FOR_vec_interleave_highv2di, "__builtin_vsx_mergeh_2di", VSX_BUILTIN_VEC_MERGEH_V2DI },
 
   { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
   { MASK_ALTIVEC|MASK_VSX, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index d078597306c..d66f1411aaa 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -51,6 +51,9 @@
 ;; Vector init/extract modes
 (define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
 
+;; Vector modes for 64-bit base types
+(define_mode_iterator VEC_64 [V2DI V2DF])
+
 ;; Vector reload iterator
 (define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF DF TI])
 
@@ -480,7 +483,7 @@
 	(eq:SI (reg:CC 74)
 	       (const_int 0)))]
   "TARGET_ALTIVEC || TARGET_VSX"
-  "")	
+  "")
 
 (define_expand "cr6_test_for_zero_reverse"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -533,7 +536,7 @@
         (not:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")))]
   "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
   "")
-  
+
 (define_expand "nor<mode>3"
   [(set (match_operand:VEC_L 0 "vlogical_operand" "")
         (not:VEC_L (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")
@@ -668,24 +671,24 @@
   "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
   "")
 
-(define_expand "vec_interleave_highv2df"
-  [(set (match_operand:V2DF 0 "vfloat_operand" "")
-	(vec_concat:V2DF
-	 (vec_select:DF (match_operand:V2DF 1 "vfloat_operand" "")
-			(parallel [(const_int 0)]))
-	 (vec_select:DF (match_operand:V2DF 2 "vfloat_operand" "")
-			(parallel [(const_int 0)]))))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
+(define_expand "vec_interleave_high<mode>"
+  [(set (match_operand:VEC_64 0 "vfloat_operand" "")
+	(vec_concat:VEC_64
+	 (vec_select:<VEC_base> (match_operand:VEC_64 1 "vfloat_operand" "")
+				(parallel [(const_int 0)]))
+	 (vec_select:<VEC_base> (match_operand:VEC_64 2 "vfloat_operand" "")
+				(parallel [(const_int 0)]))))]
+  "VECTOR_UNIT_VSX_P (<MODE>mode)"
   "")
 
-(define_expand "vec_interleave_lowv2df"
-  [(set (match_operand:V2DF 0 "vfloat_operand" "")
-	(vec_concat:V2DF
-	 (vec_select:DF (match_operand:V2DF 1 "vfloat_operand" "")
-			(parallel [(const_int 1)]))
-	 (vec_select:DF (match_operand:V2DF 2 "vfloat_operand" "")
-			(parallel [(const_int 1)]))))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
+(define_expand "vec_interleave_low<mode>"
+  [(set (match_operand:VEC_64 0 "vfloat_operand" "")
+	(vec_concat:VEC_64
+	 (vec_select:<VEC_base> (match_operand:VEC_64 1 "vfloat_operand" "")
+				(parallel [(const_int 1)]))
+	 (vec_select:<VEC_base> (match_operand:VEC_64 2 "vfloat_operand" "")
+				(parallel [(const_int 1)]))))]
+  "VECTOR_UNIT_VSX_P (<MODE>mode)"
   "")
 
 
@@ -889,7 +892,7 @@
   rtx insn;
   HOST_WIDE_INT bitshift_val;
   HOST_WIDE_INT byteshift_val;
- 
+
   if (! CONSTANT_P (bitshift))
     FAIL;
   bitshift_val = INTVAL (bitshift);
diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
index a2c1c7c67ed..03ca8f19b9a 100644
--- a/gcc/config/rx/rx.md
+++ b/gcc/config/rx/rx.md
@@ -845,10 +845,10 @@
 )
 
 (define_insn "sminsi3"
-  [(set (match_operand:SI          0 "register_operand" "=r,r,r,r,r,r,r")
-	(smin:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r")
+  [(set (match_operand:SI          0 "register_operand" "=r,r,r,r,r,r")
+	(smin:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
 		 (match_operand:SI 2 "rx_source_operand"
-				   "r,Sint08,Sint16,Sint24,i,Q,r")))]
+				   "r,Sint08,Sint16,Sint24,i,Q")))]
   ""
   "@
   min\t%Q2, %0
@@ -856,10 +856,9 @@
   min\t%Q2, %0
   min\t%Q2, %0
   min\t%Q2, %0
-  min\t%Q2, %0
-  mov.l\t%1,%0\n\tmin\t%Q2, %0"
-  [(set_attr "length"  "3,4,5,6,7,6,5")
-   (set_attr "timings" "11,11,11,11,11,33,22")]
+  min\t%Q2, %0"
+  [(set_attr "length"  "3,4,5,6,7,6")
+   (set_attr "timings" "11,11,11,11,11,33")]
 )
 
 (define_insn "mulsi3"
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 3e8ff24d041..d1105e37fed 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -107,6 +107,9 @@ static int skip_cycles = 0;
    and returned from sh_reorder2.  */
 static short cached_can_issue_more;
 
+/* Unique number for UNSPEC_BBR pattern.  */
+static unsigned int unspec_bbr_uid = 1;
+
 /* Provides the class number of the smallest class containing
    reg number.  */
 
@@ -5012,8 +5015,8 @@ gen_block_redirect (rtx jump, int addr, int need_block)
 	 branch; simplejump_p fails for indirect jumps even if they have
 	 a JUMP_LABEL.  */
       rtx insn = emit_insn_before (gen_indirect_jump_scratch
-				   (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
-				   , jump);
+				   (reg, GEN_INT (unspec_bbr_uid++)),
+				   jump);
       /* ??? We would like this to have the scope of the jump, but that
 	 scope will change when a delay slot insn of an inner scope is added.
 	 Hence, after delay slot scheduling, we'll have to expect
@@ -5028,8 +5031,8 @@ gen_block_redirect (rtx jump, int addr, int need_block)
     /* We can't use JUMP_LABEL here because it might be undefined
        when not optimizing.  */
     return emit_insn_before (gen_block_branch_redirect
-		      (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
-		      , jump);
+			     (GEN_INT (unspec_bbr_uid++)),
+			     jump);
   return prev;
 }
 
@@ -5088,7 +5091,7 @@ gen_far_branch (struct far_branch *bp)
   if (bp->far_label)
     (emit_insn_after
      (gen_stuff_delay_slot
-      (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
+      (GEN_INT (unspec_bbr_uid++),
        GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
       insn));
   /* Prevent reorg from undoing our splits.  */
diff --git a/gcc/config/sparc/gas.h b/gcc/config/sparc/gas.h
deleted file mode 100644
index e3779293532..00000000000
--- a/gcc/config/sparc/gas.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Definitions of target machine for GCC, for SPARC
-   using the GNU assembler.  */
-
-/* Switch into a generic section.  */
-#undef TARGET_ASM_NAMED_SECTION
-#define TARGET_ASM_NAMED_SECTION  default_elf_asm_named_section
diff --git a/gcc/config/sparc/sol2-64.h b/gcc/config/sparc/sol2-64.h
index d0dd284daf0..cf0bbff1ec6 100644
--- a/gcc/config/sparc/sol2-64.h
+++ b/gcc/config/sparc/sol2-64.h
@@ -1,5 +1,23 @@
 /* Definitions of target machine for GCC, for bi-arch SPARC
-   running Solaris 2, defaulting to 64-bit code generation.  */
+   running Solaris 2, defaulting to 64-bit code generation.
+
+   Copyright (C) 1999, 2010 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
 
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT \
diff --git a/gcc/config/sparc/sol2-gas-bi.h b/gcc/config/sparc/sol2-gas-bi.h
index 88b3954f820..001f978b889 100644
--- a/gcc/config/sparc/sol2-gas-bi.h
+++ b/gcc/config/sparc/sol2-gas-bi.h
@@ -1,5 +1,23 @@
 /* Definitions of target machine for GCC, for bi-arch SPARC
-   running Solaris 2 using the GNU assembler.  */
+   running Solaris 2 using the GNU assembler.
+
+   Copyright (C) 2002, 2010 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
 
 #undef  AS_SPARC64_FLAG
 #define AS_SPARC64_FLAG	"-TSO -64 -Av9"
diff --git a/gcc/config/sparc/sol2-gas.h b/gcc/config/sparc/sol2-gas.h
index 2cbfa45d4b0..e9f2490980f 100644
--- a/gcc/config/sparc/sol2-gas.h
+++ b/gcc/config/sparc/sol2-gas.h
@@ -34,3 +34,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
 #define TARGET_SUN_TLS 0
 #define TARGET_GNU_TLS 1
 #endif
+
+/* Use default ELF section syntax.  */
+#undef TARGET_ASM_NAMED_SECTION
+#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
diff --git a/gcc/config/sparc/sol2-gld.h b/gcc/config/sparc/sol2-gld.h
index eb422cb8667..b63693c002f 100644
--- a/gcc/config/sparc/sol2-gld.h
+++ b/gcc/config/sparc/sol2-gld.h
@@ -1,5 +1,23 @@
 /* Definitions of target machine for GCC, for SPARC running Solaris 2
-   using the GNU linker.  */
+   using the GNU linker.
+
+   Copyright (C) 2002, 2010 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
 
 /* Undefine this so that attribute((init_priority)) works.  */
 #undef CTORS_SECTION_ASM_OP
diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h
index a3f7647027b..21882ae206a 100644
--- a/gcc/config/sparc/sol2.h
+++ b/gcc/config/sparc/sol2.h
@@ -195,4 +195,8 @@ along with GCC; see the file COPYING3.  If not see
     }									\
   while (0)
 
+/* Use Solaris ELF section syntax.  */
+#undef TARGET_ASM_NAMED_SECTION
+#define TARGET_ASM_NAMED_SECTION sparc_solaris_elf_asm_named_section
+
 #define MD_UNWIND_SUPPORT "config/sparc/sol2-unwind.h"
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index c45460db4db..e4ef862c96d 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -368,11 +368,8 @@ static int save_or_restore_regs (int, int, rtx, int, int);
 static void emit_save_or_restore_regs (int);
 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT);
-#if defined (OBJECT_FORMAT_ELF)
-static void sparc_elf_asm_named_section (const char *, unsigned int, tree)
-    ATTRIBUTE_UNUSED;
-#endif
-
+static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
+						 tree) ATTRIBUTE_UNUSED;
 static int sparc_adjust_cost (rtx, rtx, rtx, int);
 static int sparc_issue_rate (void);
 static void sparc_sched_init (FILE *, int, int);
@@ -464,14 +461,9 @@ static bool fpu_option_set = false;
 
 /* Initialize the GCC target structure.  */
 
-/* The sparc default is to use .half rather than .short for aligned
-   HI objects.  Use .word instead of .long on non-ELF systems.  */
+/* The default is to use .half rather than .short for aligned HI objects.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
-#ifndef OBJECT_FORMAT_ELF
-#undef TARGET_ASM_ALIGNED_SI_OP
-#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
-#endif
 
 #undef TARGET_ASM_UNALIGNED_HI_OP
 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
@@ -8002,10 +7994,11 @@ sparc_profile_hook (int labelno)
     }
 }
 
-#if defined (OBJECT_FORMAT_ELF)
+/* Solaris implementation of TARGET_ASM_NAMED_SECTION.  */
+
 static void
-sparc_elf_asm_named_section (const char *name, unsigned int flags,
-			     tree decl ATTRIBUTE_UNUSED)
+sparc_solaris_elf_asm_named_section (const char *name, unsigned int flags,
+				     tree decl ATTRIBUTE_UNUSED)
 {
   fprintf (asm_out_file, "\t.section\t\"%s\"", name);
 
@@ -8022,7 +8015,6 @@ sparc_elf_asm_named_section (const char *name, unsigned int flags,
 
   fputc ('\n', asm_out_file);
 }
-#endif /* OBJECT_FORMAT_ELF */
 
 /* We do not allow indirect calls to be optimized into sibling calls.
 
diff --git a/gcc/config/sparc/sysv4.h b/gcc/config/sparc/sysv4.h
index 7620711d3b6..c78add484fe 100644
--- a/gcc/config/sparc/sysv4.h
+++ b/gcc/config/sparc/sysv4.h
@@ -127,10 +127,6 @@ do { ASM_OUTPUT_ALIGN ((FILE), Pmode == SImode ? 2 : 3);		\
 #undef DTORS_SECTION_ASM_OP
 #define DTORS_SECTION_ASM_OP    "\t.section\t\".dtors\",#alloc,#write"
 
-/* Switch into a generic section.  */
-#undef TARGET_ASM_NAMED_SECTION
-#define TARGET_ASM_NAMED_SECTION  sparc_elf_asm_named_section
-
 #undef ASM_OUTPUT_ALIGNED_BSS
 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
   asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)