diff options
| author | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-04-16 17:02:56 +0000 |
|---|---|---|
| committer | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-04-16 17:02:56 +0000 |
| commit | c8aed844acdc89884d630c7e3266ecd8d4101847 (patch) | |
| tree | 0d046a9255339220c1bbd6ba14e84e5304acbe10 /gcc/config | |
| parent | 74f8420a5b204c5e021ce05b3d0d79ba9718360a (diff) | |
| download | gcc-c8aed844acdc89884d630c7e3266ecd8d4101847.tar.gz | |
2016-04-16 Basile Starynkevitch <basile@starynkevitch.net>
{{merging with even more of GCC 6, using subversion 1.9
svn merge -r231651:232605 ^/trunk
}}
[gcc/]
2016-04-16 Basile Starynkevitch <basile@starynkevitch.net>
* melt/libmelt-ana-gimple.melt:
(melt_build_transaction_with_label_norm): New inlined function,
for gimple_transaction operator implementation...
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@235064 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
1341 files changed, 5329 insertions, 5259 deletions
diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def index 3b4fb73316c..1e9d90b1b66 100644 --- a/gcc/config/aarch64/aarch64-arches.def +++ b/gcc/config/aarch64/aarch64-arches.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. +/* Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index b268a6aaf7c..925034b626c 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -1,5 +1,5 @@ /* Builtins' description for AArch64 SIMD architecture. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -119,6 +119,10 @@ aarch64_types_unopu_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned }; #define TYPES_UNOPU (aarch64_types_unopu_qualifiers) static enum aarch64_type_qualifiers +aarch64_types_unopus_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_none }; +#define TYPES_UNOPUS (aarch64_types_unopus_qualifiers) +static enum aarch64_type_qualifiers aarch64_types_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_none, qualifier_none, qualifier_maybe_immediate }; #define TYPES_BINOP (aarch64_types_binop_qualifiers) diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c index ad95c78b989..3590ae0daa5 100644 --- a/gcc/config/aarch64/aarch64-c.c +++ b/gcc/config/aarch64/aarch64-c.c @@ -1,5 +1,5 @@ /* Target-specific code for C family languages. - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index e4b2e20d95a..251a3ebb9be 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. +/* Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-cost-tables.h b/gcc/config/aarch64/aarch64-cost-tables.h index 939125c0e88..3a3f5194b11 100644 --- a/gcc/config/aarch64/aarch64-cost-tables.h +++ b/gcc/config/aarch64/aarch64-cost-tables.h @@ -1,6 +1,6 @@ /* RTX cost tables for AArch64. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-elf-raw.h b/gcc/config/aarch64/aarch64-elf-raw.h index ecd35908aa2..2dcb6d400ec 100644 --- a/gcc/config/aarch64/aarch64-elf-raw.h +++ b/gcc/config/aarch64/aarch64-elf-raw.h @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-elf.h b/gcc/config/aarch64/aarch64-elf.h index ac47f435aef..66c0bb27c5b 100644 --- a/gcc/config/aarch64/aarch64-elf.h +++ b/gcc/config/aarch64/aarch64-elf.h @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-fusion-pairs.def b/gcc/config/aarch64/aarch64-fusion-pairs.def index 53bbef46eb2..8261da0252d 100644 --- a/gcc/config/aarch64/aarch64-fusion-pairs.def +++ b/gcc/config/aarch64/aarch64-fusion-pairs.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2015 Free Software Foundation, Inc. +/* Copyright (C) 2015-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-ldpstp.md b/gcc/config/aarch64/aarch64-ldpstp.md index 3f88703eabd..d3d53f81637 100644 --- a/gcc/config/aarch64/aarch64-ldpstp.md +++ b/gcc/config/aarch64/aarch64-ldpstp.md @@ -1,5 +1,5 @@ ;; AArch64 ldp/stp peephole optimizations. -;; Copyright (C) 2014-2015 Free Software Foundation, Inc. +;; Copyright (C) 2014-2016 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h index f2b4d415aa9..6064b2654cb 100644 --- a/gcc/config/aarch64/aarch64-linux.h +++ b/gcc/config/aarch64/aarch64-linux.h @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-modes.def b/gcc/config/aarch64/aarch64-modes.def index 3bf3b2dea3c..3fab2053ceb 100644 --- a/gcc/config/aarch64/aarch64-modes.def +++ b/gcc/config/aarch64/aarch64-modes.def @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -25,16 +25,6 @@ CC_MODE (CC_ZESWP); /* zero-extend LHS (but swap to make it RHS). */ CC_MODE (CC_SESWP); /* sign-extend LHS (but swap to make it RHS). */ CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */ CC_MODE (CC_Z); /* Only Z bit of condition flags is valid. */ -CC_MODE (CC_DNE); -CC_MODE (CC_DEQ); -CC_MODE (CC_DLE); -CC_MODE (CC_DLT); -CC_MODE (CC_DGE); -CC_MODE (CC_DGT); -CC_MODE (CC_DLEU); -CC_MODE (CC_DLTU); -CC_MODE (CC_DGEU); -CC_MODE (CC_DGTU); /* Half-precision floating point for __fp16. */ FLOAT_MODE (HF, 2, 0); diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 4f1d53515a9..fbf9a53283c 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -40,4 +40,4 @@ AARCH64_OPT_EXTENSION ("simd", AARCH64_FL_FPSIMD, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO, "asimd") AARCH64_OPT_EXTENSION("crypto", AARCH64_FL_CRYPTO | AARCH64_FL_FPSIMD, AARCH64_FL_CRYPTO, "aes pmull sha1 sha2") AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, AARCH64_FL_CRC, "crc32") -AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, AARCH64_FL_LSE, "lse") +AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, AARCH64_FL_LSE, "atomics") diff --git a/gcc/config/aarch64/aarch64-opts.h b/gcc/config/aarch64/aarch64-opts.h index bf6bb7b8f4e..c550a74456e 100644 --- a/gcc/config/aarch64/aarch64-opts.h +++ b/gcc/config/aarch64/aarch64-opts.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. +/* Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 549a89d1f69..15fc37deb9a 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -329,6 +329,7 @@ int aarch64_uxt_size (int, HOST_WIDE_INT); int aarch64_vec_fpconst_pow_of_2 (rtx); rtx aarch64_final_eh_return_addr (void); rtx aarch64_legitimize_reload_address (rtx *, machine_mode, int, int, int); +rtx aarch64_mask_from_zextract_ops (rtx, rtx); const char *aarch64_output_move_struct (rtx *operands); rtx aarch64_return_addr (int, rtx); rtx aarch64_simd_gen_const_vector_dup (machine_mode, int); diff --git a/gcc/config/aarch64/aarch64-simd-builtin-types.def b/gcc/config/aarch64/aarch64-simd-builtin-types.def index ea219b72ff9..27dbb5df219 100644 --- a/gcc/config/aarch64/aarch64-simd-builtin-types.def +++ b/gcc/config/aarch64/aarch64-simd-builtin-types.def @@ -1,5 +1,5 @@ /* Builtin AdvSIMD types. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 1952333cdb7..dd045792b21 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -275,9 +275,9 @@ VAR1 (UNOP, lbtruncv4sf, 2, v4si) VAR1 (UNOP, lbtruncv2df, 2, v2di) - VAR1 (UNOP, lbtruncuv2sf, 2, v2si) - VAR1 (UNOP, lbtruncuv4sf, 2, v4si) - VAR1 (UNOP, lbtruncuv2df, 2, v2di) + VAR1 (UNOPUS, lbtruncuv2sf, 2, v2si) + VAR1 (UNOPUS, lbtruncuv4sf, 2, v4si) + VAR1 (UNOPUS, lbtruncuv2df, 2, v2di) VAR1 (UNOP, lroundv2sf, 2, v2si) VAR1 (UNOP, lroundv4sf, 2, v4si) @@ -286,31 +286,31 @@ VAR1 (UNOP, lroundsf, 2, si) VAR1 (UNOP, lrounddf, 2, di) - VAR1 (UNOP, lrounduv2sf, 2, v2si) - VAR1 (UNOP, lrounduv4sf, 2, v4si) - VAR1 (UNOP, lrounduv2df, 2, v2di) - VAR1 (UNOP, lroundusf, 2, si) - VAR1 (UNOP, lroundudf, 2, di) + VAR1 (UNOPUS, lrounduv2sf, 2, v2si) + VAR1 (UNOPUS, lrounduv4sf, 2, v4si) + VAR1 (UNOPUS, lrounduv2df, 2, v2di) + VAR1 (UNOPUS, lroundusf, 2, si) + VAR1 (UNOPUS, lroundudf, 2, di) VAR1 (UNOP, lceilv2sf, 2, v2si) VAR1 (UNOP, lceilv4sf, 2, v4si) VAR1 (UNOP, lceilv2df, 2, v2di) - VAR1 (UNOP, lceiluv2sf, 2, v2si) - VAR1 (UNOP, lceiluv4sf, 2, v4si) - VAR1 (UNOP, lceiluv2df, 2, v2di) - VAR1 (UNOP, lceilusf, 2, si) - VAR1 (UNOP, lceiludf, 2, di) + VAR1 (UNOPUS, lceiluv2sf, 2, v2si) + VAR1 (UNOPUS, lceiluv4sf, 2, v4si) + VAR1 (UNOPUS, lceiluv2df, 2, v2di) + VAR1 (UNOPUS, lceilusf, 2, si) + VAR1 (UNOPUS, lceiludf, 2, di) VAR1 (UNOP, lfloorv2sf, 2, v2si) VAR1 (UNOP, lfloorv4sf, 2, v4si) VAR1 (UNOP, lfloorv2df, 2, v2di) - VAR1 (UNOP, lflooruv2sf, 2, v2si) - VAR1 (UNOP, lflooruv4sf, 2, v4si) - VAR1 (UNOP, lflooruv2df, 2, v2di) - VAR1 (UNOP, lfloorusf, 2, si) - VAR1 (UNOP, lfloorudf, 2, di) + VAR1 (UNOPUS, lflooruv2sf, 2, v2si) + VAR1 (UNOPUS, lflooruv4sf, 2, v4si) + VAR1 (UNOPUS, lflooruv2df, 2, v2di) + VAR1 (UNOPUS, lfloorusf, 2, si) + VAR1 (UNOPUS, lfloorudf, 2, di) VAR1 (UNOP, lfrintnv2sf, 2, v2si) VAR1 (UNOP, lfrintnv4sf, 2, v4si) @@ -318,11 +318,11 @@ VAR1 (UNOP, lfrintnsf, 2, si) VAR1 (UNOP, lfrintndf, 2, di) - VAR1 (UNOP, lfrintnuv2sf, 2, v2si) - VAR1 (UNOP, lfrintnuv4sf, 2, v4si) - VAR1 (UNOP, lfrintnuv2df, 2, v2di) - VAR1 (UNOP, lfrintnusf, 2, si) - VAR1 (UNOP, lfrintnudf, 2, di) + VAR1 (UNOPUS, lfrintnuv2sf, 2, v2si) + VAR1 (UNOPUS, lfrintnuv4sf, 2, v4si) + VAR1 (UNOPUS, lfrintnuv2df, 2, v2di) + VAR1 (UNOPUS, lfrintnusf, 2, si) + VAR1 (UNOPUS, lfrintnudf, 2, di) /* Implemented by <optab><fcvt_target><VDQF:mode>2. */ VAR1 (UNOP, floatv2si, 2, v2sf) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 030a1013caa..e1f5682165c 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 AdvSIMD architecture. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -2153,6 +2153,10 @@ ;; bit op0, op2, mask ;; if (op0 = op2) (so 0-bits in mask choose bits from op1, else op0) ;; bif op0, op1, mask +;; +;; This pattern is expanded to by the aarch64_simd_bsl<mode> expander. +;; Some forms of straight-line code may generate the equivalent form +;; in *aarch64_simd_bsl<mode>_alt. (define_insn "aarch64_simd_bsl<mode>_internal" [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w,w,w") @@ -2172,6 +2176,29 @@ [(set_attr "type" "neon_bsl<q>")] ) +;; We need this form in addition to the above pattern to match the case +;; when combine tries merging three insns such that the second operand of +;; the outer XOR matches the second operand of the inner XOR rather than +;; the first. The two are equivalent but since recog doesn't try all +;; permutations of commutative operations, we have to have a separate pattern. + +(define_insn "*aarch64_simd_bsl<mode>_alt" + [(set (match_operand:VSDQ_I_DI 0 "register_operand" "=w,w,w") + (xor:VSDQ_I_DI + (and:VSDQ_I_DI + (xor:VSDQ_I_DI + (match_operand:VSDQ_I_DI 3 "register_operand" "w,w,0") + (match_operand:VSDQ_I_DI 2 "register_operand" "w,0,w")) + (match_operand:VSDQ_I_DI 1 "register_operand" "0,w,w")) + (match_dup:VSDQ_I_DI 2)))] + "TARGET_SIMD" + "@ + bsl\\t%0.<Vbtype>, %3.<Vbtype>, %2.<Vbtype> + bit\\t%0.<Vbtype>, %3.<Vbtype>, %1.<Vbtype> + bif\\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>" + [(set_attr "type" "neon_bsl<q>")] +) + (define_expand "aarch64_simd_bsl<mode>" [(match_operand:VALLDIF 0 "register_operand") (match_operand:<V_cmp_result> 1 "register_operand") diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def b/gcc/config/aarch64/aarch64-tuning-flags.def index 6f7dbcec03d..8036cfe1ee7 100644 --- a/gcc/config/aarch64/aarch64-tuning-flags.def +++ b/gcc/config/aarch64/aarch64-tuning-flags.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2015 Free Software Foundation, Inc. +/* Copyright (C) 2015-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 1e1b864d865..03bc1b97c2b 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -4142,11 +4142,20 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y) } } + /* Equality comparisons of short modes against zero can be performed + using the TST instruction with the appropriate bitmask. */ + if (y == const0_rtx && REG_P (x) + && (code == EQ || code == NE) + && (GET_MODE (x) == HImode || GET_MODE (x) == QImode)) + return CC_NZmode; + if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode) && y == const0_rtx && (code == EQ || code == NE || code == LT || code == GE) && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS || GET_CODE (x) == AND - || GET_CODE (x) == NEG)) + || GET_CODE (x) == NEG + || (GET_CODE (x) == ZERO_EXTRACT && CONST_INT_P (XEXP (x, 1)) + && CONST_INT_P (XEXP (x, 2))))) return CC_NZmode; /* A compare with a shifted operand. Because of canonicalization, @@ -4196,7 +4205,6 @@ aarch64_get_condition_code (rtx x) static int aarch64_get_condition_code_1 (enum machine_mode mode, enum rtx_code comp_code) { - int ne = -1, eq = -1; switch (mode) { case CCFPmode: @@ -4219,56 +4227,6 @@ aarch64_get_condition_code_1 (enum machine_mode mode, enum rtx_code comp_code) } break; - case CC_DNEmode: - ne = AARCH64_NE; - eq = AARCH64_EQ; - break; - - case CC_DEQmode: - ne = AARCH64_EQ; - eq = AARCH64_NE; - break; - - case CC_DGEmode: - ne = AARCH64_GE; - eq = AARCH64_LT; - break; - - case CC_DLTmode: - ne = AARCH64_LT; - eq = AARCH64_GE; - break; - - case CC_DGTmode: - ne = AARCH64_GT; - eq = AARCH64_LE; - break; - - case CC_DLEmode: - ne = AARCH64_LE; - eq = AARCH64_GT; - break; - - case CC_DGEUmode: - ne = AARCH64_CS; - eq = AARCH64_CC; - break; - - case CC_DLTUmode: - ne = AARCH64_CC; - eq = AARCH64_CS; - break; - - case CC_DGTUmode: - ne = AARCH64_HI; - eq = AARCH64_LS; - break; - - case CC_DLEUmode: - ne = AARCH64_LS; - eq = AARCH64_HI; - break; - case CCmode: switch (comp_code) { @@ -4330,12 +4288,6 @@ aarch64_get_condition_code_1 (enum machine_mode mode, enum rtx_code comp_code) break; } - if (comp_code == NE) - return ne; - - if (comp_code == EQ) - return eq; - return -1; } @@ -4376,69 +4328,27 @@ aarch64_const_vec_all_same_int_p (rtx x, HOST_WIDE_INT val) #define AARCH64_CC_Z (1 << 2) #define AARCH64_CC_N (1 << 3) -/* N Z C V flags for ccmp. The first code is for AND op and the other - is for IOR op. Indexed by AARCH64_COND_CODE. */ -static const int aarch64_nzcv_codes[][2] = -{ - {AARCH64_CC_Z, 0}, /* EQ, Z == 1. */ - {0, AARCH64_CC_Z}, /* NE, Z == 0. */ - {AARCH64_CC_C, 0}, /* CS, C == 1. */ - {0, AARCH64_CC_C}, /* CC, C == 0. */ - {AARCH64_CC_N, 0}, /* MI, N == 1. */ - {0, AARCH64_CC_N}, /* PL, N == 0. */ - {AARCH64_CC_V, 0}, /* VS, V == 1. */ - {0, AARCH64_CC_V}, /* VC, V == 0. */ - {AARCH64_CC_C, 0}, /* HI, C ==1 && Z == 0. */ - {0, AARCH64_CC_C}, /* LS, !(C == 1 && Z == 0). */ - {0, AARCH64_CC_V}, /* GE, N == V. */ - {AARCH64_CC_V, 0}, /* LT, N != V. */ - {0, AARCH64_CC_Z}, /* GT, Z == 0 && N == V. */ - {AARCH64_CC_Z, 0}, /* LE, !(Z == 0 && N == V). */ - {0, 0}, /* AL, Any. */ - {0, 0}, /* NV, Any. */ +/* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */ +static const int aarch64_nzcv_codes[] = +{ + 0, /* EQ, Z == 1. */ + AARCH64_CC_Z, /* NE, Z == 0. */ + 0, /* CS, C == 1. */ + AARCH64_CC_C, /* CC, C == 0. */ + 0, /* MI, N == 1. */ + AARCH64_CC_N, /* PL, N == 0. */ + 0, /* VS, V == 1. */ + AARCH64_CC_V, /* VC, V == 0. */ + 0, /* HI, C ==1 && Z == 0. */ + AARCH64_CC_C, /* LS, !(C == 1 && Z == 0). */ + AARCH64_CC_V, /* GE, N == V. */ + 0, /* LT, N != V. */ + AARCH64_CC_Z, /* GT, Z == 0 && N == V. */ + 0, /* LE, !(Z == 0 && N == V). */ + 0, /* AL, Any. */ + 0 /* NV, Any. */ }; -int -aarch64_ccmp_mode_to_code (enum machine_mode mode) -{ - switch (mode) - { - case CC_DNEmode: - return NE; - - case CC_DEQmode: - return EQ; - - case CC_DLEmode: - return LE; - - case CC_DGTmode: - return GT; - - case CC_DLTmode: - return LT; - - case CC_DGEmode: - return GE; - - case CC_DLEUmode: - return LEU; - - case CC_DGTUmode: - return GTU; - - case CC_DLTUmode: - return LTU; - - case CC_DGEUmode: - return GEU; - - default: - gcc_unreachable (); - } -} - - static void aarch64_print_operand (FILE *f, rtx x, int code) { @@ -4537,36 +4447,17 @@ aarch64_print_operand (FILE *f, rtx x, int code) asm_fprintf (f, "%s", reg_names [REGNO (x) + 1]); break; - case 'm': - { - int cond_code; - /* Print a condition (eq, ne, etc). */ - - /* CONST_TRUE_RTX means always -- that's the default. */ - if (x == const_true_rtx) - return; - - if (!COMPARISON_P (x)) - { - output_operand_lossage ("invalid operand for '%%%c'", code); - return; - } - - cond_code = aarch64_get_condition_code (x); - gcc_assert (cond_code >= 0); - fputs (aarch64_condition_codes[cond_code], f); - } - break; - case 'M': + case 'm': { int cond_code; - /* Print the inverse of a condition (eq <-> ne, etc). */ + /* Print a condition (eq, ne, etc) or its inverse. */ - /* CONST_TRUE_RTX means never -- that's the default. */ - if (x == const_true_rtx) + /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */ + if (x == const_true_rtx) { - fputs ("nv", f); + if (code == 'M') + fputs ("nv", f); return; } @@ -4575,10 +4466,12 @@ aarch64_print_operand (FILE *f, rtx x, int code) output_operand_lossage ("invalid operand for '%%%c'", code); return; } + cond_code = aarch64_get_condition_code (x); gcc_assert (cond_code >= 0); - fputs (aarch64_condition_codes[AARCH64_INVERSE_CONDITION_CODE - (cond_code)], f); + if (code == 'M') + cond_code = AARCH64_INVERSE_CONDITION_CODE (cond_code); + fputs (aarch64_condition_codes[cond_code], f); } break; @@ -4819,37 +4712,20 @@ aarch64_print_operand (FILE *f, rtx x, int code) output_addr_const (asm_out_file, x); break; - case 'K': - { - int cond_code; - /* Print nzcv. */ - - if (!COMPARISON_P (x)) - { - output_operand_lossage ("invalid operand for '%%%c'", code); - return; - } - - cond_code = aarch64_get_condition_code_1 (CCmode, GET_CODE (x)); - gcc_assert (cond_code >= 0); - asm_fprintf (f, "%d", aarch64_nzcv_codes[cond_code][0]); - } - break; - case 'k': { - int cond_code; + HOST_WIDE_INT cond_code; /* Print nzcv. */ - if (!COMPARISON_P (x)) + if (!CONST_INT_P (x)) { output_operand_lossage ("invalid operand for '%%%c'", code); return; } - cond_code = aarch64_get_condition_code_1 (CCmode, GET_CODE (x)); - gcc_assert (cond_code >= 0); - asm_fprintf (f, "%d", aarch64_nzcv_codes[cond_code][1]); + cond_code = INTVAL (x); + gcc_assert (cond_code >= 0 && cond_code <= AARCH64_NV); + asm_fprintf (f, "%d", aarch64_nzcv_codes[cond_code]); } break; @@ -6128,6 +6004,26 @@ aarch64_if_then_else_costs (rtx op0, rtx op1, rtx op2, int *cost, bool speed) } else if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_CC) { + /* CCMP. */ + if ((GET_CODE (op1) == COMPARE) && CONST_INT_P (op2)) + { + /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */ + if (XEXP (op1, 1) == const0_rtx) + *cost += 1; + if (speed) + { + machine_mode mode = GET_MODE (XEXP (op1, 0)); + const struct cpu_cost_table *extra_cost + = aarch64_tune_params.insn_extra_cost; + + if (GET_MODE_CLASS (mode) == MODE_INT) + *cost += extra_cost->alu.arith; + else + *cost += extra_cost->fp[mode == DFmode].compare; + } + return true; + } + /* It's a conditional operation based on the status flags, so it must be some flavor of CSEL. */ @@ -6136,6 +6032,12 @@ aarch64_if_then_else_costs (rtx op0, rtx op1, rtx op2, int *cost, bool speed) || GET_CODE (op1) == NOT || (GET_CODE (op1) == PLUS && XEXP (op1, 1) == const1_rtx)) op1 = XEXP (op1, 0); + else if (GET_CODE (op1) == ZERO_EXTEND && GET_CODE (op2) == ZERO_EXTEND) + { + /* CSEL with zero-extension (*cmovdi_insn_uxtw). */ + op1 = XEXP (op1, 0); + op2 = XEXP (op2, 0); + } *cost += rtx_cost (op1, VOIDmode, IF_THEN_ELSE, 1, speed); *cost += rtx_cost (op2, VOIDmode, IF_THEN_ELSE, 2, speed); @@ -6146,6 +6048,50 @@ aarch64_if_then_else_costs (rtx op0, rtx op1, rtx op2, int *cost, bool speed) return false; } +/* Check whether X is a bitfield operation of the form shift + extend that + maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the + operand to which the bitfield operation is applied. Otherwise return + NULL_RTX. */ + +static rtx +aarch64_extend_bitfield_pattern_p (rtx x) +{ + rtx_code outer_code = GET_CODE (x); + machine_mode outer_mode = GET_MODE (x); + + if (outer_code != ZERO_EXTEND && outer_code != SIGN_EXTEND + && outer_mode != SImode && outer_mode != DImode) + return NULL_RTX; + + rtx inner = XEXP (x, 0); + rtx_code inner_code = GET_CODE (inner); + machine_mode inner_mode = GET_MODE (inner); + rtx op = NULL_RTX; + + switch (inner_code) + { + case ASHIFT: + if (CONST_INT_P (XEXP (inner, 1)) + && (inner_mode == QImode || inner_mode == HImode)) + op = XEXP (inner, 0); + break; + case LSHIFTRT: + if (outer_code == ZERO_EXTEND && CONST_INT_P (XEXP (inner, 1)) + && (inner_mode == QImode || inner_mode == HImode)) + op = XEXP (inner, 0); + break; + case ASHIFTRT: + if (outer_code == SIGN_EXTEND && CONST_INT_P (XEXP (inner, 1)) + && (inner_mode == QImode || inner_mode == HImode)) + op = XEXP (inner, 0); + break; + default: + break; + } + + return op; +} + /* Calculate the cost of calculating X, storing it in *COST. Result is true if the total cost of the operation has now been calculated. */ static bool @@ -6437,6 +6383,23 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED, goto cost_minus; } + if (GET_CODE (op0) == ZERO_EXTRACT && op1 == const0_rtx + && GET_MODE (x) == CC_NZmode && CONST_INT_P (XEXP (op0, 1)) + && CONST_INT_P (XEXP (op0, 2))) + { + /* COMPARE of ZERO_EXTRACT form of TST-immediate. + Handle it here directly rather than going to cost_logic + since we know the immediate generated for the TST is valid + so we can avoid creating an intermediate rtx for it only + for costing purposes. */ + if (speed) + *cost += extra_cost->alu.logical; + + *cost += rtx_cost (XEXP (op0, 0), GET_MODE (op0), + ZERO_EXTRACT, 0, speed); + return true; + } + if (GET_CODE (op1) == NEG) { /* CMN. */ @@ -6837,6 +6800,15 @@ cost_plus: return true; } + op0 = aarch64_extend_bitfield_pattern_p (x); + if (op0) + { + *cost += rtx_cost (op0, mode, ZERO_EXTEND, 0, speed); + if (speed) + *cost += extra_cost->alu.bfx; + return true; + } + if (speed) { if (VECTOR_MODE_P (mode)) @@ -6868,6 +6840,15 @@ cost_plus: return true; } + op0 = aarch64_extend_bitfield_pattern_p (x); + if (op0) + { + *cost += rtx_cost (op0, mode, SIGN_EXTEND, 0, speed); + if (speed) + *cost += extra_cost->alu.bfx; + return true; + } + if (speed) { if (VECTOR_MODE_P (mode)) @@ -8827,6 +8808,7 @@ aarch64_process_one_target_attr (char *arg_str, const char* pragma_or_attr) arg++; } const struct aarch64_attribute_info *p_attr; + bool found = false; for (p_attr = aarch64_attributes; p_attr->name; p_attr++) { /* If the names don't match up, or the user has given an argument @@ -8835,6 +8817,7 @@ aarch64_process_one_target_attr (char *arg_str, const char* pragma_or_attr) if (strcmp (str_to_check, p_attr->name) != 0) continue; + found = true; bool attr_need_arg_p = p_attr->attr_type == aarch64_attr_custom || p_attr->attr_type == aarch64_attr_enum; @@ -8914,7 +8897,10 @@ aarch64_process_one_target_attr (char *arg_str, const char* pragma_or_attr) } } - return true; + /* If we reached here we either have found an attribute and validated + it or didn't match any. If we matched an attribute but its arguments + were malformed we will have returned false already. */ + return found; } /* Count how many times the character C appears in @@ -10666,6 +10652,21 @@ aarch64_simd_imm_zero_p (rtx x, machine_mode mode) return x == CONST0_RTX (mode); } + +/* Return the bitmask CONST_INT to select the bits required by a zero extract + operation of width WIDTH at bit position POS. */ + +rtx +aarch64_mask_from_zextract_ops (rtx width, rtx pos) +{ + gcc_assert (CONST_INT_P (width)); + gcc_assert (CONST_INT_P (pos)); + + unsigned HOST_WIDE_INT mask + = ((unsigned HOST_WIDE_INT) 1 << UINTVAL (width)) - 1; + return GEN_INT (mask << UINTVAL (pos)); +} + bool aarch64_simd_imm_scalar_p (rtx x, machine_mode mode ATTRIBUTE_UNUSED) { @@ -12952,60 +12953,16 @@ aarch64_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size, return default_use_by_pieces_infrastructure_p (size, align, op, speed_p); } -static enum machine_mode -aarch64_code_to_ccmode (enum rtx_code code) -{ - switch (code) - { - case NE: - return CC_DNEmode; - - case EQ: - return CC_DEQmode; - - case LE: - return CC_DLEmode; - - case LT: - return CC_DLTmode; - - case GE: - return CC_DGEmode; - - case GT: - return CC_DGTmode; - - case LEU: - return CC_DLEUmode; - - case LTU: - return CC_DLTUmode; - - case GEU: - return CC_DGEUmode; - - case GTU: - return CC_DGTUmode; - - default: - return CCmode; - } -} - static rtx aarch64_gen_ccmp_first (rtx *prep_seq, rtx *gen_seq, int code, tree treeop0, tree treeop1) { - enum machine_mode op_mode, cmp_mode, cc_mode; - rtx op0, op1, cmp, target; + machine_mode op_mode, cmp_mode, cc_mode = CCmode; + rtx op0, op1; int unsignedp = TYPE_UNSIGNED (TREE_TYPE (treeop0)); - enum insn_code icode; + insn_code icode; struct expand_operand ops[4]; - cc_mode = aarch64_code_to_ccmode ((enum rtx_code) code); - if (cc_mode == CCmode) - return NULL_RTX; - start_sequence (); expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, EXPAND_NORMAL); @@ -13027,13 +12984,25 @@ aarch64_gen_ccmp_first (rtx *prep_seq, rtx *gen_seq, icode = CODE_FOR_cmpdi; break; + case SFmode: + cmp_mode = SFmode; + cc_mode = aarch64_select_cc_mode ((rtx_code) code, op0, op1); + icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpesf : CODE_FOR_fcmpsf; + break; + + case DFmode: + cmp_mode = DFmode; + cc_mode = aarch64_select_cc_mode ((rtx_code) code, op0, op1); + icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpedf : CODE_FOR_fcmpdf; + break; + default: end_sequence (); return NULL_RTX; } - op0 = prepare_operand (icode, op0, 2, op_mode, cmp_mode, unsignedp); - op1 = prepare_operand (icode, op1, 3, op_mode, cmp_mode, unsignedp); + op0 = prepare_operand (icode, op0, 0, op_mode, cmp_mode, unsignedp); + op1 = prepare_operand (icode, op1, 1, op_mode, cmp_mode, unsignedp); if (!op0 || !op1) { end_sequence (); @@ -13042,16 +13011,11 @@ aarch64_gen_ccmp_first (rtx *prep_seq, rtx *gen_seq, *prep_seq = get_insns (); end_sequence (); - cmp = gen_rtx_fmt_ee ((enum rtx_code) code, cmp_mode, op0, op1); - target = gen_rtx_REG (CCmode, CC_REGNUM); - - create_output_operand (&ops[0], target, CCmode); - create_fixed_operand (&ops[1], cmp); - create_fixed_operand (&ops[2], op0); - create_fixed_operand (&ops[3], op1); + create_fixed_operand (&ops[0], op0); + create_fixed_operand (&ops[1], op1); start_sequence (); - if (!maybe_expand_insn (icode, 4, ops)) + if (!maybe_expand_insn (icode, 2, ops)) { end_sequence (); return NULL_RTX; @@ -13059,22 +13023,20 @@ aarch64_gen_ccmp_first (rtx *prep_seq, rtx *gen_seq, *gen_seq = get_insns (); end_sequence (); - return gen_rtx_REG (cc_mode, CC_REGNUM); + return gen_rtx_fmt_ee ((rtx_code) code, cc_mode, + gen_rtx_REG (cc_mode, CC_REGNUM), const0_rtx); } static rtx aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code, tree treeop0, tree treeop1, int bit_code) { - rtx op0, op1, cmp0, cmp1, target; - enum machine_mode op_mode, cmp_mode, cc_mode; + rtx op0, op1, target; + machine_mode op_mode, cmp_mode, cc_mode = CCmode; int unsignedp = TYPE_UNSIGNED (TREE_TYPE (treeop0)); - enum insn_code icode = CODE_FOR_ccmp_andsi; + insn_code icode; struct expand_operand ops[6]; - - cc_mode = aarch64_code_to_ccmode ((enum rtx_code) cmp_code); - if (cc_mode == CCmode) - return NULL_RTX; + int aarch64_cond; push_to_sequence ((rtx_insn*) *prep_seq); expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, EXPAND_NORMAL); @@ -13089,14 +13051,24 @@ aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code, case HImode: case SImode: cmp_mode = SImode; - icode = (enum rtx_code) bit_code == AND ? CODE_FOR_ccmp_andsi - : CODE_FOR_ccmp_iorsi; + icode = CODE_FOR_ccmpsi; break; case DImode: cmp_mode = DImode; - icode = (enum rtx_code) bit_code == AND ? CODE_FOR_ccmp_anddi - : CODE_FOR_ccmp_iordi; + icode = CODE_FOR_ccmpdi; + break; + + case SFmode: + cmp_mode = SFmode; + cc_mode = aarch64_select_cc_mode ((rtx_code) cmp_code, op0, op1); + icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpesf : CODE_FOR_fccmpsf; + break; + + case DFmode: + cmp_mode = DFmode; + cc_mode = aarch64_select_cc_mode ((rtx_code) cmp_code, op0, op1); + icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpedf : CODE_FOR_fccmpdf; break; default: @@ -13115,15 +13087,22 @@ aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code, end_sequence (); target = gen_rtx_REG (cc_mode, CC_REGNUM); - cmp1 = gen_rtx_fmt_ee ((enum rtx_code) cmp_code, cmp_mode, op0, op1); - cmp0 = gen_rtx_fmt_ee (NE, cmp_mode, prev, const0_rtx); + aarch64_cond = aarch64_get_condition_code_1 (cc_mode, (rtx_code) cmp_code); - create_fixed_operand (&ops[0], prev); + if (bit_code != AND) + { + prev = gen_rtx_fmt_ee (REVERSE_CONDITION (GET_CODE (prev), + GET_MODE (XEXP (prev, 0))), + VOIDmode, XEXP (prev, 0), const0_rtx); + aarch64_cond = AARCH64_INVERSE_CONDITION_CODE (aarch64_cond); + } + + create_fixed_operand (&ops[0], XEXP (prev, 0)); create_fixed_operand (&ops[1], target); create_fixed_operand (&ops[2], op0); create_fixed_operand (&ops[3], op1); - create_fixed_operand (&ops[4], cmp0); - create_fixed_operand (&ops[5], cmp1); + create_fixed_operand (&ops[4], prev); + create_fixed_operand (&ops[5], GEN_INT (aarch64_cond)); push_to_sequence ((rtx_insn*) *gen_seq); if (!maybe_expand_insn (icode, 6, ops)) @@ -13135,7 +13114,7 @@ aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code, *gen_seq = get_insns (); end_sequence (); - return target; + return gen_rtx_fmt_ee ((rtx_code) cmp_code, VOIDmode, target, const0_rtx); } #undef TARGET_GEN_CCMP_FIRST diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index e2ead511076..8b463c96b2d 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -1,5 +1,5 @@ /* Machine description for AArch64 architecture. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index dd93012039d..2f543aab967 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 architecture. -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -271,18 +271,17 @@ "" "") -(define_insn "ccmp_and<mode>" - [(set (match_operand 1 "ccmp_cc_register" "") - (compare - (and:SI +(define_insn "ccmp<mode>" + [(set (match_operand:CC 1 "cc_register" "") + (if_then_else:CC (match_operator 4 "aarch64_comparison_operator" - [(match_operand 0 "ccmp_cc_register" "") + [(match_operand 0 "cc_register" "") (const_int 0)]) - (match_operator 5 "aarch64_comparison_operator" - [(match_operand:GPI 2 "register_operand" "r,r,r") - (match_operand:GPI 3 "aarch64_ccmp_operand" "r,Uss,Usn")])) - (const_int 0)))] - "aarch64_ccmp_mode_to_code (GET_MODE (operands[1])) == GET_CODE (operands[5])" + (compare:CC + (match_operand:GPI 2 "register_operand" "r,r,r") + (match_operand:GPI 3 "aarch64_ccmp_operand" "r,Uss,Usn")) + (match_operand 5 "immediate_operand")))] + "" "@ ccmp\\t%<w>2, %<w>3, %k5, %m4 ccmp\\t%<w>2, %<w>3, %k5, %m4 @@ -290,37 +289,34 @@ [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) -(define_insn "ccmp_ior<mode>" - [(set (match_operand 1 "ccmp_cc_register" "") - (compare - (ior:SI +(define_insn "fccmp<mode>" + [(set (match_operand:CCFP 1 "cc_register" "") + (if_then_else:CCFP (match_operator 4 "aarch64_comparison_operator" - [(match_operand 0 "ccmp_cc_register" "") + [(match_operand 0 "cc_register" "") (const_int 0)]) - (match_operator 5 "aarch64_comparison_operator" - [(match_operand:GPI 2 "register_operand" "r,r,r") - (match_operand:GPI 3 "aarch64_ccmp_operand" "r,Uss,Usn")])) - (const_int 0)))] - "aarch64_ccmp_mode_to_code (GET_MODE (operands[1])) == GET_CODE (operands[5])" - "@ - ccmp\\t%<w>2, %<w>3, %K5, %M4 - ccmp\\t%<w>2, %<w>3, %K5, %M4 - ccmn\\t%<w>2, #%n3, %K5, %M4" - [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] + (compare:CCFP + (match_operand:GPF 2 "register_operand" "w") + (match_operand:GPF 3 "register_operand" "w")) + (match_operand 5 "immediate_operand")))] + "TARGET_FLOAT" + "fccmp\\t%<s>2, %<s>3, %k5, %m4" + [(set_attr "type" "fcmp<s>")] ) -(define_expand "cmp<mode>" - [(set (match_operand 0 "cc_register" "") - (match_operator:CC 1 "aarch64_comparison_operator" - [(match_operand:GPI 2 "register_operand" "") - (match_operand:GPI 3 "aarch64_plus_operand" "")]))] - "" - { - operands[1] = gen_rtx_fmt_ee (COMPARE, - SELECT_CC_MODE (GET_CODE (operands[1]), - operands[2], operands[3]), - operands[2], operands[3]); - } +(define_insn "fccmpe<mode>" + [(set (match_operand:CCFPE 1 "cc_register" "") + (if_then_else:CCFPE + (match_operator 4 "aarch64_comparison_operator" + [(match_operand 0 "cc_register" "") + (const_int 0)]) + (compare:CCFPE + (match_operand:GPF 2 "register_operand" "w") + (match_operand:GPF 3 "register_operand" "w")) + (match_operand 5 "immediate_operand")))] + "TARGET_FLOAT" + "fccmpe\\t%<s>2, %<s>3, %k5, %m4" + [(set_attr "type" "fcmp<s>")] ) ;; Expansion of signed mod by a power of 2 using CSNEG. @@ -1590,96 +1586,120 @@ (plus:GPI (match_operand:GPI 1 "register_operand" "") (match_operand:GPI 2 "aarch64_pluslong_operand" "")))] "" - " - if (!aarch64_plus_operand (operands[2], VOIDmode)) +{ + if (aarch64_pluslong_strict_immedate (operands[2], <MODE>mode)) { - if (can_create_pseudo_p ()) - { - rtx tmp = gen_reg_rtx (<MODE>mode); - emit_move_insn (tmp, operands[2]); - operands[2] = tmp; - } - else + /* Give CSE the opportunity to share this constant across additions. */ + if (!cse_not_expected && can_create_pseudo_p ()) + operands[2] = force_reg (<MODE>mode, operands[2]); + + /* Split will refuse to operate on a modification to the stack pointer. + Aid the prologue and epilogue expanders by splitting this now. */ + else if (reload_completed && operands[0] == stack_pointer_rtx) { - HOST_WIDE_INT imm = INTVAL (operands[2]); - imm = imm >= 0 ? imm & 0xfff : -(-imm & 0xfff); - emit_insn (gen_add<mode>3 (operands[0], operands[1], - GEN_INT (INTVAL (operands[2]) - imm))); + HOST_WIDE_INT i = INTVAL (operands[2]); + HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff)); + emit_insn (gen_rtx_SET (operands[0], + gen_rtx_PLUS (<MODE>mode, operands[1], + GEN_INT (i - s)))); operands[1] = operands[0]; - operands[2] = GEN_INT (imm); + operands[2] = GEN_INT (s); } } - " -) - -;; Find add with a 2-instruction immediate and merge into 2 add instructions. - -(define_insn_and_split "*add<mode>3_pluslong" - [(set - (match_operand:GPI 0 "register_operand" "=r") - (plus:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand:GPI 2 "aarch64_pluslong_immediate" "i")))] - "!aarch64_plus_operand (operands[2], VOIDmode) - && !aarch64_move_imm (INTVAL (operands[2]), <MODE>mode)" - "#" - "&& true" - [(set (match_dup 0) (plus:GPI (match_dup 1) (match_dup 3))) - (set (match_dup 0) (plus:GPI (match_dup 0) (match_dup 4)))] - " - { - HOST_WIDE_INT imm = INTVAL (operands[2]); - imm = imm >= 0 ? imm & 0xfff : -(-imm & 0xfff); - operands[3] = GEN_INT (INTVAL (operands[2]) - imm); - operands[4] = GEN_INT (imm); - } - " -) +}) -(define_insn "*addsi3_aarch64" +(define_insn "*add<mode>3_aarch64" [(set - (match_operand:SI 0 "register_operand" "=rk,rk,w,rk") - (plus:SI - (match_operand:SI 1 "register_operand" "%rk,rk,w,rk") - (match_operand:SI 2 "aarch64_plus_operand" "I,r,w,J")))] + (match_operand:GPI 0 "register_operand" "=rk,rk,w,rk,r") + (plus:GPI + (match_operand:GPI 1 "register_operand" "%rk,rk,w,rk,rk") + (match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Upl")))] "" "@ - add\\t%w0, %w1, %2 - add\\t%w0, %w1, %w2 - add\\t%0.2s, %1.2s, %2.2s - sub\\t%w0, %w1, #%n2" - [(set_attr "type" "alu_imm,alu_sreg,neon_add,alu_imm") - (set_attr "simd" "*,*,yes,*")] + add\\t%<w>0, %<w>1, %2 + add\\t%<w>0, %<w>1, %<w>2 + add\\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas> + sub\\t%<w>0, %<w>1, #%n2 + #" + [(set_attr "type" "alu_imm,alu_sreg,neon_add,alu_imm,multiple") + (set_attr "simd" "*,*,yes,*,*")] ) ;; zero_extend version of above (define_insn "*addsi3_aarch64_uxtw" [(set - (match_operand:DI 0 "register_operand" "=rk,rk,rk") + (match_operand:DI 0 "register_operand" "=rk,rk,rk,r") (zero_extend:DI - (plus:SI (match_operand:SI 1 "register_operand" "%rk,rk,rk") - (match_operand:SI 2 "aarch64_plus_operand" "I,r,J"))))] + (plus:SI (match_operand:SI 1 "register_operand" "%rk,rk,rk,rk") + (match_operand:SI 2 "aarch64_pluslong_operand" "I,r,J,Upl"))))] "" "@ add\\t%w0, %w1, %2 add\\t%w0, %w1, %w2 - sub\\t%w0, %w1, #%n2" - [(set_attr "type" "alu_imm,alu_sreg,alu_imm")] + sub\\t%w0, %w1, #%n2 + #" + [(set_attr "type" "alu_imm,alu_sreg,alu_imm,multiple")] ) -(define_insn "*adddi3_aarch64" - [(set - (match_operand:DI 0 "register_operand" "=rk,rk,rk,w") - (plus:DI - (match_operand:DI 1 "register_operand" "%rk,rk,rk,w") - (match_operand:DI 2 "aarch64_plus_operand" "I,r,J,w")))] - "" - "@ - add\\t%x0, %x1, %2 - add\\t%x0, %x1, %x2 - sub\\t%x0, %x1, #%n2 - add\\t%d0, %d1, %d2" - [(set_attr "type" "alu_imm,alu_sreg,alu_imm,neon_add") - (set_attr "simd" "*,*,*,yes")] +;; If there's a free register, and we can load the constant with a +;; single instruction, do so. This has a chance to improve scheduling. +(define_peephole2 + [(match_scratch:GPI 3 "r") + (set (match_operand:GPI 0 "register_operand") + (plus:GPI + (match_operand:GPI 1 "register_operand") + (match_operand:GPI 2 "aarch64_pluslong_strict_immedate")))] + "aarch64_move_imm (INTVAL (operands[2]), <MODE>mode)" + [(set (match_dup 3) (match_dup 2)) + (set (match_dup 0) (plus:GPI (match_dup 1) (match_dup 3)))] +) + +(define_peephole2 + [(match_scratch:SI 3 "r") + (set (match_operand:DI 0 "register_operand") + (zero_extend:DI + (plus:SI + (match_operand:SI 1 "register_operand") + (match_operand:SI 2 "aarch64_pluslong_strict_immedate"))))] + "aarch64_move_imm (INTVAL (operands[2]), SImode)" + [(set (match_dup 3) (match_dup 2)) + (set (match_dup 0) (zero_extend:DI (plus:SI (match_dup 1) (match_dup 3))))] +) + +;; After peephole2 has had a chance to run, split any remaining long +;; additions into two add immediates. +(define_split + [(set (match_operand:GPI 0 "register_operand") + (plus:GPI + (match_operand:GPI 1 "register_operand") + (match_operand:GPI 2 "aarch64_pluslong_strict_immedate")))] + "epilogue_completed" + [(set (match_dup 0) (plus:GPI (match_dup 1) (match_dup 3))) + (set (match_dup 0) (plus:GPI (match_dup 0) (match_dup 4)))] + { + HOST_WIDE_INT i = INTVAL (operands[2]); + HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff)); + operands[3] = GEN_INT (i - s); + operands[4] = GEN_INT (s); + } +) + +(define_split + [(set (match_operand:DI 0 "register_operand") + (zero_extend:DI + (plus:SI + (match_operand:SI 1 "register_operand") + (match_operand:SI 2 "aarch64_pluslong_strict_immedate"))))] + "epilogue_completed" + [(set (match_dup 5) (plus:SI (match_dup 1) (match_dup 3))) + (set (match_dup 0) (zero_extend:DI (plus:SI (match_dup 5) (match_dup 4))))] + { + HOST_WIDE_INT i = INTVAL (operands[2]); + HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff)); + operands[3] = GEN_INT (i - s); + operands[4] = GEN_INT (s); + operands[5] = gen_lowpart (SImode, operands[0]); + } ) (define_expand "addti3" @@ -2850,7 +2870,7 @@ ;; Comparison insns ;; ------------------------------------------------------------------- -(define_insn "*cmp<mode>" +(define_insn "cmp<mode>" [(set (reg:CC CC_REGNUM) (compare:CC (match_operand:GPI 0 "register_operand" "r,r,r") (match_operand:GPI 1 "aarch64_plus_operand" "r,I,J")))] @@ -2862,7 +2882,7 @@ [(set_attr "type" "alus_sreg,alus_imm,alus_imm")] ) -(define_insn "*cmp<mode>" +(define_insn "fcmp<mode>" [(set (reg:CCFP CC_REGNUM) (compare:CCFP (match_operand:GPF 0 "register_operand" "w,w") (match_operand:GPF 1 "aarch64_fp_compare_operand" "Y,w")))] @@ -2873,7 +2893,7 @@ [(set_attr "type" "fcmp<s>")] ) -(define_insn "*cmpe<mode>" +(define_insn "fcmpe<mode>" [(set (reg:CCFPE CC_REGNUM) (compare:CCFPE (match_operand:GPF 0 "register_operand" "w,w") (match_operand:GPF 1 "aarch64_fp_compare_operand" "Y,w")))] @@ -2937,7 +2957,7 @@ (define_expand "cstorecc4" [(set (match_operand:SI 0 "register_operand") (match_operator 1 "aarch64_comparison_operator" - [(match_operand 2 "ccmp_cc_register") + [(match_operand 2 "cc_register") (match_operand 3 "const0_operand")]))] "" "{ @@ -3140,19 +3160,15 @@ (match_operand:ALLI 3 "register_operand" "")))] "" { + rtx ccreg; enum rtx_code code = GET_CODE (operands[1]); if (code == UNEQ || code == LTGT) FAIL; - if (!ccmp_cc_register (XEXP (operands[1], 0), - GET_MODE (XEXP (operands[1], 0)))) - { - rtx ccreg; - ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), - XEXP (operands[1], 1)); - operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); - } + ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), + XEXP (operands[1], 1)); + operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); } ) @@ -3672,6 +3688,16 @@ } ) +(define_insn "*and<mode>_compare0" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (match_operand:SHORT 0 "register_operand" "r") + (const_int 0)))] + "" + "tst\\t%<w>0, <short_mask>" + [(set_attr "type" "alus_imm")] +) + (define_insn "*and<mode>3nr_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ @@ -3683,6 +3709,28 @@ [(set_attr "type" "logics_reg,logics_imm")] ) +(define_insn "*and<mode>3nr_compare0_zextract" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (zero_extract:GPI (match_operand:GPI 0 "register_operand" "r") + (match_operand:GPI 1 "const_int_operand" "n") + (match_operand:GPI 2 "const_int_operand" "n")) + (const_int 0)))] + "INTVAL (operands[1]) > 0 + && ((INTVAL (operands[1]) + INTVAL (operands[2])) + <= GET_MODE_BITSIZE (<MODE>mode)) + && aarch64_bitmask_imm ( + UINTVAL (aarch64_mask_from_zextract_ops (operands[1], + operands[2])), + <MODE>mode)" + { + operands[1] + = aarch64_mask_from_zextract_ops (operands[1], operands[2]); + return "tst\\t%<w>0, %1"; + } + [(set_attr "type" "logics_shift_imm")] +) + (define_insn "*and_<SHIFT:optab><mode>3nr_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index a0fbfd42c09..5cbd4cd04b9 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -1,5 +1,5 @@ ; Machine description for AArch64 architecture. -; Copyright (C) 2009-2015 Free Software Foundation, Inc. +; Copyright (C) 2009-2016 Free Software Foundation, Inc. ; Contributed by ARM Ltd. ; ; This file is part of GCC. diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h index addbc6aae31..3f85d527936 100644 --- a/gcc/config/aarch64/arm_acle.h +++ b/gcc/config/aarch64/arm_acle.h @@ -1,6 +1,6 @@ /* AArch64 Non-NEON ACLE intrinsics include file. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 56db3391785..1334d64c7b4 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -1,6 +1,6 @@ /* ARM NEON intrinsics include file. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -13203,9 +13203,7 @@ vcvt_s32_f32 (float32x2_t __a) __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vcvt_u32_f32 (float32x2_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint32x2_t) __builtin_aarch64_lbtruncuv2sfv2si (__a); + return __builtin_aarch64_lbtruncuv2sfv2si_us (__a); } __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) @@ -13217,9 +13215,7 @@ vcvtq_s32_f32 (float32x4_t __a) __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcvtq_u32_f32 (float32x4_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint32x4_t) __builtin_aarch64_lbtruncuv4sfv4si (__a); + return __builtin_aarch64_lbtruncuv4sfv4si_us (__a); } __extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) @@ -13231,9 +13227,7 @@ vcvtq_s64_f64 (float64x2_t __a) __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcvtq_u64_f64 (float64x2_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint64x2_t) __builtin_aarch64_lbtruncuv2dfv2di (__a); + return __builtin_aarch64_lbtruncuv2dfv2di_us (__a); } /* vcvta */ @@ -13247,7 +13241,7 @@ vcvtad_s64_f64 (float64_t __a) __extension__ static __inline uint64_t __attribute__ ((__always_inline__)) vcvtad_u64_f64 (float64_t __a) { - return __builtin_aarch64_lroundudfdi (__a); + return __builtin_aarch64_lroundudfdi_us (__a); } __extension__ static __inline int32_t __attribute__ ((__always_inline__)) @@ -13259,7 +13253,7 @@ vcvtas_s32_f32 (float32_t __a) __extension__ static __inline uint32_t __attribute__ ((__always_inline__)) vcvtas_u32_f32 (float32_t __a) { - return __builtin_aarch64_lroundusfsi (__a); + return __builtin_aarch64_lroundusfsi_us (__a); } __extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) @@ -13271,9 +13265,7 @@ vcvta_s32_f32 (float32x2_t __a) __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vcvta_u32_f32 (float32x2_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint32x2_t) __builtin_aarch64_lrounduv2sfv2si (__a); + return __builtin_aarch64_lrounduv2sfv2si_us (__a); } __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) @@ -13285,9 +13277,7 @@ vcvtaq_s32_f32 (float32x4_t __a) __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcvtaq_u32_f32 (float32x4_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint32x4_t) __builtin_aarch64_lrounduv4sfv4si (__a); + return __builtin_aarch64_lrounduv4sfv4si_us (__a); } __extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) @@ -13299,9 +13289,7 @@ vcvtaq_s64_f64 (float64x2_t __a) __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcvtaq_u64_f64 (float64x2_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint64x2_t) __builtin_aarch64_lrounduv2dfv2di (__a); + return __builtin_aarch64_lrounduv2dfv2di_us (__a); } /* vcvtm */ @@ -13315,7 +13303,7 @@ vcvtmd_s64_f64 (float64_t __a) __extension__ static __inline uint64_t __attribute__ ((__always_inline__)) vcvtmd_u64_f64 (float64_t __a) { - return __builtin_aarch64_lfloorudfdi (__a); + return __builtin_aarch64_lfloorudfdi_us (__a); } __extension__ static __inline int32_t __attribute__ ((__always_inline__)) @@ -13327,7 +13315,7 @@ vcvtms_s32_f32 (float32_t __a) __extension__ static __inline uint32_t __attribute__ ((__always_inline__)) vcvtms_u32_f32 (float32_t __a) { - return __builtin_aarch64_lfloorusfsi (__a); + return __builtin_aarch64_lfloorusfsi_us (__a); } __extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) @@ -13339,9 +13327,7 @@ vcvtm_s32_f32 (float32x2_t __a) __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vcvtm_u32_f32 (float32x2_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint32x2_t) __builtin_aarch64_lflooruv2sfv2si (__a); + return __builtin_aarch64_lflooruv2sfv2si_us (__a); } __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) @@ -13353,9 +13339,7 @@ vcvtmq_s32_f32 (float32x4_t __a) __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcvtmq_u32_f32 (float32x4_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint32x4_t) __builtin_aarch64_lflooruv4sfv4si (__a); + return __builtin_aarch64_lflooruv4sfv4si_us (__a); } __extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) @@ -13367,9 +13351,7 @@ vcvtmq_s64_f64 (float64x2_t __a) __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcvtmq_u64_f64 (float64x2_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint64x2_t) __builtin_aarch64_lflooruv2dfv2di (__a); + return __builtin_aarch64_lflooruv2dfv2di_us (__a); } /* vcvtn */ @@ -13383,7 +13365,7 @@ vcvtnd_s64_f64 (float64_t __a) __extension__ static __inline uint64_t __attribute__ ((__always_inline__)) vcvtnd_u64_f64 (float64_t __a) { - return __builtin_aarch64_lfrintnudfdi (__a); + return __builtin_aarch64_lfrintnudfdi_us (__a); } __extension__ static __inline int32_t __attribute__ ((__always_inline__)) @@ -13395,7 +13377,7 @@ vcvtns_s32_f32 (float32_t __a) __extension__ static __inline uint32_t __attribute__ ((__always_inline__)) vcvtns_u32_f32 (float32_t __a) { - return __builtin_aarch64_lfrintnusfsi (__a); + return __builtin_aarch64_lfrintnusfsi_us (__a); } __extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) @@ -13407,9 +13389,7 @@ vcvtn_s32_f32 (float32x2_t __a) __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vcvtn_u32_f32 (float32x2_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint32x2_t) __builtin_aarch64_lfrintnuv2sfv2si (__a); + return __builtin_aarch64_lfrintnuv2sfv2si_us (__a); } __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) @@ -13421,9 +13401,7 @@ vcvtnq_s32_f32 (float32x4_t __a) __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcvtnq_u32_f32 (float32x4_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint32x4_t) __builtin_aarch64_lfrintnuv4sfv4si (__a); + return __builtin_aarch64_lfrintnuv4sfv4si_us (__a); } __extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) @@ -13435,9 +13413,7 @@ vcvtnq_s64_f64 (float64x2_t __a) __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcvtnq_u64_f64 (float64x2_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint64x2_t) __builtin_aarch64_lfrintnuv2dfv2di (__a); + return __builtin_aarch64_lfrintnuv2dfv2di_us (__a); } /* vcvtp */ @@ -13451,7 +13427,7 @@ vcvtpd_s64_f64 (float64_t __a) __extension__ static __inline uint64_t __attribute__ ((__always_inline__)) vcvtpd_u64_f64 (float64_t __a) { - return __builtin_aarch64_lceiludfdi (__a); + return __builtin_aarch64_lceiludfdi_us (__a); } __extension__ static __inline int32_t __attribute__ ((__always_inline__)) @@ -13463,7 +13439,7 @@ vcvtps_s32_f32 (float32_t __a) __extension__ static __inline uint32_t __attribute__ ((__always_inline__)) vcvtps_u32_f32 (float32_t __a) { - return __builtin_aarch64_lceilusfsi (__a); + return __builtin_aarch64_lceilusfsi_us (__a); } __extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) @@ -13475,9 +13451,7 @@ vcvtp_s32_f32 (float32x2_t __a) __extension__ static __inline uint32x2_t __attribute__ ((__always_inline__)) vcvtp_u32_f32 (float32x2_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint32x2_t) __builtin_aarch64_lceiluv2sfv2si (__a); + return __builtin_aarch64_lceiluv2sfv2si_us (__a); } __extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) @@ -13489,9 +13463,7 @@ vcvtpq_s32_f32 (float32x4_t __a) __extension__ static __inline uint32x4_t __attribute__ ((__always_inline__)) vcvtpq_u32_f32 (float32x4_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint32x4_t) __builtin_aarch64_lceiluv4sfv4si (__a); + return __builtin_aarch64_lceiluv4sfv4si_us (__a); } __extension__ static __inline int64x2_t __attribute__ ((__always_inline__)) @@ -13503,9 +13475,7 @@ vcvtpq_s64_f64 (float64x2_t __a) __extension__ static __inline uint64x2_t __attribute__ ((__always_inline__)) vcvtpq_u64_f64 (float64x2_t __a) { - /* TODO: This cast should go away when builtins have - their correct types. */ - return (uint64x2_t) __builtin_aarch64_lceiluv2dfv2di (__a); + return __builtin_aarch64_lceiluv2dfv2di_us (__a); } /* vdup_n */ diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index 68dc27add92..3b65b4b238f 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 processor synchronization primitives. -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -428,7 +428,7 @@ (match_dup 2) (match_operand:SI 3 "const_int_operand")] UNSPECV_ATOMIC_LDOP)) - (clobber (match_scratch:ALLI 4 "=r"))] + (clobber (match_scratch:ALLI 4 "=&r"))] "TARGET_LSE" "#" "&& reload_completed" diff --git a/gcc/config/aarch64/biarchilp32.h b/gcc/config/aarch64/biarchilp32.h index 2a9f6ed9b5b..41ce79109dc 100644 --- a/gcc/config/aarch64/biarchilp32.h +++ b/gcc/config/aarch64/biarchilp32.h @@ -1,7 +1,7 @@ /* Make configure files to produce biarch compiler defaulting to ilp32 ABI. This file must be included very first, while the OS specific file later to overwrite otherwise wrong defaults. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/biarchlp64.h b/gcc/config/aarch64/biarchlp64.h index d77f10789c3..2a155498645 100644 --- a/gcc/config/aarch64/biarchlp64.h +++ b/gcc/config/aarch64/biarchlp64.h @@ -1,7 +1,7 @@ /* Make configure files to produce biarch compiler defaulting to ilp64 ABI. This file must be included very first, while the OS specific file later to overwrite otherwise wrong defaults. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index 9dc21089154..d64a7ebe36f 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 architecture. -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -35,6 +35,11 @@ (and (match_code "const_int") (match_test "aarch64_uimm12_shift (ival)"))) +(define_constraint "Upl" + "@internal A constant that matches two uses of add instructions." + (and (match_code "const_int") + (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)"))) + (define_constraint "J" "A constant that can be used with a SUB operation (once negated)." (and (match_code "const_int") diff --git a/gcc/config/aarch64/cortex-a57-fma-steering.c b/gcc/config/aarch64/cortex-a57-fma-steering.c index eda35997641..5d2ec879504 100644 --- a/gcc/config/aarch64/cortex-a57-fma-steering.c +++ b/gcc/config/aarch64/cortex-a57-fma-steering.c @@ -1,5 +1,5 @@ /* FMA steering optimization pass for Cortex-A57. - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/cortex-a57-fma-steering.h b/gcc/config/aarch64/cortex-a57-fma-steering.h index e8915acb423..65bf5acc132 100644 --- a/gcc/config/aarch64/cortex-a57-fma-steering.h +++ b/gcc/config/aarch64/cortex-a57-fma-steering.h @@ -1,6 +1,6 @@ /* This file contains declarations for the FMA steering optimization pass for Cortex-A57. - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/aarch64/driver-aarch64.c b/gcc/config/aarch64/driver-aarch64.c index ae4d5a00ec5..317a8a9872e 100644 --- a/gcc/config/aarch64/driver-aarch64.c +++ b/gcc/config/aarch64/driver-aarch64.c @@ -1,5 +1,5 @@ /* Native CPU detection for aarch64. - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/aarch64/geniterators.sh b/gcc/config/aarch64/geniterators.sh index 5a51d29e6d3..ec1b1ea539a 100644 --- a/gcc/config/aarch64/geniterators.sh +++ b/gcc/config/aarch64/geniterators.sh @@ -1,6 +1,6 @@ #!/bin/sh # -# Copyright (C) 2014-2015 Free Software Foundation, Inc. +# Copyright (C) 2014-2016 Free Software Foundation, Inc. # Contributed by ARM Ltd. # # This file is part of GCC. diff --git a/gcc/config/aarch64/gentune.sh b/gcc/config/aarch64/gentune.sh index 880971cc10b..6f5bf66dedf 100644 --- a/gcc/config/aarch64/gentune.sh +++ b/gcc/config/aarch64/gentune.sh @@ -1,6 +1,6 @@ #!/bin/sh # -# Copyright (C) 2011-2015 Free Software Foundation, Inc. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. # Contributed by ARM Ltd. # # This file is part of GCC. diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 8bdd2648f89..49598a2cd93 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 architecture. -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -345,6 +345,8 @@ (define_mode_attr w1 [(SF "w") (DF "x")]) (define_mode_attr w2 [(SF "x") (DF "w")]) +(define_mode_attr short_mask [(HI "65535") (QI "255")]) + ;; For constraints used in scalar immediate vector moves (define_mode_attr hq [(HI "h") (QI "q")]) diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index c0c3ff5dc20..e96dc000bea 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -1,5 +1,5 @@ ;; Machine description for AArch64 architecture. -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -43,23 +43,6 @@ (ior (match_operand 0 "register_operand") (match_operand 0 "aarch64_ccmp_immediate"))) -(define_special_predicate "ccmp_cc_register" - (and (match_code "reg") - (and (match_test "REGNO (op) == CC_REGNUM") - (ior (match_test "mode == GET_MODE (op)") - (match_test "mode == VOIDmode - && (GET_MODE (op) == CC_DNEmode - || GET_MODE (op) == CC_DEQmode - || GET_MODE (op) == CC_DLEmode - || GET_MODE (op) == CC_DLTmode - || GET_MODE (op) == CC_DGEmode - || GET_MODE (op) == CC_DGTmode - || GET_MODE (op) == CC_DLEUmode - || GET_MODE (op) == CC_DLTUmode - || GET_MODE (op) == CC_DGEUmode - || GET_MODE (op) == CC_DGTUmode)")))) -) - (define_predicate "aarch64_simd_register" (and (match_code "reg") (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS") @@ -107,6 +90,10 @@ (and (match_code "const_int") (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)"))) +(define_predicate "aarch64_pluslong_strict_immedate" + (and (match_operand 0 "aarch64_pluslong_immediate") + (not (match_operand 0 "aarch64_plus_immediate")))) + (define_predicate "aarch64_pluslong_operand" (ior (match_operand 0 "register_operand") (match_operand 0 "aarch64_pluslong_immediate"))) diff --git a/gcc/config/aarch64/t-aarch64 b/gcc/config/aarch64/t-aarch64 index 782853b1427..dcbcac4064c 100644 --- a/gcc/config/aarch64/t-aarch64 +++ b/gcc/config/aarch64/t-aarch64 @@ -1,5 +1,5 @@ # Machine description for AArch64 architecture. -# Copyright (C) 2009-2015 Free Software Foundation, Inc. +# Copyright (C) 2009-2016 Free Software Foundation, Inc. # Contributed by ARM Ltd. # # This file is part of GCC. diff --git a/gcc/config/aarch64/t-aarch64-linux b/gcc/config/aarch64/t-aarch64-linux index c296376355a..1cfe9f3a76d 100644 --- a/gcc/config/aarch64/t-aarch64-linux +++ b/gcc/config/aarch64/t-aarch64-linux @@ -1,5 +1,5 @@ # Machine description for AArch64 architecture. -# Copyright (C) 2009-2015 Free Software Foundation, Inc. +# Copyright (C) 2009-2016 Free Software Foundation, Inc. # Contributed by ARM Ltd. # # This file is part of GCC. diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md index 3dae963fc91..922df390386 100644 --- a/gcc/config/aarch64/thunderx.md +++ b/gcc/config/aarch64/thunderx.md @@ -1,5 +1,5 @@ ;; Cavium ThunderX pipeline description -;; Copyright (C) 2014-2015 Free Software Foundation, Inc. +;; Copyright (C) 2014-2016 Free Software Foundation, Inc. ;; ;; Written by Andrew Pinski <apinski@cavium.com> diff --git a/gcc/config/alpha/alpha-modes.def b/gcc/config/alpha/alpha-modes.def index 5721aa41905..f5531a321c4 100644 --- a/gcc/config/alpha/alpha-modes.def +++ b/gcc/config/alpha/alpha-modes.def @@ -1,5 +1,5 @@ /* Alpha extra machine modes. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/alpha/alpha-protos.h b/gcc/config/alpha/alpha-protos.h index cec8329225b..da7232cfd47 100644 --- a/gcc/config/alpha/alpha-protos.h +++ b/gcc/config/alpha/alpha-protos.h @@ -1,5 +1,5 @@ /* Prototypes for alpha.c functions used in the md file & elsewhere. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 4cfae822905..e023d3bc278 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on the DEC Alpha. - Copyright (C) 1992-2015 Free Software Foundation, Inc. + Copyright (C) 1992-2016 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h index 5a198f79a2e..ba90a44d72f 100644 --- a/gcc/config/alpha/alpha.h +++ b/gcc/config/alpha/alpha.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for DEC Alpha. - Copyright (C) 1992-2015 Free Software Foundation, Inc. + Copyright (C) 1992-2016 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 5068f60ad6c..932608b0fe2 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -1,5 +1,5 @@ ;; Machine description for DEC Alpha for GNU C compiler -;; Copyright (C) 1992-2015 Free Software Foundation, Inc. +;; Copyright (C) 1992-2016 Free Software Foundation, Inc. ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) ;; ;; This file is part of GCC. diff --git a/gcc/config/alpha/alpha.opt b/gcc/config/alpha/alpha.opt index 08d71371079..3bd96ea3bac 100644 --- a/gcc/config/alpha/alpha.opt +++ b/gcc/config/alpha/alpha.opt @@ -1,6 +1,6 @@ ; Options for the DEC Alpha port of the compiler ; -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/alpha/constraints.md b/gcc/config/alpha/constraints.md index 6abba61acdc..1cc18c785cf 100644 --- a/gcc/config/alpha/constraints.md +++ b/gcc/config/alpha/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for DEC Alpha. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/alpha/driver-alpha.c b/gcc/config/alpha/driver-alpha.c index 7258cdc0df2..efef3f23253 100644 --- a/gcc/config/alpha/driver-alpha.c +++ b/gcc/config/alpha/driver-alpha.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by Arthur Loiret <aloiret@debian.org> This file is part of GCC. diff --git a/gcc/config/alpha/elf.h b/gcc/config/alpha/elf.h index 92bdfa3cfe9..093c38bba15 100644 --- a/gcc/config/alpha/elf.h +++ b/gcc/config/alpha/elf.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for DEC Alpha w/ELF. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Richard Henderson (rth@tamu.edu). This file is part of GCC. diff --git a/gcc/config/alpha/elf.opt b/gcc/config/alpha/elf.opt index fdad029f124..5624292b2d8 100644 --- a/gcc/config/alpha/elf.opt +++ b/gcc/config/alpha/elf.opt @@ -1,6 +1,6 @@ ; Alpha ELF options. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/alpha/ev4.md b/gcc/config/alpha/ev4.md index 326937f24d4..d3f19fe80fe 100644 --- a/gcc/config/alpha/ev4.md +++ b/gcc/config/alpha/ev4.md @@ -1,5 +1,5 @@ ;; Scheduling description for Alpha EV4. -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/alpha/ev5.md b/gcc/config/alpha/ev5.md index b4d472eafd6..cabb28c4f1b 100644 --- a/gcc/config/alpha/ev5.md +++ b/gcc/config/alpha/ev5.md @@ -1,5 +1,5 @@ ;; Scheduling description for Alpha EV5. -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/alpha/ev6.md b/gcc/config/alpha/ev6.md index 74852d5e4ef..6ebd94c86da 100644 --- a/gcc/config/alpha/ev6.md +++ b/gcc/config/alpha/ev6.md @@ -1,5 +1,5 @@ ;; Scheduling description for Alpha EV6. -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/alpha/freebsd.h b/gcc/config/alpha/freebsd.h index 1e0c3685bd5..08b0a7fea19 100644 --- a/gcc/config/alpha/freebsd.h +++ b/gcc/config/alpha/freebsd.h @@ -1,5 +1,5 @@ /* Definitions for DEC Alpha/AXP running FreeBSD using the ELF format - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by David E. O'Brien <obrien@FreeBSD.org> and BSDi. This file is part of GCC. diff --git a/gcc/config/alpha/linux-elf.h b/gcc/config/alpha/linux-elf.h index 2c70a2fbb9e..a0764d35ea3 100644 --- a/gcc/config/alpha/linux-elf.h +++ b/gcc/config/alpha/linux-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler for Alpha Linux-based GNU systems using ELF. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Richard Henderson. This file is part of GCC. diff --git a/gcc/config/alpha/linux.h b/gcc/config/alpha/linux.h index 475ea06a1fa..45a6a050510 100644 --- a/gcc/config/alpha/linux.h +++ b/gcc/config/alpha/linux.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for Alpha Linux-based GNU systems. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Richard Henderson. This file is part of GCC. diff --git a/gcc/config/alpha/netbsd.h b/gcc/config/alpha/netbsd.h index af2e99bea4c..9a7fe41a990 100644 --- a/gcc/config/alpha/netbsd.h +++ b/gcc/config/alpha/netbsd.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for Alpha NetBSD systems. - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/alpha/openbsd.h b/gcc/config/alpha/openbsd.h index 2ce0c98abd3..a2583923f3d 100644 --- a/gcc/config/alpha/openbsd.h +++ b/gcc/config/alpha/openbsd.h @@ -1,5 +1,5 @@ /* Configuration file for an alpha OpenBSD target. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/alpha/predicates.md b/gcc/config/alpha/predicates.md index e24b3bde37f..24fa3c2ae24 100644 --- a/gcc/config/alpha/predicates.md +++ b/gcc/config/alpha/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for DEC Alpha. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/alpha/sync.md b/gcc/config/alpha/sync.md index d5f33eb2c51..53032f55d03 100644 --- a/gcc/config/alpha/sync.md +++ b/gcc/config/alpha/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for Alpha synchronization instructions. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/alpha/t-vms b/gcc/config/alpha/t-vms index b8fd04cbfb3..6c96a8483a0 100644 --- a/gcc/config/alpha/t-vms +++ b/gcc/config/alpha/t-vms @@ -1,4 +1,4 @@ -# Copyright (C) 1996-2015 Free Software Foundation, Inc. +# Copyright (C) 1996-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/alpha/vms.h b/gcc/config/alpha/vms.h index 884b41fd00b..140130a5f04 100644 --- a/gcc/config/alpha/vms.h +++ b/gcc/config/alpha/vms.h @@ -1,5 +1,5 @@ /* Output variables, constants and external declarations, for GNU compiler. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arc/arc-modes.def b/gcc/config/arc/arc-modes.def index 2072c46f946..b64a596082e 100644 --- a/gcc/config/arc/arc-modes.def +++ b/gcc/config/arc/arc-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributor: Joern Rennecke <joern.rennecke@embecosm.com> on behalf of Synopsys Inc. diff --git a/gcc/config/arc/arc-opts.h b/gcc/config/arc/arc-opts.h index a33f4b77521..0f128850431 100644 --- a/gcc/config/arc/arc-opts.h +++ b/gcc/config/arc/arc-opts.h @@ -1,6 +1,6 @@ /* GCC option-handling definitions for the Synopsys DesignWare ARC architecture. - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h index 3581bb0ed27..3f96455a16a 100644 --- a/gcc/config/arc/arc-protos.h +++ b/gcc/config/arc/arc-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arc/arc-simd.h b/gcc/config/arc/arc-simd.h index f6e65a8a9ae..fe017b1c2c9 100644 --- a/gcc/config/arc/arc-simd.h +++ b/gcc/config/arc/arc-simd.h @@ -1,5 +1,5 @@ /* Synopsys DesignWare ARC SIMD include file. - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. Written by Saurabh Verma (saurabh.verma@celunite.com) on behalf os Synopsys Inc. diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 513d138780d..f636534c48a 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on the Synopsys DesignWare ARC cpu. - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. Sources derived from work done by Sankhya Technologies (www.sankhya.com) on behalf of Synopsys Inc. @@ -175,164 +175,6 @@ struct GTY (()) arc_ccfsm this to be no less than the 1/p */ #define MAX_INSNS_SKIPPED 3 -/* The values of unspec's first field. */ -enum { - ARC_UNSPEC_PLT = 3, - ARC_UNSPEC_GOT, - ARC_UNSPEC_GOTOFF -} ; - - -enum arc_builtins { - ARC_BUILTIN_NOP = 2, - ARC_BUILTIN_NORM = 3, - ARC_BUILTIN_NORMW = 4, - ARC_BUILTIN_SWAP = 5, - ARC_BUILTIN_BRK = 6, - ARC_BUILTIN_DIVAW = 7, - ARC_BUILTIN_EX = 8, - ARC_BUILTIN_MUL64 = 9, - ARC_BUILTIN_MULU64 = 10, - ARC_BUILTIN_RTIE = 11, - ARC_BUILTIN_SYNC = 12, - ARC_BUILTIN_CORE_READ = 13, - ARC_BUILTIN_CORE_WRITE = 14, - ARC_BUILTIN_FLAG = 15, - ARC_BUILTIN_LR = 16, - ARC_BUILTIN_SR = 17, - ARC_BUILTIN_SLEEP = 18, - ARC_BUILTIN_SWI = 19, - ARC_BUILTIN_TRAP_S = 20, - ARC_BUILTIN_UNIMP_S = 21, - ARC_BUILTIN_ALIGNED = 22, - - /* Sentinel to mark start of simd builtins. */ - ARC_SIMD_BUILTIN_BEGIN = 1000, - - ARC_SIMD_BUILTIN_VADDAW = 1001, - ARC_SIMD_BUILTIN_VADDW = 1002, - ARC_SIMD_BUILTIN_VAVB = 1003, - ARC_SIMD_BUILTIN_VAVRB = 1004, - ARC_SIMD_BUILTIN_VDIFAW = 1005, - ARC_SIMD_BUILTIN_VDIFW = 1006, - ARC_SIMD_BUILTIN_VMAXAW = 1007, - ARC_SIMD_BUILTIN_VMAXW = 1008, - ARC_SIMD_BUILTIN_VMINAW = 1009, - ARC_SIMD_BUILTIN_VMINW = 1010, - ARC_SIMD_BUILTIN_VMULAW = 1011, - ARC_SIMD_BUILTIN_VMULFAW = 1012, - ARC_SIMD_BUILTIN_VMULFW = 1013, - ARC_SIMD_BUILTIN_VMULW = 1014, - ARC_SIMD_BUILTIN_VSUBAW = 1015, - ARC_SIMD_BUILTIN_VSUBW = 1016, - ARC_SIMD_BUILTIN_VSUMMW = 1017, - ARC_SIMD_BUILTIN_VAND = 1018, - ARC_SIMD_BUILTIN_VANDAW = 1019, - ARC_SIMD_BUILTIN_VBIC = 1020, - ARC_SIMD_BUILTIN_VBICAW = 1021, - ARC_SIMD_BUILTIN_VOR = 1022, - ARC_SIMD_BUILTIN_VXOR = 1023, - ARC_SIMD_BUILTIN_VXORAW = 1024, - ARC_SIMD_BUILTIN_VEQW = 1025, - ARC_SIMD_BUILTIN_VLEW = 1026, - ARC_SIMD_BUILTIN_VLTW = 1027, - ARC_SIMD_BUILTIN_VNEW = 1028, - ARC_SIMD_BUILTIN_VMR1AW = 1029, - ARC_SIMD_BUILTIN_VMR1W = 1030, - ARC_SIMD_BUILTIN_VMR2AW = 1031, - ARC_SIMD_BUILTIN_VMR2W = 1032, - ARC_SIMD_BUILTIN_VMR3AW = 1033, - ARC_SIMD_BUILTIN_VMR3W = 1034, - ARC_SIMD_BUILTIN_VMR4AW = 1035, - ARC_SIMD_BUILTIN_VMR4W = 1036, - ARC_SIMD_BUILTIN_VMR5AW = 1037, - ARC_SIMD_BUILTIN_VMR5W = 1038, - ARC_SIMD_BUILTIN_VMR6AW = 1039, - ARC_SIMD_BUILTIN_VMR6W = 1040, - ARC_SIMD_BUILTIN_VMR7AW = 1041, - ARC_SIMD_BUILTIN_VMR7W = 1042, - ARC_SIMD_BUILTIN_VMRB = 1043, - ARC_SIMD_BUILTIN_VH264F = 1044, - ARC_SIMD_BUILTIN_VH264FT = 1045, - ARC_SIMD_BUILTIN_VH264FW = 1046, - ARC_SIMD_BUILTIN_VVC1F = 1047, - ARC_SIMD_BUILTIN_VVC1FT = 1048, - - /* Va, Vb, rlimm instructions. */ - ARC_SIMD_BUILTIN_VBADDW = 1050, - ARC_SIMD_BUILTIN_VBMAXW = 1051, - ARC_SIMD_BUILTIN_VBMINW = 1052, - ARC_SIMD_BUILTIN_VBMULAW = 1053, - ARC_SIMD_BUILTIN_VBMULFW = 1054, - ARC_SIMD_BUILTIN_VBMULW = 1055, - ARC_SIMD_BUILTIN_VBRSUBW = 1056, - ARC_SIMD_BUILTIN_VBSUBW = 1057, - - /* Va, Vb, Ic instructions. */ - ARC_SIMD_BUILTIN_VASRW = 1060, - ARC_SIMD_BUILTIN_VSR8 = 1061, - ARC_SIMD_BUILTIN_VSR8AW = 1062, - - /* Va, Vb, u6 instructions. */ - ARC_SIMD_BUILTIN_VASRRWi = 1065, - ARC_SIMD_BUILTIN_VASRSRWi = 1066, - ARC_SIMD_BUILTIN_VASRWi = 1067, - ARC_SIMD_BUILTIN_VASRPWBi = 1068, - ARC_SIMD_BUILTIN_VASRRPWBi = 1069, - ARC_SIMD_BUILTIN_VSR8AWi = 1070, - ARC_SIMD_BUILTIN_VSR8i = 1071, - - /* Va, Vb, u8 (simm) instructions. */ - ARC_SIMD_BUILTIN_VMVAW = 1075, - ARC_SIMD_BUILTIN_VMVW = 1076, - ARC_SIMD_BUILTIN_VMVZW = 1077, - ARC_SIMD_BUILTIN_VD6TAPF = 1078, - - /* Va, rlimm, u8 (simm) instructions. */ - ARC_SIMD_BUILTIN_VMOVAW = 1080, - ARC_SIMD_BUILTIN_VMOVW = 1081, - ARC_SIMD_BUILTIN_VMOVZW = 1082, - - /* Va, Vb instructions. */ - ARC_SIMD_BUILTIN_VABSAW = 1085, - ARC_SIMD_BUILTIN_VABSW = 1086, - ARC_SIMD_BUILTIN_VADDSUW = 1087, - ARC_SIMD_BUILTIN_VSIGNW = 1088, - ARC_SIMD_BUILTIN_VEXCH1 = 1089, - ARC_SIMD_BUILTIN_VEXCH2 = 1090, - ARC_SIMD_BUILTIN_VEXCH4 = 1091, - ARC_SIMD_BUILTIN_VUPBAW = 1092, - ARC_SIMD_BUILTIN_VUPBW = 1093, - ARC_SIMD_BUILTIN_VUPSBAW = 1094, - ARC_SIMD_BUILTIN_VUPSBW = 1095, - - ARC_SIMD_BUILTIN_VDIRUN = 1100, - ARC_SIMD_BUILTIN_VDORUN = 1101, - ARC_SIMD_BUILTIN_VDIWR = 1102, - ARC_SIMD_BUILTIN_VDOWR = 1103, - - ARC_SIMD_BUILTIN_VREC = 1105, - ARC_SIMD_BUILTIN_VRUN = 1106, - ARC_SIMD_BUILTIN_VRECRUN = 1107, - ARC_SIMD_BUILTIN_VENDREC = 1108, - - ARC_SIMD_BUILTIN_VLD32WH = 1110, - ARC_SIMD_BUILTIN_VLD32WL = 1111, - ARC_SIMD_BUILTIN_VLD64 = 1112, - ARC_SIMD_BUILTIN_VLD32 = 1113, - ARC_SIMD_BUILTIN_VLD64W = 1114, - ARC_SIMD_BUILTIN_VLD128 = 1115, - ARC_SIMD_BUILTIN_VST128 = 1116, - ARC_SIMD_BUILTIN_VST64 = 1117, - - ARC_SIMD_BUILTIN_VST16_N = 1120, - ARC_SIMD_BUILTIN_VST32_N = 1121, - - ARC_SIMD_BUILTIN_VINTI = 1201, - - ARC_SIMD_BUILTIN_END -}; - /* A nop is needed between a 4 byte insn that sets the condition codes and a branch that uses them (the same isn't true for an 8 byte insn that sets the condition codes). Set by arc_ccfsm_advance. Used by @@ -385,7 +227,6 @@ static bool arc_in_small_data_p (const_tree); static void arc_init_reg_tables (void); static bool arc_return_in_memory (const_tree, const_tree); -static void arc_init_simd_builtins (void); static bool arc_vector_mode_supported_p (machine_mode); static bool arc_can_use_doloop_p (const widest_int &, const widest_int &, @@ -456,6 +297,9 @@ static void arc_finalize_pic (void); #undef TARGET_EXPAND_BUILTIN #define TARGET_EXPAND_BUILTIN arc_expand_builtin +#undef TARGET_BUILTIN_DECL +#define TARGET_BUILTIN_DECL arc_builtin_decl + #undef TARGET_ASM_OUTPUT_MI_THUNK #define TARGET_ASM_OUTPUT_MI_THUNK arc_output_mi_thunk @@ -5241,91 +5085,225 @@ arc_cannot_force_const_mem (machine_mode mode, rtx x) return !arc_legitimate_constant_p (mode, x); } +/* IDs for all the ARC builtins. */ + +enum arc_builtin_id + { +#define DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, MASK) \ + ARC_BUILTIN_ ## NAME, +#include "builtins.def" +#undef DEF_BUILTIN + + ARC_BUILTIN_COUNT + }; + +struct GTY(()) arc_builtin_description +{ + enum insn_code icode; + int n_args; + tree fndecl; +}; + +static GTY(()) struct arc_builtin_description +arc_bdesc[ARC_BUILTIN_COUNT] = +{ +#define DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, MASK) \ + { (enum insn_code) CODE_FOR_ ## ICODE, N_ARGS, NULL_TREE }, +#include "builtins.def" +#undef DEF_BUILTIN +}; + +/* Transform UP into lowercase and write the result to LO. + You must provide enough space for LO. Return LO. */ + +static char* +arc_tolower (char *lo, const char *up) +{ + char *lo0 = lo; + + for (; *up; up++, lo++) + *lo = TOLOWER (*up); + + *lo = '\0'; + + return lo0; +} + +/* Implement `TARGET_BUILTIN_DECL'. */ -/* Generic function to define a builtin. */ -#define def_mbuiltin(MASK, NAME, TYPE, CODE) \ - do \ - { \ - if (MASK) \ - add_builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \ - } \ - while (0) +static tree +arc_builtin_decl (unsigned id, bool initialize_p ATTRIBUTE_UNUSED) +{ + if (id < ARC_BUILTIN_COUNT) + return arc_bdesc[id].fndecl; + return error_mark_node; +} static void arc_init_builtins (void) { - tree endlink = void_list_node; - - tree void_ftype_void - = build_function_type (void_type_node, - endlink); - - tree int_ftype_int - = build_function_type (integer_type_node, - tree_cons (NULL_TREE, integer_type_node, endlink)); - - tree pcvoid_type_node - = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); - tree int_ftype_pcvoid_int - = build_function_type (integer_type_node, - tree_cons (NULL_TREE, pcvoid_type_node, - tree_cons (NULL_TREE, integer_type_node, - endlink))); - - tree int_ftype_short_int - = build_function_type (integer_type_node, - tree_cons (NULL_TREE, short_integer_type_node, endlink)); - - tree void_ftype_int_int - = build_function_type (void_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, integer_type_node, endlink))); - tree void_ftype_usint_usint - = build_function_type (void_type_node, - tree_cons (NULL_TREE, long_unsigned_type_node, - tree_cons (NULL_TREE, long_unsigned_type_node, endlink))); - - tree int_ftype_int_int - = build_function_type (integer_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, integer_type_node, endlink))); - - tree usint_ftype_usint - = build_function_type (long_unsigned_type_node, - tree_cons (NULL_TREE, long_unsigned_type_node, endlink)); - - tree void_ftype_usint - = build_function_type (void_type_node, - tree_cons (NULL_TREE, long_unsigned_type_node, endlink)); - - /* Add the builtins. */ - def_mbuiltin (1,"__builtin_arc_nop", void_ftype_void, ARC_BUILTIN_NOP); - def_mbuiltin (TARGET_NORM, "__builtin_arc_norm", int_ftype_int, ARC_BUILTIN_NORM); - def_mbuiltin (TARGET_NORM, "__builtin_arc_normw", int_ftype_short_int, ARC_BUILTIN_NORMW); - def_mbuiltin (TARGET_SWAP, "__builtin_arc_swap", int_ftype_int, ARC_BUILTIN_SWAP); - def_mbuiltin (TARGET_MUL64_SET,"__builtin_arc_mul64", void_ftype_int_int, ARC_BUILTIN_MUL64); - def_mbuiltin (TARGET_MUL64_SET,"__builtin_arc_mulu64", void_ftype_usint_usint, ARC_BUILTIN_MULU64); - def_mbuiltin (1,"__builtin_arc_rtie", void_ftype_void, ARC_BUILTIN_RTIE); - def_mbuiltin (TARGET_ARC700,"__builtin_arc_sync", void_ftype_void, ARC_BUILTIN_SYNC); - def_mbuiltin ((TARGET_EA_SET),"__builtin_arc_divaw", int_ftype_int_int, ARC_BUILTIN_DIVAW); - def_mbuiltin (1,"__builtin_arc_brk", void_ftype_void, ARC_BUILTIN_BRK); - def_mbuiltin (1,"__builtin_arc_flag", void_ftype_usint, ARC_BUILTIN_FLAG); - def_mbuiltin (1,"__builtin_arc_sleep", void_ftype_usint, ARC_BUILTIN_SLEEP); - def_mbuiltin (1,"__builtin_arc_swi", void_ftype_void, ARC_BUILTIN_SWI); - def_mbuiltin (1,"__builtin_arc_core_read", usint_ftype_usint, ARC_BUILTIN_CORE_READ); - def_mbuiltin (1,"__builtin_arc_core_write", void_ftype_usint_usint, ARC_BUILTIN_CORE_WRITE); - def_mbuiltin (1,"__builtin_arc_lr", usint_ftype_usint, ARC_BUILTIN_LR); - def_mbuiltin (1,"__builtin_arc_sr", void_ftype_usint_usint, ARC_BUILTIN_SR); - def_mbuiltin (TARGET_ARC700,"__builtin_arc_trap_s", void_ftype_usint, ARC_BUILTIN_TRAP_S); - def_mbuiltin (TARGET_ARC700,"__builtin_arc_unimp_s", void_ftype_void, ARC_BUILTIN_UNIMP_S); - def_mbuiltin (1,"__builtin_arc_aligned", int_ftype_pcvoid_int, ARC_BUILTIN_ALIGNED); - - if (TARGET_SIMD_SET) - arc_init_simd_builtins (); -} - -static rtx arc_expand_simd_builtin (tree, rtx, rtx, machine_mode, int); + tree pcvoid_type_node + = build_pointer_type (build_qualified_type (void_type_node, + TYPE_QUAL_CONST)); + tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, + V8HImode); + + tree void_ftype_void + = build_function_type_list (void_type_node, NULL_TREE); + tree int_ftype_int + = build_function_type_list (integer_type_node, integer_type_node, + NULL_TREE); + tree int_ftype_pcvoid_int + = build_function_type_list (integer_type_node, pcvoid_type_node, + integer_type_node, NULL_TREE); + tree void_ftype_usint_usint + = build_function_type_list (void_type_node, long_unsigned_type_node, + long_unsigned_type_node, NULL_TREE); + tree int_ftype_int_int + = build_function_type_list (integer_type_node, integer_type_node, + integer_type_node, NULL_TREE); + tree usint_ftype_usint + = build_function_type_list (long_unsigned_type_node, + long_unsigned_type_node, NULL_TREE); + tree void_ftype_usint + = build_function_type_list (void_type_node, long_unsigned_type_node, + NULL_TREE); + tree int_ftype_void + = build_function_type_list (integer_type_node, void_type_node, + NULL_TREE); + tree void_ftype_int + = build_function_type_list (void_type_node, integer_type_node, + NULL_TREE); + tree int_ftype_short + = build_function_type_list (integer_type_node, short_integer_type_node, + NULL_TREE); + + /* Old ARC SIMD types. */ + tree v8hi_ftype_v8hi_v8hi + = build_function_type_list (V8HI_type_node, V8HI_type_node, + V8HI_type_node, NULL_TREE); + tree v8hi_ftype_v8hi_int + = build_function_type_list (V8HI_type_node, V8HI_type_node, + integer_type_node, NULL_TREE); + tree v8hi_ftype_v8hi_int_int + = build_function_type_list (V8HI_type_node, V8HI_type_node, + integer_type_node, integer_type_node, + NULL_TREE); + tree void_ftype_v8hi_int_int + = build_function_type_list (void_type_node, V8HI_type_node, + integer_type_node, integer_type_node, + NULL_TREE); + tree void_ftype_v8hi_int_int_int + = build_function_type_list (void_type_node, V8HI_type_node, + integer_type_node, integer_type_node, + integer_type_node, NULL_TREE); + tree v8hi_ftype_int_int + = build_function_type_list (V8HI_type_node, integer_type_node, + integer_type_node, NULL_TREE); + tree void_ftype_int_int + = build_function_type_list (void_type_node, integer_type_node, + integer_type_node, NULL_TREE); + tree v8hi_ftype_v8hi + = build_function_type_list (V8HI_type_node, V8HI_type_node, + NULL_TREE); + + /* Add the builtins. */ +#define DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, MASK) \ + { \ + int id = ARC_BUILTIN_ ## NAME; \ + const char *Name = "__builtin_arc_" #NAME; \ + char *name = (char*) alloca (1 + strlen (Name)); \ + \ + gcc_assert (id < ARC_BUILTIN_COUNT); \ + if (MASK) \ + arc_bdesc[id].fndecl \ + = add_builtin_function (arc_tolower(name, Name), TYPE, id, \ + BUILT_IN_MD, NULL, NULL_TREE); \ + } +#include "builtins.def" +#undef DEF_BUILTIN +} + +/* Helper to expand __builtin_arc_aligned (void* val, int + alignval). */ + +static rtx +arc_expand_builtin_aligned (tree exp) +{ + tree arg0 = CALL_EXPR_ARG (exp, 0); + tree arg1 = CALL_EXPR_ARG (exp, 1); + fold (arg1); + rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); + rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL); + + if (!CONST_INT_P (op1)) + { + /* If we can't fold the alignment to a constant integer + whilst optimizing, this is probably a user error. */ + if (optimize) + warning (0, "__builtin_arc_aligned with non-constant alignment"); + } + else + { + HOST_WIDE_INT alignTest = INTVAL (op1); + /* Check alignTest is positive, and a power of two. */ + if (alignTest <= 0 || alignTest != (alignTest & -alignTest)) + { + error ("invalid alignment value for __builtin_arc_aligned"); + return NULL_RTX; + } + + if (CONST_INT_P (op0)) + { + HOST_WIDE_INT pnt = INTVAL (op0); + + if ((pnt & (alignTest - 1)) == 0) + return const1_rtx; + } + else + { + unsigned align = get_pointer_alignment (arg0); + unsigned numBits = alignTest * BITS_PER_UNIT; + + if (align && align >= numBits) + return const1_rtx; + /* Another attempt to ascertain alignment. Check the type + we are pointing to. */ + if (POINTER_TYPE_P (TREE_TYPE (arg0)) + && TYPE_ALIGN (TREE_TYPE (TREE_TYPE (arg0))) >= numBits) + return const1_rtx; + } + } + + /* Default to false. */ + return const0_rtx; +} + +/* Helper arc_expand_builtin, generates a pattern for the given icode + and arguments. */ + +static rtx_insn * +apply_GEN_FCN (enum insn_code icode, rtx *arg) +{ + switch (insn_data[icode].n_generator_args) + { + case 0: + return GEN_FCN (icode) (); + case 1: + return GEN_FCN (icode) (arg[0]); + case 2: + return GEN_FCN (icode) (arg[0], arg[1]); + case 3: + return GEN_FCN (icode) (arg[0], arg[1], arg[2]); + case 4: + return GEN_FCN (icode) (arg[0], arg[1], arg[2], arg[3]); + case 5: + return GEN_FCN (icode) (arg[0], arg[1], arg[2], arg[3], arg[4]); + default: + gcc_unreachable (); + } +} /* Expand an expression EXP that calls a built-in function, with result going to TARGET if that's convenient @@ -5336,314 +5314,396 @@ static rtx arc_expand_simd_builtin (tree, rtx, rtx, machine_mode, int); static rtx arc_expand_builtin (tree exp, rtx target, - rtx subtarget, - machine_mode mode, - int ignore) -{ - tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - tree arg0; - tree arg1; - rtx op0; - rtx op1; - int fcode = DECL_FUNCTION_CODE (fndecl); - int icode; + rtx subtarget ATTRIBUTE_UNUSED, + machine_mode mode ATTRIBUTE_UNUSED, + int ignore ATTRIBUTE_UNUSED) +{ + tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); + unsigned int id = DECL_FUNCTION_CODE (fndecl); + const struct arc_builtin_description *d = &arc_bdesc[id]; + int i, j, n_args = call_expr_nargs (exp); + rtx pat = NULL_RTX; + rtx xop[5]; + enum insn_code icode = d->icode; + machine_mode tmode = insn_data[icode].operand[0].mode; + int nonvoid; + tree arg0; + tree arg1; + tree arg2; + tree arg3; + rtx op0; + rtx op1; + rtx op2; + rtx op3; + rtx op4; machine_mode mode0; machine_mode mode1; + machine_mode mode2; + machine_mode mode3; + machine_mode mode4; - if (fcode > ARC_SIMD_BUILTIN_BEGIN && fcode < ARC_SIMD_BUILTIN_END) - return arc_expand_simd_builtin (exp, target, subtarget, mode, ignore); + if (id >= ARC_BUILTIN_COUNT) + internal_error ("bad builtin fcode"); - switch (fcode) + /* 1st part: Expand special builtins. */ + switch (id) { case ARC_BUILTIN_NOP: - emit_insn (gen_nop ()); + emit_insn (gen_nopv ()); return NULL_RTX; - case ARC_BUILTIN_NORM: - icode = CODE_FOR_clrsbsi2; - arg0 = CALL_EXPR_ARG (exp, 0); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); - mode0 = insn_data[icode].operand[1].mode; - target = gen_reg_rtx (SImode); + case ARC_BUILTIN_RTIE: + case ARC_BUILTIN_SYNC: + case ARC_BUILTIN_BRK: + case ARC_BUILTIN_SWI: + case ARC_BUILTIN_UNIMP_S: + gcc_assert (icode != 0); + emit_insn (GEN_FCN (icode) (const1_rtx)); + return NULL_RTX; - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); + case ARC_BUILTIN_ALIGNED: + return arc_expand_builtin_aligned (exp); - emit_insn (gen_clrsbsi2 (target, op0)); + case ARC_BUILTIN_CLRI: + target = gen_reg_rtx (SImode); + emit_insn (gen_clri (target, const1_rtx)); return target; - case ARC_BUILTIN_NORMW: - - /* FIXME : This should all be HImode, not SImode. */ - icode = CODE_FOR_normw; + case ARC_BUILTIN_TRAP_S: + case ARC_BUILTIN_SLEEP: arg0 = CALL_EXPR_ARG (exp, 0); + fold (arg0); op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); - mode0 = insn_data[icode].operand[1].mode; - target = gen_reg_rtx (SImode); - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, convert_to_mode (mode0, op0,0)); - emit_insn (gen_normw (target, op0)); - return target; + if (!CONST_INT_P (op0) || !satisfies_constraint_L (op0)) + { + error ("builtin operand should be an unsigned 6-bit value"); + return NULL_RTX; + } + gcc_assert (icode != 0); + emit_insn (GEN_FCN (icode) (op0)); + return NULL_RTX; - case ARC_BUILTIN_MUL64: - icode = CODE_FOR_mul64; + case ARC_BUILTIN_VDORUN: + case ARC_BUILTIN_VDIRUN: arg0 = CALL_EXPR_ARG (exp, 0); arg1 = CALL_EXPR_ARG (exp, 1); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL); + op0 = expand_expr (arg0, NULL_RTX, SImode, EXPAND_NORMAL); + op1 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); - mode0 = insn_data[icode].operand[0].mode; - mode1 = insn_data[icode].operand[1].mode; + target = gen_rtx_REG (SImode, (id == ARC_BUILTIN_VDIRUN) ? 131 : 139); - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) + mode0 = insn_data[icode].operand[1].mode; + mode1 = insn_data[icode].operand[2].mode; + + if (!insn_data[icode].operand[1].predicate (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) + if (!insn_data[icode].operand[2].predicate (op1, mode1)) op1 = copy_to_mode_reg (mode1, op1); - emit_insn (gen_mul64 (op0,op1)); + pat = GEN_FCN (icode) (target, op0, op1); + if (!pat) + return NULL_RTX; + + emit_insn (pat); return NULL_RTX; - case ARC_BUILTIN_MULU64: - icode = CODE_FOR_mulu64; + case ARC_BUILTIN_VDIWR: + case ARC_BUILTIN_VDOWR: arg0 = CALL_EXPR_ARG (exp, 0); arg1 = CALL_EXPR_ARG (exp, 1); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL); + op0 = expand_expr (arg0, NULL_RTX, SImode, EXPAND_NORMAL); + op1 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); + + if (!CONST_INT_P (op0) + || !(UNSIGNED_INT3 (INTVAL (op0)))) + error ("operand 1 should be an unsigned 3-bit immediate"); - mode0 = insn_data[icode].operand[0].mode; mode1 = insn_data[icode].operand[1].mode; - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); + if (icode == CODE_FOR_vdiwr_insn) + target = gen_rtx_REG (SImode, + ARC_FIRST_SIMD_DMA_CONFIG_IN_REG + INTVAL (op0)); + else if (icode == CODE_FOR_vdowr_insn) + target = gen_rtx_REG (SImode, + ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG + INTVAL (op0)); + else + gcc_unreachable (); - if (! (*insn_data[icode].operand[0].predicate) (op1, mode1)) + if (!insn_data[icode].operand[2].predicate (op1, mode1)) op1 = copy_to_mode_reg (mode1, op1); - emit_insn (gen_mulu64 (op0,op1)); - return NULL_RTX; - - case ARC_BUILTIN_RTIE: - icode = CODE_FOR_rtie; - emit_insn (gen_rtie (const1_rtx)); - return NULL_RTX; + pat = GEN_FCN (icode) (target, op1); + if (!pat) + return NULL_RTX; - case ARC_BUILTIN_SYNC: - icode = CODE_FOR_sync; - emit_insn (gen_sync (const1_rtx)); + emit_insn (pat); return NULL_RTX; - case ARC_BUILTIN_SWAP: - icode = CODE_FOR_swap; + case ARC_BUILTIN_VASRW: + case ARC_BUILTIN_VSR8: + case ARC_BUILTIN_VSR8AW: arg0 = CALL_EXPR_ARG (exp, 0); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); + arg1 = CALL_EXPR_ARG (exp, 1); + op0 = expand_expr (arg0, NULL_RTX, V8HImode, EXPAND_NORMAL); + op1 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); + op2 = gen_rtx_REG (V8HImode, ARC_FIRST_SIMD_VR_REG); + + target = gen_reg_rtx (V8HImode); mode0 = insn_data[icode].operand[1].mode; - target = gen_reg_rtx (SImode); + mode1 = insn_data[icode].operand[2].mode; - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) + if (!insn_data[icode].operand[1].predicate (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); - emit_insn (gen_swap (target, op0)); - return target; + if ((!insn_data[icode].operand[2].predicate (op1, mode1)) + || !(UNSIGNED_INT3 (INTVAL (op1)))) + error ("operand 2 should be an unsigned 3-bit value (I0-I7)"); - case ARC_BUILTIN_DIVAW: - icode = CODE_FOR_divaw; - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); + pat = GEN_FCN (icode) (target, op0, op1, op2); + if (!pat) + return NULL_RTX; - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL); - target = gen_reg_rtx (SImode); + emit_insn (pat); + return target; - mode0 = insn_data[icode].operand[0].mode; - mode1 = insn_data[icode].operand[1].mode; + case ARC_BUILTIN_VLD32WH: + case ARC_BUILTIN_VLD32WL: + case ARC_BUILTIN_VLD64: + case ARC_BUILTIN_VLD32: + rtx src_vreg; + icode = d->icode; + arg0 = CALL_EXPR_ARG (exp, 0); /* source vreg. */ + arg1 = CALL_EXPR_ARG (exp, 1); /* [I]0-7. */ + arg2 = CALL_EXPR_ARG (exp, 2); /* u8. */ - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); + src_vreg = expand_expr (arg0, NULL_RTX, V8HImode, EXPAND_NORMAL); + op0 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); + op1 = expand_expr (arg2, NULL_RTX, SImode, EXPAND_NORMAL); + op2 = gen_rtx_REG (V8HImode, ARC_FIRST_SIMD_VR_REG); - if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); + /* target <- src vreg. */ + emit_insn (gen_move_insn (target, src_vreg)); - emit_insn (gen_divaw (target, op0, op1)); - return target; + /* target <- vec_concat: target, mem (Ib, u8). */ + mode0 = insn_data[icode].operand[3].mode; + mode1 = insn_data[icode].operand[1].mode; - case ARC_BUILTIN_BRK: - icode = CODE_FOR_brk; - emit_insn (gen_brk (const1_rtx)); - return NULL_RTX; + if ((!insn_data[icode].operand[3].predicate (op0, mode0)) + || !(UNSIGNED_INT3 (INTVAL (op0)))) + error ("operand 1 should be an unsigned 3-bit value (I0-I7)"); - case ARC_BUILTIN_SLEEP: - icode = CODE_FOR_sleep; - arg0 = CALL_EXPR_ARG (exp, 0); + if ((!insn_data[icode].operand[1].predicate (op1, mode1)) + || !(UNSIGNED_INT8 (INTVAL (op1)))) + error ("operand 2 should be an unsigned 8-bit value"); - fold (arg0); + pat = GEN_FCN (icode) (target, op1, op2, op0); + if (!pat) + return NULL_RTX; - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); - mode0 = insn_data[icode].operand[1].mode; + emit_insn (pat); + return target; - emit_insn (gen_sleep (op0)); - return NULL_RTX; + case ARC_BUILTIN_VLD64W: + case ARC_BUILTIN_VLD128: + arg0 = CALL_EXPR_ARG (exp, 0); /* dest vreg. */ + arg1 = CALL_EXPR_ARG (exp, 1); /* [I]0-7. */ - case ARC_BUILTIN_SWI: - icode = CODE_FOR_swi; - emit_insn (gen_swi (const1_rtx)); - return NULL_RTX; + op0 = gen_rtx_REG (V8HImode, ARC_FIRST_SIMD_VR_REG); + op1 = expand_expr (arg0, NULL_RTX, SImode, EXPAND_NORMAL); + op2 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); - case ARC_BUILTIN_FLAG: - icode = CODE_FOR_flag; - arg0 = CALL_EXPR_ARG (exp, 0); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); - mode0 = insn_data[icode].operand[0].mode; + /* target <- src vreg. */ + target = gen_reg_rtx (V8HImode); - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); + /* target <- vec_concat: target, mem (Ib, u8). */ + mode0 = insn_data[icode].operand[1].mode; + mode1 = insn_data[icode].operand[2].mode; + mode2 = insn_data[icode].operand[3].mode; - emit_insn (gen_flag (op0)); - return NULL_RTX; + if ((!insn_data[icode].operand[2].predicate (op1, mode1)) + || !(UNSIGNED_INT3 (INTVAL (op1)))) + error ("operand 1 should be an unsigned 3-bit value (I0-I7)"); - case ARC_BUILTIN_CORE_READ: - icode = CODE_FOR_core_read; - arg0 = CALL_EXPR_ARG (exp, 0); - target = gen_reg_rtx (SImode); + if ((!insn_data[icode].operand[3].predicate (op2, mode2)) + || !(UNSIGNED_INT8 (INTVAL (op2)))) + error ("operand 2 should be an unsigned 8-bit value"); - fold (arg0); + pat = GEN_FCN (icode) (target, op0, op1, op2); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); - mode0 = insn_data[icode].operand[1].mode; + if (!pat) + return NULL_RTX; - emit_insn (gen_core_read (target, op0)); + emit_insn (pat); return target; - case ARC_BUILTIN_CORE_WRITE: - icode = CODE_FOR_core_write; - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - - fold (arg1); + case ARC_BUILTIN_VST128: + case ARC_BUILTIN_VST64: + arg0 = CALL_EXPR_ARG (exp, 0); /* src vreg. */ + arg1 = CALL_EXPR_ARG (exp, 1); /* [I]0-7. */ + arg2 = CALL_EXPR_ARG (exp, 2); /* u8. */ - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL); + op0 = gen_rtx_REG (V8HImode, ARC_FIRST_SIMD_VR_REG); + op1 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); + op2 = expand_expr (arg2, NULL_RTX, SImode, EXPAND_NORMAL); + op3 = expand_expr (arg0, NULL_RTX, V8HImode, EXPAND_NORMAL); mode0 = insn_data[icode].operand[0].mode; mode1 = insn_data[icode].operand[1].mode; + mode2 = insn_data[icode].operand[2].mode; + mode3 = insn_data[icode].operand[3].mode; - emit_insn (gen_core_write (op0, op1)); - return NULL_RTX; - - case ARC_BUILTIN_LR: - icode = CODE_FOR_lr; - arg0 = CALL_EXPR_ARG (exp, 0); - target = gen_reg_rtx (SImode); + if ((!insn_data[icode].operand[1].predicate (op1, mode1)) + || !(UNSIGNED_INT3 (INTVAL (op1)))) + error ("operand 2 should be an unsigned 3-bit value (I0-I7)"); - fold (arg0); + if ((!insn_data[icode].operand[2].predicate (op2, mode2)) + || !(UNSIGNED_INT8 (INTVAL (op2)))) + error ("operand 3 should be an unsigned 8-bit value"); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); - mode0 = insn_data[icode].operand[1].mode; + if (!insn_data[icode].operand[3].predicate (op3, mode3)) + op3 = copy_to_mode_reg (mode3, op3); - emit_insn (gen_lr (target, op0)); - return target; + pat = GEN_FCN (icode) (op0, op1, op2, op3); + if (!pat) + return NULL_RTX; - case ARC_BUILTIN_SR: - icode = CODE_FOR_sr; - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); + emit_insn (pat); + return NULL_RTX; - fold (arg1); + case ARC_BUILTIN_VST16_N: + case ARC_BUILTIN_VST32_N: + arg0 = CALL_EXPR_ARG (exp, 0); /* source vreg. */ + arg1 = CALL_EXPR_ARG (exp, 1); /* u3. */ + arg2 = CALL_EXPR_ARG (exp, 2); /* [I]0-7. */ + arg3 = CALL_EXPR_ARG (exp, 3); /* u8. */ - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL); + op0 = expand_expr (arg3, NULL_RTX, SImode, EXPAND_NORMAL); + op1 = gen_rtx_REG (V8HImode, ARC_FIRST_SIMD_VR_REG); + op2 = expand_expr (arg2, NULL_RTX, SImode, EXPAND_NORMAL); + op3 = expand_expr (arg0, NULL_RTX, V8HImode, EXPAND_NORMAL); + op4 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); mode0 = insn_data[icode].operand[0].mode; - mode1 = insn_data[icode].operand[1].mode; + mode2 = insn_data[icode].operand[2].mode; + mode3 = insn_data[icode].operand[3].mode; + mode4 = insn_data[icode].operand[4].mode; - emit_insn (gen_sr (op0, op1)); - return NULL_RTX; + /* Do some correctness checks for the operands. */ + if ((!insn_data[icode].operand[0].predicate (op0, mode0)) + || !(UNSIGNED_INT8 (INTVAL (op0)))) + error ("operand 4 should be an unsigned 8-bit value (0-255)"); - case ARC_BUILTIN_TRAP_S: - icode = CODE_FOR_trap_s; - arg0 = CALL_EXPR_ARG (exp, 0); + if ((!insn_data[icode].operand[2].predicate (op2, mode2)) + || !(UNSIGNED_INT3 (INTVAL (op2)))) + error ("operand 3 should be an unsigned 3-bit value (I0-I7)"); - fold (arg0); + if (!insn_data[icode].operand[3].predicate (op3, mode3)) + op3 = copy_to_mode_reg (mode3, op3); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); - mode0 = insn_data[icode].operand[1].mode; + if ((!insn_data[icode].operand[4].predicate (op4, mode4)) + || !(UNSIGNED_INT3 (INTVAL (op4)))) + error ("operand 2 should be an unsigned 3-bit value (subreg 0-7)"); + else if (icode == CODE_FOR_vst32_n_insn + && ((INTVAL (op4) % 2) != 0)) + error ("operand 2 should be an even 3-bit value (subreg 0,2,4,6)"); - /* We don't give an error for non-cost values here because - we still want to allow things to be fixed up by later inlining / - constant folding / dead code elimination. */ - if (CONST_INT_P (op0) && !satisfies_constraint_L (op0)) - { - /* Keep this message in sync with the one in arc.md:trap_s, - because *.md files don't get scanned by exgettext. */ - error ("operand to trap_s should be an unsigned 6-bit value"); - } - emit_insn (gen_trap_s (op0)); - return NULL_RTX; + pat = GEN_FCN (icode) (op0, op1, op2, op3, op4); + if (!pat) + return NULL_RTX; - case ARC_BUILTIN_UNIMP_S: - icode = CODE_FOR_unimp_s; - emit_insn (gen_unimp_s (const1_rtx)); + emit_insn (pat); return NULL_RTX; - case ARC_BUILTIN_ALIGNED: - /* __builtin_arc_aligned (void* val, int alignval) */ - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - fold (arg1); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL); - target = gen_reg_rtx (SImode); + default: + break; + } + + /* 2nd part: Expand regular builtins. */ + if (icode == 0) + internal_error ("bad builtin fcode"); + + nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; + j = 0; - if (!CONST_INT_P (op1)) + if (nonvoid) + { + if (target == NULL_RTX + || GET_MODE (target) != tmode + || !insn_data[icode].operand[0].predicate (target, tmode)) { - /* If we can't fold the alignment to a constant integer - whilst optimizing, this is probably a user error. */ - if (optimize) - warning (0, "__builtin_arc_aligned with non-constant alignment"); + target = gen_reg_rtx (tmode); } - else + xop[j++] = target; + } + + gcc_assert (n_args <= 4); + for (i = 0; i < n_args; i++, j++) + { + tree arg = CALL_EXPR_ARG (exp, i); + machine_mode mode = insn_data[icode].operand[j].mode; + rtx op = expand_expr (arg, NULL_RTX, mode, EXPAND_NORMAL); + machine_mode opmode = GET_MODE (op); + char c = insn_data[icode].operand[j].constraint[0]; + + /* SIMD extension requires exact immediate operand match. */ + if ((id > ARC_BUILTIN_SIMD_BEGIN) + && (id < ARC_BUILTIN_SIMD_END) + && (c != 'v') + && (c != 'r')) { - HOST_WIDE_INT alignTest = INTVAL (op1); - /* Check alignTest is positive, and a power of two. */ - if (alignTest <= 0 || alignTest != (alignTest & -alignTest)) + if (!CONST_INT_P (op)) + error ("builtin requires an immediate for operand %d", j); + switch (c) { - error ("invalid alignment value for __builtin_arc_aligned"); - return NULL_RTX; + case 'L': + if (!satisfies_constraint_L (op)) + error ("operand %d should be a 6 bit unsigned immediate", j); + break; + case 'P': + if (!satisfies_constraint_P (op)) + error ("operand %d should be a 8 bit unsigned immediate", j); + break; + case 'K': + if (!satisfies_constraint_K (op)) + error ("operand %d should be a 3 bit unsigned immediate", j); + break; + default: + error ("unknown builtin immediate operand type for operand %d", + j); } + } - if (CONST_INT_P (op0)) - { - HOST_WIDE_INT pnt = INTVAL (op0); + if (CONST_INT_P (op)) + opmode = mode; - if ((pnt & (alignTest - 1)) == 0) - return const1_rtx; - } - else - { - unsigned align = get_pointer_alignment (arg0); - unsigned numBits = alignTest * BITS_PER_UNIT; - - if (align && align >= numBits) - return const1_rtx; - /* Another attempt to ascertain alignment. Check the type - we are pointing to. */ - if (POINTER_TYPE_P (TREE_TYPE (arg0)) - && TYPE_ALIGN (TREE_TYPE (TREE_TYPE (arg0))) >= numBits) - return const1_rtx; - } + if ((opmode == SImode) && (mode == HImode)) + { + opmode = HImode; + op = gen_lowpart (HImode, op); } - /* Default to false. */ - return const0_rtx; + /* In case the insn wants input operands in modes different from + the result, abort. */ + gcc_assert (opmode == mode || opmode == VOIDmode); - default: - break; + if (!insn_data[icode].operand[i + nonvoid].predicate (op, mode)) + op = copy_to_mode_reg (mode, op); + + xop[j] = op; } - /* @@@ Should really do something sensible here. */ - return NULL_RTX; + pat = apply_GEN_FCN (icode, xop); + if (pat == NULL_RTX) + return NULL_RTX; + + emit_insn (pat); + + if (nonvoid) + return target; + else + return const0_rtx; } /* Returns true if the operands[opno] is a valid compile-time constant to be @@ -6708,809 +6768,6 @@ arc_asm_output_aligned_decl_local (FILE * stream, tree decl, const char * name, ASM_OUTPUT_SKIP (stream, size); } - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -/* SIMD builtins support. */ -enum simd_insn_args_type { - Va_Vb_Vc, - Va_Vb_rlimm, - Va_Vb_Ic, - Va_Vb_u6, - Va_Vb_u8, - Va_rlimm_u8, - - Va_Vb, - - void_rlimm, - void_u6, - - Da_u3_rlimm, - Da_rlimm_rlimm, - - Va_Ib_u8, - void_Va_Ib_u8, - - Va_Vb_Ic_u8, - void_Va_u3_Ib_u8 -}; - -struct builtin_description -{ - enum simd_insn_args_type args_type; - const enum insn_code icode; - const char * const name; - const enum arc_builtins code; -}; - -static const struct builtin_description arc_simd_builtin_desc_list[] = -{ - /* VVV builtins go first. */ -#define SIMD_BUILTIN(type, code, string, builtin) \ - { type,CODE_FOR_##code, "__builtin_arc_" string, \ - ARC_SIMD_BUILTIN_##builtin }, - - SIMD_BUILTIN (Va_Vb_Vc, vaddaw_insn, "vaddaw", VADDAW) - SIMD_BUILTIN (Va_Vb_Vc, vaddw_insn, "vaddw", VADDW) - SIMD_BUILTIN (Va_Vb_Vc, vavb_insn, "vavb", VAVB) - SIMD_BUILTIN (Va_Vb_Vc, vavrb_insn, "vavrb", VAVRB) - SIMD_BUILTIN (Va_Vb_Vc, vdifaw_insn, "vdifaw", VDIFAW) - SIMD_BUILTIN (Va_Vb_Vc, vdifw_insn, "vdifw", VDIFW) - SIMD_BUILTIN (Va_Vb_Vc, vmaxaw_insn, "vmaxaw", VMAXAW) - SIMD_BUILTIN (Va_Vb_Vc, vmaxw_insn, "vmaxw", VMAXW) - SIMD_BUILTIN (Va_Vb_Vc, vminaw_insn, "vminaw", VMINAW) - SIMD_BUILTIN (Va_Vb_Vc, vminw_insn, "vminw", VMINW) - SIMD_BUILTIN (Va_Vb_Vc, vmulaw_insn, "vmulaw", VMULAW) - SIMD_BUILTIN (Va_Vb_Vc, vmulfaw_insn, "vmulfaw", VMULFAW) - SIMD_BUILTIN (Va_Vb_Vc, vmulfw_insn, "vmulfw", VMULFW) - SIMD_BUILTIN (Va_Vb_Vc, vmulw_insn, "vmulw", VMULW) - SIMD_BUILTIN (Va_Vb_Vc, vsubaw_insn, "vsubaw", VSUBAW) - SIMD_BUILTIN (Va_Vb_Vc, vsubw_insn, "vsubw", VSUBW) - SIMD_BUILTIN (Va_Vb_Vc, vsummw_insn, "vsummw", VSUMMW) - SIMD_BUILTIN (Va_Vb_Vc, vand_insn, "vand", VAND) - SIMD_BUILTIN (Va_Vb_Vc, vandaw_insn, "vandaw", VANDAW) - SIMD_BUILTIN (Va_Vb_Vc, vbic_insn, "vbic", VBIC) - SIMD_BUILTIN (Va_Vb_Vc, vbicaw_insn, "vbicaw", VBICAW) - SIMD_BUILTIN (Va_Vb_Vc, vor_insn, "vor", VOR) - SIMD_BUILTIN (Va_Vb_Vc, vxor_insn, "vxor", VXOR) - SIMD_BUILTIN (Va_Vb_Vc, vxoraw_insn, "vxoraw", VXORAW) - SIMD_BUILTIN (Va_Vb_Vc, veqw_insn, "veqw", VEQW) - SIMD_BUILTIN (Va_Vb_Vc, vlew_insn, "vlew", VLEW) - SIMD_BUILTIN (Va_Vb_Vc, vltw_insn, "vltw", VLTW) - SIMD_BUILTIN (Va_Vb_Vc, vnew_insn, "vnew", VNEW) - SIMD_BUILTIN (Va_Vb_Vc, vmr1aw_insn, "vmr1aw", VMR1AW) - SIMD_BUILTIN (Va_Vb_Vc, vmr1w_insn, "vmr1w", VMR1W) - SIMD_BUILTIN (Va_Vb_Vc, vmr2aw_insn, "vmr2aw", VMR2AW) - SIMD_BUILTIN (Va_Vb_Vc, vmr2w_insn, "vmr2w", VMR2W) - SIMD_BUILTIN (Va_Vb_Vc, vmr3aw_insn, "vmr3aw", VMR3AW) - SIMD_BUILTIN (Va_Vb_Vc, vmr3w_insn, "vmr3w", VMR3W) - SIMD_BUILTIN (Va_Vb_Vc, vmr4aw_insn, "vmr4aw", VMR4AW) - SIMD_BUILTIN (Va_Vb_Vc, vmr4w_insn, "vmr4w", VMR4W) - SIMD_BUILTIN (Va_Vb_Vc, vmr5aw_insn, "vmr5aw", VMR5AW) - SIMD_BUILTIN (Va_Vb_Vc, vmr5w_insn, "vmr5w", VMR5W) - SIMD_BUILTIN (Va_Vb_Vc, vmr6aw_insn, "vmr6aw", VMR6AW) - SIMD_BUILTIN (Va_Vb_Vc, vmr6w_insn, "vmr6w", VMR6W) - SIMD_BUILTIN (Va_Vb_Vc, vmr7aw_insn, "vmr7aw", VMR7AW) - SIMD_BUILTIN (Va_Vb_Vc, vmr7w_insn, "vmr7w", VMR7W) - SIMD_BUILTIN (Va_Vb_Vc, vmrb_insn, "vmrb", VMRB) - SIMD_BUILTIN (Va_Vb_Vc, vh264f_insn, "vh264f", VH264F) - SIMD_BUILTIN (Va_Vb_Vc, vh264ft_insn, "vh264ft", VH264FT) - SIMD_BUILTIN (Va_Vb_Vc, vh264fw_insn, "vh264fw", VH264FW) - SIMD_BUILTIN (Va_Vb_Vc, vvc1f_insn, "vvc1f", VVC1F) - SIMD_BUILTIN (Va_Vb_Vc, vvc1ft_insn, "vvc1ft", VVC1FT) - - SIMD_BUILTIN (Va_Vb_rlimm, vbaddw_insn, "vbaddw", VBADDW) - SIMD_BUILTIN (Va_Vb_rlimm, vbmaxw_insn, "vbmaxw", VBMAXW) - SIMD_BUILTIN (Va_Vb_rlimm, vbminw_insn, "vbminw", VBMINW) - SIMD_BUILTIN (Va_Vb_rlimm, vbmulaw_insn, "vbmulaw", VBMULAW) - SIMD_BUILTIN (Va_Vb_rlimm, vbmulfw_insn, "vbmulfw", VBMULFW) - SIMD_BUILTIN (Va_Vb_rlimm, vbmulw_insn, "vbmulw", VBMULW) - SIMD_BUILTIN (Va_Vb_rlimm, vbrsubw_insn, "vbrsubw", VBRSUBW) - SIMD_BUILTIN (Va_Vb_rlimm, vbsubw_insn, "vbsubw", VBSUBW) - - /* Va, Vb, Ic instructions. */ - SIMD_BUILTIN (Va_Vb_Ic, vasrw_insn, "vasrw", VASRW) - SIMD_BUILTIN (Va_Vb_Ic, vsr8_insn, "vsr8", VSR8) - SIMD_BUILTIN (Va_Vb_Ic, vsr8aw_insn, "vsr8aw", VSR8AW) - - /* Va, Vb, u6 instructions. */ - SIMD_BUILTIN (Va_Vb_u6, vasrrwi_insn, "vasrrwi", VASRRWi) - SIMD_BUILTIN (Va_Vb_u6, vasrsrwi_insn, "vasrsrwi", VASRSRWi) - SIMD_BUILTIN (Va_Vb_u6, vasrwi_insn, "vasrwi", VASRWi) - SIMD_BUILTIN (Va_Vb_u6, vasrpwbi_insn, "vasrpwbi", VASRPWBi) - SIMD_BUILTIN (Va_Vb_u6, vasrrpwbi_insn,"vasrrpwbi", VASRRPWBi) - SIMD_BUILTIN (Va_Vb_u6, vsr8awi_insn, "vsr8awi", VSR8AWi) - SIMD_BUILTIN (Va_Vb_u6, vsr8i_insn, "vsr8i", VSR8i) - - /* Va, Vb, u8 (simm) instructions. */ - SIMD_BUILTIN (Va_Vb_u8, vmvaw_insn, "vmvaw", VMVAW) - SIMD_BUILTIN (Va_Vb_u8, vmvw_insn, "vmvw", VMVW) - SIMD_BUILTIN (Va_Vb_u8, vmvzw_insn, "vmvzw", VMVZW) - SIMD_BUILTIN (Va_Vb_u8, vd6tapf_insn, "vd6tapf", VD6TAPF) - - /* Va, rlimm, u8 (simm) instructions. */ - SIMD_BUILTIN (Va_rlimm_u8, vmovaw_insn, "vmovaw", VMOVAW) - SIMD_BUILTIN (Va_rlimm_u8, vmovw_insn, "vmovw", VMOVW) - SIMD_BUILTIN (Va_rlimm_u8, vmovzw_insn, "vmovzw", VMOVZW) - - /* Va, Vb instructions. */ - SIMD_BUILTIN (Va_Vb, vabsaw_insn, "vabsaw", VABSAW) - SIMD_BUILTIN (Va_Vb, vabsw_insn, "vabsw", VABSW) - SIMD_BUILTIN (Va_Vb, vaddsuw_insn, "vaddsuw", VADDSUW) - SIMD_BUILTIN (Va_Vb, vsignw_insn, "vsignw", VSIGNW) - SIMD_BUILTIN (Va_Vb, vexch1_insn, "vexch1", VEXCH1) - SIMD_BUILTIN (Va_Vb, vexch2_insn, "vexch2", VEXCH2) - SIMD_BUILTIN (Va_Vb, vexch4_insn, "vexch4", VEXCH4) - SIMD_BUILTIN (Va_Vb, vupbaw_insn, "vupbaw", VUPBAW) - SIMD_BUILTIN (Va_Vb, vupbw_insn, "vupbw", VUPBW) - SIMD_BUILTIN (Va_Vb, vupsbaw_insn, "vupsbaw", VUPSBAW) - SIMD_BUILTIN (Va_Vb, vupsbw_insn, "vupsbw", VUPSBW) - - /* DIb, rlimm, rlimm instructions. */ - SIMD_BUILTIN (Da_rlimm_rlimm, vdirun_insn, "vdirun", VDIRUN) - SIMD_BUILTIN (Da_rlimm_rlimm, vdorun_insn, "vdorun", VDORUN) - - /* DIb, limm, rlimm instructions. */ - SIMD_BUILTIN (Da_u3_rlimm, vdiwr_insn, "vdiwr", VDIWR) - SIMD_BUILTIN (Da_u3_rlimm, vdowr_insn, "vdowr", VDOWR) - - /* rlimm instructions. */ - SIMD_BUILTIN (void_rlimm, vrec_insn, "vrec", VREC) - SIMD_BUILTIN (void_rlimm, vrun_insn, "vrun", VRUN) - SIMD_BUILTIN (void_rlimm, vrecrun_insn, "vrecrun", VRECRUN) - SIMD_BUILTIN (void_rlimm, vendrec_insn, "vendrec", VENDREC) - - /* Va, [Ib,u8] instructions. */ - SIMD_BUILTIN (Va_Vb_Ic_u8, vld32wh_insn, "vld32wh", VLD32WH) - SIMD_BUILTIN (Va_Vb_Ic_u8, vld32wl_insn, "vld32wl", VLD32WL) - SIMD_BUILTIN (Va_Vb_Ic_u8, vld64_insn, "vld64", VLD64) - SIMD_BUILTIN (Va_Vb_Ic_u8, vld32_insn, "vld32", VLD32) - - SIMD_BUILTIN (Va_Ib_u8, vld64w_insn, "vld64w", VLD64W) - SIMD_BUILTIN (Va_Ib_u8, vld128_insn, "vld128", VLD128) - SIMD_BUILTIN (void_Va_Ib_u8, vst128_insn, "vst128", VST128) - SIMD_BUILTIN (void_Va_Ib_u8, vst64_insn, "vst64", VST64) - - /* Va, [Ib, u8] instructions. */ - SIMD_BUILTIN (void_Va_u3_Ib_u8, vst16_n_insn, "vst16_n", VST16_N) - SIMD_BUILTIN (void_Va_u3_Ib_u8, vst32_n_insn, "vst32_n", VST32_N) - - SIMD_BUILTIN (void_u6, vinti_insn, "vinti", VINTI) -}; - -static void -arc_init_simd_builtins (void) -{ - int i; - tree endlink = void_list_node; - tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode); - - tree v8hi_ftype_v8hi_v8hi - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - endlink))); - tree v8hi_ftype_v8hi_int - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, integer_type_node, - endlink))); - - tree v8hi_ftype_v8hi_int_int - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, - integer_type_node, - endlink)))); - - tree void_ftype_v8hi_int_int - = build_function_type (void_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, - integer_type_node, - endlink)))); - - tree void_ftype_v8hi_int_int_int - = (build_function_type - (void_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, - integer_type_node, - endlink)))))); - - tree v8hi_ftype_int_int - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, integer_type_node, - endlink))); - - tree void_ftype_int_int - = build_function_type (void_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, integer_type_node, - endlink))); - - tree void_ftype_int - = build_function_type (void_type_node, - tree_cons (NULL_TREE, integer_type_node, endlink)); - - tree v8hi_ftype_v8hi - = build_function_type (V8HI_type_node, tree_cons (NULL_TREE, V8HI_type_node, - endlink)); - - /* These asserts have been introduced to ensure that the order of builtins - does not get messed up, else the initialization goes wrong. */ - gcc_assert (arc_simd_builtin_desc_list [0].args_type == Va_Vb_Vc); - for (i=0; arc_simd_builtin_desc_list [i].args_type == Va_Vb_Vc; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list[i].name, - v8hi_ftype_v8hi_v8hi, arc_simd_builtin_desc_list[i].code); - - gcc_assert (arc_simd_builtin_desc_list [i].args_type == Va_Vb_rlimm); - for (; arc_simd_builtin_desc_list [i].args_type == Va_Vb_rlimm; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list[i].name, - v8hi_ftype_v8hi_int, arc_simd_builtin_desc_list[i].code); - - gcc_assert (arc_simd_builtin_desc_list [i].args_type == Va_Vb_Ic); - for (; arc_simd_builtin_desc_list [i].args_type == Va_Vb_Ic; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list[i].name, - v8hi_ftype_v8hi_int, arc_simd_builtin_desc_list[i].code); - - gcc_assert (arc_simd_builtin_desc_list [i].args_type == Va_Vb_u6); - for (; arc_simd_builtin_desc_list [i].args_type == Va_Vb_u6; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list[i].name, - v8hi_ftype_v8hi_int, arc_simd_builtin_desc_list[i].code); - - gcc_assert (arc_simd_builtin_desc_list [i].args_type == Va_Vb_u8); - for (; arc_simd_builtin_desc_list [i].args_type == Va_Vb_u8; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list[i].name, - v8hi_ftype_v8hi_int, arc_simd_builtin_desc_list[i].code); - - gcc_assert (arc_simd_builtin_desc_list [i].args_type == Va_rlimm_u8); - for (; arc_simd_builtin_desc_list [i].args_type == Va_rlimm_u8; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list[i].name, - v8hi_ftype_int_int, arc_simd_builtin_desc_list[i].code); - - gcc_assert (arc_simd_builtin_desc_list [i].args_type == Va_Vb); - for (; arc_simd_builtin_desc_list [i].args_type == Va_Vb; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list[i].name, - v8hi_ftype_v8hi, arc_simd_builtin_desc_list[i].code); - - gcc_assert (arc_simd_builtin_desc_list [i].args_type == Da_rlimm_rlimm); - for (; arc_simd_builtin_desc_list [i].args_type == Da_rlimm_rlimm; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list [i].name, - void_ftype_int_int, arc_simd_builtin_desc_list[i].code); - - gcc_assert (arc_simd_builtin_desc_list [i].args_type == Da_u3_rlimm); - for (; arc_simd_builtin_desc_list [i].args_type == Da_u3_rlimm; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list[i].name, - void_ftype_int_int, arc_simd_builtin_desc_list[i].code); - - gcc_assert (arc_simd_builtin_desc_list [i].args_type == void_rlimm); - for (; arc_simd_builtin_desc_list [i].args_type == void_rlimm; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list[i].name, - void_ftype_int, arc_simd_builtin_desc_list[i].code); - - gcc_assert (arc_simd_builtin_desc_list [i].args_type == Va_Vb_Ic_u8); - for (; arc_simd_builtin_desc_list [i].args_type == Va_Vb_Ic_u8; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list[i].name, - v8hi_ftype_v8hi_int_int, arc_simd_builtin_desc_list[i].code); - - gcc_assert (arc_simd_builtin_desc_list [i].args_type == Va_Ib_u8); - for (; arc_simd_builtin_desc_list [i].args_type == Va_Ib_u8; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list[i].name, - v8hi_ftype_int_int, arc_simd_builtin_desc_list[i].code); - - gcc_assert (arc_simd_builtin_desc_list [i].args_type == void_Va_Ib_u8); - for (; arc_simd_builtin_desc_list [i].args_type == void_Va_Ib_u8; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list [i].name, - void_ftype_v8hi_int_int, arc_simd_builtin_desc_list[i].code); - - gcc_assert (arc_simd_builtin_desc_list [i].args_type == void_Va_u3_Ib_u8); - for (; arc_simd_builtin_desc_list [i].args_type == void_Va_u3_Ib_u8; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list[i].name, - void_ftype_v8hi_int_int_int, - arc_simd_builtin_desc_list[i].code); - - gcc_assert (arc_simd_builtin_desc_list [i].args_type == void_u6); - for (; arc_simd_builtin_desc_list [i].args_type == void_u6; i++) - def_mbuiltin (TARGET_SIMD_SET, arc_simd_builtin_desc_list[i].name, - void_ftype_int, arc_simd_builtin_desc_list[i].code); - - gcc_assert(i == ARRAY_SIZE (arc_simd_builtin_desc_list)); -} - -/* Helper function of arc_expand_builtin; has the same parameters, - except that EXP is now known to be a call to a simd builtin. */ - -static rtx -arc_expand_simd_builtin (tree exp, - rtx target, - rtx subtarget ATTRIBUTE_UNUSED, - machine_mode mode ATTRIBUTE_UNUSED, - int ignore ATTRIBUTE_UNUSED) -{ - tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); - tree arg0; - tree arg1; - tree arg2; - tree arg3; - rtx op0; - rtx op1; - rtx op2; - rtx op3; - rtx op4; - rtx pat; - unsigned int i; - int fcode = DECL_FUNCTION_CODE (fndecl); - int icode; - machine_mode mode0; - machine_mode mode1; - machine_mode mode2; - machine_mode mode3; - machine_mode mode4; - const struct builtin_description * d; - - for (i = 0, d = arc_simd_builtin_desc_list; - i < ARRAY_SIZE (arc_simd_builtin_desc_list); i++, d++) - if (d->code == (const enum arc_builtins) fcode) - break; - - /* We must get an entry here. */ - gcc_assert (i < ARRAY_SIZE (arc_simd_builtin_desc_list)); - - switch (d->args_type) - { - case Va_Vb_rlimm: - icode = d->icode; - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - op0 = expand_expr (arg0, NULL_RTX, V8HImode, EXPAND_NORMAL); - op1 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); - - target = gen_reg_rtx (V8HImode); - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - - pat = GEN_FCN (icode) (target, op0, op1); - if (! pat) - return 0; - - emit_insn (pat); - return target; - - case Va_Vb_u6: - case Va_Vb_u8: - icode = d->icode; - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - op0 = expand_expr (arg0, NULL_RTX, V8HImode, EXPAND_NORMAL); - op1 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); - - target = gen_reg_rtx (V8HImode); - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1) - || (d->args_type == Va_Vb_u6 && !UNSIGNED_INT6 (INTVAL (op1))) - || (d->args_type == Va_Vb_u8 && !UNSIGNED_INT8 (INTVAL (op1)))) - error ("operand 2 of %s instruction should be an unsigned %d-bit value", - d->name, - (d->args_type == Va_Vb_u6)? 6: 8); - - pat = GEN_FCN (icode) (target, op0, op1); - if (! pat) - return 0; - - emit_insn (pat); - return target; - - case Va_rlimm_u8: - icode = d->icode; - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - op0 = expand_expr (arg0, NULL_RTX, SImode, EXPAND_NORMAL); - op1 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); - - target = gen_reg_rtx (V8HImode); - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - - if ( (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) - || !(UNSIGNED_INT8 (INTVAL (op1)))) - error ("operand 2 of %s instruction should be an unsigned 8-bit value", - d->name); - - pat = GEN_FCN (icode) (target, op0, op1); - if (! pat) - return 0; - - emit_insn (pat); - return target; - - case Va_Vb_Ic: - icode = d->icode; - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - op0 = expand_expr (arg0, NULL_RTX, V8HImode, EXPAND_NORMAL); - op1 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); - op2 = gen_rtx_REG (V8HImode, ARC_FIRST_SIMD_VR_REG); - - target = gen_reg_rtx (V8HImode); - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - - if ( (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) - || !(UNSIGNED_INT3 (INTVAL (op1)))) - error ("operand 2 of %s instruction should be an unsigned 3-bit value (I0-I7)", - d->name); - - pat = GEN_FCN (icode) (target, op0, op1, op2); - if (! pat) - return 0; - - emit_insn (pat); - return target; - - case Va_Vb_Vc: - icode = d->icode; - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - op0 = expand_expr (arg0, NULL_RTX, V8HImode, EXPAND_NORMAL); - op1 = expand_expr (arg1, NULL_RTX, V8HImode, EXPAND_NORMAL); - - target = gen_reg_rtx (V8HImode); - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - - pat = GEN_FCN (icode) (target, op0, op1); - if (! pat) - return 0; - - emit_insn (pat); - return target; - - case Va_Vb: - icode = d->icode; - arg0 = CALL_EXPR_ARG (exp, 0); - op0 = expand_expr (arg0, NULL_RTX, V8HImode, EXPAND_NORMAL); - - target = gen_reg_rtx (V8HImode); - mode0 = insn_data[icode].operand[1].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - - pat = GEN_FCN (icode) (target, op0); - if (! pat) - return 0; - - emit_insn (pat); - return target; - - case Da_rlimm_rlimm: - icode = d->icode; - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - op0 = expand_expr (arg0, NULL_RTX, SImode, EXPAND_NORMAL); - op1 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); - - - if (icode == CODE_FOR_vdirun_insn) - target = gen_rtx_REG (SImode, 131); - else if (icode == CODE_FOR_vdorun_insn) - target = gen_rtx_REG (SImode, 139); - else - gcc_unreachable (); - - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - - - pat = GEN_FCN (icode) (target, op0, op1); - if (! pat) - return 0; - - emit_insn (pat); - return NULL_RTX; - - case Da_u3_rlimm: - icode = d->icode; - arg0 = CALL_EXPR_ARG (exp, 0); - arg1 = CALL_EXPR_ARG (exp, 1); - op0 = expand_expr (arg0, NULL_RTX, SImode, EXPAND_NORMAL); - op1 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); - - - if (! (GET_CODE (op0) == CONST_INT) - || !(UNSIGNED_INT3 (INTVAL (op0)))) - error ("operand 1 of %s instruction should be an unsigned 3-bit value (DR0-DR7)", - d->name); - - mode1 = insn_data[icode].operand[1].mode; - - if (icode == CODE_FOR_vdiwr_insn) - target = gen_rtx_REG (SImode, - ARC_FIRST_SIMD_DMA_CONFIG_IN_REG + INTVAL (op0)); - else if (icode == CODE_FOR_vdowr_insn) - target = gen_rtx_REG (SImode, - ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG + INTVAL (op0)); - else - gcc_unreachable (); - - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - - pat = GEN_FCN (icode) (target, op1); - if (! pat) - return 0; - - emit_insn (pat); - return NULL_RTX; - - case void_u6: - icode = d->icode; - arg0 = CALL_EXPR_ARG (exp, 0); - - fold (arg0); - - op0 = expand_expr (arg0, NULL_RTX, SImode, EXPAND_NORMAL); - mode0 = insn_data[icode].operand[0].mode; - - /* op0 should be u6. */ - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0) - || !(UNSIGNED_INT6 (INTVAL (op0)))) - error ("operand of %s instruction should be an unsigned 6-bit value", - d->name); - - pat = GEN_FCN (icode) (op0); - if (! pat) - return 0; - - emit_insn (pat); - return NULL_RTX; - - case void_rlimm: - icode = d->icode; - arg0 = CALL_EXPR_ARG (exp, 0); - - fold (arg0); - - op0 = expand_expr (arg0, NULL_RTX, SImode, EXPAND_NORMAL); - mode0 = insn_data[icode].operand[0].mode; - - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - - pat = GEN_FCN (icode) (op0); - if (! pat) - return 0; - - emit_insn (pat); - return NULL_RTX; - - case Va_Vb_Ic_u8: - { - rtx src_vreg; - icode = d->icode; - arg0 = CALL_EXPR_ARG (exp, 0); /* source vreg */ - arg1 = CALL_EXPR_ARG (exp, 1); /* [I]0-7 */ - arg2 = CALL_EXPR_ARG (exp, 2); /* u8 */ - - src_vreg = expand_expr (arg0, NULL_RTX, V8HImode, EXPAND_NORMAL); - op0 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); /* [I]0-7 */ - op1 = expand_expr (arg2, NULL_RTX, SImode, EXPAND_NORMAL); /* u8 */ - op2 = gen_rtx_REG (V8HImode, ARC_FIRST_SIMD_VR_REG); /* VR0 */ - - /* target <- src vreg */ - emit_insn (gen_move_insn (target, src_vreg)); - - /* target <- vec_concat: target, mem(Ib, u8) */ - mode0 = insn_data[icode].operand[3].mode; - mode1 = insn_data[icode].operand[1].mode; - - if ( (!(*insn_data[icode].operand[3].predicate) (op0, mode0)) - || !(UNSIGNED_INT3 (INTVAL (op0)))) - error ("operand 1 of %s instruction should be an unsigned 3-bit value (I0-I7)", - d->name); - - if ( (!(*insn_data[icode].operand[1].predicate) (op1, mode1)) - || !(UNSIGNED_INT8 (INTVAL (op1)))) - error ("operand 2 of %s instruction should be an unsigned 8-bit value", - d->name); - - pat = GEN_FCN (icode) (target, op1, op2, op0); - if (! pat) - return 0; - - emit_insn (pat); - return target; - } - - case void_Va_Ib_u8: - icode = d->icode; - arg0 = CALL_EXPR_ARG (exp, 0); /* src vreg */ - arg1 = CALL_EXPR_ARG (exp, 1); /* [I]0-7 */ - arg2 = CALL_EXPR_ARG (exp, 2); /* u8 */ - - op0 = gen_rtx_REG (V8HImode, ARC_FIRST_SIMD_VR_REG); /* VR0 */ - op1 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); /* I[0-7] */ - op2 = expand_expr (arg2, NULL_RTX, SImode, EXPAND_NORMAL); /* u8 */ - op3 = expand_expr (arg0, NULL_RTX, V8HImode, EXPAND_NORMAL); /* Vdest */ - - mode0 = insn_data[icode].operand[0].mode; - mode1 = insn_data[icode].operand[1].mode; - mode2 = insn_data[icode].operand[2].mode; - mode3 = insn_data[icode].operand[3].mode; - - if ( (!(*insn_data[icode].operand[1].predicate) (op1, mode1)) - || !(UNSIGNED_INT3 (INTVAL (op1)))) - error ("operand 2 of %s instruction should be an unsigned 3-bit value (I0-I7)", - d->name); - - if ( (!(*insn_data[icode].operand[2].predicate) (op2, mode2)) - || !(UNSIGNED_INT8 (INTVAL (op2)))) - error ("operand 3 of %s instruction should be an unsigned 8-bit value", - d->name); - - if (!(*insn_data[icode].operand[3].predicate) (op3, mode3)) - op3 = copy_to_mode_reg (mode3, op3); - - pat = GEN_FCN (icode) (op0, op1, op2, op3); - if (! pat) - return 0; - - emit_insn (pat); - return NULL_RTX; - - case Va_Ib_u8: - icode = d->icode; - arg0 = CALL_EXPR_ARG (exp, 0); /* dest vreg */ - arg1 = CALL_EXPR_ARG (exp, 1); /* [I]0-7 */ - - op0 = gen_rtx_REG (V8HImode, ARC_FIRST_SIMD_VR_REG); /* VR0 */ - op1 = expand_expr (arg0, NULL_RTX, SImode, EXPAND_NORMAL); /* I[0-7] */ - op2 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); /* u8 */ - - /* target <- src vreg */ - target = gen_reg_rtx (V8HImode); - - /* target <- vec_concat: target, mem(Ib, u8) */ - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - mode2 = insn_data[icode].operand[3].mode; - - if ( (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) - || !(UNSIGNED_INT3 (INTVAL (op1)))) - error ("operand 1 of %s instruction should be an unsigned 3-bit value (I0-I7)", - d->name); - - if ( (!(*insn_data[icode].operand[3].predicate) (op2, mode2)) - || !(UNSIGNED_INT8 (INTVAL (op2)))) - error ("operand 2 of %s instruction should be an unsigned 8-bit value", - d->name); - - pat = GEN_FCN (icode) (target, op0, op1, op2); - if (! pat) - return 0; - - emit_insn (pat); - return target; - - case void_Va_u3_Ib_u8: - icode = d->icode; - arg0 = CALL_EXPR_ARG (exp, 0); /* source vreg */ - arg1 = CALL_EXPR_ARG (exp, 1); /* u3 */ - arg2 = CALL_EXPR_ARG (exp, 2); /* [I]0-7 */ - arg3 = CALL_EXPR_ARG (exp, 3); /* u8 */ - - op0 = expand_expr (arg3, NULL_RTX, SImode, EXPAND_NORMAL); /* u8 */ - op1 = gen_rtx_REG (V8HImode, ARC_FIRST_SIMD_VR_REG); /* VR */ - op2 = expand_expr (arg2, NULL_RTX, SImode, EXPAND_NORMAL); /* [I]0-7 */ - op3 = expand_expr (arg0, NULL_RTX, V8HImode, EXPAND_NORMAL);/* vreg to be stored */ - op4 = expand_expr (arg1, NULL_RTX, SImode, EXPAND_NORMAL); /* vreg 0-7 subreg no. */ - - mode0 = insn_data[icode].operand[0].mode; - mode2 = insn_data[icode].operand[2].mode; - mode3 = insn_data[icode].operand[3].mode; - mode4 = insn_data[icode].operand[4].mode; - - /* Do some correctness checks for the operands. */ - if ( (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) - || !(UNSIGNED_INT8 (INTVAL (op0)))) - error ("operand 4 of %s instruction should be an unsigned 8-bit value (0-255)", - d->name); - - if ( (!(*insn_data[icode].operand[2].predicate) (op2, mode2)) - || !(UNSIGNED_INT3 (INTVAL (op2)))) - error ("operand 3 of %s instruction should be an unsigned 3-bit value (I0-I7)", - d->name); - - if (!(*insn_data[icode].operand[3].predicate) (op3, mode3)) - op3 = copy_to_mode_reg (mode3, op3); - - if ( (!(*insn_data[icode].operand[4].predicate) (op4, mode4)) - || !(UNSIGNED_INT3 (INTVAL (op4)))) - error ("operand 2 of %s instruction should be an unsigned 3-bit value (subreg 0-7)", - d->name); - else if (icode == CODE_FOR_vst32_n_insn - && ((INTVAL(op4) % 2 ) != 0)) - error ("operand 2 of %s instruction should be an even 3-bit value (subreg 0,2,4,6)", - d->name); - - pat = GEN_FCN (icode) (op0, op1, op2, op3, op4); - if (! pat) - return 0; - - emit_insn (pat); - return NULL_RTX; - - default: - gcc_unreachable (); - } - return NULL_RTX; -} - static bool arc_preserve_reload_p (rtx in) { @@ -8041,6 +7298,7 @@ static bool arc_loop_hazard (rtx_insn *pred, rtx_insn *succ) { rtx_insn *jump = NULL; + rtx label_rtx = NULL_RTX; rtx_insn *label = NULL; basic_block succ_bb; @@ -8067,22 +7325,22 @@ arc_loop_hazard (rtx_insn *pred, rtx_insn *succ) else return false; - label = JUMP_LABEL_AS_INSN (jump); - if (!label) - return false; - /* Phase 2b: Make sure is not a millicode jump. */ if ((GET_CODE (PATTERN (jump)) == PARALLEL) && (XVECEXP (PATTERN (jump), 0, 0) == ret_rtx)) return false; - /* Phase 2c: Make sure is not a simple_return. */ - if ((GET_CODE (PATTERN (jump)) == SIMPLE_RETURN) - || (GET_CODE (label) == SIMPLE_RETURN)) + label_rtx = JUMP_LABEL (jump); + if (!label_rtx) + return false; + + /* Phase 2c: Make sure is not a return. */ + if (ANY_RETURN_P (label_rtx)) return false; /* Pahse 2d: Go to the target of the jump and check for aliveness of LP_COUNT register. */ + label = safe_as_a <rtx_insn *> (label_rtx); succ_bb = BLOCK_FOR_INSN (label); if (!succ_bb) { @@ -9250,11 +8508,13 @@ arc_process_double_reg_moves (rtx *operands) /* Produce the two LR insns to get the high and low parts. */ emit_insn (gen_rtx_SET (destHigh, - gen_rtx_UNSPEC_VOLATILE (Pmode, gen_rtvec (1, src), - VUNSPEC_LR_HIGH))); + gen_rtx_UNSPEC_VOLATILE (Pmode, + gen_rtvec (1, src), + VUNSPEC_ARC_LR_HIGH))); emit_insn (gen_rtx_SET (destLow, - gen_rtx_UNSPEC_VOLATILE (Pmode, gen_rtvec (1, src), - VUNSPEC_LR))); + gen_rtx_UNSPEC_VOLATILE (Pmode, + gen_rtvec (1, src), + VUNSPEC_ARC_LR))); } } else if (state == destDx) @@ -9266,7 +8526,7 @@ arc_process_double_reg_moves (rtx *operands) emit_insn (gen_rtx_UNSPEC_VOLATILE (Pmode, gen_rtvec (3, dest, srcHigh, srcLow), - VUNSPEC_DEXCL_NORES)); + VUNSPEC_ARC_DEXCL_NORES)); } else diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index c895725e623..70a2b1d14ca 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu. - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. Sources derived from work done by Sankhya Technologies (www.sankhya.com) on behalf of Synopsys Inc. diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index ac181a98895..80f1daabd88 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -1,5 +1,5 @@ ;; Machine description of the Synopsys DesignWare ARC cpu for GNU C compiler -;; Copyright (C) 1994-2015 Free Software Foundation, Inc. +;; Copyright (C) 1994-2016 Free Software Foundation, Inc. ;; Sources derived from work done by Sankhya Technologies (www.sankhya.com) on ;; behalf of Synopsys Inc. @@ -104,35 +104,66 @@ ;; GOTBASE.(Referenced as @GOTOFF) ;; ---------------------------------------------------------------------------- +(define_c_enum "unspec" [ + DUMMY_0 + DUMMY_1 + DUMMY_2 + ARC_UNSPEC_PLT + ARC_UNSPEC_GOT + ARC_UNSPEC_GOTOFF + UNSPEC_ARC_NORM + UNSPEC_ARC_NORMW + UNSPEC_ARC_SWAP + UNSPEC_ARC_DIVAW + UNSPEC_ARC_DIRECT + UNSPEC_ARC_LP + UNSPEC_ARC_CASESI + UNSPEC_ARC_FFS + UNSPEC_ARC_FLS + UNSPEC_ARC_MEMBAR + UNSPEC_ARC_DMACH + UNSPEC_ARC_DMACHU + UNSPEC_ARC_DMACWH + UNSPEC_ARC_DMACWHU + UNSPEC_ARC_QMACH + UNSPEC_ARC_QMACHU + UNSPEC_ARC_QMPYH + UNSPEC_ARC_QMPYHU + UNSPEC_ARC_VMAC2H + UNSPEC_ARC_VMAC2HU + UNSPEC_ARC_VMPY2H + UNSPEC_ARC_VMPY2HU + ]) + +(define_c_enum "vunspec" [ + VUNSPEC_ARC_RTIE + VUNSPEC_ARC_SYNC + VUNSPEC_ARC_BRK + VUNSPEC_ARC_FLAG + VUNSPEC_ARC_SLEEP + VUNSPEC_ARC_SWI + VUNSPEC_ARC_CORE_READ + VUNSPEC_ARC_CORE_WRITE + VUNSPEC_ARC_LR + VUNSPEC_ARC_SR + VUNSPEC_ARC_TRAP_S + VUNSPEC_ARC_UNIMP_S + VUNSPEC_ARC_KFLAG + VUNSPEC_ARC_CLRI + VUNSPEC_ARC_SETI + VUNSPEC_ARC_NOP + VUNSPEC_ARC_STACK_IRQ + VUNSPEC_ARC_DEXCL + VUNSPEC_ARC_DEXCL_NORES + VUNSPEC_ARC_LR_HIGH + VUNSPEC_ARC_EX + VUNSPEC_ARC_CAS + VUNSPEC_ARC_SC + VUNSPEC_ARC_LL + ]) (define_constants - [(UNSPEC_SWAP 13) ; swap generation through builtins. candidate for scheduling - (UNSPEC_MUL64 14) ; mul64 generation through builtins. candidate for scheduling - (UNSPEC_MULU64 15) ; mulu64 generation through builtins. candidate for scheduling - (UNSPEC_DIVAW 16) ; divaw generation through builtins. candidate for scheduling - (UNSPEC_DIRECT 17) - (UNSPEC_PROF 18) ; profile callgraph counter - (UNSPEC_LP 19) ; to set LP_END - (UNSPEC_CASESI 20) - (VUNSPEC_RTIE 17) ; blockage insn for rtie generation - (VUNSPEC_SYNC 18) ; blockage insn for sync generation - (VUNSPEC_BRK 19) ; blockage insn for brk generation - (VUNSPEC_FLAG 20) ; blockage insn for flag generation - (VUNSPEC_SLEEP 21) ; blockage insn for sleep generation - (VUNSPEC_SWI 22) ; blockage insn for swi generation - (VUNSPEC_CORE_READ 23) ; blockage insn for reading a core register - (VUNSPEC_CORE_WRITE 24) ; blockage insn for writing to a core register - (VUNSPEC_LR 25) ; blockage insn for reading an auxiliary register - (VUNSPEC_SR 26) ; blockage insn for writing to an auxiliary register - (VUNSPEC_TRAP_S 27) ; blockage insn for trap_s generation - (VUNSPEC_UNIMP_S 28) ; blockage insn for unimp_s generation - (VUNSPEC_NOP 29) ; volatile NOP - - (UNSPEC_ARC_MEMBAR 30) - (VUNSPEC_ARC_CAS 31) - (VUNSPEC_ARC_LL 32) - (VUNSPEC_ARC_SC 33) - (VUNSPEC_ARC_EX 34) + [(UNSPEC_PROF 18) ; profile callgraph counter (R0_REG 0) (R1_REG 1) @@ -145,10 +176,6 @@ (RETURN_ADDR_REGNUM 31) (MUL64_OUT_REG 58) - (VUNSPEC_DEXCL 32) ; blockage insn for reading an auxiliary register without LR support - (VUNSPEC_DEXCL_NORES 33) ; blockage insn for reading an auxiliary register without LR support - (VUNSPEC_LR_HIGH 34) ; blockage insn for reading an auxiliary register - (LP_COUNT 60) (CC_REG 61) (LP_START 144) @@ -716,7 +743,7 @@ (define_insn "store_direct" [(set (match_operand:SI 0 "move_dest_operand" "=m") (unspec:SI [(match_operand:SI 1 "register_operand" "c")] - UNSPEC_DIRECT))] + UNSPEC_ARC_DIRECT))] "" "st%U0 %1,%0\;st%U0.di %1,%0" [(set_attr "type" "store")]) @@ -1083,10 +1110,10 @@ ; dexcl2 r0, r1, r0 (set (match_dup 4) ; aka r0result ; aka DF, r1, r0 - (unspec_volatile:SI [(match_dup 1) (match_dup 5) (match_dup 4)] VUNSPEC_DEXCL )) + (unspec_volatile:SI [(match_dup 1) (match_dup 5) (match_dup 4)] VUNSPEC_ARC_DEXCL )) ; Generate the second, which makes sure operand5 and operand4 values ; are put back in the Dx register properly. - (unspec_volatile:SI [(match_dup 1) (match_dup 5) (match_dup 4)] VUNSPEC_DEXCL_NORES ) + (unspec_volatile:SI [(match_dup 1) (match_dup 5) (match_dup 4)] VUNSPEC_ARC_DEXCL_NORES ) ; Note: we cannot use a (clobber (match_scratch)) here because ; the combine pass will end up replacing uses of it with 0 @@ -1114,9 +1141,9 @@ ;; Note: loadqi_update has no 16-bit variant (define_insn "*loadqi_update" [(set (match_operand:QI 3 "dest_reg_operand" "=r,r") - (match_operator:QI 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")])) + (match_operator:QI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])) (set (match_operand:SI 0 "dest_reg_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1126,9 +1153,9 @@ (define_insn "*load_zeroextendqisi_update" [(set (match_operand:SI 3 "dest_reg_operand" "=r,r") - (zero_extend:SI (match_operator:QI 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")]))) + (zero_extend:SI (match_operator:QI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))) (set (match_operand:SI 0 "dest_reg_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1138,9 +1165,9 @@ (define_insn "*load_signextendqisi_update" [(set (match_operand:SI 3 "dest_reg_operand" "=r,r") - (sign_extend:SI (match_operator:QI 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")]))) + (sign_extend:SI (match_operator:QI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))) (set (match_operand:SI 0 "dest_reg_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1149,9 +1176,9 @@ (set_attr "length" "4,8")]) (define_insn "*storeqi_update" - [(set (match_operator:QI 4 "store_update_operand" - [(match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "short_immediate_operand" "I")]) + [(set (match_operator:QI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "short_immediate_operand" "I"))]) (match_operand:QI 3 "register_operand" "c")) (set (match_operand:SI 0 "dest_reg_operand" "=w") (plus:SI (match_dup 1) (match_dup 2)))] @@ -1164,9 +1191,9 @@ ;; Note: no 16-bit variant for this pattern (define_insn "*loadhi_update" [(set (match_operand:HI 3 "dest_reg_operand" "=r,r") - (match_operator:HI 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")])) + (match_operator:HI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])) (set (match_operand:SI 0 "dest_reg_operand" "=w,w") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1176,9 +1203,9 @@ (define_insn "*load_zeroextendhisi_update" [(set (match_operand:SI 3 "dest_reg_operand" "=r,r") - (zero_extend:SI (match_operator:HI 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")]))) + (zero_extend:SI (match_operator:HI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))) (set (match_operand:SI 0 "dest_reg_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1189,9 +1216,9 @@ ;; Note: no 16-bit variant for this instruction (define_insn "*load_signextendhisi_update" [(set (match_operand:SI 3 "dest_reg_operand" "=r,r") - (sign_extend:SI (match_operator:HI 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")]))) + (sign_extend:SI (match_operator:HI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))) (set (match_operand:SI 0 "dest_reg_operand" "=w,w") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1200,9 +1227,9 @@ (set_attr "length" "4,8")]) (define_insn "*storehi_update" - [(set (match_operator:HI 4 "store_update_operand" - [(match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "short_immediate_operand" "I")]) + [(set (match_operator:HI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "short_immediate_operand" "I"))]) (match_operand:HI 3 "register_operand" "c")) (set (match_operand:SI 0 "dest_reg_operand" "=w") (plus:SI (match_dup 1) (match_dup 2)))] @@ -1214,9 +1241,9 @@ ;; No 16-bit variant for this instruction pattern (define_insn "*loadsi_update" [(set (match_operand:SI 3 "dest_reg_operand" "=r,r") - (match_operator:SI 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")])) + (match_operator:SI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])) (set (match_operand:SI 0 "dest_reg_operand" "=w,w") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1225,9 +1252,9 @@ (set_attr "length" "4,8")]) (define_insn "*storesi_update" - [(set (match_operator:SI 4 "store_update_operand" - [(match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "short_immediate_operand" "I")]) + [(set (match_operator:SI 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "short_immediate_operand" "I"))]) (match_operand:SI 3 "register_operand" "c")) (set (match_operand:SI 0 "dest_reg_operand" "=w") (plus:SI (match_dup 1) (match_dup 2)))] @@ -1238,9 +1265,9 @@ (define_insn "*loadsf_update" [(set (match_operand:SF 3 "dest_reg_operand" "=r,r") - (match_operator:SF 4 "load_update_operand" - [(match_operand:SI 1 "register_operand" "0,0") - (match_operand:SI 2 "nonmemory_operand" "rI,Cal")])) + (match_operator:SF 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0,0") + (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])) (set (match_operand:SI 0 "dest_reg_operand" "=w,w") (plus:SI (match_dup 1) (match_dup 2)))] "" @@ -1249,9 +1276,9 @@ (set_attr "length" "4,8")]) (define_insn "*storesf_update" - [(set (match_operator:SF 4 "store_update_operand" - [(match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "short_immediate_operand" "I")]) + [(set (match_operator:SF 4 "any_mem_operand" + [(plus:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "short_immediate_operand" "I"))]) (match_operand:SF 3 "register_operand" "c")) (set (match_operand:SI 0 "dest_reg_operand" "=w") (plus:SI (match_dup 1) (match_dup 2)))] @@ -3646,7 +3673,7 @@ (pc))) (set (match_dup 6) (unspec:SI [(match_operand 3 "" "") - (match_dup 5) (match_dup 7)] UNSPEC_CASESI)) + (match_dup 5) (match_dup 7)] UNSPEC_ARC_CASESI)) (parallel [(set (pc) (match_dup 6)) (use (match_dup 7))])] "" " @@ -3684,7 +3711,7 @@ [(set (match_operand:SI 0 "register_operand" "=Rcq,r,r") (unspec:SI [(match_operand:SI 1 "nonmemory_operand" "Rcq,c,Cal") (match_operand:SI 2 "register_operand" "Rcq,c,c") - (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))] + (label_ref (match_operand 3 "" ""))] UNSPEC_ARC_CASESI))] "" "* { @@ -3749,7 +3776,7 @@ (define_insn "casesi_compact_jump" [(set (pc) (unspec:SI [(match_operand:SI 0 "register_operand" "c,q")] - UNSPEC_CASESI)) + UNSPEC_ARC_CASESI)) (use (label_ref (match_operand 1 "" ""))) (clobber (match_scratch:SI 2 "=q,0"))] "TARGET_COMPACT_CASESI" @@ -4000,7 +4027,7 @@ (set_attr "length" "2")]) (define_insn "nopv" - [(unspec_volatile [(const_int 0)] VUNSPEC_NOP)] + [(unspec_volatile [(const_int 0)] VUNSPEC_ARC_NOP)] "" "nop%?" [(set_attr "type" "misc") @@ -4245,7 +4272,7 @@ (define_insn "swap" [(set (match_operand:SI 0 "dest_reg_operand" "=w,w,w") (unspec:SI [(match_operand:SI 1 "general_operand" "L,Cal,c")] - UNSPEC_SWAP))] + UNSPEC_ARC_SWAP))] "TARGET_SWAP" "@ swap \t%0, %1 @@ -4254,41 +4281,11 @@ [(set_attr "length" "4,8,4") (set_attr "type" "two_cycle_core,two_cycle_core,two_cycle_core")]) -;; FIXME: an intrinsic for multiply is daft. Can we remove this? -(define_insn "mul64" - [(unspec [(match_operand:SI 0 "general_operand" "%q,r,r,r") - (match_operand:SI 1 "general_operand" "q,rL,I,Cal")] - UNSPEC_MUL64)] - "TARGET_MUL64_SET" - "@ - mul64%? \t0, %0, %1%& - mul64%? \t0, %0, %1 - mul64 \t0, %0, %1 - mul64%? \t0, %0, %S1" - [(set_attr "length" "2,4,4,8") - (set_attr "iscompact" "true,false,false,false") - (set_attr "type" "binary,binary,binary,binary") - (set_attr "cond" "canuse,canuse, nocond, canuse")]) - -(define_insn "mulu64" - [(unspec [(match_operand:SI 0 "general_operand" "%r,r,r,r") - (match_operand:SI 1 "general_operand" "rL,I,r,Cal")] - UNSPEC_MULU64)] - "TARGET_MUL64_SET" - "@ - mulu64%? \t0, %0, %1 - mulu64 \t0, %0, %1 - mulu64 \t0, %0, %1 - mulu64%? \t0, %0, %S1" - [(set_attr "length" "4,4,4,8") - (set_attr "type" "binary,binary,binary,binary") - (set_attr "cond" "canuse,nocond,nocond,canuse")]) - (define_insn "divaw" [(set (match_operand:SI 0 "dest_reg_operand" "=&w,&w,&w") (unspec:SI [(div:SI (match_operand:SI 1 "general_operand" "r,Cal,r") (match_operand:SI 2 "general_operand" "r,r,Cal"))] - UNSPEC_DIVAW))] + UNSPEC_ARC_DIVAW))] "TARGET_ARC700 || TARGET_EA_SET" "@ divaw \t%0, %1, %2 @@ -4299,7 +4296,7 @@ (define_insn "flag" [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "rL,I,Cal")] - VUNSPEC_FLAG)] + VUNSPEC_ARC_FLAG)] "" "@ flag%? %0 @@ -4312,7 +4309,7 @@ (define_insn "brk" [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "N")] - VUNSPEC_BRK)] + VUNSPEC_ARC_BRK)] "" "brk" [(set_attr "length" "4") @@ -4320,7 +4317,7 @@ (define_insn "rtie" [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "N")] - VUNSPEC_RTIE)] + VUNSPEC_ARC_RTIE)] "" "rtie" [(set_attr "length" "4") @@ -4329,7 +4326,7 @@ (define_insn "sync" [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "N")] - VUNSPEC_SYNC)] + VUNSPEC_ARC_SYNC)] "" "sync" [(set_attr "length" "4") @@ -4337,7 +4334,7 @@ (define_insn "swi" [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "N")] - VUNSPEC_SWI)] + VUNSPEC_ARC_SWI)] "" "* { @@ -4352,7 +4349,7 @@ (define_insn "sleep" [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "L")] - VUNSPEC_SLEEP)] + VUNSPEC_ARC_SLEEP)] "check_if_valid_sleep_operand(operands,0)" "sleep %0" [(set_attr "length" "4") @@ -4361,7 +4358,7 @@ (define_insn "core_read" [(set (match_operand:SI 0 "dest_reg_operand" "=r,r") (unspec_volatile:SI [(match_operand:SI 1 "general_operand" "Hn,!r")] - VUNSPEC_CORE_READ))] + VUNSPEC_ARC_CORE_READ))] "" "* if (check_if_valid_regno_const (operands, 1)) @@ -4374,7 +4371,7 @@ (define_insn "core_write" [(unspec_volatile [(match_operand:SI 0 "general_operand" "r,r") (match_operand:SI 1 "general_operand" "Hn,!r")] - VUNSPEC_CORE_WRITE)] + VUNSPEC_ARC_CORE_WRITE)] "" "* if (check_if_valid_regno_const (operands, 1)) @@ -4387,7 +4384,7 @@ (define_insn "lr" [(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r,r") (unspec_volatile:SI [(match_operand:SI 1 "general_operand" "I,HCal,r,D")] - VUNSPEC_LR))] + VUNSPEC_ARC_LR))] "" "lr\t%0, [%1]" [(set_attr "length" "4,8,4,8") @@ -4396,7 +4393,7 @@ (define_insn "sr" [(unspec_volatile [(match_operand:SI 0 "general_operand" "Cal,r,r,r") (match_operand:SI 1 "general_operand" "Ir,I,HCal,r")] - VUNSPEC_SR)] + VUNSPEC_ARC_SR)] "" "sr\t%S0, [%1]" [(set_attr "length" "8,4,8,4") @@ -4404,8 +4401,8 @@ (define_insn "trap_s" [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "L,Cal")] - VUNSPEC_TRAP_S)] - "TARGET_ARC700" + VUNSPEC_ARC_TRAP_S)] + "!TARGET_ARC600_FAMILY" { if (which_alternative == 0) { @@ -4423,8 +4420,8 @@ (define_insn "unimp_s" [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "N")] - VUNSPEC_UNIMP_S)] - "TARGET_ARC700" + VUNSPEC_ARC_UNIMP_S)] + "!TARGET_ARC600_FAMILY" "unimp_s" [(set_attr "length" "4") (set_attr "type" "misc")]) @@ -4867,7 +4864,7 @@ ; hoist the SETs. ;(define_insn "doloop_begin_i" ; [(set (reg:SI LP_START) (pc)) -; (set (reg:SI LP_END) (unspec:SI [(pc)] UNSPEC_LP)) +; (set (reg:SI LP_END) (unspec:SI [(pc)] UNSPEC_ARC_LP)) ; (use (match_operand 0 "const_int_operand" "n"))] ; "" ; "lp .L__GCC__LP%0" @@ -4881,7 +4878,7 @@ ; ; N in XVECEXP PATTERN (lp, 0 N) ; V rtl purpose -; 0 unspec UNSPEC_LP identify pattern +; 0 unspec UNSPEC_ARC_LP identify pattern ; 1 clobber LP_START show LP_START is set ; 2 clobber LP_END show LP_END is set ; 3 use operand0 loop count pseudo register @@ -4896,7 +4893,7 @@ ; There is no point is reloading this insn - then lp_count would still not ; be available for the loop end. (define_insn "doloop_begin_i" - [(unspec:SI [(pc)] UNSPEC_LP) + [(unspec:SI [(pc)] UNSPEC_ARC_LP) (clobber (reg:SI LP_START)) (clobber (reg:SI LP_END)) (use (match_operand:SI 0 "register_operand" "l,l,????*X")) @@ -5533,6 +5530,87 @@ (set_attr "predicable" "yes,no,no,yes,no") (set_attr "cond" "canuse,nocond,nocond,canuse,nocond")]) +(define_insn "kflag" + [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "rL,I,Cal")] + VUNSPEC_ARC_KFLAG)] + "TARGET_V2" + "@ + kflag%? %0 + kflag %0 + kflag%? %S0" + [(set_attr "length" "4,4,8") + (set_attr "type" "misc,misc,misc") + (set_attr "predicable" "yes,no,yes") + (set_attr "cond" "clob,clob,clob")]) + +(define_insn "clri" + [(set (match_operand:SI 0 "dest_reg_operand" "=r") + (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "N")] + VUNSPEC_ARC_CLRI))] + "TARGET_V2" + "clri %0" + [(set_attr "length" "4") + (set_attr "type" "misc")]) + +(define_insn "ffs" + [(set (match_operand:SI 0 "dest_reg_operand" "=w,w") + (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")] + UNSPEC_ARC_FFS))] + "TARGET_NORM && TARGET_V2" + "@ + ffs \t%0, %1 + ffs \t%0, %S1" + [(set_attr "length" "4,8") + (set_attr "type" "two_cycle_core,two_cycle_core")]) + +(define_insn "ffs_f" + [(set (match_operand:SI 0 "dest_reg_operand" "=w,w") + (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")] + UNSPEC_ARC_FFS)) + (set (reg:CC_ZN CC_REG) + (compare:CC_ZN (match_dup 1) (const_int 0)))] + "TARGET_NORM && TARGET_V2" + "@ + ffs.f\t%0, %1 + ffs.f\t%0, %S1" + [(set_attr "length" "4,8") + (set_attr "type" "two_cycle_core,two_cycle_core")]) + +(define_expand "ffssi2" + [(parallel [(set (match_dup 2) + (unspec:SI [(match_operand:SI 1 "register_operand" "")] + UNSPEC_ARC_FFS)) + (set (reg:CC_ZN CC_REG) + (compare:CC_ZN (match_dup 1) (const_int 0)))]) + (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1))) + (set (match_operand:SI 0 "dest_reg_operand" "") + (if_then_else:SI (eq:SI (reg:CC_ZN CC_REG) (const_int 0)) + (const_int 0) + (match_dup 2)))] + "TARGET_NORM && TARGET_V2" + { + operands[2] = gen_reg_rtx (SImode); + }) + +(define_insn "fls" + [(set (match_operand:SI 0 "dest_reg_operand" "=w,w") + (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")] + UNSPEC_ARC_FLS))] + "TARGET_NORM && TARGET_V2" + "@ + fls \t%0, %1 + fls \t%0, %S1" + [(set_attr "length" "4,8") + (set_attr "type" "two_cycle_core,two_cycle_core")]) + +(define_insn "seti" + [(unspec_volatile:SI [(match_operand:SI 0 "general_operand" "rL")] + VUNSPEC_ARC_SETI)] + "TARGET_V2" + "seti %0" + [(set_attr "length" "4") + (set_attr "type" "misc")]) + ;; include the arc-FPX instructions (include "fpx.md") diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt index 5b818357921..79113a5753f 100644 --- a/gcc/config/arc/arc.opt +++ b/gcc/config/arc/arc.opt @@ -1,6 +1,6 @@ ; Options for the Synopsys DesignWare ARC port of the compiler ; -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -59,11 +59,11 @@ Target RejectNegative Joined UInteger Var(arc_mpy_option) Init(2) mdiv-rem Target Report Mask(DIVREM) -Enable DIV-REM instructions for ARCv2 +Enable DIV-REM instructions for ARCv2. mcode-density Target Report Mask(CODE_DENSITY) -Enable code density instructions for ARCv2 +Enable code density instructions for ARCv2. mmixed-code Target Report Mask(MIXED_CODE_SET) diff --git a/gcc/config/arc/arc600.md b/gcc/config/arc/arc600.md index e1a5b60c506..aee1ca341f7 100644 --- a/gcc/config/arc/arc600.md +++ b/gcc/config/arc/arc600.md @@ -1,6 +1,6 @@ ;; DFA scheduling description of the Synopsys DesignWare ARC600 cpu ;; for GNU C compiler -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; Contributor: Joern Rennecke <joern.rennecke@embecosm.com> ;; on behalf of Synopsys Inc. diff --git a/gcc/config/arc/arc700.md b/gcc/config/arc/arc700.md index 88ea4f3aca4..4d9bddfdb35 100644 --- a/gcc/config/arc/arc700.md +++ b/gcc/config/arc/arc700.md @@ -5,7 +5,7 @@ ;; Ramana Radhakrishnan(ramana.radhakrishnan@codito.com) ;; Factoring out and improvement of ARC700 Scheduling by ;; Joern Rennecke (joern.rennecke@embecosm.com) -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/arc/arcEM.md b/gcc/config/arc/arcEM.md index a72d2504e52..198660db568 100644 --- a/gcc/config/arc/arcEM.md +++ b/gcc/config/arc/arcEM.md @@ -1,6 +1,6 @@ ;; DFA scheduling description of the Synopsys DesignWare ARC EM cpu ;; for GNU C compiler -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; Contributor: Claudiu Zissulescu <claudiu.zissulescu@synopsys.com> ;; This file is part of GCC. diff --git a/gcc/config/arc/arcHS.md b/gcc/config/arc/arcHS.md index 06937445a47..067e8ca342d 100644 --- a/gcc/config/arc/arcHS.md +++ b/gcc/config/arc/arcHS.md @@ -1,6 +1,6 @@ ;; DFA scheduling description of the Synopsys DesignWare ARC HS cpu ;; for GNU C compiler -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; Contributor: Claudiu Zissulescu <claudiu.zissulescu@synopsys.com> ;; This file is part of GCC. diff --git a/gcc/config/arc/atomic.md b/gcc/config/arc/atomic.md index 665cab5ca0f..9dc1cd5c57c 100644 --- a/gcc/config/arc/atomic.md +++ b/gcc/config/arc/atomic.md @@ -1,5 +1,5 @@ ;; GCC machine description for ARC atomic instructions. -;; Copyright (C) 2015 Free Software Foundation, Inc. +;; Copyright (C) 2015-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arc/builtins.def b/gcc/config/arc/builtins.def new file mode 100644 index 00000000000..19be1d21852 --- /dev/null +++ b/gcc/config/arc/builtins.def @@ -0,0 +1,195 @@ +/* Copyright (C) 2015-2016 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 3, or (at your option) any later + version. + + GCC is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + <http://www.gnu.org/licenses/>. */ + +/* This file contains the definitions and documentation for the + builtins defined in the ARC part of the GNU compiler. Before + including this file, define a macro + + DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, MASK) + + NAME: `__builtin_arc_name' will be the user-level name of the builtin. + `ARC_BUILTIN_NAME' will be the internal builtin's id. + N_ARGS: Number of input arguments. If special treatment is needed, + set to -1 and handle it by hand, see arc.c:arc_expand_builtin(). + TYPE: A tree node describing the prototype of the built-in. + ICODE: Name of attached insn or expander. If special treatment in arc.c + is needed to expand the built-in, use `nothing'. + MASK: CPU selector mask. */ + +/* Special builtins. */ +DEF_BUILTIN (NOP, 0, void_ftype_void, nothing, 1) +DEF_BUILTIN (RTIE, 0, void_ftype_void, rtie, 1) +DEF_BUILTIN (SYNC, 0, void_ftype_void, sync, TARGET_ARC700) +DEF_BUILTIN (BRK, 0, void_ftype_void, brk, 1) +DEF_BUILTIN (SWI, 0, void_ftype_void, swi, 1) +DEF_BUILTIN (UNIMP_S, 0, void_ftype_void, unimp_s, !TARGET_ARC600_FAMILY) +DEF_BUILTIN (TRAP_S, 1, void_ftype_usint, trap_s, !TARGET_ARC600_FAMILY) +DEF_BUILTIN (ALIGNED, 2, int_ftype_pcvoid_int, nothing, 1) +DEF_BUILTIN (CLRI, 0, int_ftype_void, clri, TARGET_V2) +DEF_BUILTIN (SLEEP, 1, void_ftype_usint, sleep, 1) + +DEF_BUILTIN (FLAG, 1, void_ftype_usint, flag, 1) +DEF_BUILTIN (SR, 2, void_ftype_usint_usint, sr, 1) +DEF_BUILTIN (KFLAG, 1, void_ftype_usint, kflag, TARGET_V2) +DEF_BUILTIN (CORE_WRITE, 2, void_ftype_usint_usint, core_write, 1) +DEF_BUILTIN (SETI, 1, void_ftype_int, seti, TARGET_V2) + +/* Regular builtins. */ +DEF_BUILTIN (NORM, 1, int_ftype_int, clrsbsi2, TARGET_NORM) +DEF_BUILTIN (NORMW, 1, int_ftype_short, normw, TARGET_NORM) +DEF_BUILTIN (SWAP, 1, int_ftype_int, swap, TARGET_SWAP) +DEF_BUILTIN (DIVAW, 2, int_ftype_int_int, divaw, TARGET_EA_SET) +DEF_BUILTIN (CORE_READ, 1, usint_ftype_usint, core_read, 1) +DEF_BUILTIN (LR, 1, usint_ftype_usint, lr, 1) +DEF_BUILTIN (FFS, 1, int_ftype_int, ffs, (TARGET_EM && TARGET_NORM) || TARGET_HS) +DEF_BUILTIN (FLS, 1, int_ftype_int, fls, (TARGET_EM && TARGET_NORM) || TARGET_HS) + +/* ARC SIMD extenssion. */ +/* BEGIN SIMD marker. */ +DEF_BUILTIN (SIMD_BEGIN, 0, void_ftype_void, nothing, 0) + +DEF_BUILTIN ( VADDAW, 2, v8hi_ftype_v8hi_v8hi, vaddaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VADDW, 2, v8hi_ftype_v8hi_v8hi, vaddw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VAVB, 2, v8hi_ftype_v8hi_v8hi, vavb_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VAVRB, 2, v8hi_ftype_v8hi_v8hi, vavrb_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VDIFAW, 2, v8hi_ftype_v8hi_v8hi, vdifaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VDIFW, 2, v8hi_ftype_v8hi_v8hi, vdifw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMAXAW, 2, v8hi_ftype_v8hi_v8hi, vmaxaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMAXW, 2, v8hi_ftype_v8hi_v8hi, vmaxw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMINAW, 2, v8hi_ftype_v8hi_v8hi, vminaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMINW, 2, v8hi_ftype_v8hi_v8hi, vminw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMULAW, 2, v8hi_ftype_v8hi_v8hi, vmulaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VMULFAW, 2, v8hi_ftype_v8hi_v8hi, vmulfaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMULFW, 2, v8hi_ftype_v8hi_v8hi, vmulfw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMULW, 2, v8hi_ftype_v8hi_v8hi, vmulw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VSUBAW, 2, v8hi_ftype_v8hi_v8hi, vsubaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VSUBW, 2, v8hi_ftype_v8hi_v8hi, vsubw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VSUMMW, 2, v8hi_ftype_v8hi_v8hi, vsummw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VAND, 2, v8hi_ftype_v8hi_v8hi, vand_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VANDAW, 2, v8hi_ftype_v8hi_v8hi, vandaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VBIC, 2, v8hi_ftype_v8hi_v8hi, vbic_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VBICAW, 2, v8hi_ftype_v8hi_v8hi, vbicaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VOR, 2, v8hi_ftype_v8hi_v8hi, vor_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VXOR, 2, v8hi_ftype_v8hi_v8hi, vxor_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VXORAW, 2, v8hi_ftype_v8hi_v8hi, vxoraw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VEQW, 2, v8hi_ftype_v8hi_v8hi, veqw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VLEW, 2, v8hi_ftype_v8hi_v8hi, vlew_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VLTW, 2, v8hi_ftype_v8hi_v8hi, vltw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VNEW, 2, v8hi_ftype_v8hi_v8hi, vnew_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMR1AW, 2, v8hi_ftype_v8hi_v8hi, vmr1aw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMR1W, 2, v8hi_ftype_v8hi_v8hi, vmr1w_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMR2AW, 2, v8hi_ftype_v8hi_v8hi, vmr2aw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMR2W, 2, v8hi_ftype_v8hi_v8hi, vmr2w_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMR3AW, 2, v8hi_ftype_v8hi_v8hi, vmr3aw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMR3W, 2, v8hi_ftype_v8hi_v8hi, vmr3w_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMR4AW, 2, v8hi_ftype_v8hi_v8hi, vmr4aw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMR4W, 2, v8hi_ftype_v8hi_v8hi, vmr4w_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMR5AW, 2, v8hi_ftype_v8hi_v8hi, vmr5aw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMR5W, 2, v8hi_ftype_v8hi_v8hi, vmr5w_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMR6AW, 2, v8hi_ftype_v8hi_v8hi, vmr6aw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMR6W, 2, v8hi_ftype_v8hi_v8hi, vmr6w_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMR7AW, 2, v8hi_ftype_v8hi_v8hi, vmr7aw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMR7W, 2, v8hi_ftype_v8hi_v8hi, vmr7w_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMRB, 2, v8hi_ftype_v8hi_v8hi, vmrb_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VH264F, 2, v8hi_ftype_v8hi_v8hi, vh264f_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VH264FT, 2, v8hi_ftype_v8hi_v8hi, vh264ft_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VH264FW, 2, v8hi_ftype_v8hi_v8hi, vh264fw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VVC1F, 2, v8hi_ftype_v8hi_v8hi, vvc1f_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VVC1FT, 2, v8hi_ftype_v8hi_v8hi, vvc1ft_insn, TARGET_SIMD_SET) + +DEF_BUILTIN ( VBADDW, 2, v8hi_ftype_v8hi_int, vbaddw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VBMAXW, 2, v8hi_ftype_v8hi_int, vbmaxw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VBMINW, 2, v8hi_ftype_v8hi_int, vbminw_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VBMULAW, 2, v8hi_ftype_v8hi_int, vbmulaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VBMULFW, 2, v8hi_ftype_v8hi_int, vbmulfw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VBMULW, 2, v8hi_ftype_v8hi_int, vbmulw_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VBRSUBW, 2, v8hi_ftype_v8hi_int, vbrsubw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VBSUBW, 2, v8hi_ftype_v8hi_int, vbsubw_insn, TARGET_SIMD_SET) + +/* Va, Vb, Ic instructions. */ +DEF_BUILTIN ( VASRW, 2, v8hi_ftype_v8hi_int, vasrw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VSR8, 2, v8hi_ftype_v8hi_int, vsr8_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VSR8AW, 2, v8hi_ftype_v8hi_int, vsr8aw_insn, TARGET_SIMD_SET) + +/* Va, Vb, u6 instructions. */ +DEF_BUILTIN ( VASRRWi, 2, v8hi_ftype_v8hi_int, vasrrwi_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VASRSRWi, 2, v8hi_ftype_v8hi_int, vasrsrwi_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VASRWi, 2, v8hi_ftype_v8hi_int, vasrwi_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VASRPWBi, 2, v8hi_ftype_v8hi_int, vasrpwbi_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VASRRPWBi, 2, v8hi_ftype_v8hi_int, vasrrpwbi_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VSR8AWi, 2, v8hi_ftype_v8hi_int, vsr8awi_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VSR8i, 2, v8hi_ftype_v8hi_int, vsr8i_insn, TARGET_SIMD_SET) + +/* Va, Vb, u8 (simm) instructions. */ +DEF_BUILTIN ( VMVAW, 2, v8hi_ftype_v8hi_int, vmvaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMVW, 2, v8hi_ftype_v8hi_int, vmvw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMVZW, 2, v8hi_ftype_v8hi_int, vmvzw_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VD6TAPF, 2, v8hi_ftype_v8hi_int, vd6tapf_insn, TARGET_SIMD_SET) + +/* Va, rlimm, u8 (simm) instructions. */ +DEF_BUILTIN (VMOVAW, 2, v8hi_ftype_int_int, vmovaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VMOVW, 2, v8hi_ftype_int_int, vmovw_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VMOVZW, 2, v8hi_ftype_int_int, vmovzw_insn, TARGET_SIMD_SET) + +/* Va, Vb instructions. */ +DEF_BUILTIN ( VABSAW, 1, v8hi_ftype_v8hi, vabsaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VABSW, 1, v8hi_ftype_v8hi, vabsw_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VADDSUW, 1, v8hi_ftype_v8hi, vaddsuw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VSIGNW, 1, v8hi_ftype_v8hi, vsignw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VEXCH1, 1, v8hi_ftype_v8hi, vexch1_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VEXCH2, 1, v8hi_ftype_v8hi, vexch2_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VEXCH4, 1, v8hi_ftype_v8hi, vexch4_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VUPBAW, 1, v8hi_ftype_v8hi, vupbaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VUPBW, 1, v8hi_ftype_v8hi, vupbw_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VUPSBAW, 1, v8hi_ftype_v8hi, vupsbaw_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VUPSBW, 1, v8hi_ftype_v8hi, vupsbw_insn, TARGET_SIMD_SET) + +/* SIMD special DIb, rlimm, rlimm instructions. */ +DEF_BUILTIN (VDIRUN, 2, void_ftype_int_int, vdirun_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VDORUN, 2, void_ftype_int_int, vdorun_insn, TARGET_SIMD_SET) + +/* SIMD special DIb, limm, rlimm instructions. */ +DEF_BUILTIN (VDIWR, 2, void_ftype_int_int, vdiwr_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VDOWR, 2, void_ftype_int_int, vdowr_insn, TARGET_SIMD_SET) + +/* rlimm instructions. */ +DEF_BUILTIN ( VREC, 1, void_ftype_int, vrec_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VRUN, 1, void_ftype_int, vrun_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VRECRUN, 1, void_ftype_int, vrecrun_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VENDREC, 1, void_ftype_int, vendrec_insn, TARGET_SIMD_SET) + +/* Va, [Ib,u8] instructions. */ +DEF_BUILTIN (VLD32WH, 3, v8hi_ftype_v8hi_int_int, vld32wh_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VLD32WL, 3, v8hi_ftype_v8hi_int_int, vld32wl_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VLD64, 3, v8hi_ftype_v8hi_int_int, vld64_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VLD32, 3, v8hi_ftype_v8hi_int_int, vld32_insn, TARGET_SIMD_SET) + +DEF_BUILTIN (VLD64W, 2, v8hi_ftype_int_int, vld64w_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VLD128, 2, v8hi_ftype_int_int, vld128_insn, TARGET_SIMD_SET) + +DEF_BUILTIN (VST128, 3, void_ftype_v8hi_int_int, vst128_insn, TARGET_SIMD_SET) +DEF_BUILTIN ( VST64, 3, void_ftype_v8hi_int_int, vst64_insn, TARGET_SIMD_SET) + +/* Va, [Ib, u8] instructions. */ +DEF_BUILTIN (VST16_N, 4, void_ftype_v8hi_int_int_int, vst16_n_insn, TARGET_SIMD_SET) +DEF_BUILTIN (VST32_N, 4, void_ftype_v8hi_int_int_int, vst32_n_insn, TARGET_SIMD_SET) + +DEF_BUILTIN (VINTI, 1, void_ftype_int, vinti_insn, TARGET_SIMD_SET) + +/* END SIMD marker. */ +DEF_BUILTIN (SIMD_END, 0, void_ftype_void, nothing, 0) diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md index 18309cc8073..668b60a6b3a 100644 --- a/gcc/config/arc/constraints.md +++ b/gcc/config/arc/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Synopsys DesignWare ARC. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arc/fpx.md b/gcc/config/arc/fpx.md index 231b809c4ce..a4ecc4a9bf2 100644 --- a/gcc/config/arc/fpx.md +++ b/gcc/config/arc/fpx.md @@ -1,6 +1,6 @@ ;; Machine description of the Synopsys DesignWare ARC cpu Floating Point ;; extensions for GNU C compiler -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; This file is part of GCC. @@ -151,7 +151,7 @@ ;; op0_reg = D1_reg.low (define_insn "*lr_double_lower" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")] VUNSPEC_LR ))] + (unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")] VUNSPEC_ARC_LR ))] "TARGET_DPFP && !TARGET_DPFP_DISABLE_LRSR" "lr %0, [%1l] ; *lr_double_lower" [(set_attr "length" "8") @@ -160,7 +160,8 @@ (define_insn "*lr_double_higher" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")] VUNSPEC_LR_HIGH ))] + (unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")] + VUNSPEC_ARC_LR_HIGH ))] "TARGET_DPFP && !TARGET_DPFP_DISABLE_LRSR" "lr %0, [%1h] ; *lr_double_higher" [(set_attr "length" "8") @@ -174,7 +175,7 @@ (match_operand:DF 1 "arc_double_register_operand" "D") (match_operand:SI 2 "shouldbe_register_operand" "r") ; r1 (match_operand:SI 3 "shouldbe_register_operand" "r") ; r0 - ] VUNSPEC_DEXCL )) + ] VUNSPEC_ARC_DEXCL )) ] "TARGET_DPFP" "dexcl%F1 %0, %2, %3" @@ -188,7 +189,7 @@ (match_operand:DF 0 "arc_double_register_operand" "D") (match_operand:SI 1 "shouldbe_register_operand" "r") ; r1 (match_operand:SI 2 "shouldbe_register_operand" "r") ; r0 - ] VUNSPEC_DEXCL_NORES ) + ] VUNSPEC_ARC_DEXCL_NORES ) ] "TARGET_DPFP" "dexcl%F0 0, %1, %2" @@ -199,7 +200,7 @@ ;; dexcl a,b,c pattern generated by the peephole2 above (define_insn "*dexcl_3op_peep2_insn_lr" [(parallel [(set (match_operand:SI 0 "register_operand" "=r") - (unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "=D")] VUNSPEC_LR )) + (unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "=D")] VUNSPEC_ARC_LR )) (set (match_dup 1) (match_operand:DF 2 "register_operand" "r"))] ) ] @@ -413,7 +414,7 @@ ;; (parallel [ ;; ;; (set (subreg:SI (match_dup 5) 0) ;; (set (match_dup 7) -;; (unspec_volatile [(match_dup 0)] VUNSPEC_LR )) +;; (unspec_volatile [(match_dup 0)] VUNSPEC_ARC_LR )) ;; (set (match_dup 0) (match_dup 6))] ;; ) ;; ] @@ -472,7 +473,7 @@ (parallel [ ;; (set (subreg:SI (match_dup 7) 0) (set (match_dup 9) - (unspec_volatile:SI [(match_dup 0)] VUNSPEC_LR )) + (unspec_volatile:SI [(match_dup 0)] VUNSPEC_ARC_LR )) (set (match_dup 0) (match_dup 8))] ) ] @@ -522,7 +523,7 @@ ;; (match_dup 3)]))]) ;; ; (set (subreg:SI (match_dup 5) 0) ;; (set (match_dup 6) -;; (unspec_volatile [(match_dup 0)] VUNSPEC_LR )) +;; (unspec_volatile [(match_dup 0)] VUNSPEC_ARC_LR )) ;; ] ;; "operands[6] = simplify_gen_subreg(SImode,operands[5],DFmode,0);" ;; ) @@ -572,7 +573,7 @@ (match_dup 3)]))]) ; (set (subreg:SI (match_dup 7) 0) (set (match_dup 8) - (unspec_volatile:SI [(match_dup 0)] VUNSPEC_LR )) + (unspec_volatile:SI [(match_dup 0)] VUNSPEC_ARC_LR )) ] "operands[8] = simplify_gen_subreg(SImode,operands[7],DFmode,0);" ) diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md index de0735a4071..fba878bb452 100644 --- a/gcc/config/arc/predicates.md +++ b/gcc/config/arc/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Synopsys DesignWare ARC. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -460,42 +460,6 @@ } ) -;; Return true if OP is valid load with update operand. -(define_predicate "load_update_operand" - (match_code "mem") -{ - if (GET_CODE (op) != MEM - || GET_MODE (op) != mode) - return 0; - op = XEXP (op, 0); - if (GET_CODE (op) != PLUS - || GET_MODE (op) != Pmode - || !register_operand (XEXP (op, 0), Pmode) - || !nonmemory_operand (XEXP (op, 1), Pmode)) - return 0; - return 1; - -} -) - -;; Return true if OP is valid store with update operand. -(define_predicate "store_update_operand" - (match_code "mem") -{ - if (GET_CODE (op) != MEM - || GET_MODE (op) != mode) - return 0; - op = XEXP (op, 0); - if (GET_CODE (op) != PLUS - || GET_MODE (op) != Pmode - || !register_operand (XEXP (op, 0), Pmode) - || !(GET_CODE (XEXP (op, 1)) == CONST_INT - && SMALL_INT (INTVAL (XEXP (op, 1))))) - return 0; - return 1; -} -) - ;; Return true if OP is a non-volatile non-immediate operand. ;; Volatile memory refs require a special "cache-bypass" instruction ;; and only the standard movXX patterns are set up to handle them. @@ -817,3 +781,6 @@ (define_predicate "mem_noofs_operand" (and (match_code "mem") (match_code "reg" "0"))) + +(define_predicate "any_mem_operand" + (match_code "mem"))
\ No newline at end of file diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md index 15b51822b18..9fd9d62e048 100644 --- a/gcc/config/arc/simdext.md +++ b/gcc/config/arc/simdext.md @@ -1,5 +1,5 @@ ;; Machine description of the Synopsys DesignWare ARC cpu for GNU C compiler -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; This file is part of GCC. @@ -17,119 +17,117 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. -(define_constants - [ +(define_c_enum "unspec" [ ;; Va, Vb, Vc builtins - (UNSPEC_ARC_SIMD_VADDAW 1000) - (UNSPEC_ARC_SIMD_VADDW 1001) - (UNSPEC_ARC_SIMD_VAVB 1002) - (UNSPEC_ARC_SIMD_VAVRB 1003) - (UNSPEC_ARC_SIMD_VDIFAW 1004) - (UNSPEC_ARC_SIMD_VDIFW 1005) - (UNSPEC_ARC_SIMD_VMAXAW 1006) - (UNSPEC_ARC_SIMD_VMAXW 1007) - (UNSPEC_ARC_SIMD_VMINAW 1008) - (UNSPEC_ARC_SIMD_VMINW 1009) - (UNSPEC_ARC_SIMD_VMULAW 1010) - (UNSPEC_ARC_SIMD_VMULFAW 1011) - (UNSPEC_ARC_SIMD_VMULFW 1012) - (UNSPEC_ARC_SIMD_VMULW 1013) - (UNSPEC_ARC_SIMD_VSUBAW 1014) - (UNSPEC_ARC_SIMD_VSUBW 1015) - (UNSPEC_ARC_SIMD_VSUMMW 1016) - (UNSPEC_ARC_SIMD_VAND 1017) - (UNSPEC_ARC_SIMD_VANDAW 1018) - (UNSPEC_ARC_SIMD_VBIC 1019) - (UNSPEC_ARC_SIMD_VBICAW 1020) - (UNSPEC_ARC_SIMD_VOR 1021) - (UNSPEC_ARC_SIMD_VXOR 1022) - (UNSPEC_ARC_SIMD_VXORAW 1023) - (UNSPEC_ARC_SIMD_VEQW 1024) - (UNSPEC_ARC_SIMD_VLEW 1025) - (UNSPEC_ARC_SIMD_VLTW 1026) - (UNSPEC_ARC_SIMD_VNEW 1027) - (UNSPEC_ARC_SIMD_VMR1AW 1028) - (UNSPEC_ARC_SIMD_VMR1W 1029) - (UNSPEC_ARC_SIMD_VMR2AW 1030) - (UNSPEC_ARC_SIMD_VMR2W 1031) - (UNSPEC_ARC_SIMD_VMR3AW 1032) - (UNSPEC_ARC_SIMD_VMR3W 1033) - (UNSPEC_ARC_SIMD_VMR4AW 1034) - (UNSPEC_ARC_SIMD_VMR4W 1035) - (UNSPEC_ARC_SIMD_VMR5AW 1036) - (UNSPEC_ARC_SIMD_VMR5W 1037) - (UNSPEC_ARC_SIMD_VMR6AW 1038) - (UNSPEC_ARC_SIMD_VMR6W 1039) - (UNSPEC_ARC_SIMD_VMR7AW 1040) - (UNSPEC_ARC_SIMD_VMR7W 1041) - (UNSPEC_ARC_SIMD_VMRB 1042) - (UNSPEC_ARC_SIMD_VH264F 1043) - (UNSPEC_ARC_SIMD_VH264FT 1044) - (UNSPEC_ARC_SIMD_VH264FW 1045) - (UNSPEC_ARC_SIMD_VVC1F 1046) - (UNSPEC_ARC_SIMD_VVC1FT 1047) + UNSPEC_ARC_SIMD_VADDAW + UNSPEC_ARC_SIMD_VADDW + UNSPEC_ARC_SIMD_VAVB + UNSPEC_ARC_SIMD_VAVRB + UNSPEC_ARC_SIMD_VDIFAW + UNSPEC_ARC_SIMD_VDIFW + UNSPEC_ARC_SIMD_VMAXAW + UNSPEC_ARC_SIMD_VMAXW + UNSPEC_ARC_SIMD_VMINAW + UNSPEC_ARC_SIMD_VMINW + UNSPEC_ARC_SIMD_VMULAW + UNSPEC_ARC_SIMD_VMULFAW + UNSPEC_ARC_SIMD_VMULFW + UNSPEC_ARC_SIMD_VMULW + UNSPEC_ARC_SIMD_VSUBAW + UNSPEC_ARC_SIMD_VSUBW + UNSPEC_ARC_SIMD_VSUMMW + UNSPEC_ARC_SIMD_VAND + UNSPEC_ARC_SIMD_VANDAW + UNSPEC_ARC_SIMD_VBIC + UNSPEC_ARC_SIMD_VBICAW + UNSPEC_ARC_SIMD_VOR + UNSPEC_ARC_SIMD_VXOR + UNSPEC_ARC_SIMD_VXORAW + UNSPEC_ARC_SIMD_VEQW + UNSPEC_ARC_SIMD_VLEW + UNSPEC_ARC_SIMD_VLTW + UNSPEC_ARC_SIMD_VNEW + UNSPEC_ARC_SIMD_VMR1AW + UNSPEC_ARC_SIMD_VMR1W + UNSPEC_ARC_SIMD_VMR2AW + UNSPEC_ARC_SIMD_VMR2W + UNSPEC_ARC_SIMD_VMR3AW + UNSPEC_ARC_SIMD_VMR3W + UNSPEC_ARC_SIMD_VMR4AW + UNSPEC_ARC_SIMD_VMR4W + UNSPEC_ARC_SIMD_VMR5AW + UNSPEC_ARC_SIMD_VMR5W + UNSPEC_ARC_SIMD_VMR6AW + UNSPEC_ARC_SIMD_VMR6W + UNSPEC_ARC_SIMD_VMR7AW + UNSPEC_ARC_SIMD_VMR7W + UNSPEC_ARC_SIMD_VMRB + UNSPEC_ARC_SIMD_VH264F + UNSPEC_ARC_SIMD_VH264FT + UNSPEC_ARC_SIMD_VH264FW + UNSPEC_ARC_SIMD_VVC1F + UNSPEC_ARC_SIMD_VVC1FT ;; Va, Vb, rc/limm builtins - (UNSPEC_ARC_SIMD_VBADDW 1050) - (UNSPEC_ARC_SIMD_VBMAXW 1051) - (UNSPEC_ARC_SIMD_VBMINW 1052) - (UNSPEC_ARC_SIMD_VBMULAW 1053) - (UNSPEC_ARC_SIMD_VBMULFW 1054) - (UNSPEC_ARC_SIMD_VBMULW 1055) - (UNSPEC_ARC_SIMD_VBRSUBW 1056) - (UNSPEC_ARC_SIMD_VBSUBW 1057) + UNSPEC_ARC_SIMD_VBADDW + UNSPEC_ARC_SIMD_VBMAXW + UNSPEC_ARC_SIMD_VBMINW + UNSPEC_ARC_SIMD_VBMULAW + UNSPEC_ARC_SIMD_VBMULFW + UNSPEC_ARC_SIMD_VBMULW + UNSPEC_ARC_SIMD_VBRSUBW + UNSPEC_ARC_SIMD_VBSUBW ;; Va, Vb, Ic builtins - (UNSPEC_ARC_SIMD_VASRW 1060) - (UNSPEC_ARC_SIMD_VSR8 1061) - (UNSPEC_ARC_SIMD_VSR8AW 1062) + UNSPEC_ARC_SIMD_VASRW + UNSPEC_ARC_SIMD_VSR8 + UNSPEC_ARC_SIMD_VSR8AW ;; Va, Vb, Ic builtins - (UNSPEC_ARC_SIMD_VASRRWi 1065) - (UNSPEC_ARC_SIMD_VASRSRWi 1066) - (UNSPEC_ARC_SIMD_VASRWi 1067) - (UNSPEC_ARC_SIMD_VASRPWBi 1068) - (UNSPEC_ARC_SIMD_VASRRPWBi 1069) - (UNSPEC_ARC_SIMD_VSR8AWi 1070) - (UNSPEC_ARC_SIMD_VSR8i 1071) + UNSPEC_ARC_SIMD_VASRRWi + UNSPEC_ARC_SIMD_VASRSRWi + UNSPEC_ARC_SIMD_VASRWi + UNSPEC_ARC_SIMD_VASRPWBi + UNSPEC_ARC_SIMD_VASRRPWBi + UNSPEC_ARC_SIMD_VSR8AWi + UNSPEC_ARC_SIMD_VSR8i ;; Va, Vb, u8 (simm) builtins - (UNSPEC_ARC_SIMD_VMVAW 1075) - (UNSPEC_ARC_SIMD_VMVW 1076) - (UNSPEC_ARC_SIMD_VMVZW 1077) - (UNSPEC_ARC_SIMD_VD6TAPF 1078) + UNSPEC_ARC_SIMD_VMVAW + UNSPEC_ARC_SIMD_VMVW + UNSPEC_ARC_SIMD_VMVZW + UNSPEC_ARC_SIMD_VD6TAPF ;; Va, rlimm, u8 (simm) builtins - (UNSPEC_ARC_SIMD_VMOVAW 1080) - (UNSPEC_ARC_SIMD_VMOVW 1081) - (UNSPEC_ARC_SIMD_VMOVZW 1082) + UNSPEC_ARC_SIMD_VMOVAW + UNSPEC_ARC_SIMD_VMOVW + UNSPEC_ARC_SIMD_VMOVZW ;; Va, Vb builtins - (UNSPEC_ARC_SIMD_VABSAW 1085) - (UNSPEC_ARC_SIMD_VABSW 1086) - (UNSPEC_ARC_SIMD_VADDSUW 1087) - (UNSPEC_ARC_SIMD_VSIGNW 1088) - (UNSPEC_ARC_SIMD_VEXCH1 1089) - (UNSPEC_ARC_SIMD_VEXCH2 1090) - (UNSPEC_ARC_SIMD_VEXCH4 1091) - (UNSPEC_ARC_SIMD_VUPBAW 1092) - (UNSPEC_ARC_SIMD_VUPBW 1093) - (UNSPEC_ARC_SIMD_VUPSBAW 1094) - (UNSPEC_ARC_SIMD_VUPSBW 1095) - - (UNSPEC_ARC_SIMD_VDIRUN 1100) - (UNSPEC_ARC_SIMD_VDORUN 1101) - (UNSPEC_ARC_SIMD_VDIWR 1102) - (UNSPEC_ARC_SIMD_VDOWR 1103) - - (UNSPEC_ARC_SIMD_VREC 1105) - (UNSPEC_ARC_SIMD_VRUN 1106) - (UNSPEC_ARC_SIMD_VRECRUN 1107) - (UNSPEC_ARC_SIMD_VENDREC 1108) - - (UNSPEC_ARC_SIMD_VCAST 1200) - (UNSPEC_ARC_SIMD_VINTI 1201) - ] -) + UNSPEC_ARC_SIMD_VABSAW + UNSPEC_ARC_SIMD_VABSW + UNSPEC_ARC_SIMD_VADDSUW + UNSPEC_ARC_SIMD_VSIGNW + UNSPEC_ARC_SIMD_VEXCH1 + UNSPEC_ARC_SIMD_VEXCH2 + UNSPEC_ARC_SIMD_VEXCH4 + UNSPEC_ARC_SIMD_VUPBAW + UNSPEC_ARC_SIMD_VUPBW + UNSPEC_ARC_SIMD_VUPSBAW + UNSPEC_ARC_SIMD_VUPSBW + + UNSPEC_ARC_SIMD_VDIRUN + UNSPEC_ARC_SIMD_VDORUN + UNSPEC_ARC_SIMD_VDIWR + UNSPEC_ARC_SIMD_VDOWR + + UNSPEC_ARC_SIMD_VREC + UNSPEC_ARC_SIMD_VRUN + UNSPEC_ARC_SIMD_VRECRUN + UNSPEC_ARC_SIMD_VENDREC + + UNSPEC_ARC_SIMD_VCAST + UNSPEC_ARC_SIMD_VINTI + ]) ;; Scheduler descriptions for the simd instructions (define_insn_reservation "simd_lat_0_insn" 1 @@ -138,19 +136,19 @@ (define_insn_reservation "simd_lat_1_insn" 2 (eq_attr "type" "simd_vcompare, simd_vlogic, - simd_vmove_else_zero, simd_varith_1cycle") + simd_vmove_else_zero, simd_varith_1cycle") "issue+simd_unit, nothing") (define_insn_reservation "simd_lat_2_insn" 3 (eq_attr "type" "simd_valign, simd_vpermute, - simd_vpack, simd_varith_2cycle") + simd_vpack, simd_varith_2cycle") "issue+simd_unit, nothing*2") (define_insn_reservation "simd_lat_3_insn" 4 (eq_attr "type" "simd_valign_with_acc, simd_vpack_with_acc, - simd_vlogic_with_acc, simd_vload128, - simd_vmove_with_acc, simd_vspecial_3cycle, - simd_varith_with_acc") + simd_vlogic_with_acc, simd_vload128, + simd_vmove_with_acc, simd_vspecial_3cycle, + simd_varith_with_acc") "issue+simd_unit, nothing*3") (define_insn_reservation "simd_lat_4_insn" 5 @@ -917,7 +915,7 @@ (define_insn "vmvaw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") + (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVAW))] "TARGET_SIMD_SET" "vmvaw %0, %1, %2" @@ -927,7 +925,7 @@ (define_insn "vmvw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") + (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVW))] "TARGET_SIMD_SET" "vmvw %0, %1, %2" @@ -937,7 +935,7 @@ (define_insn "vmvzw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") + (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVZW))] "TARGET_SIMD_SET" "vmvzw %0, %1, %2" @@ -947,7 +945,7 @@ (define_insn "vd6tapf_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") + (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v") (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VD6TAPF))] "TARGET_SIMD_SET" "vd6tapf %0, %1, %2" @@ -958,7 +956,7 @@ ;; Va, rlimm, u8 (simm) insns (define_insn "vmovaw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") - (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r") + (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r") (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVAW))] "TARGET_SIMD_SET" "vmovaw %0, %1, %2" @@ -968,7 +966,7 @@ (define_insn "vmovw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") - (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r") + (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r") (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVW))] "TARGET_SIMD_SET" "vmovw %0, %1, %2" @@ -978,7 +976,7 @@ (define_insn "vmovzw_insn" [(set (match_operand:V8HI 0 "vector_register_operand" "=v") - (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r") + (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r") (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVZW))] "TARGET_SIMD_SET" "vmovzw %0, %1, %2" @@ -1123,7 +1121,7 @@ ; DMA setup instructions (define_insn "vdirun_insn" [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d") - (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r") + (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r") (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VDIRUN))] "TARGET_SIMD_SET" "vdirun %1, %2" @@ -1133,7 +1131,7 @@ (define_insn "vdorun_insn" [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d") - (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r") + (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r") (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VDORUN))] "TARGET_SIMD_SET" "vdorun %1, %2" @@ -1143,7 +1141,7 @@ (define_insn "vdiwr_insn" [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d,d") - (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r,Cal")] UNSPEC_ARC_SIMD_VDIWR))] + (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r,Cal")] UNSPEC_ARC_SIMD_VDIWR))] "TARGET_SIMD_SET" "vdiwr %0, %1" [(set_attr "type" "simd_dma") @@ -1152,7 +1150,7 @@ (define_insn "vdowr_insn" [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d,d") - (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r,Cal")] UNSPEC_ARC_SIMD_VDOWR))] + (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r,Cal")] UNSPEC_ARC_SIMD_VDOWR))] "TARGET_SIMD_SET" "vdowr %0, %1" [(set_attr "type" "simd_dma") diff --git a/gcc/config/arc/t-arc-newlib b/gcc/config/arc/t-arc-newlib index ea43a52cdc0..c49a3fcc146 100644 --- a/gcc/config/arc/t-arc-newlib +++ b/gcc/config/arc/t-arc-newlib @@ -1,6 +1,6 @@ # GCC Makefile fragment for Synopsys DesignWare ARC with newlib. -# Copyright (C) 2007-2015 Free Software Foundation, Inc. +# Copyright (C) 2007-2016 Free Software Foundation, Inc. # This file is part of GCC. diff --git a/gcc/config/arc/t-arc-uClibc b/gcc/config/arc/t-arc-uClibc index 8e16cc9e94a..11e81f1ee5e 100644 --- a/gcc/config/arc/t-arc-uClibc +++ b/gcc/config/arc/t-arc-uClibc @@ -1,6 +1,6 @@ # GCC Makefile fragment for Synopsys DesignWare ARC with uClibc -# Copyright (C) 2007-2015 Free Software Foundation, Inc. +# Copyright (C) 2007-2016 Free Software Foundation, Inc. # This file is part of GCC. diff --git a/gcc/config/arm/README-interworking b/gcc/config/arm/README-interworking index d060b2f0a2a..f2743d99aee 100644 --- a/gcc/config/arm/README-interworking +++ b/gcc/config/arm/README-interworking @@ -742,7 +742,7 @@ used. interworking as the --support-old-code switch has taken care if this. -Copyright (C) 1998-2015 Free Software Foundation, Inc. +Copyright (C) 1998-2016 Free Software Foundation, Inc. Copying and distribution of this file, with or without modification, are permitted in any medium without royalty provided the copyright diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h index 348ae7495fe..8e9fb7a895b 100644 --- a/gcc/config/arm/aarch-common-protos.h +++ b/gcc/config/arm/aarch-common-protos.h @@ -1,6 +1,6 @@ /* Functions and structures shared between arm and aarch64. - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/aarch-common.c b/gcc/config/arm/aarch-common.c index e6668d5742c..13058b7324b 100644 --- a/gcc/config/arm/aarch-common.c +++ b/gcc/config/arm/aarch-common.c @@ -1,7 +1,7 @@ /* Dependency checks for instruction scheduling, shared between ARM and AARCH64. - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/aarch-cost-tables.h b/gcc/config/arm/aarch-cost-tables.h index 850bde060b0..c971b308a57 100644 --- a/gcc/config/arm/aarch-cost-tables.h +++ b/gcc/config/arm/aarch-cost-tables.h @@ -1,6 +1,6 @@ /* RTX cost tables shared between arm and aarch64. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h index 6973d157a51..048f70e8eaa 100644 --- a/gcc/config/arm/aout.h +++ b/gcc/config/arm/aout.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for ARM with a.out - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rearnsha@armltd.co.uk). This file is part of GCC. diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def index ddf6c3c330f..fd02b18db01 100644 --- a/gcc/config/arm/arm-arches.def +++ b/gcc/config/arm/arm-arches.def @@ -1,5 +1,5 @@ /* ARM CPU architectures. - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -57,6 +57,11 @@ ARM_ARCH("armv7-m", cortexm3, 7M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ ARM_ARCH("armv7e-m", cortexm4, 7EM, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7EM)) ARM_ARCH("armv8-a", cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH8A)) ARM_ARCH("armv8-a+crc",cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A)) +ARM_ARCH("armv8.1-a", cortexa53, 8A, + ARM_FSET_MAKE (FL_CO_PROC | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A)) +ARM_ARCH("armv8.1-a+crc",cortexa53, 8A, + ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A, + FL2_FOR_ARCH8_1A)) ARM_ARCH("iwmmxt", iwmmxt, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT)) ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2)) diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 11cd17d0b8f..db6b29d310d 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -1,5 +1,5 @@ /* Description of builtins used by the ARM backend. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -526,6 +526,8 @@ enum arm_builtins #define CRYPTO3(L, U, M1, M2, M3, M4) \ ARM_BUILTIN_CRYPTO_##U, + ARM_BUILTIN_CRYPTO_BASE, + #include "crypto.def" #undef CRYPTO1 @@ -893,8 +895,13 @@ arm_init_simd_builtin_scalar_types (void) "__builtin_neon_uti"); } +/* Set up all the NEON builtins, even builtins for instructions that are not + in the current target ISA to allow the user to compile particular modules + with different target specific options that differ from the command line + options. Such builtins will be rejected in arm_expand_builtin. */ + static void -arm_init_neon_builtins_internal (void) +arm_init_neon_builtins (void) { unsigned int i, fcode = ARM_BUILTIN_NEON_PATTERN_START; @@ -1018,7 +1025,7 @@ arm_init_neon_builtins_internal (void) } static void -arm_init_crypto_builtins_internal (void) +arm_init_crypto_builtins (void) { tree V16UQI_type_node = arm_simd_builtin_type (V16QImode, true, false); @@ -1098,25 +1105,6 @@ arm_init_crypto_builtins_internal (void) #undef FT3 } -static bool neon_set_p = false; -static bool neon_crypto_set_p = false; - -void -arm_init_neon_builtins (void) -{ - if (! neon_set_p) - { - neon_set_p = true; - arm_init_neon_builtins_internal (); - } - - if (! neon_crypto_set_p && TARGET_CRYPTO && TARGET_HARD_FLOAT) - { - neon_crypto_set_p = true; - arm_init_crypto_builtins_internal (); - } -} - #undef NUM_DREG_TYPES #undef NUM_QREG_TYPES @@ -1777,8 +1765,12 @@ arm_init_builtins (void) arm_init_neon_builtins which uses it. */ arm_init_fp16_builtins (); - if (TARGET_NEON) - arm_init_neon_builtins (); + if (TARGET_HARD_FLOAT) + { + arm_init_neon_builtins (); + + arm_init_crypto_builtins (); + } if (TARGET_CRC32) arm_init_crc32_builtins (); @@ -2146,7 +2138,8 @@ constant_arg: if (!(*insn_data[icode].operand[opno].predicate) (op[argc], mode[argc])) op[argc] = (replace_equiv_address - (op[argc], force_reg (Pmode, XEXP (op[argc], 0)))); + (op[argc], + copy_to_mode_reg (Pmode, XEXP (op[argc], 0)))); break; case NEON_ARG_STOP: @@ -2225,6 +2218,15 @@ constant_arg: static rtx arm_expand_neon_builtin (int fcode, tree exp, rtx target) { + /* Check in the context of the function making the call whether the + builtin is supported. */ + if (! TARGET_NEON) + { + fatal_error (input_location, + "You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use these intrinsics."); + return const0_rtx; + } + if (fcode == ARM_BUILTIN_NEON_LANE_CHECK) { /* Builtin is only to check bounds of the lane passed to some intrinsics @@ -2335,6 +2337,16 @@ arm_expand_builtin (tree exp, if (fcode >= ARM_BUILTIN_NEON_BASE) return arm_expand_neon_builtin (fcode, exp, target); + /* Check in the context of the function making the call whether the + builtin is supported. */ + if (fcode >= ARM_BUILTIN_CRYPTO_BASE + && (!TARGET_CRYPTO || !TARGET_HARD_FLOAT)) + { + fatal_error (input_location, + "You must enable crypto intrinsics (e.g. include -mfloat-abi=softfp -mfpu=crypto-neon...) to use these intrinsics."); + return const0_rtx; + } + switch (fcode) { case ARM_BUILTIN_GET_FPSCR: diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c index 7dee28ec52d..5810608873e 100644 --- a/gcc/config/arm/arm-c.c +++ b/gcc/config/arm/arm-c.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -23,6 +23,7 @@ #include "c-family/c-common.h" #include "tm_p.h" #include "c-family/c-pragma.h" +#include "stringpool.h" /* Output C specific EABI object attributes. These can not be done in arm.c because they require information from the C frontend. */ @@ -62,19 +63,21 @@ static void arm_cpu_builtins (struct cpp_reader* pfile) { def_or_undef_macro (pfile, "__ARM_FEATURE_DSP", TARGET_DSP_MULTIPLY); - def_or_undef_macro (pfile, "__ARM_FEATURE_QBIT", TARGET_ARM_QBIT); + def_or_undef_macro (pfile, "__ARM_FEATURE_QBIT", TARGET_ARM_QBIT); def_or_undef_macro (pfile, "__ARM_FEATURE_SAT", TARGET_ARM_SAT); def_or_undef_macro (pfile, "__ARM_FEATURE_CRYPTO", TARGET_CRYPTO); def_or_undef_macro (pfile, "__ARM_FEATURE_UNALIGNED", unaligned_access); + def_or_undef_macro (pfile, "__ARM_FEATURE_QRDMX", TARGET_NEON_RDMA); + if (TARGET_CRC32) builtin_define ("__ARM_FEATURE_CRC32"); - def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT); + def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT); if (TARGET_ARM_FEATURE_LDREX) - builtin_define_with_int_value ("__ARM_FEATURE_LDREX", + builtin_define_with_int_value ("__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); else cpp_undef (pfile, "__ARM_FEATURE_LDREX"); @@ -243,8 +246,18 @@ arm_pragma_target_parse (tree args, tree pop_target) /* Update macros. */ gcc_assert (cur_opt->x_target_flags == target_flags); - /* This one can be redefined by the pragma without warning. */ - cpp_undef (parse_in, "__ARM_FP"); + + /* Don't warn for macros that have context sensitive values depending on + other attributes. + See warn_of_redefinition, Reset after cpp_create_definition. */ + tree acond_macro = get_identifier ("__ARM_NEON_FP"); + C_CPP_HASHNODE (acond_macro)->flags |= NODE_CONDITIONAL ; + + acond_macro = get_identifier ("__ARM_FP"); + C_CPP_HASHNODE (acond_macro)->flags |= NODE_CONDITIONAL; + + acond_macro = get_identifier ("__ARM_FEATURE_LDREX"); + C_CPP_HASHNODE (acond_macro)->flags |= NODE_CONDITIONAL; arm_cpu_builtins (parse_in); diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 642c840bed7..65388618986 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -1,5 +1,5 @@ /* ARM CPU Cores - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. Written by CodeSourcery, LLC This file is part of GCC. diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md index f4c2f03ce2e..4c56f91883c 100644 --- a/gcc/config/arm/arm-fixed.md +++ b/gcc/config/arm/arm-fixed.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def index efd589628fe..d340e26fd3f 100644 --- a/gcc/config/arm/arm-fpus.def +++ b/gcc/config/arm/arm-fpus.def @@ -1,5 +1,5 @@ /* ARM FPU variants. - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arm/arm-generic.md b/gcc/config/arm/arm-generic.md index ab3d2fcf5da..85c6ec09f8c 100644 --- a/gcc/config/arm/arm-generic.md +++ b/gcc/config/arm/arm-generic.md @@ -1,5 +1,5 @@ ;; Generic ARM Pipeline Description -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arm/arm-ldmstm.ml b/gcc/config/arm/arm-ldmstm.ml index 62982df594d..27af564fd8a 100644 --- a/gcc/config/arm/arm-ldmstm.ml +++ b/gcc/config/arm/arm-ldmstm.ml @@ -1,5 +1,5 @@ (* Auto-generate ARM ldm/stm patterns - Copyright (C) 2010-2015 Free Software Foundation, Inc. + Copyright (C) 2010-2016 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. @@ -335,7 +335,7 @@ let _ = "/* ARM ldm/stm instruction patterns. This file was automatically generated"; " using arm-ldmstm.ml. Please do not edit manually."; ""; -" Copyright (C) 2010-2015 Free Software Foundation, Inc."; +" Copyright (C) 2010-2016 Free Software Foundation, Inc."; " Contributed by CodeSourcery."; ""; " This file is part of GCC."; diff --git a/gcc/config/arm/arm-modes.def b/gcc/config/arm/arm-modes.def index 95a8fc67363..18195534e66 100644 --- a/gcc/config/arm/arm-modes.def +++ b/gcc/config/arm/arm-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for ARM. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). More major hacks by Richard Earnshaw (rearnsha@arm.com) diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h index 039e3330edf..a649ba59e47 100644 --- a/gcc/config/arm/arm-opts.h +++ b/gcc/config/arm/arm-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for ARM. - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index e7328e79650..28f226324a0 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in arm.c and pe.c - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rearnsha@arm.com) Minor hacks by Nick Clifton (nickc@cygnus.com) @@ -213,7 +213,6 @@ extern void arm_mark_dllimport (tree); extern bool arm_change_mode_p (tree); #endif -extern void arm_init_neon_builtins (void); extern tree arm_valid_target_attribute_tree (tree, struct gcc_options *, struct gcc_options *); extern void arm_pr_long_calls (struct cpp_reader *); @@ -387,6 +386,8 @@ extern bool arm_is_constant_pool_ref (rtx); #define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */ #define FL_ARCH6KZ (1 << 31) /* ARMv6KZ architecture. */ +#define FL2_ARCH8_1 (1 << 0) /* Architecture 8.1. */ + /* Flags that only effect tuning, not available instructions. */ #define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ | FL_CO_PROC) @@ -415,6 +416,7 @@ extern bool arm_is_constant_pool_ref (rtx); #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV) #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM) #define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8) +#define FL2_FOR_ARCH8_1A FL2_ARCH8_1 /* There are too many feature bits to fit in a single word so the set of cpu and fpu capabilities is a structure. A feature set is created and manipulated diff --git a/gcc/config/arm/arm-simd-builtin-types.def b/gcc/config/arm/arm-simd-builtin-types.def index b178ae6c05f..6eda0f3b48e 100644 --- a/gcc/config/arm/arm-simd-builtin-types.def +++ b/gcc/config/arm/arm-simd-builtin-types.def @@ -1,5 +1,5 @@ /* Builtin AdvSIMD types. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 48aac41c37a..6d6ee968281 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -2,7 +2,7 @@ ; Generated automatically by genopt.sh from arm-cores.def, arm-arches.def ; and arm-fpus.def. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -416,10 +416,16 @@ EnumValue Enum(arm_arch) String(armv8-a+crc) Value(26) EnumValue -Enum(arm_arch) String(iwmmxt) Value(27) +Enum(arm_arch) String(armv8.1-a) Value(27) EnumValue -Enum(arm_arch) String(iwmmxt2) Value(28) +Enum(arm_arch) String(armv8.1-a+crc) Value(28) + +EnumValue +Enum(arm_arch) String(iwmmxt) Value(29) + +EnumValue +Enum(arm_arch) String(iwmmxt2) Value(30) Enum Name(arm_fpu) Type(int) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 3588b839fb6..f152afa4019 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1,5 +1,5 @@ /* Output routines for GCC for ARM. - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). More major hacks by Richard Earnshaw (rearnsha@arm.com). @@ -817,6 +817,9 @@ int arm_arch7em = 0; /* Nonzero if instructions present in ARMv8 can be used. */ int arm_arch8 = 0; +/* Nonzero if this chip supports the ARMv8.1 extensions. */ +int arm_arch8_1 = 0; + /* Nonzero if this chip can benefit from load scheduling. */ int arm_ld_sched = 0; @@ -2951,6 +2954,10 @@ arm_option_override_internal (struct gcc_options *opts, /* Thumb2 inline assembly code should always use unified syntax. This will apply to ARM and Thumb1 eventually. */ opts->x_inline_asm_unified = TARGET_THUMB2_P (opts->x_target_flags); + +#ifdef SUBTARGET_OVERRIDE_INTERNAL_OPTIONS + SUBTARGET_OVERRIDE_INTERNAL_OPTIONS; +#endif } /* Fix up any incompatible options that the user has specified. */ @@ -3154,6 +3161,7 @@ arm_option_override (void) arm_arch7 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7); arm_arch7em = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7EM); arm_arch8 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH8); + arm_arch8_1 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_1); arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2); arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE); @@ -5842,7 +5850,10 @@ aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED, if (!use_vfp_abi (pcs_variant, false)) return NULL; - if (mode == BLKmode || (mode == TImode && !TARGET_NEON)) + if (mode == BLKmode + || (GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_SIZE (mode) >= GET_MODE_SIZE (TImode) + && !TARGET_NEON)) { int count; machine_mode ag_mode; @@ -17195,7 +17206,7 @@ thumb1_reorg (void) FOR_EACH_BB_FN (bb, cfun) { rtx dest, src; - rtx pat, op0, set = NULL; + rtx cmp, op0, op1, set = NULL; rtx_insn *prev, *insn = BB_END (bb); bool insn_clobbered = false; @@ -17208,8 +17219,13 @@ thumb1_reorg (void) continue; /* Get the register with which we are comparing. */ - pat = PATTERN (insn); - op0 = XEXP (XEXP (SET_SRC (pat), 0), 0); + cmp = XEXP (SET_SRC (PATTERN (insn)), 0); + op0 = XEXP (cmp, 0); + op1 = XEXP (cmp, 1); + + /* Check that comparison is against ZERO. */ + if (!CONST_INT_P (op1) || INTVAL (op1) != 0) + continue; /* Find the first flag setting insn before INSN in basic block BB. */ gcc_assert (insn != BB_HEAD (bb)); @@ -17249,7 +17265,7 @@ thumb1_reorg (void) PATTERN (prev) = gen_rtx_SET (dest, src); INSN_CODE (prev) = -1; /* Set test register in INSN to dest. */ - XEXP (XEXP (SET_SRC (pat), 0), 0) = copy_rtx (dest); + XEXP (cmp, 0) = copy_rtx (dest); INSN_CODE (insn) = -1; } } @@ -29926,9 +29942,6 @@ arm_valid_target_attribute_tree (tree args, struct gcc_options *opts, /* Do any overrides, such as global options arch=xxx. */ arm_option_override_internal (opts, opts_set); - if (TARGET_NEON) - arm_init_neon_builtins (); - return build_target_option_node (opts); } diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index fd999dd0941..a32ae4c6aaa 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for ARM. - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). More major hacks by Richard Earnshaw (rearnsha@arm.com) @@ -218,6 +218,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void); (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP \ && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON)) +/* FPU supports ARMv8.1 Adv.SIMD extensions. */ +#define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) + /* Q-bit is present. */ #define TARGET_ARM_QBIT \ (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7)) @@ -437,6 +440,9 @@ extern int arm_arch7em; /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ extern int arm_arch8; +/* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */ +extern int arm_arch8_1; + /* Nonzero if this chip can benefit from load scheduling. */ extern int arm_ld_sched; diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index a91873c8948..64873a2ded8 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1,5 +1,5 @@ ;;- Machine description for ARM for GNU compiler -;; Copyright (C) 1991-2015 Free Software Foundation, Inc. +;; Copyright (C) 1991-2016 Free Software Foundation, Inc. ;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) ;; and Martin Simmons (@harleqn.co.uk). ;; More major hacks by Richard Earnshaw (rearnsha@arm.com). @@ -3228,8 +3228,22 @@ "#" ; "orr%?\\t%0, %1, %2\;bic%?\\t%0, %0, %3" "&& reload_completed" [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 2))) - (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 0)))] - "" + (set (match_dup 0) (and:SI (match_dup 4) (match_dup 5)))] + { + /* If operands[3] is a constant make sure to fold the NOT into it + to avoid creating a NOT of a CONST_INT. */ + rtx not_rtx = simplify_gen_unary (NOT, SImode, operands[3], SImode); + if (CONST_INT_P (not_rtx)) + { + operands[4] = operands[0]; + operands[5] = not_rtx; + } + else + { + operands[5] = operands[0]; + operands[4] = not_rtx; + } + } [(set_attr "length" "8") (set_attr "ce_count" "2") (set_attr "predicable" "yes") diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index 1e438a9c092..0ebe0174390 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -1,6 +1,6 @@ ; Options for the ARM port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md index 3c1bfb08795..7cdab57ddb3 100644 --- a/gcc/config/arm/arm1020e.md +++ b/gcc/config/arm/arm1020e.md @@ -1,5 +1,5 @@ ;; ARM 1020E & ARM 1022E Pipeline Description -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Richard Earnshaw (richard.earnshaw@arm.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/arm1026ejs.md b/gcc/config/arm/arm1026ejs.md index 54fbedd1089..c431307a340 100644 --- a/gcc/config/arm/arm1026ejs.md +++ b/gcc/config/arm/arm1026ejs.md @@ -1,5 +1,5 @@ ;; ARM 1026EJ-S Pipeline Description -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; Written by CodeSourcery, LLC. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/arm1136jfs.md b/gcc/config/arm/arm1136jfs.md index 8777472b74f..554de644f50 100644 --- a/gcc/config/arm/arm1136jfs.md +++ b/gcc/config/arm/arm1136jfs.md @@ -1,5 +1,5 @@ ;; ARM 1136J[F]-S Pipeline Description -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; Written by CodeSourcery, LLC. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/arm926ejs.md b/gcc/config/arm/arm926ejs.md index 27a8aba1a16..b355a7faa5b 100644 --- a/gcc/config/arm/arm926ejs.md +++ b/gcc/config/arm/arm926ejs.md @@ -1,5 +1,5 @@ ;; ARM 926EJ-S Pipeline Description -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; Written by CodeSourcery, LLC. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/arm_acle.h b/gcc/config/arm/arm_acle.h index 418b39c0945..5d937168e10 100644 --- a/gcc/config/arm/arm_acle.h +++ b/gcc/config/arm/arm_acle.h @@ -1,6 +1,6 @@ /* ARM Non-NEON ACLE intrinsics include file. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 0a33d21f2fc..b311b3a06fb 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -1,6 +1,6 @@ /* ARM NEON intrinsics include file. - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. @@ -1158,6 +1158,56 @@ vqrdmulhq_s32 (int32x4_t __a, int32x4_t __b) return (int32x4_t)__builtin_neon_vqrdmulhv4si (__a, __b); } +#ifdef __ARM_FEATURE_QRDMX +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqrdmlah_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c) +{ + return (int16x4_t)__builtin_neon_vqrdmlahv4hi (__a, __b, __c); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqrdmlah_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c) +{ + return (int32x2_t)__builtin_neon_vqrdmlahv2si (__a, __b, __c); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqrdmlahq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c) +{ + return (int16x8_t)__builtin_neon_vqrdmlahv8hi (__a, __b, __c); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqrdmlahq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c) +{ + return (int32x4_t)__builtin_neon_vqrdmlahv4si (__a, __b, __c); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqrdmlsh_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c) +{ + return (int16x4_t)__builtin_neon_vqrdmlshv4hi (__a, __b, __c); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqrdmlsh_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c) +{ + return (int32x2_t)__builtin_neon_vqrdmlshv2si (__a, __b, __c); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqrdmlshq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c) +{ + return (int16x8_t)__builtin_neon_vqrdmlshv8hi (__a, __b, __c); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqrdmlshq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c) +{ + return (int32x4_t)__builtin_neon_vqrdmlshv4si (__a, __b, __c); +} +#endif + __extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) vmull_s8 (int8x8_t __a, int8x8_t __b) { @@ -7046,6 +7096,56 @@ vqrdmulh_lane_s32 (int32x2_t __a, int32x2_t __b, const int __c) return (int32x2_t)__builtin_neon_vqrdmulh_lanev2si (__a, __b, __c); } +#ifdef __ARM_FEATURE_QRDMX +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqrdmlahq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d) +{ + return (int16x8_t)__builtin_neon_vqrdmlah_lanev8hi (__a, __b, __c, __d); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqrdmlahq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d) +{ + return (int32x4_t)__builtin_neon_vqrdmlah_lanev4si (__a, __b, __c, __d); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqrdmlah_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d) +{ + return (int16x4_t)__builtin_neon_vqrdmlah_lanev4hi (__a, __b, __c, __d); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqrdmlah_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d) +{ + return (int32x2_t)__builtin_neon_vqrdmlah_lanev2si (__a, __b, __c, __d); +} + +__extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) +vqrdmlshq_lane_s16 (int16x8_t __a, int16x8_t __b, int16x4_t __c, const int __d) +{ + return (int16x8_t)__builtin_neon_vqrdmlsh_lanev8hi (__a, __b, __c, __d); +} + +__extension__ static __inline int32x4_t __attribute__ ((__always_inline__)) +vqrdmlshq_lane_s32 (int32x4_t __a, int32x4_t __b, int32x2_t __c, const int __d) +{ + return (int32x4_t)__builtin_neon_vqrdmlsh_lanev4si (__a, __b, __c, __d); +} + +__extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) +vqrdmlsh_lane_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c, const int __d) +{ + return (int16x4_t)__builtin_neon_vqrdmlsh_lanev4hi (__a, __b, __c, __d); +} + +__extension__ static __inline int32x2_t __attribute__ ((__always_inline__)) +vqrdmlsh_lane_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c, const int __d) +{ + return (int32x2_t)__builtin_neon_vqrdmlsh_lanev2si (__a, __b, __c, __d); +} +#endif + __extension__ static __inline int16x4_t __attribute__ ((__always_inline__)) vmul_n_s16 (int16x4_t __a, int16_t __b) { diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index 0b719df7607..70ba4865753 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -1,5 +1,5 @@ /* NEON builtin definitions for ARM. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. @@ -45,6 +45,8 @@ VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si) VAR4 (BINOP, vqrdmulh, v4hi, v2si, v8hi, v4si) VAR2 (TERNOP, vqdmlal, v4hi, v2si) VAR2 (TERNOP, vqdmlsl, v4hi, v2si) +VAR4 (TERNOP, vqrdmlah, v4hi, v2si, v8hi, v4si) +VAR4 (TERNOP, vqrdmlsh, v4hi, v2si, v8hi, v4si) VAR3 (BINOP, vmullp, v8qi, v4hi, v2si) VAR3 (BINOP, vmulls, v8qi, v4hi, v2si) VAR3 (BINOP, vmullu, v8qi, v4hi, v2si) @@ -58,6 +60,8 @@ VAR4 (BINOP, vqdmulh_n, v4hi, v2si, v8hi, v4si) VAR4 (BINOP, vqrdmulh_n, v4hi, v2si, v8hi, v4si) VAR4 (SETLANE, vqdmulh_lane, v4hi, v2si, v8hi, v4si) VAR4 (SETLANE, vqrdmulh_lane, v4hi, v2si, v8hi, v4si) +VAR4 (MAC_LANE, vqrdmlah_lane, v4hi, v2si, v8hi, v4si) +VAR4 (MAC_LANE, vqrdmlsh_lane, v4hi, v2si, v8hi, v4si) VAR2 (BINOP, vqdmull, v4hi, v2si) VAR8 (BINOP, vshls, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) VAR8 (BINOP, vshlu, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index e522064441f..82128ef0735 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -1,5 +1,5 @@ /* Configuration file for ARM BPABI targets. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC This file is part of GCC. diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 901cfe54d24..3b71c4a5270 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for ARM and Thumb -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; This file is part of GCC. diff --git a/gcc/config/arm/cortex-a15-neon.md b/gcc/config/arm/cortex-a15-neon.md index 3e86214e4a8..082ccd73e94 100644 --- a/gcc/config/arm/cortex-a15-neon.md +++ b/gcc/config/arm/cortex-a15-neon.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A15 NEON pipeline description -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md index 90cd8f24c0f..a5453a6207b 100644 --- a/gcc/config/arm/cortex-a15.md +++ b/gcc/config/arm/cortex-a15.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A15 pipeline description -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; ;; Written by Matthew Gretton-Dann <matthew.gretton-dann@arm.com> diff --git a/gcc/config/arm/cortex-a17-neon.md b/gcc/config/arm/cortex-a17-neon.md index 29836466f37..1385560fd43 100644 --- a/gcc/config/arm/cortex-a17-neon.md +++ b/gcc/config/arm/cortex-a17-neon.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A17 NEON pipeline description -;; Copyright (C) 2014-2015 Free Software Foundation, Inc. +;; Copyright (C) 2014-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arm/cortex-a17.md b/gcc/config/arm/cortex-a17.md index a9be18222df..25a52dc0f13 100644 --- a/gcc/config/arm/cortex-a17.md +++ b/gcc/config/arm/cortex-a17.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A17 pipeline description -;; Copyright (C) 2014-2015 Free Software Foundation, Inc. +;; Copyright (C) 2014-2016 Free Software Foundation, Inc. ;; ;; Contributed by ARM Ltd. ;; diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md index 5816b76e379..65c12a5eaf7 100644 --- a/gcc/config/arm/cortex-a5.md +++ b/gcc/config/arm/cortex-a5.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A5 pipeline description -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index 4632cd88f23..c1eeedb72dd 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A53 pipeline description -;; Copyright (C) 2013-2015 Free Software Foundation, Inc. +;; Copyright (C) 2013-2016 Free Software Foundation, Inc. ;; ;; Contributed by ARM Ltd. ;; diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index c751dd43b0e..0d28951cb27 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A57 pipeline description -;; Copyright (C) 2014-2015 Free Software Foundation, Inc. +;; Copyright (C) 2014-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md index ab6a7f83602..a7ee4669728 100644 --- a/gcc/config/arm/cortex-a7.md +++ b/gcc/config/arm/cortex-a7.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A7 pipeline description -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; Contributed by ARM Ltd. ;; Based on cortex-a5.md which was originally contributed by CodeSourcery. diff --git a/gcc/config/arm/cortex-a8-neon.md b/gcc/config/arm/cortex-a8-neon.md index 04fa01e265c..45f861f6c6f 100644 --- a/gcc/config/arm/cortex-a8-neon.md +++ b/gcc/config/arm/cortex-a8-neon.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A8 NEON scheduling description. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; This file is part of GCC. diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md index a3fb3050f88..43172222058 100644 --- a/gcc/config/arm/cortex-a8.md +++ b/gcc/config/arm/cortex-a8.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A8 scheduling description. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; This file is part of GCC. diff --git a/gcc/config/arm/cortex-a9-neon.md b/gcc/config/arm/cortex-a9-neon.md index 491b35b58aa..9e9773ee1a9 100644 --- a/gcc/config/arm/cortex-a9-neon.md +++ b/gcc/config/arm/cortex-a9-neon.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A9 pipeline description -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; ;; Neon pipeline description contributed by ARM Ltd. ;; diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md index 90b595ff5d1..7905816f596 100644 --- a/gcc/config/arm/cortex-a9.md +++ b/gcc/config/arm/cortex-a9.md @@ -1,5 +1,5 @@ ;; ARM Cortex-A9 pipeline description -;; Copyright (C) 2008-2015 Free Software Foundation, Inc. +;; Copyright (C) 2008-2016 Free Software Foundation, Inc. ;; Originally written by CodeSourcery for VFP. ;; ;; Rewritten by Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> diff --git a/gcc/config/arm/cortex-m4-fpu.md b/gcc/config/arm/cortex-m4-fpu.md index 4520955408d..db02568c55c 100644 --- a/gcc/config/arm/cortex-m4-fpu.md +++ b/gcc/config/arm/cortex-m4-fpu.md @@ -1,5 +1,5 @@ ;; ARM Cortex-M4 FPU pipeline description -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md index 3963bd86ebb..f1b1b8ad210 100644 --- a/gcc/config/arm/cortex-m4.md +++ b/gcc/config/arm/cortex-m4.md @@ -1,5 +1,5 @@ ;; ARM Cortex-M4 pipeline description -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/cortex-m7.md b/gcc/config/arm/cortex-m7.md index e26b3f5eb57..71d04f0e03a 100644 --- a/gcc/config/arm/cortex-m7.md +++ b/gcc/config/arm/cortex-m7.md @@ -1,5 +1,5 @@ ;; ARM Cortex-M7 pipeline description -;; Copyright (C) 2014-2015 Free Software Foundation, Inc. +;; Copyright (C) 2014-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arm/cortex-r4.md b/gcc/config/arm/cortex-r4.md index f1d6413723a..432a9e01b67 100644 --- a/gcc/config/arm/cortex-r4.md +++ b/gcc/config/arm/cortex-r4.md @@ -1,5 +1,5 @@ ;; ARM Cortex-R4 scheduling description. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; This file is part of GCC. diff --git a/gcc/config/arm/cortex-r4f.md b/gcc/config/arm/cortex-r4f.md index 43134c95232..a34feb72a3a 100644 --- a/gcc/config/arm/cortex-r4f.md +++ b/gcc/config/arm/cortex-r4f.md @@ -1,5 +1,5 @@ ;; ARM Cortex-R4F VFP pipeline description -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; Written by CodeSourcery. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/crypto.def b/gcc/config/arm/crypto.def index 792922e566b..c2a5bb6dde9 100644 --- a/gcc/config/arm/crypto.def +++ b/gcc/config/arm/crypto.def @@ -1,5 +1,5 @@ /* Cryptographic instruction builtin definitions. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GCC. diff --git a/gcc/config/arm/crypto.md b/gcc/config/arm/crypto.md index d8c448d0466..c6f17270b1d 100644 --- a/gcc/config/arm/crypto.md +++ b/gcc/config/arm/crypto.md @@ -1,5 +1,5 @@ ;; ARMv8-A crypto patterns. -;; Copyright (C) 2013-2015 Free Software Foundation, Inc. +;; Copyright (C) 2013-2016 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; This file is part of GCC. diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c index 9d24a3fb378..466743b9d47 100644 --- a/gcc/config/arm/driver-arm.c +++ b/gcc/config/arm/driver-arm.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h index 3795728ca90..77f30554d52 100644 --- a/gcc/config/arm/elf.h +++ b/gcc/config/arm/elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. For ARM with ELF obj format. - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. Contributed by Philip Blundell <philb@gnu.org> and Catherine Moore <clm@cygnus.com> diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md index fd73353188b..044807321fa 100644 --- a/gcc/config/arm/exynos-m1.md +++ b/gcc/config/arm/exynos-m1.md @@ -1,5 +1,5 @@ ;; Samsung Exynos M1 pipeline description -;; Copyright (C) 2014-2015 Free Software Foundation, Inc. +;; Copyright (C) 2014-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arm/fa526.md b/gcc/config/arm/fa526.md index 34eb0d39f50..ad63a07d931 100644 --- a/gcc/config/arm/fa526.md +++ b/gcc/config/arm/fa526.md @@ -1,5 +1,5 @@ ;; Faraday FA526 Pipeline Description -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description. ;; This file is part of GCC. diff --git a/gcc/config/arm/fa606te.md b/gcc/config/arm/fa606te.md index 60662a7f1f4..93d7c2380a7 100644 --- a/gcc/config/arm/fa606te.md +++ b/gcc/config/arm/fa606te.md @@ -1,5 +1,5 @@ ;; Faraday FA606TE Pipeline Description -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Written by Mingfeng Wu, based on ARM926EJ-S Pipeline Description. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/fa626te.md b/gcc/config/arm/fa626te.md index 573e2c1e148..7dd8cdd9e2c 100644 --- a/gcc/config/arm/fa626te.md +++ b/gcc/config/arm/fa626te.md @@ -1,5 +1,5 @@ ;; Faraday FA626TE Pipeline Description -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md index 63459f24ee0..f3885fd3057 100644 --- a/gcc/config/arm/fa726te.md +++ b/gcc/config/arm/fa726te.md @@ -1,5 +1,5 @@ ;; Faraday FA726TE Pipeline Description -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/fmp626.md b/gcc/config/arm/fmp626.md index 5d43bd10764..48e736a2970 100644 --- a/gcc/config/arm/fmp626.md +++ b/gcc/config/arm/fmp626.md @@ -1,5 +1,5 @@ ;; Faraday FA626TE Pipeline Description -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Written by Mingfeng Wu, based on ARM926EJ-S Pipeline Description. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/freebsd.h b/gcc/config/arm/freebsd.h index 2febf4b6091..948fdd6843e 100644 --- a/gcc/config/arm/freebsd.h +++ b/gcc/config/arm/freebsd.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, FreeBSD/arm version. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. This file is part of GCC. @@ -120,10 +120,12 @@ #define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm9 #endif -#define SUBTARGET_OVERRIDE_OPTIONS \ -do { \ - if (unaligned_access) \ - unaligned_access = 0; \ +#define SUBTARGET_OVERRIDE_INTERNAL_OPTIONS \ +do { \ + if (opts_set->x_unaligned_access == 1) \ + warning (0, "target OS does not support unaligned accesses"); \ + if (opts->x_unaligned_access) \ + opts->x_unaligned_access = 0; \ } while (0) #undef MAX_SYNC_LIBFUNC_SIZE diff --git a/gcc/config/arm/genopt.sh b/gcc/config/arm/genopt.sh index 4ee2bcd12ae..9e973423f03 100755 --- a/gcc/config/arm/genopt.sh +++ b/gcc/config/arm/genopt.sh @@ -1,6 +1,6 @@ #!/bin/sh # Generate arm-tables.opt from the lists in *.def. -# Copyright (C) 2011-2015 Free Software Foundation, Inc. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -23,7 +23,7 @@ cat <<EOF ; Generated automatically by genopt.sh from arm-cores.def, arm-arches.def ; and arm-fpus.def. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/arm/gentune.sh b/gcc/config/arm/gentune.sh index 37e2949a2d8..f71dfd7779c 100755 --- a/gcc/config/arm/gentune.sh +++ b/gcc/config/arm/gentune.sh @@ -1,7 +1,7 @@ #!/bin/sh # Generate arm-tune.md, a file containing the tune attribute from the list of # CPUs in arm-cores.def -# Copyright (C) 2004-2015 Free Software Foundation, Inc. +# Copyright (C) 2004-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 6a541251ed1..974cf51cb60 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -1,5 +1,5 @@ ;; Code and mode itertator and attribute definitions for the ARM backend -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. @@ -308,6 +308,8 @@ (define_int_iterator VMAXMINF [UNSPEC_VMAX UNSPEC_VMIN]) +(define_int_iterator VMAXMINFNM [UNSPEC_VMAXNM UNSPEC_VMINNM]) + (define_int_iterator VPADDL [UNSPEC_VPADDL_S UNSPEC_VPADDL_U]) (define_int_iterator VPADAL [UNSPEC_VPADAL_S UNSPEC_VPADAL_U]) @@ -362,6 +364,8 @@ (define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P]) +(define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH]) + ;;---------------------------------------------------------------------------- ;; Mode attributes ;;---------------------------------------------------------------------------- @@ -743,6 +747,13 @@ (UNSPEC_VPMIN "min") (UNSPEC_VPMIN_U "min") ]) +(define_int_attr fmaxmin [ + (UNSPEC_VMAXNM "fmax") (UNSPEC_VMINNM "fmin")]) + +(define_int_attr fmaxmin_op [ + (UNSPEC_VMAXNM "vmaxnm") (UNSPEC_VMINNM "vminnm") +]) + (define_int_attr shift_op [ (UNSPEC_VSHL_S "shl") (UNSPEC_VSHL_U "shl") (UNSPEC_VRSHL_S "rshl") (UNSPEC_VRSHL_U "rshl") @@ -831,3 +842,6 @@ (simple_return " && use_simple_return_p ()")]) (define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)") (simple_return " && use_simple_return_p ()")]) + +;; Attributes for VQRDMLAH/VQRDMLSH +(define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")]) diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md index d1a60ff9caf..36c53af97a9 100644 --- a/gcc/config/arm/iwmmxt.md +++ b/gcc/config/arm/iwmmxt.md @@ -1,5 +1,5 @@ ;; Patterns for the Intel Wireless MMX technology architecture. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/arm/iwmmxt2.md b/gcc/config/arm/iwmmxt2.md index 2e1cb6bcb61..3c28f40005a 100644 --- a/gcc/config/arm/iwmmxt2.md +++ b/gcc/config/arm/iwmmxt2.md @@ -1,5 +1,5 @@ ;; Patterns for the Intel Wireless MMX technology architecture. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Written by Marvell, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/ldmstm.md b/gcc/config/arm/ldmstm.md index ebb09ab86e7..e266f19a380 100644 --- a/gcc/config/arm/ldmstm.md +++ b/gcc/config/arm/ldmstm.md @@ -1,7 +1,7 @@ /* ARM ldm/stm instruction patterns. This file was automatically generated using arm-ldmstm.ml. Please do not edit manually. - Copyright (C) 2010-2015 Free Software Foundation, Inc. + Copyright (C) 2010-2016 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. diff --git a/gcc/config/arm/ldrdstrd.md b/gcc/config/arm/ldrdstrd.md index ce0ab114ffd..e7ef542e379 100644 --- a/gcc/config/arm/ldrdstrd.md +++ b/gcc/config/arm/ldrdstrd.md @@ -1,6 +1,6 @@ ;; ARM ldrd/strd peephole optimizations. ;; -;; Copyright (C) 2013-2015 Free Software Foundation, Inc. +;; Copyright (C) 2013-2016 Free Software Foundation, Inc. ;; ;; Written by Greta Yorsh <greta.yorsh@arm.com> diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h index d51376fc3cb..ace84816e06 100644 --- a/gcc/config/arm/linux-eabi.h +++ b/gcc/config/arm/linux-eabi.h @@ -1,5 +1,5 @@ /* Configuration file for ARM GNU/Linux EABI targets. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC This file is part of GCC. diff --git a/gcc/config/arm/linux-elf.h b/gcc/config/arm/linux-elf.h index 297a83f1f77..472141dc915 100644 --- a/gcc/config/arm/linux-elf.h +++ b/gcc/config/arm/linux-elf.h @@ -1,5 +1,5 @@ /* Definitions for ARM running Linux-based GNU systems using ELF - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. Contributed by Philip Blundell <philb@gnu.org> This file is part of GCC. diff --git a/gcc/config/arm/linux-gas.h b/gcc/config/arm/linux-gas.h index d3a31961a14..5e36a076192 100644 --- a/gcc/config/arm/linux-gas.h +++ b/gcc/config/arm/linux-gas.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. ARM Linux-based GNU systems version. - Copyright (C) 1997-2015 Free Software Foundation, Inc. + Copyright (C) 1997-2016 Free Software Foundation, Inc. Contributed by Russell King <rmk92@ecs.soton.ac.uk>. This file is part of GCC. diff --git a/gcc/config/arm/marvell-f-iwmmxt.md b/gcc/config/arm/marvell-f-iwmmxt.md index 8dba191899f..14807cefb48 100644 --- a/gcc/config/arm/marvell-f-iwmmxt.md +++ b/gcc/config/arm/marvell-f-iwmmxt.md @@ -1,5 +1,5 @@ ;; Marvell WMMX2 pipeline description -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Written by Marvell, Inc. ;; This file is part of GCC. diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md index bb46fdf3dcc..c1bc99e026d 100644 --- a/gcc/config/arm/marvell-pj4.md +++ b/gcc/config/arm/marvell-pj4.md @@ -1,5 +1,5 @@ ;; Marvell ARM Processor Pipeline Description -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Marvell. ;; This file is part of GCC. diff --git a/gcc/config/arm/mmintrin.h b/gcc/config/arm/mmintrin.h index a4045afa0cf..5ab938a1d0d 100644 --- a/gcc/config/arm/mmintrin.h +++ b/gcc/config/arm/mmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002-2015 Free Software Foundation, Inc. +/* Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arm/neon-testgen.ml b/gcc/config/arm/neon-testgen.ml index a80c05dfe09..c1af5de5ea1 100644 --- a/gcc/config/arm/neon-testgen.ml +++ b/gcc/config/arm/neon-testgen.ml @@ -1,5 +1,5 @@ (* Auto-generate ARM Neon intrinsics tests. - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 62fb6daae99..aff5023f4fd 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -1,5 +1,5 @@ ;; ARM NEON coprocessor Machine Description -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; Written by CodeSourcery. ;; ;; This file is part of GCC. @@ -2014,6 +2014,18 @@ [(set_attr "type" "neon_sat_mul_<V_elem_ch><q>")] ) +;; vqrdmlah, vqrdmlsh +(define_insn "neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h<mode>" + [(set (match_operand:VMDQI 0 "s_register_operand" "=w") + (unspec:VMDQI [(match_operand:VMDQI 1 "s_register_operand" "0") + (match_operand:VMDQI 2 "s_register_operand" "w") + (match_operand:VMDQI 3 "s_register_operand" "w")] + VQRDMLH_AS))] + "TARGET_NEON_RDMA" + "vqrdml<VQRDMLH_AS:neon_rdma_as>h.<V_s_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3" + [(set_attr "type" "neon_sat_mla_<V_elem_ch>_long")] +) + (define_insn "neon_vqdmlal<mode>" [(set (match_operand:<V_widen> 0 "s_register_operand" "=w") (unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0") @@ -2354,6 +2366,17 @@ [(set_attr "type" "neon_fp_minmax_s<q>")] ) +;; Vector forms for the IEEE-754 fmax()/fmin() functions +(define_insn "<fmaxmin><mode>3" + [(set (match_operand:VCVTF 0 "s_register_operand" "=w") + (unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w") + (match_operand:VCVTF 2 "s_register_operand" "w")] + VMAXMINFNM))] + "TARGET_NEON && TARGET_FPU_ARMV8" + "<fmaxmin_op>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2" + [(set_attr "type" "neon_fp_minmax_s<q>")] +) + (define_expand "neon_vpadd<mode>" [(match_operand:VD 0 "s_register_operand" "=w") (match_operand:VD 1 "s_register_operand" "w") @@ -3176,6 +3199,39 @@ if (BYTES_BIG_ENDIAN) [(set_attr "type" "neon_sat_mul_<V_elem_ch>_scalar_q")] ) +;; vqrdmlah_lane, vqrdmlsh_lane +(define_insn "neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h_lane<mode>" + [(set (match_operand:VMQI 0 "s_register_operand" "=w") + (unspec:VMQI [(match_operand:VMQI 1 "s_register_operand" "0") + (match_operand:VMQI 2 "s_register_operand" "w") + (match_operand:<V_HALF> 3 "s_register_operand" + "<scalar_mul_constraint>") + (match_operand:SI 4 "immediate_operand" "i")] + VQRDMLH_AS))] + "TARGET_NEON_RDMA" +{ + return + "vqrdml<VQRDMLH_AS:neon_rdma_as>h.<V_s_elem>\t%q0, %q2, %P3[%c4]"; +} + [(set_attr "type" "neon_mla_<V_elem_ch>_scalar<q>")] +) + +(define_insn "neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h_lane<mode>" + [(set (match_operand:VMDI 0 "s_register_operand" "=w") + (unspec:VMDI [(match_operand:VMDI 1 "s_register_operand" "0") + (match_operand:VMDI 2 "s_register_operand" "w") + (match_operand:VMDI 3 "s_register_operand" + "<scalar_mul_constraint>") + (match_operand:SI 4 "immediate_operand" "i")] + VQRDMLH_AS))] + "TARGET_NEON_RDMA" +{ + return + "vqrdml<VQRDMLH_AS:neon_rdma_as>h.<V_s_elem>\t%P0, %P2, %P3[%c4]"; +} + [(set_attr "type" "neon_mla_<V_elem_ch>_scalar")] +) + (define_insn "neon_vmla_lane<mode>" [(set (match_operand:VMD 0 "s_register_operand" "=w") (unspec:VMD [(match_operand:VMD 1 "s_register_operand" "0") diff --git a/gcc/config/arm/neon.ml b/gcc/config/arm/neon.ml index e9c1588a7a6..99350bef727 100644 --- a/gcc/config/arm/neon.ml +++ b/gcc/config/arm/neon.ml @@ -1,7 +1,7 @@ (* Common code for ARM NEON header file, documentation and test case generators. - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. diff --git a/gcc/config/arm/netbsd-elf.h b/gcc/config/arm/netbsd-elf.h index 65460979410..414fcddca41 100644 --- a/gcc/config/arm/netbsd-elf.h +++ b/gcc/config/arm/netbsd-elf.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, NetBSD/arm ELF version. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. This file is part of GCC. diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 48e4ba86e7b..41a6ea4bb27 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for ARM and Thumb -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; This file is part of GCC. diff --git a/gcc/config/arm/rtems.h b/gcc/config/arm/rtems.h index e6dfa5303f6..9a2c9315f9e 100644 --- a/gcc/config/arm/rtems.h +++ b/gcc/config/arm/rtems.h @@ -1,5 +1,5 @@ /* Definitions for RTEMS based ARM systems using EABI. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/arm/semi.h b/gcc/config/arm/semi.h index 1c938d39197..4091cb771f9 100644 --- a/gcc/config/arm/semi.h +++ b/gcc/config/arm/semi.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. ARM on semi-hosted platform - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. Contributed by Richard Earnshaw (richard.earnshaw@arm.com) This file is part of GCC. diff --git a/gcc/config/arm/symbian.h b/gcc/config/arm/symbian.h index b1ef9118f28..fc9c350cd08 100644 --- a/gcc/config/arm/symbian.h +++ b/gcc/config/arm/symbian.h @@ -1,5 +1,5 @@ /* Configuration file for Symbian OS on ARM processors. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC This file is part of GCC. diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index fc7836fea7c..6dd2dc39621 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -1,5 +1,5 @@ ;; Machine description for ARM processor synchronization primitives. -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Written by Marcus Shawcroft (marcus.shawcroft@arm.com) ;; 64bit Atomics by Dave Gilbert (david.gilbert@linaro.org) ;; diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile index cf3416110d4..609570643ca 100644 --- a/gcc/config/arm/t-aprofile +++ b/gcc/config/arm/t-aprofile @@ -1,4 +1,4 @@ -# Copyright (C) 2012-2015 Free Software Foundation, Inc. +# Copyright (C) 2012-2016 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -98,6 +98,8 @@ MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1 # Arch Matches MULTILIB_MATCHES += march?armv8-a=march?armv8-a+crc +MULTILIB_MATCHES += march?armv8-a=march?armv8.1-a +MULTILIB_MATCHES += march?armv8-a=march?armv8.1-a+crc # FPU matches MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3 diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm index ab5b6e7d598..749a58d65eb 100644 --- a/gcc/config/arm/t-arm +++ b/gcc/config/arm/t-arm @@ -1,6 +1,6 @@ # Rules common to all arm targets # -# Copyright (C) 2004-2015 Free Software Foundation, Inc. +# Copyright (C) 2004-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/t-arm-elf b/gcc/config/arm/t-arm-elf index 9428290289a..fce3eed21f8 100644 --- a/gcc/config/arm/t-arm-elf +++ b/gcc/config/arm/t-arm-elf @@ -1,4 +1,4 @@ -# Copyright (C) 1998-2015 Free Software Foundation, Inc. +# Copyright (C) 1998-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/t-linux-eabi b/gcc/config/arm/t-linux-eabi index ae457d55fe5..582e39648ed 100644 --- a/gcc/config/arm/t-linux-eabi +++ b/gcc/config/arm/t-linux-eabi @@ -1,4 +1,4 @@ -# Copyright (C) 2005-2015 Free Software Foundation, Inc. +# Copyright (C) 2005-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/t-rtems b/gcc/config/arm/t-rtems index 3b6218150aa..02dcd65970f 100644 --- a/gcc/config/arm/t-rtems +++ b/gcc/config/arm/t-rtems @@ -1,7 +1,7 @@ # Custom RTEMS multilibs for ARM -MULTILIB_OPTIONS = mbig-endian mthumb march=armv6-m/march=armv7-a/march=armv7-r/march=armv7-m mfpu=neon/mfpu=vfpv3-d16/mfpu=fpv4-sp-d16 mfloat-abi=hard -MULTILIB_DIRNAMES = eb thumb armv6-m armv7-a armv7-r armv7-m neon vfpv3-d16 fpv4-sp-d16 hard +MULTILIB_OPTIONS = mbig-endian mthumb march=armv6-m/march=armv7-a/march=armv7-r/march=armv7-m/mcpu=cortex-m7 mfpu=neon/mfpu=vfpv3-d16/mfpu=fpv4-sp-d16/mfpu=fpv5-d16 mfloat-abi=hard +MULTILIB_DIRNAMES = eb thumb armv6-m armv7-a armv7-r armv7-m cortex-m7 neon vfpv3-d16 fpv4-sp-d16 fpv5-d16 hard # Enumeration of multilibs @@ -16,5 +16,6 @@ MULTILIB_REQUIRED += mthumb/march=armv7-a MULTILIB_REQUIRED += mthumb/march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard MULTILIB_REQUIRED += mthumb/march=armv7-r MULTILIB_REQUIRED += mthumb/march=armv7-m/mfpu=fpv4-sp-d16/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/mcpu=cortex-m7/mfpu=fpv5-d16/mfloat-abi=hard MULTILIB_REQUIRED += mthumb/march=armv7-m MULTILIB_REQUIRED += mthumb diff --git a/gcc/config/arm/t-symbian b/gcc/config/arm/t-symbian index 33af7a7fb3f..bb74192acb4 100644 --- a/gcc/config/arm/t-symbian +++ b/gcc/config/arm/t-symbian @@ -1,4 +1,4 @@ -# Copyright (C) 2004-2015 Free Software Foundation, Inc. +# Copyright (C) 2004-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/t-vxworks b/gcc/config/arm/t-vxworks index aa165258526..8320c100016 100644 --- a/gcc/config/arm/t-vxworks +++ b/gcc/config/arm/t-vxworks @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2015 Free Software Foundation, Inc. +# Copyright (C) 2003-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index 3847b33bd9c..072ed4da47a 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -1,5 +1,5 @@ ;; ARM Thumb-1 Machine Description -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index a724752a39c..3e762018e4d 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1,5 +1,5 @@ ;; ARM Thumb-2 Machine Description -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; Written by CodeSourcery, LLC. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index 73f482d8438..321ff898bd8 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -1,6 +1,6 @@ ;; Instruction Classification for ARM for GNU compiler. -;; Copyright (C) 1991-2015 Free Software Foundation, Inc. +;; Copyright (C) 1991-2016 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; This file is part of GCC. diff --git a/gcc/config/arm/uclinux-eabi.h b/gcc/config/arm/uclinux-eabi.h index 10d8f0c55fc..848a21eedec 100644 --- a/gcc/config/arm/uclinux-eabi.h +++ b/gcc/config/arm/uclinux-eabi.h @@ -1,5 +1,5 @@ /* Definitions for ARM EABI ucLinux - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. Contributed by Paul Brook <paul@codesourcery.com> This file is part of GCC. diff --git a/gcc/config/arm/uclinux-elf.h b/gcc/config/arm/uclinux-elf.h index 799a0c81a83..d8e8ec1a2bf 100644 --- a/gcc/config/arm/uclinux-elf.h +++ b/gcc/config/arm/uclinux-elf.h @@ -1,5 +1,5 @@ /* Definitions for ARM running ucLinux using ELF - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by Philip Blundell <pb@nexus.co.uk> This file is part of GCC. diff --git a/gcc/config/arm/unknown-elf.h b/gcc/config/arm/unknown-elf.h index d1d4f7a1c66..fafe0574ee1 100644 --- a/gcc/config/arm/unknown-elf.h +++ b/gcc/config/arm/unknown-elf.h @@ -1,5 +1,5 @@ /* Definitions for non-Linux based ARM systems using ELF - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. Contributed by Catherine Moore <clm@cygnus.com> This file is part of GCC. diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 67acafd075f..c17550cf869 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -1,5 +1,5 @@ ;; Unspec defintions. -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; This file is part of GCC. @@ -226,8 +226,10 @@ UNSPEC_VLD4_LANE UNSPEC_VMAX UNSPEC_VMAX_U + UNSPEC_VMAXNM UNSPEC_VMIN UNSPEC_VMIN_U + UNSPEC_VMINNM UNSPEC_VMLA UNSPEC_VMLA_LANE UNSPEC_VMLAL_S @@ -360,5 +362,7 @@ UNSPEC_NVRINTX UNSPEC_NVRINTA UNSPEC_NVRINTN + UNSPEC_VQRDMLAH + UNSPEC_VQRDMLSH ]) diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 31a14644af5..ce98f71164c 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -1,5 +1,5 @@ ;; Machine Description for shared bits common to IWMMXT and Neon. -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; Written by CodeSourcery. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index baeac622d29..ac5f3b862b5 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -1,5 +1,5 @@ ;; ARM VFP instruction patterns -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; Written by CodeSourcery. ;; ;; This file is part of GCC. @@ -1334,8 +1334,9 @@ [(match_operand:SDF 1 "register_operand" "<F_constraint>")] VCVT)))] "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>" - "vcvt<vrint_variant>%?.<su>32.<V_if_elem>\\t%0, %<V_reg>1" + "vcvt<vrint_variant>.<su>32.<V_if_elem>\\t%0, %<V_reg>1" [(set_attr "predicable" "no") + (set_attr "conds" "unconditional") (set_attr "type" "f_cvtf2i")] ) @@ -1366,6 +1367,18 @@ (set_attr "conds" "unconditional")] ) +;; Scalar forms for the IEEE-754 fmax()/fmin() functions +(define_insn "<fmaxmin><mode>3" + [(set (match_operand:SDF 0 "s_register_operand" "=<F_constraint>") + (unspec:SDF [(match_operand:SDF 1 "s_register_operand" "<F_constraint>") + (match_operand:SDF 2 "s_register_operand" "<F_constraint>")] + VMAXMINFNM))] + "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>" + "<fmaxmin_op>.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2" + [(set_attr "type" "f_minmax<vfp_type>") + (set_attr "conds" "unconditional")] +) + ;; Write Floating-point Status and Control Register. (define_insn "set_fpscr" [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR)] diff --git a/gcc/config/arm/vfp11.md b/gcc/config/arm/vfp11.md index ede25ee5b34..9fac4ce2cf6 100644 --- a/gcc/config/arm/vfp11.md +++ b/gcc/config/arm/vfp11.md @@ -1,5 +1,5 @@ ;; ARM VFP11 pipeline description -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; Written by CodeSourcery. ;; ;; This file is part of GCC. diff --git a/gcc/config/arm/vxworks.h b/gcc/config/arm/vxworks.h index 4b23fdf2954..4d846333601 100644 --- a/gcc/config/arm/vxworks.h +++ b/gcc/config/arm/vxworks.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for ARM with targeting the VXWorks run time environment. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by: Mike Stump <mrs@wrs.com> Brought up to date by CodeSourcery, LLC. diff --git a/gcc/config/arm/vxworks.opt b/gcc/config/arm/vxworks.opt index 975b5af221c..a29a9ab7c0e 100644 --- a/gcc/config/arm/vxworks.opt +++ b/gcc/config/arm/vxworks.opt @@ -1,6 +1,6 @@ ; ARM VxWorks options. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md index 703cfae7b07..8dfd8a188b9 100644 --- a/gcc/config/arm/xgene1.md +++ b/gcc/config/arm/xgene1.md @@ -1,5 +1,5 @@ ;; Machine description for AppliedMicro xgene1 core. -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Theobroma Systems Design und Consulting GmbH. ;; ;; This file is part of GCC. diff --git a/gcc/config/avr/avr-arch.h b/gcc/config/avr/avr-arch.h index 080b0b86dc4..42eaee56b7b 100644 --- a/gcc/config/avr/avr-arch.h +++ b/gcc/config/avr/avr-arch.h @@ -1,6 +1,6 @@ /* Definitions of types that are used to store AVR architecture and device information. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Georg-Johann Lay (avr@gjlay.de) This file is part of GCC. diff --git a/gcc/config/avr/avr-c.c b/gcc/config/avr/avr-c.c index a43525e6074..440e801ab0f 100644 --- a/gcc/config/avr/avr-c.c +++ b/gcc/config/avr/avr-c.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2015 Free Software Foundation, Inc. +/* Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by Anatoly Sokolov (aesok@post.ru) This file is part of GCC. diff --git a/gcc/config/avr/avr-devices.c b/gcc/config/avr/avr-devices.c index 58ef0e32d50..7d13ba4da66 100644 --- a/gcc/config/avr/avr-devices.c +++ b/gcc/config/avr/avr-devices.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2015 Free Software Foundation, Inc. +/* Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by Anatoly Sokolov (aesok@post.ru) This file is part of GCC. diff --git a/gcc/config/avr/avr-dimode.md b/gcc/config/avr/avr-dimode.md index a1cd6d91c6d..6956f08da43 100644 --- a/gcc/config/avr/avr-dimode.md +++ b/gcc/config/avr/avr-dimode.md @@ -1,6 +1,6 @@ ;; Machine description for GNU compiler, ;; for Atmel AVR micro controllers. -;; Copyright (C) 1998-2015 Free Software Foundation, Inc. +;; Copyright (C) 1998-2016 Free Software Foundation, Inc. ;; Contributed by Georg Lay (avr@gjlay.de) ;; ;; This file is part of GCC. diff --git a/gcc/config/avr/avr-fixed.md b/gcc/config/avr/avr-fixed.md index f0eff2ea98a..d5dad918de7 100644 --- a/gcc/config/avr/avr-fixed.md +++ b/gcc/config/avr/avr-fixed.md @@ -1,6 +1,6 @@ ;; This file contains instructions that support fixed-point operations ;; for Atmel AVR micro controllers. -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; Contributed by Sean D'Epagnier (sean@depagnier.com) ;; Georg-Johann Lay (avr@gjlay.de) diff --git a/gcc/config/avr/avr-log.c b/gcc/config/avr/avr-log.c index 887b90498d3..fe2cae46eff 100644 --- a/gcc/config/avr/avr-log.c +++ b/gcc/config/avr/avr-log.c @@ -1,5 +1,5 @@ /* Subroutines for log output for Atmel AVR back end. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Georg-Johann Lay (avr@gjlay.de) This file is part of GCC. diff --git a/gcc/config/avr/avr-mcus.def b/gcc/config/avr/avr-mcus.def index 560839d456a..6bcc6ff08ae 100644 --- a/gcc/config/avr/avr-mcus.def +++ b/gcc/config/avr/avr-mcus.def @@ -1,5 +1,5 @@ /* AVR MCUs. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/avr/avr-modes.def b/gcc/config/avr/avr-modes.def index a14daac19a0..58db7d75bd9 100644 --- a/gcc/config/avr/avr-modes.def +++ b/gcc/config/avr/avr-modes.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h index b5de42709e5..afd056b40f7 100644 --- a/gcc/config/avr/avr-protos.h +++ b/gcc/config/avr/avr-protos.h @@ -1,6 +1,6 @@ /* Prototypes for exported functions defined in avr.c - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Denis Chertykov (chertykov@gmail.com) This file is part of GCC. diff --git a/gcc/config/avr/avr-stdint.h b/gcc/config/avr/avr-stdint.h index 910ee9e2586..c321ba99041 100644 --- a/gcc/config/avr/avr-stdint.h +++ b/gcc/config/avr/avr-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using newlib. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c index 609a42b00e4..e5577726c96 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for ATMEL AVR micro controllers - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. Contributed by Denis Chertykov (chertykov@gmail.com) This file is part of GCC. @@ -2431,6 +2431,27 @@ avr_print_operand (FILE *file, rtx x, int code) } +/* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */ + +/* Prefer sequence of loads/stores for moves of size upto + two - two pairs of load/store instructions are always better + than the 5 instruction sequence for a loop (1 instruction + for loop counter setup, and 4 for the body of the loop). */ + +static bool +avr_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size, + unsigned int align ATTRIBUTE_UNUSED, + enum by_pieces_operation op, + bool speed_p) +{ + + if (op != MOVE_BY_PIECES || (speed_p && (size > (MOVE_MAX_PIECES)))) + return default_use_by_pieces_infrastructure_p (size, align, op, speed_p); + + return size <= (MOVE_MAX_PIECES); +} + + /* Worker function for `NOTICE_UPDATE_CC'. */ /* Update the condition code in the INSN. */ @@ -13763,6 +13784,10 @@ avr_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *arg, #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P #define TARGET_PRINT_OPERAND_PUNCT_VALID_P avr_print_operand_punct_valid_p +#undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P +#define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \ + avr_use_by_pieces_infrastructure_p + struct gcc_target targetm = TARGET_INITIALIZER; diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h index 74399647e0a..01da70867e4 100644 --- a/gcc/config/avr/avr.h +++ b/gcc/config/avr/avr.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for ATMEL AVR at90s8515, ATmega103/103L, ATmega603/603L microcontrollers. - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. Contributed by Denis Chertykov (chertykov@gmail.com) This file is part of GCC. @@ -453,7 +453,22 @@ typedef struct avr_args #undef WORD_REGISTER_OPERATIONS -#define MOVE_MAX 4 +/* Can move only a single byte from memory to reg in a + single instruction. */ + +#define MOVE_MAX 1 + +/* Allow upto two bytes moves to occur using by_pieces + infrastructure */ + +#define MOVE_MAX_PIECES 2 + +/* Set MOVE_RATIO to 3 to allow memory moves upto 4 bytes to happen + by pieces when optimizing for speed, like it did when MOVE_MAX_PIECES + was 4. When optimizing for size, allow memory moves upto 2 bytes. + Also see avr_use_by_pieces_infrastructure_p. */ + +#define MOVE_RATIO(speed) ((speed) ? 3 : 2) #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 1b39ddbd158..ff26f2e325b 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -1,6 +1,6 @@ ;; Machine description for GNU compiler, ;; for ATMEL AVR micro controllers. -;; Copyright (C) 1998-2015 Free Software Foundation, Inc. +;; Copyright (C) 1998-2016 Free Software Foundation, Inc. ;; Contributed by Denis Chertykov (chertykov@gmail.com) ;; This file is part of GCC. diff --git a/gcc/config/avr/avr.opt b/gcc/config/avr/avr.opt index 86245768064..8809b9b0cff 100644 --- a/gcc/config/avr/avr.opt +++ b/gcc/config/avr/avr.opt @@ -1,6 +1,6 @@ ; Options for the ATMEL AVR port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/avr/avrlibc.h b/gcc/config/avr/avrlibc.h index 59e64850b24..c1be595f37f 100644 --- a/gcc/config/avr/avrlibc.h +++ b/gcc/config/avr/avrlibc.h @@ -1,6 +1,6 @@ /* Definitions of target machine for the GNU compiler collection for Atmel AVR micro controller if configured for AVR-Libc. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Georg-Johann Lay (avr@gjlay.de) This file is part of GCC. diff --git a/gcc/config/avr/builtins.def b/gcc/config/avr/builtins.def index 007ff33d98c..a262dc5eaf6 100644 --- a/gcc/config/avr/builtins.def +++ b/gcc/config/avr/builtins.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/avr/constraints.md b/gcc/config/avr/constraints.md index 3819fcb6bb1..0c25592970c 100644 --- a/gcc/config/avr/constraints.md +++ b/gcc/config/avr/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for ATMEL AVR micro controllers. -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/avr/driver-avr.c b/gcc/config/avr/driver-avr.c index 75d7e6f6791..83ca3736195 100644 --- a/gcc/config/avr/driver-avr.c +++ b/gcc/config/avr/driver-avr.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by Georg-Johann Lay <avr@gjlay.de> This file is part of GCC. diff --git a/gcc/config/avr/elf.h b/gcc/config/avr/elf.h index 56fa0b2d4f0..45a99981a52 100644 --- a/gcc/config/avr/elf.h +++ b/gcc/config/avr/elf.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. +/* Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Georg-Johann Lay (avr@gjlay.de) This file is part of GCC. diff --git a/gcc/config/avr/gen-avr-mmcu-specs.c b/gcc/config/avr/gen-avr-mmcu-specs.c index d21125b39cc..de8680a8a1b 100644 --- a/gcc/config/avr/gen-avr-mmcu-specs.c +++ b/gcc/config/avr/gen-avr-mmcu-specs.c @@ -1,4 +1,4 @@ -/* Copyright (C) 1998-2015 Free Software Foundation, Inc. +/* Copyright (C) 1998-2016 Free Software Foundation, Inc. Contributed by Joern Rennecke This file is part of GCC. diff --git a/gcc/config/avr/gen-avr-mmcu-texi.c b/gcc/config/avr/gen-avr-mmcu-texi.c index ea0de49f9d7..8b2ef846051 100644 --- a/gcc/config/avr/gen-avr-mmcu-texi.c +++ b/gcc/config/avr/gen-avr-mmcu-texi.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Georg-Johann Lay (avr@gjlay.de) This file is part of GCC. @@ -100,7 +100,7 @@ int main (void) size_t i, n_mcus = 0; const avr_mcu_t *mcu; - printf ("@c Copyright (C) 2012-2015 Free Software Foundation, Inc.\n"); + printf ("@c Copyright (C) 2012-2016 Free Software Foundation, Inc.\n"); printf ("@c This is part of the GCC manual.\n"); printf ("@c For copying conditions, see the file " "gcc/doc/include/fdl.texi.\n\n"); diff --git a/gcc/config/avr/genmultilib.awk b/gcc/config/avr/genmultilib.awk index 903322edecb..e6b372885fb 100644 --- a/gcc/config/avr/genmultilib.awk +++ b/gcc/config/avr/genmultilib.awk @@ -1,4 +1,4 @@ -# Copyright (C) 2011-2015 Free Software Foundation, Inc. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/avr/predicates.md b/gcc/config/avr/predicates.md index 622bc0b0831..4570656e0c8 100644 --- a/gcc/config/avr/predicates.md +++ b/gcc/config/avr/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for ATMEL AVR micro controllers. -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/avr/rtems.h b/gcc/config/avr/rtems.h index 8ea06803f5c..73cdfd0a6cc 100644 --- a/gcc/config/avr/rtems.h +++ b/gcc/config/avr/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a AVR using ELF. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. Contributed by Ralf Corsepius (ralf.corsepius@rtems.org). This file is part of GCC. diff --git a/gcc/config/avr/specs.h b/gcc/config/avr/specs.h index e685ca244f8..52763cc607a 100644 --- a/gcc/config/avr/specs.h +++ b/gcc/config/avr/specs.h @@ -1,6 +1,6 @@ /* Specs definitions for Atmel AVR back end. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Georg-Johann Lay (avr@gjlay.de) This file is part of GCC. diff --git a/gcc/config/avr/stdfix.h b/gcc/config/avr/stdfix.h index 51f848b3bcd..8df41813e72 100644 --- a/gcc/config/avr/stdfix.h +++ b/gcc/config/avr/stdfix.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/avr/t-avr b/gcc/config/avr/t-avr index e2975612ed1..48b77013dde 100644 --- a/gcc/config/avr/t-avr +++ b/gcc/config/avr/t-avr @@ -1,4 +1,4 @@ -# Copyright (C) 2000-2015 Free Software Foundation, Inc. +# Copyright (C) 2000-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/avr/t-multilib b/gcc/config/avr/t-multilib index 4f80db757c7..c1f86e50a8b 100644 --- a/gcc/config/avr/t-multilib +++ b/gcc/config/avr/t-multilib @@ -3,7 +3,7 @@ # Generated from : ./gcc/config/avr/avr-mcus.def # Used by : tmake_file from Makefile and genmultilib -# Copyright (C) 2011-2015 Free Software Foundation, Inc. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/bfin/bfin-modes.def b/gcc/config/bfin/bfin-modes.def index 5de16fc9acc..a667fac5f61 100644 --- a/gcc/config/bfin/bfin-modes.def +++ b/gcc/config/bfin/bfin-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for Blackfin. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. Contributed by Analog Devices. This file is part of GCC. diff --git a/gcc/config/bfin/bfin-opts.h b/gcc/config/bfin/bfin-opts.h index 46568734ecf..30ef3004b97 100644 --- a/gcc/config/bfin/bfin-opts.h +++ b/gcc/config/bfin/bfin-opts.h @@ -1,5 +1,5 @@ /* Definitions for the Blackfin port needed for option handling. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/bfin/bfin-protos.h b/gcc/config/bfin/bfin-protos.h index a9f49c39225..ebd13d655af 100644 --- a/gcc/config/bfin/bfin-protos.h +++ b/gcc/config/bfin/bfin-protos.h @@ -1,5 +1,5 @@ /* Prototypes for Blackfin functions used in the md file & elsewhere. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GNU CC. diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c index d359fd4341b..120cd791927 100644 --- a/gcc/config/bfin/bfin.c +++ b/gcc/config/bfin/bfin.c @@ -1,5 +1,5 @@ /* The Blackfin code generation auxiliary output file. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. Contributed by Analog Devices. This file is part of GCC. diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h index 26ba7c2e015..a85c8c4c79a 100644 --- a/gcc/config/bfin/bfin.h +++ b/gcc/config/bfin/bfin.h @@ -1,5 +1,5 @@ /* Definitions for the Blackfin port. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. Contributed by Analog Devices. This file is part of GCC. diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md index 18152eef1e5..83f6dd3b456 100644 --- a/gcc/config/bfin/bfin.md +++ b/gcc/config/bfin/bfin.md @@ -1,5 +1,5 @@ ;;- Machine description for Blackfin for GNU compiler -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Analog Devices. ;; This file is part of GCC. diff --git a/gcc/config/bfin/bfin.opt b/gcc/config/bfin/bfin.opt index bf7ad5b0886..346b654c2dd 100644 --- a/gcc/config/bfin/bfin.opt +++ b/gcc/config/bfin/bfin.opt @@ -1,6 +1,6 @@ ; Options for the Blackfin port of the compiler ; -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/bfin/constraints.md b/gcc/config/bfin/constraints.md index d4115e842b8..95ecd9d1f2f 100644 --- a/gcc/config/bfin/constraints.md +++ b/gcc/config/bfin/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Blackfin -;; Copyright (C) 2008-2015 Free Software Foundation, Inc. +;; Copyright (C) 2008-2016 Free Software Foundation, Inc. ;; Contributed by Analog Devices ;; This file is part of GCC. diff --git a/gcc/config/bfin/elf.h b/gcc/config/bfin/elf.h index 5a408ef306c..0bb8496e170 100644 --- a/gcc/config/bfin/elf.h +++ b/gcc/config/bfin/elf.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2005-2015 Free Software Foundation, Inc. +/* Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/bfin/linux.h b/gcc/config/bfin/linux.h index dd053ec3c36..c02ff44c30a 100644 --- a/gcc/config/bfin/linux.h +++ b/gcc/config/bfin/linux.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/bfin/predicates.md b/gcc/config/bfin/predicates.md index 9b7da2aa67a..ecf75c7b57d 100644 --- a/gcc/config/bfin/predicates.md +++ b/gcc/config/bfin/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for the Blackfin. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Analog Devices. ;; ;; This file is part of GCC. diff --git a/gcc/config/bfin/print-sysroot-suffix.sh b/gcc/config/bfin/print-sysroot-suffix.sh index 2c73e67ea10..6b5cbc2ecc4 100644 --- a/gcc/config/bfin/print-sysroot-suffix.sh +++ b/gcc/config/bfin/print-sysroot-suffix.sh @@ -1,5 +1,5 @@ #!/bin/sh -# Copyright (C) 2007-2015 Free Software Foundation, Inc. +# Copyright (C) 2007-2016 Free Software Foundation, Inc. # This file is part of GCC. # GCC is free software; you can redistribute it and/or modify diff --git a/gcc/config/bfin/rtems.h b/gcc/config/bfin/rtems.h index 845fa8c9ef4..19bf415cfda 100644 --- a/gcc/config/bfin/rtems.h +++ b/gcc/config/bfin/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a bfin - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. Contributed by Ralf Corsépius (ralf.corsepius@rtems.org). This file is part of GCC. diff --git a/gcc/config/bfin/sync.md b/gcc/config/bfin/sync.md index 966ed3cee44..cb5aefd0b66 100644 --- a/gcc/config/bfin/sync.md +++ b/gcc/config/bfin/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for Blackfin synchronization instructions. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Analog Devices. ;; ;; This file is part of GCC. diff --git a/gcc/config/bfin/t-bfin-elf b/gcc/config/bfin/t-bfin-elf index 9a96075cc16..e05355a268a 100644 --- a/gcc/config/bfin/t-bfin-elf +++ b/gcc/config/bfin/t-bfin-elf @@ -1,4 +1,4 @@ -# Copyright (C) 2005-2015 Free Software Foundation, Inc. +# Copyright (C) 2005-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/bfin/t-bfin-linux b/gcc/config/bfin/t-bfin-linux index a47cc5fe7e1..421e7e26c9f 100644 --- a/gcc/config/bfin/t-bfin-linux +++ b/gcc/config/bfin/t-bfin-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2007-2015 Free Software Foundation, Inc. +# Copyright (C) 2007-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/bfin/t-bfin-uclinux b/gcc/config/bfin/t-bfin-uclinux index f0c4809f48e..54b6324294d 100644 --- a/gcc/config/bfin/t-bfin-uclinux +++ b/gcc/config/bfin/t-bfin-uclinux @@ -1,4 +1,4 @@ -# Copyright (C) 2007-2015 Free Software Foundation, Inc. +# Copyright (C) 2007-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/bfin/uclinux.h b/gcc/config/bfin/uclinux.h index 143f016b4eb..cca57d3c622 100644 --- a/gcc/config/bfin/uclinux.h +++ b/gcc/config/bfin/uclinux.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2005-2015 Free Software Foundation, Inc. +/* Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/c6x/c6x-isas.def b/gcc/config/c6x/c6x-isas.def index 86d563d236f..56b493db486 100644 --- a/gcc/config/c6x/c6x-isas.def +++ b/gcc/config/c6x/c6x-isas.def @@ -1,5 +1,5 @@ /* C6X ISA names. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/c6x/c6x-modes.def b/gcc/config/c6x/c6x-modes.def index e8821ad1409..7164b44ee27 100644 --- a/gcc/config/c6x/c6x-modes.def +++ b/gcc/config/c6x/c6x-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for TI C6x. - Copyright (C) 2010-2015 Free Software Foundation, Inc. + Copyright (C) 2010-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/c6x/c6x-mult.md b/gcc/config/c6x/c6x-mult.md index f023a6754a8..2e0d6d4b5df 100644 --- a/gcc/config/c6x/c6x-mult.md +++ b/gcc/config/c6x/c6x-mult.md @@ -3,7 +3,7 @@ ;; Multiplication patterns for TI C6X. ;; This file is processed by genmult.sh to produce two variants of each ;; pattern, a normal one and a real_mult variant for modulo scheduling. -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; @@ -424,7 +424,7 @@ ;; Multiplication patterns for TI C6X. ;; This file is processed by genmult.sh to produce two variants of each ;; pattern, a normal one and a real_mult variant for modulo scheduling. -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; diff --git a/gcc/config/c6x/c6x-mult.md.in b/gcc/config/c6x/c6x-mult.md.in index 780aa221847..9f008321d77 100644 --- a/gcc/config/c6x/c6x-mult.md.in +++ b/gcc/config/c6x/c6x-mult.md.in @@ -1,7 +1,7 @@ ;; Multiplication patterns for TI C6X. ;; This file is processed by genmult.sh to produce two variants of each ;; pattern, a normal one and a real_mult variant for modulo scheduling. -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; diff --git a/gcc/config/c6x/c6x-opts.h b/gcc/config/c6x/c6x-opts.h index 1adbc50a38f..09d8bb31970 100644 --- a/gcc/config/c6x/c6x-opts.h +++ b/gcc/config/c6x/c6x-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for TI C6X. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/c6x/c6x-protos.h b/gcc/config/c6x/c6x-protos.h index aba13252865..45c8e4c83b9 100644 --- a/gcc/config/c6x/c6x-protos.h +++ b/gcc/config/c6x/c6x-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in c6x.c. - Copyright (C) 2010-2015 Free Software Foundation, Inc. + Copyright (C) 2010-2016 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. diff --git a/gcc/config/c6x/c6x-sched.md b/gcc/config/c6x/c6x-sched.md index 4bbb61d35f8..80bbde05f60 100644 --- a/gcc/config/c6x/c6x-sched.md +++ b/gcc/config/c6x/c6x-sched.md @@ -4,7 +4,7 @@ ;; Definitions for side 1, cross n ;; Scheduling description for TI C6X. -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; @@ -237,7 +237,7 @@ ;; Definitions for side 2, cross n ;; Scheduling description for TI C6X. -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; @@ -470,7 +470,7 @@ ;; Definitions for side 1, cross y ;; Scheduling description for TI C6X. -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; @@ -703,7 +703,7 @@ ;; Definitions for side 2, cross y ;; Scheduling description for TI C6X. -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; diff --git a/gcc/config/c6x/c6x-sched.md.in b/gcc/config/c6x/c6x-sched.md.in index a07c311c7b7..eb9abc26c41 100644 --- a/gcc/config/c6x/c6x-sched.md.in +++ b/gcc/config/c6x/c6x-sched.md.in @@ -1,5 +1,5 @@ ;; Scheduling description for TI C6X. -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. ;; diff --git a/gcc/config/c6x/c6x-tables.opt b/gcc/config/c6x/c6x-tables.opt index 7c9207503d2..89d093c968c 100644 --- a/gcc/config/c6x/c6x-tables.opt +++ b/gcc/config/c6x/c6x-tables.opt @@ -1,7 +1,7 @@ ; -*- buffer-read-only: t -*- ; Generated automatically by genopt.sh from c6x-isas.def. ; -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c index f0d274e765c..4cbe63c9bf2 100644 --- a/gcc/config/c6x/c6x.c +++ b/gcc/config/c6x/c6x.c @@ -1,5 +1,5 @@ /* Target Code for TI C6X - Copyright (C) 2010-2015 Free Software Foundation, Inc. + Copyright (C) 2010-2016 Free Software Foundation, Inc. Contributed by Andrew Jenner <andrew@codesourcery.com> Contributed by Bernd Schmidt <bernds@codesourcery.com> diff --git a/gcc/config/c6x/c6x.h b/gcc/config/c6x/c6x.h index 1c304697db2..3209bf66815 100644 --- a/gcc/config/c6x/c6x.h +++ b/gcc/config/c6x/c6x.h @@ -1,5 +1,5 @@ /* Target Definitions for TI C6X. - Copyright (C) 2010-2015 Free Software Foundation, Inc. + Copyright (C) 2010-2016 Free Software Foundation, Inc. Contributed by Andrew Jenner <andrew@codesourcery.com> Contributed by Bernd Schmidt <bernds@codesourcery.com> diff --git a/gcc/config/c6x/c6x.md b/gcc/config/c6x/c6x.md index fa8958719ef..51571e32c7d 100644 --- a/gcc/config/c6x/c6x.md +++ b/gcc/config/c6x/c6x.md @@ -1,5 +1,5 @@ ;; Machine description for TI C6X. -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Andrew Jenner <andrew@codesourcery.com> ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. diff --git a/gcc/config/c6x/c6x.opt b/gcc/config/c6x/c6x.opt index 72fd8fb6dad..e7f079a5672 100644 --- a/gcc/config/c6x/c6x.opt +++ b/gcc/config/c6x/c6x.opt @@ -1,5 +1,5 @@ ; Option definitions for TI C6X. -; Copyright (C) 2010-2015 Free Software Foundation, Inc. +; Copyright (C) 2010-2016 Free Software Foundation, Inc. ; Contributed by Bernd Schmidt <bernds@codesourcery.com> ; Contributed by CodeSourcery. ; diff --git a/gcc/config/c6x/c6x_intrinsics.h b/gcc/config/c6x/c6x_intrinsics.h index bb6edada9c3..c73e3f55cdf 100644 --- a/gcc/config/c6x/c6x_intrinsics.h +++ b/gcc/config/c6x/c6x_intrinsics.h @@ -1,6 +1,6 @@ /* Intrinsics for TI C6X. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. diff --git a/gcc/config/c6x/constraints.md b/gcc/config/c6x/constraints.md index b8cdc0e65bd..d34e214337b 100644 --- a/gcc/config/c6x/constraints.md +++ b/gcc/config/c6x/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for TI C6X. -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Andrew Jenner <andrew@codesourcery.com> ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; Contributed by CodeSourcery. diff --git a/gcc/config/c6x/elf-common.h b/gcc/config/c6x/elf-common.h index 2a7cd524534..0d7b283e277 100644 --- a/gcc/config/c6x/elf-common.h +++ b/gcc/config/c6x/elf-common.h @@ -1,5 +1,5 @@ /* ELF definitions for TI C6X - Copyright (C) 2010-2015 Free Software Foundation, Inc. + Copyright (C) 2010-2016 Free Software Foundation, Inc. Contributed by Andrew Jenner <andrew@codesourcery.com> Contributed by Bernd Schmidt <bernds@codesourcery.com> diff --git a/gcc/config/c6x/elf.h b/gcc/config/c6x/elf.h index 9699c5fa2d1..aa87b8906f8 100644 --- a/gcc/config/c6x/elf.h +++ b/gcc/config/c6x/elf.h @@ -1,5 +1,5 @@ /* ELF definitions for TI C6X - Copyright (C) 2010-2015 Free Software Foundation, Inc. + Copyright (C) 2010-2016 Free Software Foundation, Inc. Contributed by Andrew Jenner <andrew@codesourcery.com> Contributed by Bernd Schmidt <bernds@codesourcery.com> diff --git a/gcc/config/c6x/genmult.sh b/gcc/config/c6x/genmult.sh index ba99a400606..d848887b79e 100644 --- a/gcc/config/c6x/genmult.sh +++ b/gcc/config/c6x/genmult.sh @@ -2,7 +2,7 @@ # Generate c6x-mult.md from c6x-mult.md.in # The input file is passed as an argument. -# Copyright (C) 2011-2015 Free Software Foundation, Inc. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. #This file is part of GCC. diff --git a/gcc/config/c6x/genopt.sh b/gcc/config/c6x/genopt.sh index 04f924ce2c7..61d560c263d 100644 --- a/gcc/config/c6x/genopt.sh +++ b/gcc/config/c6x/genopt.sh @@ -1,6 +1,6 @@ #!/bin/sh # Generate c6x-tables.opt from the lists in *.def. -# Copyright (C) 2011-2015 Free Software Foundation, Inc. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -22,7 +22,7 @@ cat <<EOF ; -*- buffer-read-only: t -*- ; Generated automatically by genopt.sh from c6x-isas.def. ; -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/c6x/gensched.sh b/gcc/config/c6x/gensched.sh index e2676f94721..38710ff7fea 100644 --- a/gcc/config/c6x/gensched.sh +++ b/gcc/config/c6x/gensched.sh @@ -2,7 +2,7 @@ # Generate c6x-sched.md from c6x-sched.md.in # The input file is passed as an argument. -# Copyright (C) 2010-2015 Free Software Foundation, Inc. +# Copyright (C) 2010-2016 Free Software Foundation, Inc. #This file is part of GCC. diff --git a/gcc/config/c6x/predicates.md b/gcc/config/c6x/predicates.md index f3e50587f5a..9db6002ea13 100644 --- a/gcc/config/c6x/predicates.md +++ b/gcc/config/c6x/predicates.md @@ -1,5 +1,5 @@ /* Predicates for TI C6X - Copyright (C) 2010-2015 Free Software Foundation, Inc. + Copyright (C) 2010-2016 Free Software Foundation, Inc. Contributed by Andrew Jenner <andrew@codesourcery.com> Contributed by Bernd Schmidt <bernds@codesourcery.com> diff --git a/gcc/config/c6x/sync.md b/gcc/config/c6x/sync.md index d7c0aee6a97..c2fbf399a96 100644 --- a/gcc/config/c6x/sync.md +++ b/gcc/config/c6x/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for C6X synchronization instructions. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/c6x/t-c6x b/gcc/config/c6x/t-c6x index 128b5ac13d3..eea10943616 100644 --- a/gcc/config/c6x/t-c6x +++ b/gcc/config/c6x/t-c6x @@ -1,5 +1,5 @@ # Target Makefile Fragment for TI C6X. -# Copyright (C) 2010-2015 Free Software Foundation, Inc. +# Copyright (C) 2010-2016 Free Software Foundation, Inc. # Contributed by CodeSourcery. # # This file is part of GCC. diff --git a/gcc/config/c6x/t-c6x-elf b/gcc/config/c6x/t-c6x-elf index aa6e14c687b..4e487115fd3 100644 --- a/gcc/config/c6x/t-c6x-elf +++ b/gcc/config/c6x/t-c6x-elf @@ -1,5 +1,5 @@ # Target Makefile Fragment for TI C6X using ELF. -# Copyright (C) 2010-2015 Free Software Foundation, Inc. +# Copyright (C) 2010-2016 Free Software Foundation, Inc. # Contributed by CodeSourcery. # # This file is part of GCC. diff --git a/gcc/config/c6x/uclinux-elf.h b/gcc/config/c6x/uclinux-elf.h index 5a04b9dc5d2..66c86f9427a 100644 --- a/gcc/config/c6x/uclinux-elf.h +++ b/gcc/config/c6x/uclinux-elf.h @@ -1,5 +1,5 @@ /* Definitions for TI C6X running ucLinux using ELF - Copyright (C) 2010-2015 Free Software Foundation, Inc. + Copyright (C) 2010-2016 Free Software Foundation, Inc. Contributed by Andrew Jenner <andrew@codesourcery.com> Contributed by Bernd Schmidt <bernds@codesourcery.com> diff --git a/gcc/config/cr16/constraints.md b/gcc/config/cr16/constraints.md index 5725e155714..b8a0bc4f98f 100644 --- a/gcc/config/cr16/constraints.md +++ b/gcc/config/cr16/constraints.md @@ -1,5 +1,5 @@ ;; Predicates of machine description for CR16. -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by KPIT Cummins Infosystems Limited. ;; ;; This file is part of GCC. diff --git a/gcc/config/cr16/cr16-protos.h b/gcc/config/cr16/cr16-protos.h index 6b3d60c8159..3d948fc75ed 100644 --- a/gcc/config/cr16/cr16-protos.h +++ b/gcc/config/cr16/cr16-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in cr16.c - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by KPIT Cummins Infosystems Limited. This file is part of GCC. diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c index 8fe836940bd..141b8bc895f 100644 --- a/gcc/config/cr16/cr16.c +++ b/gcc/config/cr16/cr16.c @@ -1,5 +1,5 @@ /* Output routines for CR16 processor. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by KPIT Cummins Infosystems Limited. This file is part of GCC. diff --git a/gcc/config/cr16/cr16.h b/gcc/config/cr16/cr16.h index 5767be9f44f..2d08c2b2fa8 100644 --- a/gcc/config/cr16/cr16.h +++ b/gcc/config/cr16/cr16.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for CR16. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by KPIT Cummins Infosystems Limited. This file is part of GCC. diff --git a/gcc/config/cr16/cr16.md b/gcc/config/cr16/cr16.md index 7765fe7f570..b2da93b572c 100644 --- a/gcc/config/cr16/cr16.md +++ b/gcc/config/cr16/cr16.md @@ -1,5 +1,5 @@ ;; GCC machine description for CR16. -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by KPIT Cummins Infosystems Limited. ;; This file is part of GCC. diff --git a/gcc/config/cr16/cr16.opt b/gcc/config/cr16/cr16.opt index 02d8609e914..3fb6cefce90 100644 --- a/gcc/config/cr16/cr16.opt +++ b/gcc/config/cr16/cr16.opt @@ -1,5 +1,5 @@ ; Options for the National Semiconductor CR16 port of the compiler. -; Copyright (C) 2012-2015 Free Software Foundation, Inc. +; Copyright (C) 2012-2016 Free Software Foundation, Inc. ; Contributed by KPIT Cummins Infosystems Limited. ; ; This file is part of GCC. diff --git a/gcc/config/cr16/predicates.md b/gcc/config/cr16/predicates.md index 73d3d3b2a77..ba15762c84a 100644 --- a/gcc/config/cr16/predicates.md +++ b/gcc/config/cr16/predicates.md @@ -1,5 +1,5 @@ ;; Predicates of machine description for CR16. -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by KPIT Cummins Infosystems Limited. ;; ;; This file is part of GCC. diff --git a/gcc/config/cr16/t-cr16 b/gcc/config/cr16/t-cr16 index f46651cc8c6..ac40f643bfa 100644 --- a/gcc/config/cr16/t-cr16 +++ b/gcc/config/cr16/t-cr16 @@ -1,5 +1,5 @@ # CR16 Target Makefile -# Copyright (C) 2012-2015 Free Software Foundation, Inc. +# Copyright (C) 2012-2016 Free Software Foundation, Inc. # Contributed by KPIT Cummins Infosystems Limited. # # This file is part of GCC. diff --git a/gcc/config/cris/constraints.md b/gcc/config/cris/constraints.md index 8c415f733d0..9269bf0ac1a 100644 --- a/gcc/config/cris/constraints.md +++ b/gcc/config/cris/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for CRIS. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/cris/cris-protos.h b/gcc/config/cris/cris-protos.h index c28ac2b3764..906816672d4 100644 --- a/gcc/config/cris/cris-protos.h +++ b/gcc/config/cris/cris-protos.h @@ -1,5 +1,5 @@ /* Definitions for GCC. Part of the machine description for CRIS. - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. Contributed by Axis Communications. This file is part of GCC. diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c index 6e40ea14877..0df3c5d7e4d 100644 --- a/gcc/config/cris/cris.c +++ b/gcc/config/cris/cris.c @@ -1,5 +1,5 @@ /* Definitions for GCC. Part of the machine description for CRIS. - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. Contributed by Axis Communications. Written by Hans-Peter Nilsson. This file is part of GCC. diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index 1561cd1f0e7..6cf8c3e86da 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -1,5 +1,5 @@ /* Definitions for GCC. Part of the machine description for CRIS. - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. Contributed by Axis Communications. Written by Hans-Peter Nilsson. This file is part of GCC. diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md index b90d6b1b3a1..59a386252c6 100644 --- a/gcc/config/cris/cris.md +++ b/gcc/config/cris/cris.md @@ -1,5 +1,5 @@ ;; GCC machine description for CRIS cpu cores. -;; Copyright (C) 1998-2015 Free Software Foundation, Inc. +;; Copyright (C) 1998-2016 Free Software Foundation, Inc. ;; Contributed by Axis Communications. ;; This file is part of GCC. diff --git a/gcc/config/cris/cris.opt b/gcc/config/cris/cris.opt index 63f8a779068..918c824368b 100644 --- a/gcc/config/cris/cris.opt +++ b/gcc/config/cris/cris.opt @@ -1,6 +1,6 @@ ; Options for the CRIS port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/cris/elf.opt b/gcc/config/cris/elf.opt index a073afe44e0..15f92d9f92c 100644 --- a/gcc/config/cris/elf.opt +++ b/gcc/config/cris/elf.opt @@ -1,6 +1,6 @@ ; ELF-specific options for the CRIS port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/cris/linux.h b/gcc/config/cris/linux.h index 262aac5c16c..ca1d904e1d4 100644 --- a/gcc/config/cris/linux.h +++ b/gcc/config/cris/linux.h @@ -1,5 +1,5 @@ /* Definitions for GCC. Part of the machine description for CRIS. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Axis Communications. Written by Hans-Peter Nilsson. This file is part of GCC. diff --git a/gcc/config/cris/linux.opt b/gcc/config/cris/linux.opt index 84ee07457b2..883d6bbbc9c 100644 --- a/gcc/config/cris/linux.opt +++ b/gcc/config/cris/linux.opt @@ -1,6 +1,6 @@ ; GNU/Linux-specific options for the CRIS port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/cris/predicates.md b/gcc/config/cris/predicates.md index 946d425ec1b..94ccd2c9363 100644 --- a/gcc/config/cris/predicates.md +++ b/gcc/config/cris/predicates.md @@ -1,5 +1,5 @@ ;; Operand and operator predicates for the GCC CRIS port. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; This file is part of GCC. ;; diff --git a/gcc/config/cris/sync.md b/gcc/config/cris/sync.md index 5b21d9de271..11740c556a9 100644 --- a/gcc/config/cris/sync.md +++ b/gcc/config/cris/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for CRIS atomic memory sequences. -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/cris/t-cris b/gcc/config/cris/t-cris index 00517edf5ce..b0cae8d5366 100644 --- a/gcc/config/cris/t-cris +++ b/gcc/config/cris/t-cris @@ -3,7 +3,7 @@ # # The Makefile fragment to include when compiling gcc et al for CRIS. # -# Copyright (C) 2001-2015 Free Software Foundation, Inc. +# Copyright (C) 2001-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/cris/t-elfmulti b/gcc/config/cris/t-elfmulti index e4c9a893905..4fc7a8c2bae 100644 --- a/gcc/config/cris/t-elfmulti +++ b/gcc/config/cris/t-elfmulti @@ -1,4 +1,4 @@ -# Copyright (C) 2001-2015 Free Software Foundation, Inc. +# Copyright (C) 2001-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/darwin-c.c b/gcc/config/darwin-c.c index 8f098f7d853..23ec1804195 100644 --- a/gcc/config/darwin-c.c +++ b/gcc/config/darwin-c.c @@ -1,5 +1,5 @@ /* Darwin support needed only by C/C++ frontends. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/darwin-driver.c b/gcc/config/darwin-driver.c index 597e0c4d087..db8d72c2a81 100644 --- a/gcc/config/darwin-driver.c +++ b/gcc/config/darwin-driver.c @@ -1,5 +1,5 @@ /* Additional functions for the GCC driver on Darwin native. - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/darwin-f.c b/gcc/config/darwin-f.c index 5712659ad67..0dba3762f9e 100644 --- a/gcc/config/darwin-f.c +++ b/gcc/config/darwin-f.c @@ -1,5 +1,5 @@ /* Darwin support needed only by Fortran frontends. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. Contributed by Daniel Franke. This file is part of GCC. diff --git a/gcc/config/darwin-ppc-ldouble-patch.def b/gcc/config/darwin-ppc-ldouble-patch.def index 0c09931191b..7160bf7980c 100644 --- a/gcc/config/darwin-ppc-ldouble-patch.def +++ b/gcc/config/darwin-ppc-ldouble-patch.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2015 Free Software Foundation, Inc. +/* Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/darwin-protos.h b/gcc/config/darwin-protos.h index 249b9c1de7a..62c72596461 100644 --- a/gcc/config/darwin-protos.h +++ b/gcc/config/darwin-protos.h @@ -1,5 +1,5 @@ /* Prototypes. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/darwin-sections.def b/gcc/config/darwin-sections.def index bb2999ef1fe..cbf3e41e9ac 100644 --- a/gcc/config/darwin-sections.def +++ b/gcc/config/darwin-sections.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2005-2015 Free Software Foundation, Inc. +/* Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c index 1f421c36489..0055d805441 100644 --- a/gcc/config/darwin.c +++ b/gcc/config/darwin.c @@ -1,5 +1,5 @@ /* Functions for generic Darwin as target machine for GNU C compiler. - Copyright (C) 1989-2015 Free Software Foundation, Inc. + Copyright (C) 1989-2016 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/darwin.h b/gcc/config/darwin.h index 7d093c9077a..9f686d3ad3a 100644 --- a/gcc/config/darwin.h +++ b/gcc/config/darwin.h @@ -1,5 +1,5 @@ /* Target definitions for Darwin (Mac OS X) systems. - Copyright (C) 1989-2015 Free Software Foundation, Inc. + Copyright (C) 1989-2016 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. @@ -400,12 +400,13 @@ extern GTY(()) int darwin_ms_struct; #define ASM_DEBUG_SPEC "%{g*:%{!g0:%{!gdwarf*:--gstabs}}}" -/* We still allow output of STABS. */ - +/* We still allow output of STABS if the assembler supports it. */ +#ifdef HAVE_AS_STABS_DIRECTIVE #define DBX_DEBUGGING_INFO 1 +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG +#endif #define DWARF2_DEBUGGING_INFO 1 -#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG #define DEBUG_FRAME_SECTION "__DWARF,__debug_frame,regular,debug" #define DEBUG_INFO_SECTION "__DWARF,__debug_info,regular,debug" diff --git a/gcc/config/darwin.opt b/gcc/config/darwin.opt index 518a6d14901..50937315438 100644 --- a/gcc/config/darwin.opt +++ b/gcc/config/darwin.opt @@ -1,6 +1,6 @@ ; Processor-independent options for Darwin. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/darwin10.h b/gcc/config/darwin10.h index 116fe20de78..5829d788eb9 100644 --- a/gcc/config/darwin10.h +++ b/gcc/config/darwin10.h @@ -1,5 +1,5 @@ /* Target definitions for Darwin (Mac OS X) systems. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by Jack Howarth <howarth@bromo.med.uc.edu>. This file is part of GCC. diff --git a/gcc/config/darwin12.h b/gcc/config/darwin12.h index 506364acc4b..e3669826dc3 100644 --- a/gcc/config/darwin12.h +++ b/gcc/config/darwin12.h @@ -1,5 +1,5 @@ /* Target definitions for Darwin (Mac OS X) systems. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by Jack Howarth <howarth.at.gcc@gmail.com>. This file is part of GCC. diff --git a/gcc/config/darwin9.h b/gcc/config/darwin9.h index 309c835b6ee..f989ec781eb 100644 --- a/gcc/config/darwin9.h +++ b/gcc/config/darwin9.h @@ -1,5 +1,5 @@ /* Target definitions for Darwin (Mac OS X) systems. - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. Contributed by Apple Inc. This file is part of GCC. diff --git a/gcc/config/dbx.h b/gcc/config/dbx.h index ae40a4fbd0a..01b44afbcf9 100644 --- a/gcc/config/dbx.h +++ b/gcc/config/dbx.h @@ -1,5 +1,5 @@ /* Prefer DBX (stabs) debugging information. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/dbxcoff.h b/gcc/config/dbxcoff.h index 5074be03b0d..2335544b423 100644 --- a/gcc/config/dbxcoff.h +++ b/gcc/config/dbxcoff.h @@ -1,5 +1,5 @@ /* Definitions needed when using stabs embedded in COFF sections. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/dbxelf.h b/gcc/config/dbxelf.h index b4b4a247dcb..0bff1931107 100644 --- a/gcc/config/dbxelf.h +++ b/gcc/config/dbxelf.h @@ -1,5 +1,5 @@ /* Definitions needed when using stabs embedded in ELF sections. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/default-c.c b/gcc/config/default-c.c index 7570c985712..1f90b052e39 100644 --- a/gcc/config/default-c.c +++ b/gcc/config/default-c.c @@ -1,5 +1,5 @@ /* Default C-family target hooks initializer. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/dragonfly-stdint.h b/gcc/config/dragonfly-stdint.h index 5e571ffd85d..23e94752d3d 100644 --- a/gcc/config/dragonfly-stdint.h +++ b/gcc/config/dragonfly-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types for DragonFly systems. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by John Marino <gnugcc@marino.st> This file is part of GCC. diff --git a/gcc/config/dragonfly.h b/gcc/config/dragonfly.h index bdc2e768138..03f1ffee965 100644 --- a/gcc/config/dragonfly.h +++ b/gcc/config/dragonfly.h @@ -1,5 +1,5 @@ /* Base configuration file for all DragonFly targets. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by John Marino <gnugcc@marino.st> This file is part of GCC. diff --git a/gcc/config/dragonfly.opt b/gcc/config/dragonfly.opt index ddbebea656e..cce5365cf35 100644 --- a/gcc/config/dragonfly.opt +++ b/gcc/config/dragonfly.opt @@ -1,6 +1,6 @@ ; DragonFly BSD options. -; Copyright (C) 2014-2015 Free Software Foundation, Inc. +; Copyright (C) 2014-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/elfos.h b/gcc/config/elfos.h index bcc3870d93c..d32055b278e 100644 --- a/gcc/config/elfos.h +++ b/gcc/config/elfos.h @@ -1,6 +1,6 @@ /* elfos.h -- operating system specific defines to be used when targeting GCC for some generic ELF system - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. Based on svr4.h contributed by Ron Guilmette (rfg@netcom.com). This file is part of GCC. diff --git a/gcc/config/epiphany/constraints.md b/gcc/config/epiphany/constraints.md index 9c05e4c9996..656c6158caf 100644 --- a/gcc/config/epiphany/constraints.md +++ b/gcc/config/epiphany/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Adaptiva epiphany -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; Contributed by Embecosm on behalf of Adapteva, Inc. ;; This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany-modes.def b/gcc/config/epiphany/epiphany-modes.def index dc0e77dd08e..09e4a04cc4f 100644 --- a/gcc/config/epiphany/epiphany-modes.def +++ b/gcc/config/epiphany/epiphany-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, Adapteva Epiphany cpu. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany-protos.h b/gcc/config/epiphany/epiphany-protos.h index 2ea3ba1e4d6..0038aae573f 100644 --- a/gcc/config/epiphany/epiphany-protos.h +++ b/gcc/config/epiphany/epiphany-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, EPIPHANY cpu. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany-sched.md b/gcc/config/epiphany/epiphany-sched.md index 703237059fe..e116e4b2815 100644 --- a/gcc/config/epiphany/epiphany-sched.md +++ b/gcc/config/epiphany/epiphany-sched.md @@ -1,5 +1,5 @@ ;; DFA scheduling description for EPIPHANY -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; Contributed by Embecosm on behalf of Adapteva, Inc. ;; This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany.c b/gcc/config/epiphany/epiphany.c index 1313fb44cbd..f09a65769ca 100644 --- a/gcc/config/epiphany/epiphany.c +++ b/gcc/config/epiphany/epiphany.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on the EPIPHANY cpu. - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany.h b/gcc/config/epiphany/epiphany.h index 62a3d9d7ee6..9e7ee506134 100644 --- a/gcc/config/epiphany/epiphany.h +++ b/gcc/config/epiphany/epiphany.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, Argonaut EPIPHANY cpu. - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany.md b/gcc/config/epiphany/epiphany.md index 4c8b5d6af83..15a61513e97 100644 --- a/gcc/config/epiphany/epiphany.md +++ b/gcc/config/epiphany/epiphany.md @@ -1,5 +1,5 @@ ;; Machine description of the Adaptiva epiphany cpu for GNU C compiler -;; Copyright (C) 1994-2015 Free Software Foundation, Inc. +;; Copyright (C) 1994-2016 Free Software Foundation, Inc. ;; Contributed by Embecosm on behalf of Adapteva, Inc. ;; This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany.opt b/gcc/config/epiphany/epiphany.opt index 297ceb81a39..158fe8247a6 100644 --- a/gcc/config/epiphany/epiphany.opt +++ b/gcc/config/epiphany/epiphany.opt @@ -1,6 +1,6 @@ ; Options for the Adapteva EPIPHANY port of the compiler ; -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; Contributed by Embecosm on behalf of Adapteva, Inc. ; ; This file is part of GCC. diff --git a/gcc/config/epiphany/epiphany_intrinsics.h b/gcc/config/epiphany/epiphany_intrinsics.h index 36cad23ee5c..738303b3da6 100644 --- a/gcc/config/epiphany/epiphany_intrinsics.h +++ b/gcc/config/epiphany/epiphany_intrinsics.h @@ -1,5 +1,5 @@ /* Epiphany intrinsic functions - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/mode-switch-use.c b/gcc/config/epiphany/mode-switch-use.c index 589ca336bc3..d7fbae31868 100644 --- a/gcc/config/epiphany/mode-switch-use.c +++ b/gcc/config/epiphany/mode-switch-use.c @@ -1,6 +1,6 @@ /* Insert USEs in instructions that require mode switching. This should probably be merged into mode-switching.c . - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/predicates.md b/gcc/config/epiphany/predicates.md index 5b20917263d..99fab6b6efe 100644 --- a/gcc/config/epiphany/predicates.md +++ b/gcc/config/epiphany/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for code generation on the EPIPHANY cpu. -;; Copyright (C) 1994-2015 Free Software Foundation, Inc. +;; Copyright (C) 1994-2016 Free Software Foundation, Inc. ;; Contributed by Embecosm on behalf of Adapteva, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/epiphany/resolve-sw-modes.c b/gcc/config/epiphany/resolve-sw-modes.c index 4f3d1b01344..603886b57ce 100644 --- a/gcc/config/epiphany/resolve-sw-modes.c +++ b/gcc/config/epiphany/resolve-sw-modes.c @@ -1,5 +1,5 @@ /* Mode switching cleanup pass for the EPIPHANY cpu. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of GCC. diff --git a/gcc/config/epiphany/t-epiphany b/gcc/config/epiphany/t-epiphany index b09af49683a..9f45e23469e 100644 --- a/gcc/config/epiphany/t-epiphany +++ b/gcc/config/epiphany/t-epiphany @@ -1,4 +1,4 @@ -# Copyright (C) 1997-2015 Free Software Foundation, Inc. +# Copyright (C) 1997-2016 Free Software Foundation, Inc. # Contributed by Embecosm on behalf of Adapteva, Inc. # # This file is part of GCC. diff --git a/gcc/config/flat.h b/gcc/config/flat.h index bdad8211bd9..a0d9f999077 100644 --- a/gcc/config/flat.h +++ b/gcc/config/flat.h @@ -1,5 +1,5 @@ /* Defines to be used for targets that support flat executables. - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/fr30/constraints.md b/gcc/config/fr30/constraints.md index 05f682f3876..605b3afa1ec 100644 --- a/gcc/config/fr30/constraints.md +++ b/gcc/config/fr30/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for the FR30. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/fr30/fr30-protos.h b/gcc/config/fr30/fr30-protos.h index 0feac275ccc..f7164c7026b 100644 --- a/gcc/config/fr30/fr30-protos.h +++ b/gcc/config/fr30/fr30-protos.h @@ -1,5 +1,5 @@ /* Prototypes for fr30.c functions used in the md file & elsewhere. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/fr30/fr30.c b/gcc/config/fr30/fr30.c index c52a4e0c3c3..f4fef2b3f04 100644 --- a/gcc/config/fr30/fr30.c +++ b/gcc/config/fr30/fr30.c @@ -1,5 +1,5 @@ /* FR30 specific functions. - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. Contributed by Cygnus Solutions. This file is part of GCC. diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h index cde302078f2..51a05db9c2d 100644 --- a/gcc/config/fr30/fr30.h +++ b/gcc/config/fr30/fr30.h @@ -1,7 +1,7 @@ /*{{{ Comment. */ /* Definitions of FR30 target. - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. Contributed by Cygnus Solutions. This file is part of GCC. diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md index 9ed4d83a33e..fd445c05edc 100644 --- a/gcc/config/fr30/fr30.md +++ b/gcc/config/fr30/fr30.md @@ -1,5 +1,5 @@ ;; FR30 machine description. -;; Copyright (C) 1998-2015 Free Software Foundation, Inc. +;; Copyright (C) 1998-2016 Free Software Foundation, Inc. ;; Contributed by Cygnus Solutions. ;; This file is part of GCC. diff --git a/gcc/config/fr30/fr30.opt b/gcc/config/fr30/fr30.opt index 5a46014f2d9..2eee9ca07b6 100644 --- a/gcc/config/fr30/fr30.opt +++ b/gcc/config/fr30/fr30.opt @@ -1,6 +1,6 @@ ; Options for the FR30 port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/fr30/predicates.md b/gcc/config/fr30/predicates.md index 461b7eb5917..343383dd6fa 100644 --- a/gcc/config/fr30/predicates.md +++ b/gcc/config/fr30/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for FR30. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/freebsd-nthr.h b/gcc/config/freebsd-nthr.h index ea92df30296..ada6a1fce7f 100644 --- a/gcc/config/freebsd-nthr.h +++ b/gcc/config/freebsd-nthr.h @@ -1,5 +1,5 @@ /* FreeBSD configuration setting for FreeBSD systems. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Loren J. Rittle <ljrittle@acm.org> This file is part of GCC. diff --git a/gcc/config/freebsd-spec.h b/gcc/config/freebsd-spec.h index 9341db789eb..fc47c217db7 100644 --- a/gcc/config/freebsd-spec.h +++ b/gcc/config/freebsd-spec.h @@ -1,5 +1,5 @@ /* Base configuration file for all FreeBSD targets. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/freebsd-stdint.h b/gcc/config/freebsd-stdint.h index 07dcf52ba32..58ad407d5dd 100644 --- a/gcc/config/freebsd-stdint.h +++ b/gcc/config/freebsd-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types for FreeBSD systems. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by Gerald Pfeifer <gerald@pfeifer.com>. This file is part of GCC. diff --git a/gcc/config/freebsd.h b/gcc/config/freebsd.h index 0e8e63ed57e..5ded869d286 100644 --- a/gcc/config/freebsd.h +++ b/gcc/config/freebsd.h @@ -1,5 +1,5 @@ /* Base configuration file for all FreeBSD targets. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/freebsd.opt b/gcc/config/freebsd.opt index f7d3ec37666..adafa2f74d8 100644 --- a/gcc/config/freebsd.opt +++ b/gcc/config/freebsd.opt @@ -1,6 +1,6 @@ ; FreeBSD options. -; Copyright (C) 2010-2015 Free Software Foundation, Inc. +; Copyright (C) 2010-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/frv/constraints.md b/gcc/config/frv/constraints.md index 13f03191005..72946607338 100644 --- a/gcc/config/frv/constraints.md +++ b/gcc/config/frv/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for FRV. -;; Copyright (C) 2001-2015 Free Software Foundation, Inc. +;; Copyright (C) 2001-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/frv/frv-asm.h b/gcc/config/frv/frv-asm.h index 5a6ee0d1c43..95dbdc1cae4 100644 --- a/gcc/config/frv/frv-asm.h +++ b/gcc/config/frv/frv-asm.h @@ -1,5 +1,5 @@ /* Assembler Support. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/frv/frv-modes.def b/gcc/config/frv/frv-modes.def index 7c7da05cb25..96bd12d077c 100644 --- a/gcc/config/frv/frv-modes.def +++ b/gcc/config/frv/frv-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for FRV. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/frv/frv-opts.h b/gcc/config/frv/frv-opts.h index 001a92b0bc7..ae31ade88d2 100644 --- a/gcc/config/frv/frv-opts.h +++ b/gcc/config/frv/frv-opts.h @@ -1,5 +1,5 @@ /* Frv option-handling defitions. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/frv/frv-protos.h b/gcc/config/frv/frv-protos.h index 5aa23dcfdc1..4ff98ae25bf 100644 --- a/gcc/config/frv/frv-protos.h +++ b/gcc/config/frv/frv-protos.h @@ -1,5 +1,5 @@ /* Frv prototypes. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c index 275b597b2e8..957ff0390a0 100644 --- a/gcc/config/frv/frv.c +++ b/gcc/config/frv/frv.c @@ -1,4 +1,4 @@ -/* Copyright (C) 1997-2015 Free Software Foundation, Inc. +/* Copyright (C) 1997-2016 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h index b0d66fdf610..8d41b6aa84a 100644 --- a/gcc/config/frv/frv.h +++ b/gcc/config/frv/frv.h @@ -1,5 +1,5 @@ /* Target macros for the FRV port of GCC. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by Red Hat Inc. This file is part of GCC. diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md index 0604b239080..931a71ddfa8 100644 --- a/gcc/config/frv/frv.md +++ b/gcc/config/frv/frv.md @@ -1,5 +1,5 @@ ;; Frv Machine Description -;; Copyright (C) 1999-2015 Free Software Foundation, Inc. +;; Copyright (C) 1999-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat, Inc. ;; This file is part of GCC. diff --git a/gcc/config/frv/frv.opt b/gcc/config/frv/frv.opt index 7a8659d243c..c17a9945c81 100644 --- a/gcc/config/frv/frv.opt +++ b/gcc/config/frv/frv.opt @@ -1,6 +1,6 @@ ; Options for the FR-V port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/frv/linux.h b/gcc/config/frv/linux.h index 02b0d526d61..0c368b563c6 100644 --- a/gcc/config/frv/linux.h +++ b/gcc/config/frv/linux.h @@ -1,5 +1,5 @@ /* Target macros for the FRV Linux port of GCC. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by Red Hat Inc. This file is part of GCC. diff --git a/gcc/config/frv/predicates.md b/gcc/config/frv/predicates.md index ad834a56444..41eb83b24bc 100644 --- a/gcc/config/frv/predicates.md +++ b/gcc/config/frv/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Frv. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/frv/t-frv b/gcc/config/frv/t-frv index ebb2f74e21f..5e2505d0b19 100644 --- a/gcc/config/frv/t-frv +++ b/gcc/config/frv/t-frv @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/frv/t-linux b/gcc/config/frv/t-linux index f7b30df6d10..80acccd220c 100644 --- a/gcc/config/frv/t-linux +++ b/gcc/config/frv/t-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2004-2015 Free Software Foundation, Inc. +# Copyright (C) 2004-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/ft32/constraints.md b/gcc/config/ft32/constraints.md index 8bd838930da..6db1a7cf8ce 100644 --- a/gcc/config/ft32/constraints.md +++ b/gcc/config/ft32/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for FT32 -;; Copyright (C) 2015 Free Software Foundation, Inc. +;; Copyright (C) 2015-2016 Free Software Foundation, Inc. ;; Contributed by FTDI <support@ftdi.com> ;; This file is part of GCC. diff --git a/gcc/config/ft32/ft32-protos.h b/gcc/config/ft32/ft32-protos.h index 8e8e6da6817..e9d674d245c 100644 --- a/gcc/config/ft32/ft32-protos.h +++ b/gcc/config/ft32/ft32-protos.h @@ -1,5 +1,5 @@ /* Prototypes for ft32.c functions used in the md file & elsewhere. - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/ft32/ft32.c b/gcc/config/ft32/ft32.c index ab620617bf7..def560aa068 100644 --- a/gcc/config/ft32/ft32.c +++ b/gcc/config/ft32/ft32.c @@ -1,5 +1,5 @@ /* Target Code for ft32 - Copyright (C) 2015 Free Software Foundation + Copyright (C) 2015-2016 Free Software Foundation, Inc. Contributed by FTDI <support@ftdi.com> This file is part of GCC. diff --git a/gcc/config/ft32/ft32.h b/gcc/config/ft32/ft32.h index a1722a88c0d..9f891dabe2b 100644 --- a/gcc/config/ft32/ft32.h +++ b/gcc/config/ft32/ft32.h @@ -1,5 +1,5 @@ /* Target Definitions for ft32. - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. Contributed by FTDI <support@ftdi.com> This file is part of GCC. diff --git a/gcc/config/ft32/ft32.md b/gcc/config/ft32/ft32.md index 5c1594d5e45..e8029af76ea 100644 --- a/gcc/config/ft32/ft32.md +++ b/gcc/config/ft32/ft32.md @@ -1,5 +1,5 @@ ;; Machine description for FT32 -;; Copyright (C) 2015 Free Software Foundation, Inc. +;; Copyright (C) 2015-2016 Free Software Foundation, Inc. ;; Contributed by FTDI <support@ftdi.com> ;; This file is part of GCC. diff --git a/gcc/config/ft32/ft32.opt b/gcc/config/ft32/ft32.opt index b9b7797c094..e48c72b172e 100644 --- a/gcc/config/ft32/ft32.opt +++ b/gcc/config/ft32/ft32.opt @@ -1,6 +1,6 @@ ; Options for the FT32 port of the compiler. -; Copyright (C) 2015 Free Software Foundation, Inc. +; Copyright (C) 2015-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/ft32/predicates.md b/gcc/config/ft32/predicates.md index 32ca8c6b2ad..d89418d8117 100644 --- a/gcc/config/ft32/predicates.md +++ b/gcc/config/ft32/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for FT32 -;; Copyright (C) 2015 Free Software Foundation, Inc. +;; Copyright (C) 2015-2016 Free Software Foundation, Inc. ;; Contributed by FTDI <support@ftdi.com> ;; This file is part of GCC. diff --git a/gcc/config/ft32/t-ft32 b/gcc/config/ft32/t-ft32 index 93763130068..e1126c7b936 100644 --- a/gcc/config/ft32/t-ft32 +++ b/gcc/config/ft32/t-ft32 @@ -1,5 +1,5 @@ # Target Makefile Fragment for ft32 -# Copyright (C) 2015 Free Software Foundation, Inc. +# Copyright (C) 2015-2016 Free Software Foundation, Inc. # Contributed by FTDI <support@ftdi.com> # # This file is part of GCC. diff --git a/gcc/config/fused-madd.opt b/gcc/config/fused-madd.opt index 87f26cd2177..a2a13d7e1bb 100644 --- a/gcc/config/fused-madd.opt +++ b/gcc/config/fused-madd.opt @@ -1,6 +1,6 @@ ; -mfused-madd option (some targets only). ; -; Copyright (C) 2010-2015 Free Software Foundation, Inc. +; Copyright (C) 2010-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/g.opt b/gcc/config/g.opt index 993dfa4dd92..8de1c9c99d8 100644 --- a/gcc/config/g.opt +++ b/gcc/config/g.opt @@ -1,6 +1,6 @@ ; -G option (small data, some targets only). -; Copyright (C) 2003-2015 Free Software Foundation, Inc. +; Copyright (C) 2003-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/glibc-c.c b/gcc/config/glibc-c.c index 0b51279fb86..11c345e6753 100644 --- a/gcc/config/glibc-c.c +++ b/gcc/config/glibc-c.c @@ -1,5 +1,5 @@ /* C-family target hooks initializer for targets possibly using glibc. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/glibc-stdint.h b/gcc/config/glibc-stdint.h index 98f4f04e112..c546c92e98f 100644 --- a/gcc/config/glibc-stdint.h +++ b/gcc/config/glibc-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using GNU libc or uClibc. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h index 82a3e07b30b..2f1bbccb055 100644 --- a/gcc/config/gnu-user.h +++ b/gcc/config/gnu-user.h @@ -1,7 +1,7 @@ /* Definitions for systems using, at least optionally, a GNU (glibc-based) userspace or other userspace with libc derived from glibc (e.g. uClibc) or for which similar specs are appropriate. - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. Contributed by Eric Youngdale. Modified for stabs-in-ELF by H.J. Lu (hjl@lucon.org). diff --git a/gcc/config/gnu-user.opt b/gcc/config/gnu-user.opt index 02157e3d6df..93b63a92150 100644 --- a/gcc/config/gnu-user.opt +++ b/gcc/config/gnu-user.opt @@ -1,6 +1,6 @@ ; Options for systems using gnu-user.h. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/gnu.h b/gcc/config/gnu.h index 03df7e73448..1d98ec831e8 100644 --- a/gcc/config/gnu.h +++ b/gcc/config/gnu.h @@ -1,7 +1,7 @@ /* Configuration common to all targets running the GNU system. */ /* -Copyright (C) 1994-2015 Free Software Foundation, Inc. +Copyright (C) 1994-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/h8300/constraints.md b/gcc/config/h8300/constraints.md index 94f850a8682..53082cda84f 100644 --- a/gcc/config/h8300/constraints.md +++ b/gcc/config/h8300/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Renesas H8/300. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/h8300/elf.h b/gcc/config/h8300/elf.h index dbabbb9e5ff..7343b7f0631 100644 --- a/gcc/config/h8300/elf.h +++ b/gcc/config/h8300/elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. Renesas H8/300 version generating elf - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com), Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). diff --git a/gcc/config/h8300/genmova.sh b/gcc/config/h8300/genmova.sh index 0101cb92f2e..aa2e607ec69 100644 --- a/gcc/config/h8300/genmova.sh +++ b/gcc/config/h8300/genmova.sh @@ -2,7 +2,7 @@ # Generate mova.md, a file containing patterns that can be implemented # using the h8sx mova instruction. -# Copyright (C) 2004-2015 Free Software Foundation, Inc. +# Copyright (C) 2004-2016 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -22,7 +22,7 @@ echo ";; -*- buffer-read-only: t -*-" echo ";; Generated automatically from genmova.sh" -echo ";; Copyright (C) 2004-2015 Free Software Foundation, Inc." +echo ";; Copyright (C) 2004-2016 Free Software Foundation, Inc." echo ";;" echo ";; This file is part of GCC." echo ";;" diff --git a/gcc/config/h8300/h8300-protos.h b/gcc/config/h8300/h8300-protos.h index f27b7497232..721b6c71743 100644 --- a/gcc/config/h8300/h8300-protos.h +++ b/gcc/config/h8300/h8300-protos.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. Renesas H8/300 version - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com), Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c index d5a726e32f3..1818684c72b 100644 --- a/gcc/config/h8300/h8300.c +++ b/gcc/config/h8300/h8300.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for Renesas H8/300. - Copyright (C) 1992-2015 Free Software Foundation, Inc. + Copyright (C) 1992-2016 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com), Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h index a829cfa9100..bcdcfda66f2 100644 --- a/gcc/config/h8300/h8300.h +++ b/gcc/config/h8300/h8300.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. Renesas H8/300 (generic) - Copyright (C) 1992-2015 Free Software Foundation, Inc. + Copyright (C) 1992-2016 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com), Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index 52213ace20f..a7a62b287a0 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -1,5 +1,5 @@ ;; GCC machine description for Renesas H8/300 -;; Copyright (C) 1992-2015 Free Software Foundation, Inc. +;; Copyright (C) 1992-2016 Free Software Foundation, Inc. ;; Contributed by Steve Chamberlain (sac@cygnus.com), ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com). diff --git a/gcc/config/h8300/h8300.opt b/gcc/config/h8300/h8300.opt index 24ba66257bb..4f2056b6033 100644 --- a/gcc/config/h8300/h8300.opt +++ b/gcc/config/h8300/h8300.opt @@ -1,6 +1,6 @@ ; Options for the Renesas H8/300 port of the compiler ; -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/h8300/linux.h b/gcc/config/h8300/linux.h index ef31e8659f1..bb5d484b9fa 100644 --- a/gcc/config/h8300/linux.h +++ b/gcc/config/h8300/linux.h @@ -1,7 +1,6 @@ /* Definitions of target machine for GNU compiler. Renesas H8/300 (linux variant) - Copyright (C) 2015 - Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. Contributed by Yoshinori Sato <ysato@users.sourceforge.jp> This file is part of GCC. diff --git a/gcc/config/h8300/mova.md b/gcc/config/h8300/mova.md index 201fd976aa0..dc1af97dc40 100644 --- a/gcc/config/h8300/mova.md +++ b/gcc/config/h8300/mova.md @@ -1,6 +1,6 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically from genmova.sh -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/h8300/predicates.md b/gcc/config/h8300/predicates.md index 3476e0465c9..b88db185b26 100644 --- a/gcc/config/h8300/predicates.md +++ b/gcc/config/h8300/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Renesas H8/300. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/h8300/rtems.h b/gcc/config/h8300/rtems.h index 8d867d86c17..eb16f1d8d7e 100644 --- a/gcc/config/h8300/rtems.h +++ b/gcc/config/h8300/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a H8 - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/h8300/t-h8300 b/gcc/config/h8300/t-h8300 index a786a67edeb..64b2695b737 100644 --- a/gcc/config/h8300/t-h8300 +++ b/gcc/config/h8300/t-h8300 @@ -1,4 +1,4 @@ -# Copyright (C) 1993-2015 Free Software Foundation, Inc. +# Copyright (C) 1993-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/h8300/t-linux b/gcc/config/h8300/t-linux index 11237ea99f7..aee9f91107f 100644 --- a/gcc/config/h8300/t-linux +++ b/gcc/config/h8300/t-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2015 Free Software Foundation, Inc. +# Copyright (C) 2015-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/host-darwin.c b/gcc/config/host-darwin.c index 0919867526f..10d243ce4a5 100644 --- a/gcc/config/host-darwin.c +++ b/gcc/config/host-darwin.c @@ -1,5 +1,5 @@ /* Darwin host-specific hook definitions. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/host-darwin.h b/gcc/config/host-darwin.h index ae9cbb8e728..e275062c166 100644 --- a/gcc/config/host-darwin.h +++ b/gcc/config/host-darwin.h @@ -1,5 +1,5 @@ /* Darwin host-specific hook definitions. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/host-hpux.c b/gcc/config/host-hpux.c index 7b5b498e841..6cb19917d3c 100644 --- a/gcc/config/host-hpux.c +++ b/gcc/config/host-hpux.c @@ -1,5 +1,5 @@ /* HP-UX host-specific hook definitions. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/host-linux.c b/gcc/config/host-linux.c index 69d4581ed63..1fd82887476 100644 --- a/gcc/config/host-linux.c +++ b/gcc/config/host-linux.c @@ -1,5 +1,5 @@ /* Linux host-specific hook definitions. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/host-openbsd.c b/gcc/config/host-openbsd.c index 6399ab4cd29..6aaf7f17226 100644 --- a/gcc/config/host-openbsd.c +++ b/gcc/config/host-openbsd.c @@ -1,5 +1,5 @@ /* OpenBSD host-specific hook definitions. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/host-solaris.c b/gcc/config/host-solaris.c index d9a94c9d1a2..cf0d3eab07c 100644 --- a/gcc/config/host-solaris.c +++ b/gcc/config/host-solaris.c @@ -1,5 +1,5 @@ /* Solaris host-specific hook definitions. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/hpux11.opt b/gcc/config/hpux11.opt index bd3930771dd..22cc9849e22 100644 --- a/gcc/config/hpux11.opt +++ b/gcc/config/hpux11.opt @@ -1,6 +1,6 @@ ; HP-UX 11 options. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/adxintrin.h b/gcc/config/i386/adxintrin.h index dd2a26ca9b0..36014ec2b18 100644 --- a/gcc/config/i386/adxintrin.h +++ b/gcc/config/i386/adxintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/ammintrin.h b/gcc/config/i386/ammintrin.h index fb9a53f43f4..0e509c31d64 100644 --- a/gcc/config/i386/ammintrin.h +++ b/gcc/config/i386/ammintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/athlon.md b/gcc/config/i386/athlon.md index d6913d3691a..a4b9c4ff7d1 100644 --- a/gcc/config/i386/athlon.md +++ b/gcc/config/i386/athlon.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/atom.md b/gcc/config/i386/atom.md index ad2cd3452a1..240eecf139e 100644 --- a/gcc/config/i386/atom.md +++ b/gcc/config/i386/atom.md @@ -1,5 +1,5 @@ ;; Atom Scheduling -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/att.h b/gcc/config/i386/att.h index f58bef93492..71edb93351b 100644 --- a/gcc/config/i386/att.h +++ b/gcc/config/i386/att.h @@ -1,5 +1,5 @@ /* Definitions for AT&T assembler syntax for the Intel 80386. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx2intrin.h b/gcc/config/i386/avx2intrin.h index b2a2f488c01..16c0ea8679f 100644 --- a/gcc/config/i386/avx2intrin.h +++ b/gcc/config/i386/avx2intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. +/* Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512bwintrin.h b/gcc/config/i386/avx512bwintrin.h index 3114849fdd1..f40a7d91df3 100644 --- a/gcc/config/i386/avx512bwintrin.h +++ b/gcc/config/i386/avx512bwintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2015 Free Software Foundation, Inc. +/* Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512cdintrin.h b/gcc/config/i386/avx512cdintrin.h index 4da5250d379..93362c544d3 100644 --- a/gcc/config/i386/avx512cdintrin.h +++ b/gcc/config/i386/avx512cdintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h index b36ef48f2a1..14a4e8869a1 100644 --- a/gcc/config/i386/avx512dqintrin.h +++ b/gcc/config/i386/avx512dqintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2015 Free Software Foundation, Inc. +/* Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512erintrin.h b/gcc/config/i386/avx512erintrin.h index b7b103ca1f4..7b76b686b56 100644 --- a/gcc/config/i386/avx512erintrin.h +++ b/gcc/config/i386/avx512erintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512fintrin.h b/gcc/config/i386/avx512fintrin.h index d7e7020577b..e009d8c55bb 100644 --- a/gcc/config/i386/avx512fintrin.h +++ b/gcc/config/i386/avx512fintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512ifmaintrin.h b/gcc/config/i386/avx512ifmaintrin.h index b558981b258..c2f43111e1a 100644 --- a/gcc/config/i386/avx512ifmaintrin.h +++ b/gcc/config/i386/avx512ifmaintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512ifmavlintrin.h b/gcc/config/i386/avx512ifmavlintrin.h index 750eaff3ed6..9091f899cae 100644 --- a/gcc/config/i386/avx512ifmavlintrin.h +++ b/gcc/config/i386/avx512ifmavlintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512pfintrin.h b/gcc/config/i386/avx512pfintrin.h index 433e182344b..06599c3082d 100644 --- a/gcc/config/i386/avx512pfintrin.h +++ b/gcc/config/i386/avx512pfintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vbmiintrin.h b/gcc/config/i386/avx512vbmiintrin.h index f93b13b47d2..a00cf70f527 100644 --- a/gcc/config/i386/avx512vbmiintrin.h +++ b/gcc/config/i386/avx512vbmiintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vbmivlintrin.h b/gcc/config/i386/avx512vbmivlintrin.h index cab4e5c07c5..4af9fb9b019 100644 --- a/gcc/config/i386/avx512vbmivlintrin.h +++ b/gcc/config/i386/avx512vbmivlintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vlbwintrin.h b/gcc/config/i386/avx512vlbwintrin.h index 601dcdd91a1..f260526d06f 100644 --- a/gcc/config/i386/avx512vlbwintrin.h +++ b/gcc/config/i386/avx512vlbwintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2015 Free Software Foundation, Inc. +/* Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vldqintrin.h b/gcc/config/i386/avx512vldqintrin.h index 7ccb62b45cb..697b81c4017 100644 --- a/gcc/config/i386/avx512vldqintrin.h +++ b/gcc/config/i386/avx512vldqintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2015 Free Software Foundation, Inc. +/* Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avx512vlintrin.h b/gcc/config/i386/avx512vlintrin.h index b995cecc8c0..d0ffb2b4d35 100644 --- a/gcc/config/i386/avx512vlintrin.h +++ b/gcc/config/i386/avx512vlintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2015 Free Software Foundation, Inc. +/* Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avxintrin.h b/gcc/config/i386/avxintrin.h index f49fe9d16b7..9519400176d 100644 --- a/gcc/config/i386/avxintrin.h +++ b/gcc/config/i386/avxintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2015 Free Software Foundation, Inc. +/* Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/avxmath.h b/gcc/config/i386/avxmath.h index 76246c7908e..e4ee1fc425e 100644 --- a/gcc/config/i386/avxmath.h +++ b/gcc/config/i386/avxmath.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2010-2015 Free Software Foundation, Inc. +/* Copyright (C) 2010-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bdver1.md b/gcc/config/i386/bdver1.md index 3ef23612e25..f05da31de3d 100644 --- a/gcc/config/i386/bdver1.md +++ b/gcc/config/i386/bdver1.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/bdver3.md b/gcc/config/i386/bdver3.md index eb93d41830a..d324201900d 100644 --- a/gcc/config/i386/bdver3.md +++ b/gcc/config/i386/bdver3.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/biarch64.h b/gcc/config/i386/biarch64.h index b8eccf8333c..43bb18b6803 100644 --- a/gcc/config/i386/biarch64.h +++ b/gcc/config/i386/biarch64.h @@ -1,7 +1,7 @@ /* Make configure files to produce biarch compiler defaulting to 64bit mode. This file must be included very first, while the OS specific file later to overwrite otherwise wrong defaults. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Bo Thorsen <bo@suse.de>. This file is part of GCC. diff --git a/gcc/config/i386/biarchx32.h b/gcc/config/i386/biarchx32.h index a71e819fbb9..a09a3462bee 100644 --- a/gcc/config/i386/biarchx32.h +++ b/gcc/config/i386/biarchx32.h @@ -1,7 +1,7 @@ /* Make configure files to produce biarch compiler defaulting to x32 mode. This file must be included very first, while the OS specific file later to overwrite otherwise wrong defaults. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bmi2intrin.h b/gcc/config/i386/bmi2intrin.h index 9f4df7794ad..f925b516b35 100644 --- a/gcc/config/i386/bmi2intrin.h +++ b/gcc/config/i386/bmi2intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. +/* Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bmiintrin.h b/gcc/config/i386/bmiintrin.h index a2e966cce16..a838a927be9 100644 --- a/gcc/config/i386/bmiintrin.h +++ b/gcc/config/i386/bmiintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2010-2015 Free Software Foundation, Inc. +/* Copyright (C) 2010-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bmmintrin.h b/gcc/config/i386/bmmintrin.h index 93efce79d29..104cda34ce8 100644 --- a/gcc/config/i386/bmmintrin.h +++ b/gcc/config/i386/bmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/bsd.h b/gcc/config/i386/bsd.h index 2c2c08545b7..fb83c4fb4ec 100644 --- a/gcc/config/i386/bsd.h +++ b/gcc/config/i386/bsd.h @@ -1,7 +1,7 @@ /* Definitions for BSD assembler syntax for Intel 386 (actually AT&T syntax for insns and operands, adapted to BSD conventions for symbol names and debugging.) - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/btver2.md b/gcc/config/i386/btver2.md index 617e5264dae..cc8edd5e988 100644 --- a/gcc/config/i386/btver2.md +++ b/gcc/config/i386/btver2.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/clflushoptintrin.h b/gcc/config/i386/clflushoptintrin.h index 16a00c9733e..c079e39c51c 100644 --- a/gcc/config/i386/clflushoptintrin.h +++ b/gcc/config/i386/clflushoptintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/clwbintrin.h b/gcc/config/i386/clwbintrin.h index bde6de4f870..47931ff327b 100644 --- a/gcc/config/i386/clwbintrin.h +++ b/gcc/config/i386/clwbintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/clzerointrin.h b/gcc/config/i386/clzerointrin.h index 696585b6d88..c353f205b6e 100644 --- a/gcc/config/i386/clzerointrin.h +++ b/gcc/config/i386/clzerointrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index 2861d8dfdd2..bac9d6668a8 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for IA-32 and x86-64. -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -148,6 +148,7 @@ ;; We use the B prefix to denote any number of internal operands: ;; f FLAGS_REG ;; g GOT memory operand. +;; m Vector memory operand ;; s Sibcall memory operand, not valid for TARGET_X32 ;; w Call memory operand, not valid for TARGET_X32 ;; z Constant call address operand. @@ -160,15 +161,23 @@ "@internal GOT memory operand." (match_operand 0 "GOT_memory_operand")) +(define_constraint "Bm" + "@internal Vector memory operand." + (match_operand 0 "vector_memory_operand")) + (define_constraint "Bs" "@internal Sibcall memory operand." - (and (not (match_test "TARGET_X32")) - (match_operand 0 "sibcall_memory_operand"))) + (ior (and (not (match_test "TARGET_X32")) + (match_operand 0 "sibcall_memory_operand")) + (and (match_test "TARGET_X32 && Pmode == DImode") + (match_operand 0 "GOT_memory_operand")))) (define_constraint "Bw" "@internal Call memory operand." - (and (not (match_test "TARGET_X32")) - (match_operand 0 "memory_operand"))) + (ior (and (not (match_test "TARGET_X32")) + (match_operand 0 "memory_operand")) + (and (match_test "TARGET_X32 && Pmode == DImode") + (match_operand 0 "GOT_memory_operand")))) (define_constraint "Bz" "@internal Constant call address operand." diff --git a/gcc/config/i386/core2.md b/gcc/config/i386/core2.md index 43964085374..2235cb661cd 100644 --- a/gcc/config/i386/core2.md +++ b/gcc/config/i386/core2.md @@ -1,5 +1,5 @@ ;; Scheduling for Core 2 and derived processors. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index fccdf1f8782..8760e60d382 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007-2015 Free Software Foundation, Inc. + * Copyright (C) 2007-2016 Free Software Foundation, Inc. * * This file is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -95,6 +95,8 @@ /* %ecx */ #define bit_PREFETCHWT1 (1 << 0) #define bit_AVX512VBMI (1 << 1) +#define bit_PKU (1 << 3) +#define bit_OSPKE (1 << 4) /* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */ #define bit_BNDREGS (1 << 3) diff --git a/gcc/config/i386/cross-stdarg.h b/gcc/config/i386/cross-stdarg.h index 867415037e4..7d77b0edf55 100644 --- a/gcc/config/i386/cross-stdarg.h +++ b/gcc/config/i386/cross-stdarg.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002-2015 Free Software Foundation, Inc. +/* Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/crtdll.h b/gcc/config/i386/crtdll.h index b3ffd659273..23346839c0d 100644 --- a/gcc/config/i386/crtdll.h +++ b/gcc/config/i386/crtdll.h @@ -1,7 +1,7 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows32, using GNU tools and the Windows32 API Library. This variant uses CRTDLL.DLL instead of MSVCRTDLL.DLL. - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/cygming.h b/gcc/config/i386/cygming.h index 71506ecbcd0..71019cbfdbc 100644 --- a/gcc/config/i386/cygming.h +++ b/gcc/config/i386/cygming.h @@ -1,6 +1,6 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows32, using a Unix style C library and tools. - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -432,6 +432,11 @@ do { \ fputc ('\n', (FILE)); \ } \ while (0) + +/* Use the weak support for ONE_ONLY decls. */ +#undef MAKE_DECL_ONE_ONLY +#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1) + #endif /* HAVE_GAS_WEAK */ /* FIXME: SUPPORTS_WEAK && TARGET_HAVE_NAMED_SECTIONS is true, diff --git a/gcc/config/i386/cygming.opt b/gcc/config/i386/cygming.opt index d9c1259e69c..a9074bfa928 100644 --- a/gcc/config/i386/cygming.opt +++ b/gcc/config/i386/cygming.opt @@ -1,6 +1,6 @@ ; Cygwin- and MinGW-specific options. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/cygwin-stdint.h b/gcc/config/i386/cygwin-stdint.h index 13b2bfe584a..f5ea488a307 100644 --- a/gcc/config/i386/cygwin-stdint.h +++ b/gcc/config/i386/cygwin-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using Cygwin. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/cygwin-w64.h b/gcc/config/i386/cygwin-w64.h index 586ce051046..4faf5d96a56 100644 --- a/gcc/config/i386/cygwin-w64.h +++ b/gcc/config/i386/cygwin-w64.h @@ -1,7 +1,7 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows 32/64 via Cygwin runtime, using GNU tools and the Windows API Library. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/cygwin.h b/gcc/config/i386/cygwin.h index d1b6bc51b53..182e4d62658 100644 --- a/gcc/config/i386/cygwin.h +++ b/gcc/config/i386/cygwin.h @@ -1,6 +1,6 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows32, using a Unix style C library and tools. - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/cygwin.opt b/gcc/config/i386/cygwin.opt index 569863b9272..fa976b37dce 100644 --- a/gcc/config/i386/cygwin.opt +++ b/gcc/config/i386/cygwin.opt @@ -1,6 +1,6 @@ ; Cygwin-specific options. -; Copyright (C) 2013-2015 Free Software Foundation, Inc. +; Copyright (C) 2013-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/darwin.h b/gcc/config/i386/darwin.h index 2006a750013..c10ceff0cc2 100644 --- a/gcc/config/i386/darwin.h +++ b/gcc/config/i386/darwin.h @@ -1,5 +1,5 @@ /* Target definitions for x86 running Darwin. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. @@ -226,7 +226,11 @@ do { \ compiles default to stabs+. darwin9+ defaults to dwarf-2. */ #ifndef DARWIN_PREFER_DWARF #undef PREFERRED_DEBUGGING_TYPE +#ifdef HAVE_AS_STABS_DIRECTIVE #define PREFERRED_DEBUGGING_TYPE (TARGET_64BIT ? DWARF2_DEBUG : DBX_DEBUG) +#else +#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG +#endif #endif /* Darwin uses the standard DWARF register numbers but the default diff --git a/gcc/config/i386/darwin64.h b/gcc/config/i386/darwin64.h index 8e641b71e35..bb6bf512cbb 100644 --- a/gcc/config/i386/darwin64.h +++ b/gcc/config/i386/darwin64.h @@ -1,5 +1,5 @@ /* Target definitions for x86_64 running Darwin. - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/i386/djgpp-stdint.h b/gcc/config/i386/djgpp-stdint.h index 84f2b5099fe..7045611761f 100644 --- a/gcc/config/i386/djgpp-stdint.h +++ b/gcc/config/i386/djgpp-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using DJGPP. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -22,21 +22,21 @@ along with GCC; see the file COPYING3. If not see /* Exact-width integer types */ #define INT8_TYPE "signed char" -#define INT16_TYPE "signed short int" -#define INT32_TYPE "signed long int" -#define INT64_TYPE "signed long long int" +#define INT16_TYPE "short int" +#define INT32_TYPE "int" +#define INT64_TYPE "long long int" #define UINT8_TYPE "unsigned char" #define UINT16_TYPE "short unsigned int" -#define UINT32_TYPE "long unsigned int" +#define UINT32_TYPE "unsigned int" #define UINT64_TYPE "long long unsigned int" /* Minimum-width integer types */ #define INT_LEAST8_TYPE "signed char" -#define INT_LEAST16_TYPE "signed short int" -#define INT_LEAST32_TYPE "signed int" -#define INT_LEAST64_TYPE "signed long long int" +#define INT_LEAST16_TYPE "short int" +#define INT_LEAST32_TYPE "int" +#define INT_LEAST64_TYPE "long long int" #define UINT_LEAST8_TYPE "unsigned char" #define UINT_LEAST16_TYPE "short unsigned int" @@ -46,12 +46,12 @@ along with GCC; see the file COPYING3. If not see /* Fastest minimum-width integer types */ #define INT_FAST8_TYPE "signed char" -#define INT_FAST16_TYPE "signed int" -#define INT_FAST32_TYPE "signed int" -#define INT_FAST64_TYPE "long long signed int" +#define INT_FAST16_TYPE "short int" +#define INT_FAST32_TYPE "int" +#define INT_FAST64_TYPE "long long int" #define UINT_FAST8_TYPE "unsigned char" -#define UINT_FAST16_TYPE "unsigned int" +#define UINT_FAST16_TYPE "short unsigned int" #define UINT_FAST32_TYPE "unsigned int" #define UINT_FAST64_TYPE "long long unsigned int" diff --git a/gcc/config/i386/djgpp.c b/gcc/config/i386/djgpp.c new file mode 100644 index 00000000000..7414338e4a5 --- /dev/null +++ b/gcc/config/i386/djgpp.c @@ -0,0 +1,47 @@ +/* Subroutines for DJGPP. + Copyright (C) 2013-2016 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" +#include "output.h" +#include "lto-section-names.h" + +void +i386_djgpp_asm_named_section(const char *name, unsigned int flags, + tree) +{ + char flagchars[8], *f = flagchars; + + if (flags & SECTION_WRITE) + *f++ = 'w'; + if (flags & SECTION_CODE) + *f++ = 'x'; + + /* LTO sections need 1-byte alignment to avoid confusing the + zlib decompression algorithm with trailing zero pad bytes. */ + if (strncmp (name, LTO_SECTION_NAME_PREFIX, + strlen (LTO_SECTION_NAME_PREFIX)) == 0) + *f++ = '0'; + + *f++ = '\0'; + + fprintf (asm_out_file, "\t.section\t%s,\"%s\"\n", name, flagchars); +} diff --git a/gcc/config/i386/djgpp.h b/gcc/config/i386/djgpp.h index f8b90313529..c758f5f789d 100644 --- a/gcc/config/i386/djgpp.h +++ b/gcc/config/i386/djgpp.h @@ -1,5 +1,5 @@ /* Configuration for an i386 running MS-DOS with DJGPP. - Copyright (C) 1997-2015 Free Software Foundation, Inc. + Copyright (C) 1997-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -20,6 +20,9 @@ along with GCC; see the file COPYING3. If not see /* Support generation of DWARF2 debugging info. */ #define DWARF2_DEBUGGING_INFO 1 +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG + /* Don't assume anything about the header files. */ #define NO_IMPLICIT_EXTERN_C @@ -30,6 +33,10 @@ along with GCC; see the file COPYING3. If not see #undef DATA_SECTION_ASM_OP #define DATA_SECTION_ASM_OP "\t.section .data" +/* Define the name of the .ident op. */ +#undef TARGET_ASM_OUTPUT_IDENT +#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive + /* Enable alias attribute support. */ #ifndef SET_ASM_OP #define SET_ASM_OP "\t.set\t" @@ -39,56 +46,25 @@ along with GCC; see the file COPYING3. If not see #undef TEXT_SECTION_ASM_OP #define TEXT_SECTION_ASM_OP "\t.section .text" -/* Define standard DJGPP installation paths. */ -/* We override default /usr or /usr/local part with /dev/env/DJDIR which */ -/* points to actual DJGPP installation directory. */ - -/* Search for as.exe and ld.exe in DJGPP's binary directory. */ -#undef MD_EXEC_PREFIX -#define MD_EXEC_PREFIX "/dev/env/DJDIR/bin/" - -/* Standard DJGPP library and startup files */ -#undef MD_STARTFILE_PREFIX -#define MD_STARTFILE_PREFIX "/dev/env/DJDIR/lib/" - -/* Correctly handle absolute filename detection in cp/xref.c */ -#define FILE_NAME_ABSOLUTE_P(NAME) \ - (((NAME)[0] == '/') || ((NAME)[0] == '\\') || \ - (((NAME)[0] >= 'A') && ((NAME)[0] <= 'z') && ((NAME)[1] == ':'))) - #define TARGET_OS_CPP_BUILTINS() \ do \ { \ + if (!flag_iso) \ + builtin_define_with_int_value ("DJGPP",2); \ + builtin_define_with_int_value ("__DJGPP",2); \ + builtin_define_with_int_value ("__DJGPP__",2); \ builtin_define_std ("MSDOS"); \ builtin_define_std ("GO32"); \ + builtin_define_std ("unix"); \ builtin_assert ("system=msdos"); \ } \ while (0) -/* Include <sys/version.h> so __DJGPP__ and __DJGPP_MINOR__ are defined. */ #undef CPP_SPEC -#define CPP_SPEC "-remap %{posix:-D_POSIX_SOURCE} \ - -imacros %s../include/sys/version.h" - -/* We need to override link_command_spec in gcc.c so support -Tdjgpp.djl. - This cannot be done in LINK_SPECS as that LINK_SPECS is processed - before library search directories are known by the linker. - This avoids problems when specs file is not available. An alternate way, - suggested by Robert Hoehne, is to use SUBTARGET_EXTRA_SPECS instead. -*/ - -#undef LINK_COMMAND_SPEC -#define LINK_COMMAND_SPEC \ -"%{!fsyntax-only: \ -%{!c:%{!M:%{!MM:%{!E:%{!S:%(linker) %l " LINK_COMPRESS_DEBUG_SPEC \ -"%X %{o*} %{e*} %{N} %{n} \ -\t%{r} %{s} %{t} %{u*} %{z} %{Z}\ -\t%{!nostdlib:%{!nostartfiles:%S}}\ -\t%{static:} %{L*} %D %o\ -\t%{!nostdlib:%{!nodefaultlibs:%G %L %G}}\ -\t%{!nostdlib:%{!nostartfiles:%E}}\ -\t-Tdjgpp.djl %{T*}}}}}}}\n\ -%{!c:%{!M:%{!MM:%{!E:%{!S:stubify %{v} %{o*:%*} %{!o*:a.out} }}}}}" +#define CPP_SPEC "-remap %{posix:-D_POSIX_SOURCE}" + +#undef POST_LINK_SPEC +#define POST_LINK_SPEC "stubify %{v} %{o*:%*} %{!o*:a.out}" /* Always just link in 'libc.a'. */ #undef LIB_SPEC @@ -98,12 +74,8 @@ along with GCC; see the file COPYING3. If not see #undef STARTFILE_SPEC #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s}" -/* Make sure that gcc will not look for .h files in /usr/local/include - unless user explicitly requests it. */ -#undef LOCAL_INCLUDE_DIR - /* Switch into a generic section. */ -#define TARGET_ASM_NAMED_SECTION default_coff_asm_named_section +#define TARGET_ASM_NAMED_SECTION i386_djgpp_asm_named_section /* This is how to output an assembler line that says to advance the location counter @@ -159,23 +131,37 @@ along with GCC; see the file COPYING3. If not see #undef PTRDIFF_TYPE #define PTRDIFF_TYPE "int" -/* Used to be defined in xm-djgpp.h, but moved here for cross-compilers. */ -#define LIBSTDCXX "stdcxx" - -/* Warn that -mbnu210 is now obsolete. */ -#undef SUBTARGET_OVERRIDE_OPTIONS -#define SUBTARGET_OVERRIDE_OPTIONS \ -do \ - { \ - if (TARGET_BNU210) \ - { \ - warning (0, "-mbnu210 is ignored (option is obsolete)"); \ - } \ - } \ -while (0) +#undef DBX_REGISTER_NUMBER +#define DBX_REGISTER_NUMBER(n) svr4_dbx_register_map[n] + +/* Default to pcc-struct-return. */ +#define DEFAULT_PCC_STRUCT_RETURN 1 + +/* Ignore (with warning) -fPIC for DJGPP */ +#undef SUBTARGET_OVERRIDE_OPTIONS +#define SUBTARGET_OVERRIDE_OPTIONS \ + do { \ + if (flag_pic) \ + { \ + fnotice(stdout, "-f%s ignored (not supported for DJGPP)\n", \ + (flag_pic > 1) ? "PIC" : "pic"); \ + flag_pic = 0; \ + } \ + \ + /* Don't emit DWARF3/4 unless specifically selected. */ \ + /* DWARF3/4 currently does not work for DJGPP. */ \ + if (!global_options_set.x_dwarf_version) \ + dwarf_version = 2; \ + \ + } \ + while (0) /* Support for C++ templates. */ #undef MAKE_DECL_ONE_ONLY #define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1) -#define IX86_MAYBE_NO_LIBGCC_TFMODE +/* Function protypes for gcc/i386/djgpp.c */ + +void +i386_djgpp_asm_named_section(const char *name, unsigned int flags, + tree decl); diff --git a/gcc/config/i386/djgpp.opt b/gcc/config/i386/djgpp.opt index d52c77dee85..b4ae04fdf12 100644 --- a/gcc/config/i386/djgpp.opt +++ b/gcc/config/i386/djgpp.opt @@ -1,6 +1,6 @@ ; DJGPP-specific options. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -18,11 +18,5 @@ ; along with GCC; see the file COPYING3. If not see ; <http://www.gnu.org/licenses/>. -;; -mbnu210 is now ignored and obsolete. It was used to enable support for -;; weak symbols, and .gnu.linkonce support. -mbnu210 -Target Var(TARGET_BNU210) -Ignored (obsolete). - posix Driver diff --git a/gcc/config/i386/dragonfly.h b/gcc/config/i386/dragonfly.h index ab98429a967..8c68eff0d09 100644 --- a/gcc/config/i386/dragonfly.h +++ b/gcc/config/i386/dragonfly.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running DragonFly with ELF format - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by John Marino <gnugcc@marino.st> This file is part of GCC. diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index 8ec1e40c2ac..b12146663e4 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -414,7 +414,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0; unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0; unsigned int has_pcommit = 0, has_mwaitx = 0; - unsigned int has_clzero = 0; + unsigned int has_clzero = 0, has_pku = 0; bool arch; @@ -501,7 +501,8 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_avx512vl = ebx & bit_AVX512IFMA; has_prefetchwt1 = ecx & bit_PREFETCHWT1; - has_avx512vl = ecx & bit_AVX512VBMI; + has_avx512vbmi = ecx & bit_AVX512VBMI; + has_pku = ecx & bit_OSPKE; } if (max_level >= 13) @@ -971,6 +972,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) const char *pcommit = has_pcommit ? " -mpcommit" : " -mno-pcommit"; const char *mwaitx = has_mwaitx ? " -mmwaitx" : " -mno-mwaitx"; const char *clzero = has_clzero ? " -mclzero" : " -mno-clzero"; + const char *pku = has_pku ? " -mpku" : " -mno-pku"; options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3, sse4a, cx16, sahf, movbe, aes, sha, pclmul, popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2, @@ -980,7 +982,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) avx512cd, avx512pf, prefetchwt1, clflushopt, xsavec, xsaves, avx512dq, avx512bw, avx512vl, avx512ifma, avx512vbmi, clwb, pcommit, mwaitx, - clzero, NULL); + clzero, pku, NULL); } done: diff --git a/gcc/config/i386/emmintrin.h b/gcc/config/i386/emmintrin.h index b19f05a1021..8652fe96d0e 100644 --- a/gcc/config/i386/emmintrin.h +++ b/gcc/config/i386/emmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2003-2015 Free Software Foundation, Inc. +/* Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/f16cintrin.h b/gcc/config/i386/f16cintrin.h index d810a93914a..0d46d3b90f3 100644 --- a/gcc/config/i386/f16cintrin.h +++ b/gcc/config/i386/f16cintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. +/* Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/fma4intrin.h b/gcc/config/i386/fma4intrin.h index 06668e859a8..ecd4d1c9fd0 100644 --- a/gcc/config/i386/fma4intrin.h +++ b/gcc/config/i386/fma4intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/fmaintrin.h b/gcc/config/i386/fmaintrin.h index 9128b4d138b..d131d49e9a9 100644 --- a/gcc/config/i386/fmaintrin.h +++ b/gcc/config/i386/fmaintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. +/* Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/freebsd.h b/gcc/config/i386/freebsd.h index 78d5e198576..d66cf51bae9 100644 --- a/gcc/config/i386/freebsd.h +++ b/gcc/config/i386/freebsd.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running FreeBSD with ELF format - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Eric Youngdale. Modified for stabs-in-ELF by H.J. Lu. Adapted from GNU/Linux version by John Polstra. diff --git a/gcc/config/i386/freebsd64.h b/gcc/config/i386/freebsd64.h index 24cb221e5fa..8e0090018d1 100644 --- a/gcc/config/i386/freebsd64.h +++ b/gcc/config/i386/freebsd64.h @@ -1,5 +1,5 @@ /* Definitions for AMD x86-64 running FreeBSD with ELF format - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by David O'Brien <obrien@FreeBSD.org> This file is part of GCC. diff --git a/gcc/config/i386/fxsrintrin.h b/gcc/config/i386/fxsrintrin.h index a3932e07506..b18b898c26a 100644 --- a/gcc/config/i386/fxsrintrin.h +++ b/gcc/config/i386/fxsrintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/gas.h b/gcc/config/i386/gas.h index 086ce5344f3..c2ae8b088c6 100644 --- a/gcc/config/i386/gas.h +++ b/gcc/config/i386/gas.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 using GAS. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/geode.md b/gcc/config/i386/geode.md index 9f1411db052..1cf0036a869 100644 --- a/gcc/config/i386/geode.md +++ b/gcc/config/i386/geode.md @@ -1,5 +1,5 @@ ;; Geode Scheduling -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/gmm_malloc.h b/gcc/config/i386/gmm_malloc.h index 52b853ceb2c..0582e0c444e 100644 --- a/gcc/config/i386/gmm_malloc.h +++ b/gcc/config/i386/gmm_malloc.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2004-2015 Free Software Foundation, Inc. +/* Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/gnu-user-common.h b/gcc/config/i386/gnu-user-common.h index bd32fe2e667..6b7b0743aa3 100644 --- a/gcc/config/i386/gnu-user-common.h +++ b/gcc/config/i386/gnu-user-common.h @@ -1,5 +1,5 @@ /* Common definitions for Intel 386 and AMD x86-64 systems using - GNU userspace. Copyright (C) 2012-2015 Free Software Foundation, Inc. + GNU userspace. Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Ilya Enkovich. This file is part of GCC. diff --git a/gcc/config/i386/gnu-user.h b/gcc/config/i386/gnu-user.h index 0d001e22f9e..fee33a3efdc 100644 --- a/gcc/config/i386/gnu-user.h +++ b/gcc/config/i386/gnu-user.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 systems using GNU userspace. - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. Contributed by Eric Youngdale. Modified for stabs-in-ELF by H.J. Lu. diff --git a/gcc/config/i386/gnu-user64.h b/gcc/config/i386/gnu-user64.h index 734310f8f56..7a02a7eb4d7 100644 --- a/gcc/config/i386/gnu-user64.h +++ b/gcc/config/i386/gnu-user64.h @@ -1,5 +1,5 @@ /* Definitions for AMD x86-64 using GNU userspace. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Jan Hubicka <jh@suse.cz>, based on linux.h. This file is part of GCC. diff --git a/gcc/config/i386/gnu.h b/gcc/config/i386/gnu.h index 8892a4f4455..c726d31f496 100644 --- a/gcc/config/i386/gnu.h +++ b/gcc/config/i386/gnu.h @@ -1,7 +1,7 @@ /* Configuration for an i386 running GNU with ELF as the target machine. */ /* -Copyright (C) 1994-2015 Free Software Foundation, Inc. +Copyright (C) 1994-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/haswell.md b/gcc/config/i386/haswell.md index 2bb0ac9873c..1f49c237ae7 100644 --- a/gcc/config/i386/haswell.md +++ b/gcc/config/i386/haswell.md @@ -1,5 +1,5 @@ ;; Scheduling for Haswell and derived processors. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/host-cygwin.c b/gcc/config/i386/host-cygwin.c index b62cdeeab12..dd59ab99c92 100644 --- a/gcc/config/i386/host-cygwin.c +++ b/gcc/config/i386/host-cygwin.c @@ -1,5 +1,5 @@ /* Cygwin host-specific hook definitions. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/host-i386-darwin.c b/gcc/config/i386/host-i386-darwin.c index 9c948f560b6..6283696902d 100644 --- a/gcc/config/i386/host-i386-darwin.c +++ b/gcc/config/i386/host-i386-darwin.c @@ -1,5 +1,5 @@ /* i386-darwin host-specific hook definitions. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/host-mingw32.c b/gcc/config/i386/host-mingw32.c index 7eb47cc51ee..f51219abfd6 100644 --- a/gcc/config/i386/host-mingw32.c +++ b/gcc/config/i386/host-mingw32.c @@ -1,5 +1,5 @@ /* mingw32 host-specific hook definitions. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386-builtin-types.awk b/gcc/config/i386/i386-builtin-types.awk index 944c7a400d7..1825e9f7b44 100644 --- a/gcc/config/i386/i386-builtin-types.awk +++ b/gcc/config/i386/i386-builtin-types.awk @@ -1,4 +1,4 @@ -# Copyright (C) 2009-2015 Free Software Foundation, Inc. +# Copyright (C) 2009-2016 Free Software Foundation, Inc. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 0f3c3ec452c..ea0c5df059f 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -1,5 +1,5 @@ /* Subroutines used for macro/preprocessor support on the ia-32. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -439,8 +439,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__CLWB__"); if (isa_flag & OPTION_MASK_ISA_MWAITX) def_or_undef (parse_in, "__MWAITX__"); - if (isa_flag & OPTION_MASK_ISA_CLZERO) - def_or_undef (parse_in, "__CLZERO__"); + if (isa_flag & OPTION_MASK_ISA_PKU) + def_or_undef (parse_in, "__PKU__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386-interix.h b/gcc/config/i386/i386-interix.h index 97dbcd97ef5..7d4b8721ecd 100644 --- a/gcc/config/i386/i386-interix.h +++ b/gcc/config/i386/i386-interix.h @@ -1,5 +1,5 @@ /* Target definitions for GCC for Intel 80386 running Interix - Parts Copyright (C) 1991-2015 Free Software Foundation, Inc. + Parts Copyright (C) 1991-2016 Free Software Foundation, Inc. Parts: by Douglas B. Rupp (drupp@cs.washington.edu). diff --git a/gcc/config/i386/i386-modes.def b/gcc/config/i386/i386-modes.def index 714c138cc6a..d524313adc3 100644 --- a/gcc/config/i386/i386-modes.def +++ b/gcc/config/i386/i386-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC for IA-32. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386-opts.h b/gcc/config/i386/i386-opts.h index 960f1d89e76..b7f92e3bea1 100644 --- a/gcc/config/i386/i386-opts.h +++ b/gcc/config/i386/i386-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for IA-32. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index bd084dc9714..252bb192aa7 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC for IA-32. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index cecea2496a9..92d8ee1a88f 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on IA-32. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -2815,7 +2815,11 @@ scalar_to_vector_candidate_p (rtx_insn *insn) return false; } - if (!REG_P (XEXP (src, 0)) && !MEM_P (XEXP (src, 0))) + if (!REG_P (XEXP (src, 0)) && !MEM_P (XEXP (src, 0)) + /* Check for andnot case. */ + && (GET_CODE (src) != AND + || GET_CODE (XEXP (src, 0)) != NOT + || !REG_P (XEXP (XEXP (src, 0), 0)))) return false; if (!REG_P (XEXP (src, 1)) && !MEM_P (XEXP (src, 1))) @@ -3150,13 +3154,13 @@ scalar_chain::compute_convert_gain () } if (dump_file) - fprintf (dump_file, " Instruction convertion gain: %d\n", gain); + fprintf (dump_file, " Instruction conversion gain: %d\n", gain); EXECUTE_IF_SET_IN_BITMAP (defs_conv, 0, insn_uid, bi) cost += DF_REG_DEF_COUNT (insn_uid) * ix86_cost->mmxsse_to_integer; if (dump_file) - fprintf (dump_file, " Registers convertion cost: %d\n", cost); + fprintf (dump_file, " Registers conversion cost: %d\n", cost); gain -= cost; @@ -3383,7 +3387,12 @@ scalar_chain::convert_op (rtx *op, rtx_insn *insn) { *op = copy_rtx_if_shared (*op); - if (MEM_P (*op)) + if (GET_CODE (*op) == NOT) + { + convert_op (&XEXP (*op, 0), insn); + PUT_MODE (*op, V2DImode); + } + else if (MEM_P (*op)) { rtx tmp = gen_reg_rtx (DImode); @@ -3531,7 +3540,7 @@ convert_scalars_to_vector () /* Find all instructions we want to convert into vector mode. */ if (dump_file) - fprintf (dump_file, "Searching for mode convertion candidates...\n"); + fprintf (dump_file, "Searching for mode conversion candidates...\n"); FOR_EACH_BB_FN (bb, cfun) { @@ -3755,6 +3764,7 @@ ix86_target_string (HOST_WIDE_INT isa, int flags, const char *arch, { "-mpcommit", OPTION_MASK_ISA_PCOMMIT }, { "-mmwaitx", OPTION_MASK_ISA_MWAITX }, { "-mclzero", OPTION_MASK_ISA_CLZERO }, + { "-mpku", OPTION_MASK_ISA_PKU }, }; /* Flag options. */ @@ -4310,6 +4320,7 @@ ix86_option_override_internal (bool main_args_p, #define PTA_MWAITX (HOST_WIDE_INT_1 << 57) #define PTA_CLZERO (HOST_WIDE_INT_1 << 58) #define PTA_NO_80387 (HOST_WIDE_INT_1 << 59) +#define PTA_PKU (HOST_WIDE_INT_1 << 60) #define PTA_CORE2 \ (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \ @@ -4331,7 +4342,7 @@ ix86_option_override_internal (bool main_args_p, (PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES) #define PTA_SKYLAKE_AVX512 \ (PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL \ - | PTA_AVX512BW | PTA_AVX512DQ) + | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU) #define PTA_KNL \ (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD) #define PTA_BONNELL \ @@ -4934,6 +4945,9 @@ ix86_option_override_internal (bool main_args_p, if (processor_alias_table[i].flags & PTA_MWAITX && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MWAITX)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MWAITX; + if (processor_alias_table[i].flags & PTA_PKU + && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PKU)) + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU; if (!(opts_set->x_target_flags & MASK_80387)) { @@ -5338,6 +5352,13 @@ ix86_option_override_internal (bool main_args_p, opts->x_param_values, opts_set->x_param_values); + /* Restrict number of if-converted SET insns to 1. */ + if (TARGET_ONE_IF_CONV_INSN) + maybe_set_param_value (PARAM_MAX_RTL_IF_CONVERSION_INSNS, + 1, + opts->x_param_values, + opts_set->x_param_values); + /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */ if (opts->x_flag_prefetch_loop_arrays < 0 && HAVE_prefetch @@ -5930,6 +5951,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[], IX86_ATTR_ISA ("pcommit", OPT_mpcommit), IX86_ATTR_ISA ("mwaitx", OPT_mmwaitx), IX86_ATTR_ISA ("clzero", OPT_mclzero), + IX86_ATTR_ISA ("pku", OPT_mpku), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), @@ -6657,6 +6679,7 @@ ix86_function_ok_for_sibcall (tree decl, tree exp) { tree type, decl_or_type; rtx a, b; + bool bind_global = decl && !targetm.binds_local_p (decl); /* If we are generating position-independent code, we cannot sibcall optimize direct calls to global functions, as the PLT requires @@ -6665,7 +6688,7 @@ ix86_function_ok_for_sibcall (tree decl, tree exp) && !TARGET_64BIT && flag_pic && flag_plt - && decl && !targetm.binds_local_p (decl)) + && bind_global) return false; /* If we need to align the outgoing stack, then sibcalling would @@ -6723,8 +6746,10 @@ ix86_function_ok_for_sibcall (tree decl, tree exp) /* If this call is indirect, we'll need to be able to use a call-clobbered register for the address of the target function. Make sure that all such registers are not used for passing - parameters. Note that DLLIMPORT functions are indirect. */ + parameters. Note that DLLIMPORT functions and call to global + function via GOT slot are indirect. */ if (!decl + || (bind_global && flag_pic && !flag_plt) || (TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (decl))) { /* Check if regparm >= 3 since arg_reg_available is set to @@ -10894,6 +10919,10 @@ ix86_frame_pointer_required (void) if (TARGET_64BIT_MS_ABI && get_frame_size () > SEH_MAX_FRAME_SIZE) return true; + /* SSE saves require frame-pointer when stack is misaligned. */ + if (TARGET_64BIT_MS_ABI && ix86_incoming_stack_boundary < 128) + return true; + /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER turns off the frame pointer by default. Turn it back on now if we've not got a leaf function. */ @@ -19350,11 +19379,11 @@ ix86_expand_vector_logical_operator (enum rtx_code code, machine_mode mode, { op1 = operands[1]; op2 = SUBREG_REG (operands[2]); - if (!nonimmediate_operand (op2, GET_MODE (dst))) + if (!vector_operand (op2, GET_MODE (dst))) op2 = force_reg (GET_MODE (dst), op2); } op1 = SUBREG_REG (op1); - if (!nonimmediate_operand (op1, GET_MODE (dst))) + if (!vector_operand (op1, GET_MODE (dst))) op1 = force_reg (GET_MODE (dst), op1); emit_insn (gen_rtx_SET (dst, gen_rtx_fmt_ee (code, GET_MODE (dst), @@ -19365,9 +19394,9 @@ ix86_expand_vector_logical_operator (enum rtx_code code, machine_mode mode, break; } } - if (!nonimmediate_operand (operands[1], mode)) + if (!vector_operand (operands[1], mode)) operands[1] = force_reg (mode, operands[1]); - if (!nonimmediate_operand (operands[2], mode)) + if (!vector_operand (operands[2], mode)) operands[2] = force_reg (mode, operands[2]); ix86_fixup_binary_operands_no_copy (code, mode, operands); emit_insn (gen_rtx_SET (operands[0], @@ -21679,6 +21708,19 @@ ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label) case DImode: if (TARGET_64BIT) goto simple; + /* For 32-bit target DI comparison may be performed on + SSE registers. To allow this we should avoid split + to SI mode which is achieved by doing xor in DI mode + and then comparing with zero (which is recognized by + STV pass). We don't compare using xor when optimizing + for size. */ + if (!optimize_insn_for_size_p () + && TARGET_STV + && (code == EQ || code == NE)) + { + op0 = force_reg (mode, gen_rtx_XOR (mode, op0, op1)); + op1 = const0_rtx; + } case TImode: /* Expand DImode branch into multiple compare+branch. */ { @@ -32283,6 +32325,10 @@ enum ix86_builtins IX86_BUILTIN_READ_FLAGS, IX86_BUILTIN_WRITE_FLAGS, + /* PKU instructions. */ + IX86_BUILTIN_RDPKRU, + IX86_BUILTIN_WRPKRU, + IX86_BUILTIN_MAX }; @@ -32788,6 +32834,10 @@ static const struct builtin_description bdesc_special_args[] = /* PCOMMIT. */ { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID }, + + /* RDPKRU and WRPKRU. */ + { OPTION_MASK_ISA_PKU, CODE_FOR_rdpkru, "__builtin_ia32_rdpkru", IX86_BUILTIN_RDPKRU, UNKNOWN, (int) UNSIGNED_FTYPE_VOID }, + { OPTION_MASK_ISA_PKU, CODE_FOR_wrpkru, "__builtin_ia32_wrpkru", IX86_BUILTIN_WRPKRU, UNKNOWN, (int) VOID_FTYPE_UNSIGNED } }; /* Builtins with variable number of arguments. */ @@ -35186,48 +35236,6 @@ static const struct builtin_description bdesc_tm[] = { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID }, }; -/* TM callbacks. */ - -/* Return the builtin decl needed to load a vector of TYPE. */ - -static tree -ix86_builtin_tm_load (tree type) -{ - if (TREE_CODE (type) == VECTOR_TYPE) - { - switch (tree_to_uhwi (TYPE_SIZE (type))) - { - case 64: - return builtin_decl_explicit (BUILT_IN_TM_LOAD_M64); - case 128: - return builtin_decl_explicit (BUILT_IN_TM_LOAD_M128); - case 256: - return builtin_decl_explicit (BUILT_IN_TM_LOAD_M256); - } - } - return NULL_TREE; -} - -/* Return the builtin decl needed to store a vector of TYPE. */ - -static tree -ix86_builtin_tm_store (tree type) -{ - if (TREE_CODE (type) == VECTOR_TYPE) - { - switch (tree_to_uhwi (TYPE_SIZE (type))) - { - case 64: - return builtin_decl_explicit (BUILT_IN_TM_STORE_M64); - case 128: - return builtin_decl_explicit (BUILT_IN_TM_STORE_M128); - case 256: - return builtin_decl_explicit (BUILT_IN_TM_STORE_M256); - } - } - return NULL_TREE; -} - /* Initialize the transactional memory vector load/store builtins. */ static void @@ -39755,7 +39763,11 @@ ix86_expand_special_args_builtin (const struct builtin_description *d, memory = 0; break; case VOID_FTYPE_PV8DF_V8DF_UQI: + case VOID_FTYPE_PV4DF_V4DF_UQI: + case VOID_FTYPE_PV2DF_V2DF_UQI: case VOID_FTYPE_PV16SF_V16SF_UHI: + case VOID_FTYPE_PV8SF_V8SF_UQI: + case VOID_FTYPE_PV4SF_V4SF_UQI: case VOID_FTYPE_PV8DI_V8DI_UQI: case VOID_FTYPE_PV4DI_V4DI_UQI: case VOID_FTYPE_PV2DI_V2DI_UQI: @@ -39813,10 +39825,6 @@ ix86_expand_special_args_builtin (const struct builtin_description *d, case VOID_FTYPE_PV16QI_V16QI_UHI: case VOID_FTYPE_PV32QI_V32QI_USI: case VOID_FTYPE_PV64QI_V64QI_UDI: - case VOID_FTYPE_PV4DF_V4DF_UQI: - case VOID_FTYPE_PV2DF_V2DF_UQI: - case VOID_FTYPE_PV8SF_V8SF_UQI: - case VOID_FTYPE_PV4SF_V4SF_UQI: nargs = 2; klass = store; /* Reserve memory operand for target. */ @@ -41800,13 +41808,12 @@ rdseed_step: op0 = fixup_modeless_constant (op0, mode0); - if (GET_MODE (op0) == mode0 - || (GET_MODE (op0) == VOIDmode && op0 != constm1_rtx)) + if (GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode) { if (!insn_data[icode].operand[0].predicate (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); } - else if (op0 != constm1_rtx) + else { op0 = copy_to_reg (op0); op0 = simplify_gen_subreg (mode0, op0, GET_MODE (op0), 0); @@ -54313,12 +54320,6 @@ ix86_addr_space_zero_address_valid (addr_space_t as) #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \ ix86_builtin_vectorized_function -#undef TARGET_VECTORIZE_BUILTIN_TM_LOAD -#define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load - -#undef TARGET_VECTORIZE_BUILTIN_TM_STORE -#define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store - #undef TARGET_VECTORIZE_BUILTIN_GATHER #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index e69c9cc4563..9062d631165 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC for IA-32. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -158,6 +158,9 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) #define TARGET_MWAITX TARGET_ISA_MWAITX #define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x) +#define TARGET_PKU TARGET_ISA_PKU +#define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x) + #define TARGET_LP64 TARGET_ABI_64 #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) @@ -496,6 +499,8 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST]; ix86_tune_features[X86_TUNE_ADJUST_UNROLL] #define TARGET_AVOID_FALSE_DEP_FOR_BMI \ ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] +#define TARGET_ONE_IF_CONV_INSN \ + ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN] /* Feature tests against the various architecture variations. */ enum ix86_arch_indices { @@ -688,8 +693,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); only SSE, rounding is correct; when using both SSE and the FPU, the rounding precision is indeterminate, since either may be chosen apparently at random. */ -#define TARGET_FLT_EVAL_METHOD \ - (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) +#define TARGET_FLT_EVAL_METHOD \ + (TARGET_80387 \ + ? (TARGET_MIX_SSE_I387 ? -1 \ + : (TARGET_SSE_MATH ? (TARGET_SSE2 ? 0 : -1) : 2)) \ + : 0) /* Whether to allow x87 floating-point arithmetic on MODE (one of SFmode, DFmode and XFmode) in the current excess precision diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 49b221665fd..f16b42ab884 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1,5 +1,5 @@ ;; GCC machine description for IA-32 and x86-64. -;; Copyright (C) 1988-2015 Free Software Foundation, Inc. +;; Copyright (C) 1988-2016 Free Software Foundation, Inc. ;; Mostly by William Schelter. ;; x86_64 support added by Jan Hubicka ;; @@ -268,6 +268,8 @@ ;; For CLZERO support UNSPECV_CLZERO + ;; For RDPKRU and WRPKRU support + UNSPECV_PKU ]) ;; Constants to represent rounding modes in the ROUND instruction @@ -7868,7 +7870,7 @@ ;; Combine likes to form bit extractions for some tests. Humor it. (define_insn "*testqi_ext_3" [(set (reg FLAGS_REG) - (compare (zero_extract:SWI48 + (compare (zero_extract:SWI248 (match_operand 0 "nonimmediate_operand" "rm") (match_operand 1 "const_int_operand" "n") (match_operand 2 "const_int_operand" "n")) @@ -8643,6 +8645,23 @@ (clobber (reg:CC FLAGS_REG))])] "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);") +(define_insn_and_split "*andndi3_doubleword" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (and:DI + (not:DI (match_operand:DI 1 "register_operand" "r,r")) + (match_operand:DI 2 "nonimmediate_operand" "r,m"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_BMI && !TARGET_64BIT && TARGET_STV && TARGET_SSE" + "#" + "&& reload_completed" + [(parallel [(set (match_dup 0) + (and:SI (not:SI (match_dup 1)) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))]) + (parallel [(set (match_dup 3) + (and:SI (not:SI (match_dup 4)) (match_dup 5))) + (clobber (reg:CC FLAGS_REG))])] + "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);") + (define_insn "*<code>hi_1" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm,!k") (any_or:HI @@ -11865,6 +11884,22 @@ "* return ix86_output_call_insn (insn, operands[0]);" [(set_attr "type" "call")]) +;; Since sibcall never returns, we can only use call-clobbered register +;; as GOT base. +(define_insn "*sibcall_GOT_32" + [(call (mem:QI + (mem:SI (plus:SI + (match_operand:SI 0 "register_no_elim_operand" "U") + (match_operand:SI 1 "GOT32_symbol_operand")))) + (match_operand 2))] + "!TARGET_MACHO && !TARGET_64BIT && SIBLING_CALL_P (insn)" +{ + rtx fnaddr = gen_rtx_PLUS (Pmode, operands[0], operands[1]); + fnaddr = gen_const_mem (Pmode, fnaddr); + return ix86_output_call_insn (insn, fnaddr); +} + [(set_attr "type" "call")]) + (define_insn "*sibcall" [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "UBsBz")) (match_operand 1))] @@ -12042,6 +12077,23 @@ "* return ix86_output_call_insn (insn, operands[1]);" [(set_attr "type" "callv")]) +;; Since sibcall never returns, we can only use call-clobbered register +;; as GOT base. +(define_insn "*sibcall_value_GOT_32" + [(set (match_operand 0) + (call (mem:QI + (mem:SI (plus:SI + (match_operand:SI 1 "register_no_elim_operand" "U") + (match_operand:SI 2 "GOT32_symbol_operand")))) + (match_operand 3)))] + "!TARGET_MACHO && !TARGET_64BIT && SIBLING_CALL_P (insn)" +{ + rtx fnaddr = gen_rtx_PLUS (Pmode, operands[1], operands[2]); + fnaddr = gen_const_mem (Pmode, fnaddr); + return ix86_output_call_insn (insn, fnaddr); +} + [(set_attr "type" "callv")]) + (define_insn "*sibcall_value" [(set (match_operand 0) (call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "UBsBz")) @@ -19287,6 +19339,48 @@ [(set_attr "type" "imov") (set_attr "mode" "<MODE>")]) +;; RDPKRU and WRPKRU + +(define_expand "rdpkru" + [(parallel + [(set (match_operand:SI 0 "register_operand") + (unspec_volatile:SI [(match_dup 1)] UNSPECV_PKU)) + (set (match_dup 2) (const_int 0))])] + "TARGET_PKU" +{ + operands[1] = force_reg (SImode, const0_rtx); + operands[2] = gen_reg_rtx (SImode); +}) + +(define_insn "*rdpkru" + [(set (match_operand:SI 0 "register_operand" "=a") + (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "c")] + UNSPECV_PKU)) + (set (match_operand:SI 1 "register_operand" "=d") + (const_int 0))] + "TARGET_PKU" + "rdpkru" + [(set_attr "type" "other")]) + +(define_expand "wrpkru" + [(unspec_volatile:SI + [(match_operand:SI 0 "register_operand") + (match_dup 1) (match_dup 2)] UNSPECV_PKU)] + "TARGET_PKU" +{ + operands[1] = force_reg (SImode, const0_rtx); + operands[2] = force_reg (SImode, const0_rtx); +}) + +(define_insn "*wrpkru" + [(unspec_volatile:SI + [(match_operand:SI 0 "register_operand" "a") + (match_operand:SI 1 "register_operand" "d") + (match_operand:SI 2 "register_operand" "c")] UNSPECV_PKU)] + "TARGET_PKU" + "wrpkru" + [(set_attr "type" "other")]) + (include "mmx.md") (include "sse.md") (include "sync.md") diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 730b753ba4b..36dd4bd1572 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1,6 +1,6 @@ ; Options for the IA-32 and AMD64 ports of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -876,6 +876,10 @@ mclzero Target Report Mask(ISA_CLZERO) Var(ix86_isa_flags) Save Support CLZERO built-in functions and code generation. +mpku +Target Report Mask(ISA_PKU) Var(ix86_isa_flags) Save +Support PKU built-in functions and code generation. + mstack-protector-guard= Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS) Use given stack-protector guard. diff --git a/gcc/config/i386/i386elf.h b/gcc/config/i386/i386elf.h index aed5e045083..e2a6a10d600 100644 --- a/gcc/config/i386/i386elf.h +++ b/gcc/config/i386/i386elf.h @@ -1,5 +1,5 @@ /* Target definitions for GCC for Intel 80386 using ELF - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. Derived from sysv4.h written by Ron Guilmette (rfg@netcom.com). diff --git a/gcc/config/i386/ia32intrin.h b/gcc/config/i386/ia32intrin.h index b8d1c315dd4..650c93820a1 100644 --- a/gcc/config/i386/ia32intrin.h +++ b/gcc/config/i386/ia32intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2015 Free Software Foundation, Inc. +/* Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/iamcu.h b/gcc/config/i386/iamcu.h index c20c2db6910..e16c9d63a7c 100644 --- a/gcc/config/i386/iamcu.h +++ b/gcc/config/i386/iamcu.h @@ -1,5 +1,5 @@ /* Definitions of target machine for Intel MCU psABI. - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -94,3 +94,19 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see goto DONE; \ } \ } while (0) + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "long int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE BITS_PER_WORD + +/* Use int, instead of long int, for int32_t and uint32_t. */ +#undef STDINT_LONG32 +#define STDINT_LONG32 0 diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h index a1e9c3c07da..93331113d97 100644 --- a/gcc/config/i386/immintrin.h +++ b/gcc/config/i386/immintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2015 Free Software Foundation, Inc. +/* Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/intelmic-mkoffload.c b/gcc/config/i386/intelmic-mkoffload.c index 828b415015e..a78e48c0eb6 100644 --- a/gcc/config/i386/intelmic-mkoffload.c +++ b/gcc/config/i386/intelmic-mkoffload.c @@ -1,6 +1,6 @@ /* Offload image generation tool for Intel MIC devices. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by Ilya Verbin <ilya.verbin@intel.com>. diff --git a/gcc/config/i386/intelmic-offload.h b/gcc/config/i386/intelmic-offload.h index 4fb4b65aa91..12aca578af2 100644 --- a/gcc/config/i386/intelmic-offload.h +++ b/gcc/config/i386/intelmic-offload.h @@ -1,6 +1,6 @@ /* Support for Intel MIC offloading. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/interix.opt b/gcc/config/i386/interix.opt index 04de55b1c2e..bd65432fe59 100644 --- a/gcc/config/i386/interix.opt +++ b/gcc/config/i386/interix.opt @@ -1,6 +1,6 @@ ; Interix-specific options. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/k6.md b/gcc/config/i386/k6.md index bbdc5d8c218..8118b3c9cc4 100644 --- a/gcc/config/i386/k6.md +++ b/gcc/config/i386/k6.md @@ -1,5 +1,5 @@ ;; AMD K6/K6-2 Scheduling -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/kfreebsd-gnu.h b/gcc/config/i386/kfreebsd-gnu.h index d7b88a0738f..97be2184106 100644 --- a/gcc/config/i386/kfreebsd-gnu.h +++ b/gcc/config/i386/kfreebsd-gnu.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running kFreeBSD-based GNU systems with ELF format - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/i386/kfreebsd-gnu64.h b/gcc/config/i386/kfreebsd-gnu64.h index da30cab2304..59d21a42b4f 100644 --- a/gcc/config/i386/kfreebsd-gnu64.h +++ b/gcc/config/i386/kfreebsd-gnu64.h @@ -1,5 +1,5 @@ /* Definitions for AMD x86-64 running kFreeBSD-based GNU systems with ELF format - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/i386/knetbsd-gnu.h b/gcc/config/i386/knetbsd-gnu.h index 86a6833d29f..51f8a0c4609 100644 --- a/gcc/config/i386/knetbsd-gnu.h +++ b/gcc/config/i386/knetbsd-gnu.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running kNetBSD-based GNU systems with ELF format - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/i386/knetbsd-gnu64.h b/gcc/config/i386/knetbsd-gnu64.h index d621bbee6a4..fb9e2c0cdf0 100644 --- a/gcc/config/i386/knetbsd-gnu64.h +++ b/gcc/config/i386/knetbsd-gnu64.h @@ -1,6 +1,5 @@ /* Definitions for AMD x86-64 running kNetBSD-based GNU systems with ELF format - Copyright (C) 2012 - Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/kopensolaris-gnu.h b/gcc/config/i386/kopensolaris-gnu.h index 03b8de26433..a9deb5087d0 100644 --- a/gcc/config/i386/kopensolaris-gnu.h +++ b/gcc/config/i386/kopensolaris-gnu.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running kOpenSolaris-based GNU systems with ELF format - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/i386/linux-common.h b/gcc/config/i386/linux-common.h index 7617490a119..4b9910fa902 100644 --- a/gcc/config/i386/linux-common.h +++ b/gcc/config/i386/linux-common.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running Linux-based GNU systems with ELF format. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Ilya Enkovich. This file is part of GCC. diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h index 385aefd046b..d37a875ed6f 100644 --- a/gcc/config/i386/linux.h +++ b/gcc/config/i386/linux.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running Linux-based GNU systems with ELF format. - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. Contributed by Eric Youngdale. Modified for stabs-in-ELF by H.J. Lu. diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h index e300480fc70..73d22e357cf 100644 --- a/gcc/config/i386/linux64.h +++ b/gcc/config/i386/linux64.h @@ -1,5 +1,5 @@ /* Definitions for AMD x86-64 running Linux-based GNU systems with ELF format. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Jan Hubicka <jh@suse.cz>, based on linux.h. This file is part of GCC. diff --git a/gcc/config/i386/lwpintrin.h b/gcc/config/i386/lwpintrin.h index 714b565b4b4..1ffac23e1d2 100644 --- a/gcc/config/i386/lwpintrin.h +++ b/gcc/config/i386/lwpintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/lynx.h b/gcc/config/i386/lynx.h index aa7980ef4e2..6c4fec6264e 100644 --- a/gcc/config/i386/lynx.h +++ b/gcc/config/i386/lynx.h @@ -1,5 +1,5 @@ /* Definitions for LynxOS on i386. - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/lzcntintrin.h b/gcc/config/i386/lzcntintrin.h index 9f9f145c4bd..413267ac21c 100644 --- a/gcc/config/i386/lzcntintrin.h +++ b/gcc/config/i386/lzcntintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2015 Free Software Foundation, Inc. +/* Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mingw-pthread.h b/gcc/config/i386/mingw-pthread.h index 56af1244430..9c1413c8dd2 100644 --- a/gcc/config/i386/mingw-pthread.h +++ b/gcc/config/i386/mingw-pthread.h @@ -1,6 +1,6 @@ /* Defines that pthread library shall be enabled by default for target. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mingw-stdint.h b/gcc/config/i386/mingw-stdint.h index 5fee1b62c2d..d53290e739d 100644 --- a/gcc/config/i386/mingw-stdint.h +++ b/gcc/config/i386/mingw-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using mingw. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mingw-w64.h b/gcc/config/i386/mingw-w64.h index 578a7b7c699..fe11333a2d1 100644 --- a/gcc/config/i386/mingw-w64.h +++ b/gcc/config/i386/mingw-w64.h @@ -1,7 +1,7 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows 32/64 via mingw-w64 runtime, using GNU tools and the Windows API Library. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mingw-w64.opt b/gcc/config/i386/mingw-w64.opt index 40f06c3e30c..6d82c1d6be1 100644 --- a/gcc/config/i386/mingw-w64.opt +++ b/gcc/config/i386/mingw-w64.opt @@ -1,6 +1,6 @@ ; MinGW-w64-specific options. -; Copyright (C) 2009-2015 Free Software Foundation, Inc. +; Copyright (C) 2009-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/mingw.opt b/gcc/config/i386/mingw.opt index 03c7a14703f..bdb91581431 100644 --- a/gcc/config/i386/mingw.opt +++ b/gcc/config/i386/mingw.opt @@ -1,6 +1,6 @@ ; MinGW-specific options. -; Copyright (C) 2008-2015 Free Software Foundation, Inc. +; Copyright (C) 2008-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/mingw32.h b/gcc/config/i386/mingw32.h index eef90fb17aa..4ac5f688033 100644 --- a/gcc/config/i386/mingw32.h +++ b/gcc/config/i386/mingw32.h @@ -1,6 +1,6 @@ /* Operating system specific defines to be used when targeting GCC for hosting on Windows32, using GNU tools and the Windows32 API Library. - Copyright (C) 1997-2015 Free Software Foundation, Inc. + Copyright (C) 1997-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mm3dnow.h b/gcc/config/i386/mm3dnow.h index 2a88997232d..f7371f76640 100644 --- a/gcc/config/i386/mm3dnow.h +++ b/gcc/config/i386/mm3dnow.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2004-2015 Free Software Foundation, Inc. +/* Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h index d0984735717..d5a1f00216d 100644 --- a/gcc/config/i386/mmintrin.h +++ b/gcc/config/i386/mmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002-2015 Free Software Foundation, Inc. +/* Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 673ed7af123..a2e7231e1a9 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1,5 +1,5 @@ ;; GCC machine description for MMX and 3dNOW! instructions -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/msformat-c.c b/gcc/config/i386/msformat-c.c index 1b05eac78b7..651f1db91b1 100644 --- a/gcc/config/i386/msformat-c.c +++ b/gcc/config/i386/msformat-c.c @@ -1,5 +1,5 @@ /* Check calls to formatted I/O functions (-Wformat). - Copyright (C) 1992-2015 Free Software Foundation, Inc. + Copyright (C) 1992-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/mwaitxintrin.h b/gcc/config/i386/mwaitxintrin.h index d7112dad205..270034d9249 100644 --- a/gcc/config/i386/mwaitxintrin.h +++ b/gcc/config/i386/mwaitxintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/netbsd-elf.h b/gcc/config/i386/netbsd-elf.h index 426441984b4..a6668200f05 100644 --- a/gcc/config/i386/netbsd-elf.h +++ b/gcc/config/i386/netbsd-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for i386/ELF NetBSD systems. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by matthew green <mrg@eterna.com.au> This file is part of GCC. diff --git a/gcc/config/i386/netbsd64.h b/gcc/config/i386/netbsd64.h index 3d9c705316f..d1e2925ebcb 100644 --- a/gcc/config/i386/netbsd64.h +++ b/gcc/config/i386/netbsd64.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for x86-64/ELF NetBSD systems. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. This file is part of GCC. diff --git a/gcc/config/i386/nmmintrin.h b/gcc/config/i386/nmmintrin.h index da9311e7606..9cb284747ac 100644 --- a/gcc/config/i386/nmmintrin.h +++ b/gcc/config/i386/nmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/nto.h b/gcc/config/i386/nto.h index 606311221f5..1866cf7141b 100644 --- a/gcc/config/i386/nto.h +++ b/gcc/config/i386/nto.h @@ -1,5 +1,5 @@ /* Definitions for Intel 386 running QNX/Neutrino. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/nto.opt b/gcc/config/i386/nto.opt index 25fa4ca770a..12486383316 100644 --- a/gcc/config/i386/nto.opt +++ b/gcc/config/i386/nto.opt @@ -1,6 +1,6 @@ ; QNX options. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/i386/openbsd.h b/gcc/config/i386/openbsd.h index 260d3555553..325f1b93de7 100644 --- a/gcc/config/i386/openbsd.h +++ b/gcc/config/i386/openbsd.h @@ -1,5 +1,5 @@ /* Configuration for an OpenBSD i386 target. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/openbsdelf.h b/gcc/config/i386/openbsdelf.h index f9ce55902f6..eb8d9868489 100644 --- a/gcc/config/i386/openbsdelf.h +++ b/gcc/config/i386/openbsdelf.h @@ -1,6 +1,6 @@ /* Configuration for an OpenBSD i386 target. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/pcommitintrin.h b/gcc/config/i386/pcommitintrin.h index f9bc2f891f8..44e7a779909 100644 --- a/gcc/config/i386/pcommitintrin.h +++ b/gcc/config/i386/pcommitintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/pentium.md b/gcc/config/i386/pentium.md index 5064dd3a0a4..bb62b12a574 100644 --- a/gcc/config/i386/pentium.md +++ b/gcc/config/i386/pentium.md @@ -1,5 +1,5 @@ ;; Pentium Scheduling -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/pkuintrin.h b/gcc/config/i386/pkuintrin.h new file mode 100644 index 00000000000..09fdcd1d3f3 --- /dev/null +++ b/gcc/config/i386/pkuintrin.h @@ -0,0 +1,56 @@ +/* Copyright (C) 2015-2016 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#if !defined _X86INTRIN_H_INCLUDED +# error "Never use <pkuintrin.h> directly; include <x86intrin.h> instead." +#endif + +#ifndef _PKUINTRIN_H_INCLUDED +#define _PKUINTRIN_H_INCLUDED + +#ifndef __PKU__ +#pragma GCC push_options +#pragma GCC target("pku") +#define __DISABLE_PKU__ +#endif /* __PKU__ */ + +extern __inline unsigned int +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_rdpkru_u32(void) +{ + return __builtin_ia32_rdpkru (); +} + +extern __inline void +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_wrpkru(unsigned int key) +{ + return __builtin_ia32_wrpkru (key); +} + +#ifdef __DISABLE_PKU__ +#undef __DISABLE_PKU__ +#pragma GCC pop_options +#endif /* __DISABLE_PKU__ */ + +#endif /* _PKUINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h index 901001b524a..a1f98d3d105 100644 --- a/gcc/config/i386/pmm_malloc.h +++ b/gcc/config/i386/pmm_malloc.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2004-2015 Free Software Foundation, Inc. +/* Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/pmmintrin.h b/gcc/config/i386/pmmintrin.h index feb42deadfc..6fb8e5d3df2 100644 --- a/gcc/config/i386/pmmintrin.h +++ b/gcc/config/i386/pmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2003-2015 Free Software Foundation, Inc. +/* Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/popcntintrin.h b/gcc/config/i386/popcntintrin.h index d5ccf3164e1..9fd196f31a4 100644 --- a/gcc/config/i386/popcntintrin.h +++ b/gcc/config/i386/popcntintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2015 Free Software Foundation, Inc. +/* Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/ppro.md b/gcc/config/i386/ppro.md index 979acc1e33e..f8a101b8721 100644 --- a/gcc/config/i386/ppro.md +++ b/gcc/config/i386/ppro.md @@ -1,5 +1,5 @@ ;; Scheduling for the Intel P6 family of processors -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 8bdd5d88efb..14e80d9b48f 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for IA-32 and x86-64. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -597,14 +597,38 @@ (match_operand 0 "memory_operand")))) ;; Return true if OP is a memory operands that can be used in sibcalls. +;; Since sibcall never returns, we can only use call-clobbered register +;; as GOT base. Allow GOT slot here only with pseudo register as GOT +;; base. Properly handle sibcall over GOT slot with *sibcall_GOT_32 +;; and *sibcall_value_GOT_32 patterns. (define_predicate "sibcall_memory_operand" - (and (match_operand 0 "memory_operand") - (match_test "CONSTANT_P (XEXP (op, 0)) - || (GET_CODE (XEXP (op, 0)) == PLUS - && REG_P (XEXP (XEXP (op, 0), 0)) - && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST - && GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 0)) == UNSPEC - && XINT (XEXP (XEXP (XEXP (op, 0), 1), 0), 1) == UNSPEC_GOT)"))) + (match_operand 0 "memory_operand") +{ + op = XEXP (op, 0); + if (CONSTANT_P (op)) + return true; + if (GET_CODE (op) == PLUS && REG_P (XEXP (op, 0))) + { + int regno = REGNO (XEXP (op, 0)); + if (!HARD_REGISTER_NUM_P (regno) || call_used_regs[regno]) + { + op = XEXP (op, 1); + if (GOT32_symbol_operand (op, VOIDmode)) + return true; + } + } + return false; +}) + +;; Return true if OP is a GOT memory operand. +(define_predicate "GOT_memory_operand" + (match_operand 0 "memory_operand") +{ + op = XEXP (op, 0); + return (GET_CODE (op) == CONST + && GET_CODE (XEXP (op, 0)) == UNSPEC + && XINT (XEXP (op, 0), 1) == UNSPEC_GOTPCREL); +}) ;; Test for a valid operand for a call instruction. ;; Allow constant call address operands in Pmode only. @@ -612,26 +636,26 @@ (ior (match_test "constant_call_address_operand (op, mode == VOIDmode ? mode : Pmode)") (match_operand 0 "call_register_no_elim_operand") - (and (not (match_test "TARGET_X32")) - (match_operand 0 "memory_operand")))) + (ior (and (not (match_test "TARGET_X32")) + (match_operand 0 "sibcall_memory_operand")) + (and (match_test "TARGET_X32 && Pmode == DImode") + (match_operand 0 "GOT_memory_operand"))))) ;; Similarly, but for tail calls, in which we cannot allow memory references. (define_special_predicate "sibcall_insn_operand" (ior (match_test "constant_call_address_operand (op, mode == VOIDmode ? mode : Pmode)") (match_operand 0 "register_no_elim_operand") - (and (not (match_test "TARGET_X32")) - (match_operand 0 "sibcall_memory_operand")))) + (ior (and (not (match_test "TARGET_X32")) + (match_operand 0 "sibcall_memory_operand")) + (and (match_test "TARGET_X32 && Pmode == DImode") + (match_operand 0 "GOT_memory_operand"))))) -;; Return true if OP is a GOT memory operand. -(define_predicate "GOT_memory_operand" - (match_operand 0 "memory_operand") -{ - op = XEXP (op, 0); - return (GET_CODE (op) == CONST - && GET_CODE (XEXP (op, 0)) == UNSPEC - && XINT (XEXP (op, 0), 1) == UNSPEC_GOTPCREL); -}) +;; Return true if OP is a 32-bit GOT symbol operand. +(define_predicate "GOT32_symbol_operand" + (match_test "GET_CODE (op) == CONST + && GET_CODE (XEXP (op, 0)) == UNSPEC + && XINT (XEXP (op, 0), 1) == UNSPEC_GOT")) ;; Match exactly zero. (define_predicate "const0_operand" @@ -927,6 +951,18 @@ (match_test "INTEGRAL_MODE_P (GET_MODE (op))") (match_test "op == CONSTM1_RTX (GET_MODE (op))"))) +; Return true when OP is operand acceptable for vector memory operand. +; Only AVX can have misaligned memory operand. +(define_predicate "vector_memory_operand" + (and (match_operand 0 "memory_operand") + (ior (match_test "TARGET_AVX") + (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)")))) + +; Return true when OP is register_operand or vector_memory_operand. +(define_predicate "vector_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "vector_memory_operand"))) + ; Return true when OP is operand acceptable for standard SSE move. (define_predicate "vector_move_operand" (ior (match_operand 0 "nonimmediate_operand") @@ -1567,9 +1603,9 @@ return val == ((low << 8) | low); }) -;; Return true if OP is nonimmediate_operand or CONST_VECTOR. +;; Return true if OP is vector_operand or CONST_VECTOR. (define_predicate "general_vector_operand" - (ior (match_operand 0 "nonimmediate_operand") + (ior (match_operand 0 "vector_operand") (match_code "const_vector"))) ;; Return true if OP is either -1 constant or stored in register. diff --git a/gcc/config/i386/prfchwintrin.h b/gcc/config/i386/prfchwintrin.h index 2f157162736..91d905d9fe3 100644 --- a/gcc/config/i386/prfchwintrin.h +++ b/gcc/config/i386/prfchwintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/rdos.h b/gcc/config/i386/rdos.h index ccf6b78824a..d98146d5d45 100644 --- a/gcc/config/i386/rdos.h +++ b/gcc/config/i386/rdos.h @@ -1,5 +1,5 @@ /* Definitions for RDOS on i386. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/rdos64.h b/gcc/config/i386/rdos64.h index efd3f60c0de..f5a8b86acfa 100644 --- a/gcc/config/i386/rdos64.h +++ b/gcc/config/i386/rdos64.h @@ -1,5 +1,5 @@ /* Definitions for RDOS on x86_64. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/rdseedintrin.h b/gcc/config/i386/rdseedintrin.h index b65fbc91cae..5af5eac4ad8 100644 --- a/gcc/config/i386/rdseedintrin.h +++ b/gcc/config/i386/rdseedintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/rtemself.h b/gcc/config/i386/rtemself.h index f5c4d854102..8b7dc5e5d17 100644 --- a/gcc/config/i386/rtemself.h +++ b/gcc/config/i386/rtemself.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting an ix86 using ELF. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/i386/rtmintrin.h b/gcc/config/i386/rtmintrin.h index 6396c9dbc48..14e29fc1556 100644 --- a/gcc/config/i386/rtmintrin.h +++ b/gcc/config/i386/rtmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/shaintrin.h b/gcc/config/i386/shaintrin.h index a483b458dea..2059a662633 100644 --- a/gcc/config/i386/shaintrin.h +++ b/gcc/config/i386/shaintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2013-2015 Free Software Foundation, Inc. +/* Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/slm.md b/gcc/config/i386/slm.md index 9052323ebae..24ab3f8da1a 100644 --- a/gcc/config/i386/slm.md +++ b/gcc/config/i386/slm.md @@ -1,5 +1,5 @@ ;; Slivermont(SLM) Scheduling -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/smmintrin.h b/gcc/config/i386/smmintrin.h index b078780ce02..47e0a909689 100644 --- a/gcc/config/i386/smmintrin.h +++ b/gcc/config/i386/smmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/sol2.h b/gcc/config/i386/sol2.h index ed963f89201..51d1c55de0d 100644 --- a/gcc/config/i386/sol2.h +++ b/gcc/config/i386/sol2.h @@ -1,5 +1,5 @@ /* Target definitions for GCC for Intel 80386 running Solaris 2 - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. Contributed by Fred Fish (fnf@cygnus.com). This file is part of GCC. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 6740edf7a9f..84d2b7af59b 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1,5 +1,5 @@ ;; GCC machine description for SSE instructions -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -960,30 +960,20 @@ (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")))] "TARGET_AVX512F" { - static char buf [64]; - - const char *insn_op; - const char *sse_suffix; - const char *align; if (FLOAT_MODE_P (GET_MODE_INNER (<MODE>mode))) { - insn_op = "vmov"; - sse_suffix = "<ssemodesuffix>"; + if (misaligned_operand (operands[1], <MODE>mode)) + return "vmovu<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"; + else + return "vmova<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"; } else { - insn_op = "vmovdq"; - sse_suffix = "<ssescalarsize>"; + if (misaligned_operand (operands[1], <MODE>mode)) + return "vmovdqu<ssescalarsize>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"; + else + return "vmovdqa<ssescalarsize>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"; } - - if (misaligned_operand (operands[1], <MODE>mode)) - align = "u"; - else - align = "a"; - - snprintf (buf, sizeof (buf), "%s%s%s\t{%%1, %%0%%{%%3%%}%%N2|%%0%%{%%3%%}%%N2, %%1}", - insn_op, align, sse_suffix); - return buf; } [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -1035,30 +1025,20 @@ (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")))] "TARGET_AVX512F" { - static char buf [64]; - - const char *insn_op; - const char *sse_suffix; - const char *align; if (FLOAT_MODE_P (GET_MODE_INNER (<MODE>mode))) { - insn_op = "vmov"; - sse_suffix = "<ssemodesuffix>"; + if (misaligned_operand (operands[0], <MODE>mode)) + return "vmovu<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}"; + else + return "vmova<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}"; } else { - insn_op = "vmovdq"; - sse_suffix = "<ssescalarsize>"; + if (misaligned_operand (operands[0], <MODE>mode)) + return "vmovdqu<ssescalarsize>\t{%1, %0%{%2%}|%0%{%2%}, %1}"; + else + return "vmovdqa<ssescalarsize>\t{%1, %0%{%2%}|%0%{%2%}, %1}"; } - - if (misaligned_operand (operands[0], <MODE>mode)) - align = "u"; - else - align = "a"; - - snprintf (buf, sizeof (buf), "%s%s%s\t{%%1, %%0%%{%%2%%}|%%0%%{%%2%%}, %%1}", - insn_op, align, sse_suffix); - return buf; } [(set_attr "type" "ssemov") (set_attr "prefix" "evex") @@ -1629,8 +1609,8 @@ (define_insn_and_split "*absneg<mode>2" [(set (match_operand:VF 0 "register_operand" "=x,x,v,v") (match_operator:VF 3 "absneg_operator" - [(match_operand:VF 1 "nonimmediate_operand" "0, xm, v, m")])) - (use (match_operand:VF 2 "nonimmediate_operand" "xm, 0, vm,v"))] + [(match_operand:VF 1 "vector_operand" "0, xBm,v, m")])) + (use (match_operand:VF 2 "vector_operand" "xBm,0, vm,v"))] "TARGET_SSE" "#" "&& reload_completed" @@ -1676,7 +1656,7 @@ [(set (match_operand:VF 0 "register_operand" "=x,v") (plusminus:VF (match_operand:VF 1 "<round_nimm_predicate>" "<comm>0,v") - (match_operand:VF 2 "<round_nimm_predicate>" "xm,<round_constraint>")))] + (match_operand:VF 2 "<round_nimm_predicate>" "xBm,<round_constraint>")))] "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) && <mask_mode512bit_condition> && <round_mode512bit_condition>" "@ <plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2} @@ -1691,7 +1671,7 @@ (vec_merge:VF_128 (plusminus:VF_128 (match_operand:VF_128 1 "register_operand" "0,v") - (match_operand:VF_128 2 "nonimmediate_operand" "xm,<round_constraint>")) + (match_operand:VF_128 2 "vector_operand" "xBm,<round_constraint>")) (match_dup 1) (const_int 1)))] "TARGET_SSE" @@ -1715,7 +1695,7 @@ [(set (match_operand:VF 0 "register_operand" "=x,v") (mult:VF (match_operand:VF 1 "<round_nimm_predicate>" "%0,v") - (match_operand:VF 2 "<round_nimm_predicate>" "xm,<round_constraint>")))] + (match_operand:VF 2 "<round_nimm_predicate>" "xBm,<round_constraint>")))] "TARGET_SSE && ix86_binary_operator_ok (MULT, <MODE>mode, operands) && <mask_mode512bit_condition> && <round_mode512bit_condition>" "@ mul<ssemodesuffix>\t{%2, %0|%0, %2} @@ -1731,7 +1711,7 @@ (vec_merge:VF_128 (multdiv:VF_128 (match_operand:VF_128 1 "register_operand" "0,v") - (match_operand:VF_128 2 "nonimmediate_operand" "xm,<round_constraint>")) + (match_operand:VF_128 2 "vector_operand" "xBm,<round_constraint>")) (match_dup 1) (const_int 1)))] "TARGET_SSE" @@ -1747,14 +1727,14 @@ (define_expand "div<mode>3" [(set (match_operand:VF2 0 "register_operand") (div:VF2 (match_operand:VF2 1 "register_operand") - (match_operand:VF2 2 "nonimmediate_operand")))] + (match_operand:VF2 2 "vector_operand")))] "TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands);") (define_expand "div<mode>3" [(set (match_operand:VF1 0 "register_operand") (div:VF1 (match_operand:VF1 1 "register_operand") - (match_operand:VF1 2 "nonimmediate_operand")))] + (match_operand:VF1 2 "vector_operand")))] "TARGET_SSE" { ix86_fixup_binary_operands_no_copy (DIV, <MODE>mode, operands); @@ -1774,7 +1754,7 @@ [(set (match_operand:VF 0 "register_operand" "=x,v") (div:VF (match_operand:VF 1 "register_operand" "0,v") - (match_operand:VF 2 "<round_nimm_predicate>" "xm,<round_constraint>")))] + (match_operand:VF 2 "<round_nimm_predicate>" "xBm,<round_constraint>")))] "TARGET_SSE && <mask_mode512bit_condition> && <round_mode512bit_condition>" "@ div<ssemodesuffix>\t{%2, %0|%0, %2} @@ -1787,7 +1767,7 @@ (define_insn "<sse>_rcp<mode>2" [(set (match_operand:VF1_128_256 0 "register_operand" "=x") (unspec:VF1_128_256 - [(match_operand:VF1_128_256 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))] + [(match_operand:VF1_128_256 1 "vector_operand" "xBm")] UNSPEC_RCP))] "TARGET_SSE" "%vrcpps\t{%1, %0|%0, %1}" [(set_attr "type" "sse") @@ -1842,12 +1822,12 @@ (define_expand "sqrt<mode>2" [(set (match_operand:VF2 0 "register_operand") - (sqrt:VF2 (match_operand:VF2 1 "nonimmediate_operand")))] + (sqrt:VF2 (match_operand:VF2 1 "vector_operand")))] "TARGET_SSE2") (define_expand "sqrt<mode>2" [(set (match_operand:VF1 0 "register_operand") - (sqrt:VF1 (match_operand:VF1 1 "nonimmediate_operand")))] + (sqrt:VF1 (match_operand:VF1 1 "vector_operand")))] "TARGET_SSE" { if (TARGET_SSE_MATH @@ -1862,11 +1842,14 @@ }) (define_insn "<sse>_sqrt<mode>2<mask_name><round_name>" - [(set (match_operand:VF 0 "register_operand" "=v") - (sqrt:VF (match_operand:VF 1 "<round_nimm_predicate>" "<round_constraint>")))] + [(set (match_operand:VF 0 "register_operand" "=x,v") + (sqrt:VF (match_operand:VF 1 "<round_nimm_predicate>" "xBm,<round_constraint>")))] "TARGET_SSE && <mask_mode512bit_condition> && <round_mode512bit_condition>" - "%vsqrt<ssemodesuffix>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" - [(set_attr "type" "sse") + "@ + sqrt<ssemodesuffix>\t{%1, %0|%0, %1} + vsqrt<ssemodesuffix>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sse") (set_attr "atom_sse_attr" "sqrt") (set_attr "btver2_sse_attr" "sqrt") (set_attr "prefix" "maybe_vex") @@ -1876,7 +1859,7 @@ [(set (match_operand:VF_128 0 "register_operand" "=x,v") (vec_merge:VF_128 (sqrt:VF_128 - (match_operand:VF_128 1 "nonimmediate_operand" "xm,<round_constraint>")) + (match_operand:VF_128 1 "vector_operand" "xBm,<round_constraint>")) (match_operand:VF_128 2 "register_operand" "0,v") (const_int 1)))] "TARGET_SSE" @@ -1893,7 +1876,7 @@ (define_expand "rsqrt<mode>2" [(set (match_operand:VF1_128_256 0 "register_operand") (unspec:VF1_128_256 - [(match_operand:VF1_128_256 1 "nonimmediate_operand")] UNSPEC_RSQRT))] + [(match_operand:VF1_128_256 1 "vector_operand")] UNSPEC_RSQRT))] "TARGET_SSE_MATH" { ix86_emit_swsqrtsf (operands[0], operands[1], <MODE>mode, true); @@ -1903,7 +1886,7 @@ (define_insn "<sse>_rsqrt<mode>2" [(set (match_operand:VF1_128_256 0 "register_operand" "=x") (unspec:VF1_128_256 - [(match_operand:VF1_128_256 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))] + [(match_operand:VF1_128_256 1 "vector_operand" "xBm")] UNSPEC_RSQRT))] "TARGET_SSE" "%vrsqrtps\t{%1, %0|%0, %1}" [(set_attr "type" "sse") @@ -1972,7 +1955,7 @@ [(set (match_operand:VF 0 "register_operand" "=x,v") (smaxmin:VF (match_operand:VF 1 "<round_saeonly_nimm_predicate>" "%0,v") - (match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xm,<round_saeonly_constraint>")))] + (match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xBm,<round_saeonly_constraint>")))] "TARGET_SSE && flag_finite_math_only && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands) && <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>" @@ -1989,7 +1972,7 @@ [(set (match_operand:VF 0 "register_operand" "=x,v") (smaxmin:VF (match_operand:VF 1 "register_operand" "0,v") - (match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xm,<round_saeonly_constraint>")))] + (match_operand:VF 2 "<round_saeonly_nimm_predicate>" "xBm,<round_saeonly_constraint>")))] "TARGET_SSE && !flag_finite_math_only && <mask_mode512bit_condition> && <round_saeonly_mode512bit_condition>" "@ @@ -2006,7 +1989,7 @@ (vec_merge:VF_128 (smaxmin:VF_128 (match_operand:VF_128 1 "register_operand" "0,v") - (match_operand:VF_128 2 "nonimmediate_operand" "xm,<round_saeonly_constraint>")) + (match_operand:VF_128 2 "vector_operand" "xBm,<round_saeonly_constraint>")) (match_dup 1) (const_int 1)))] "TARGET_SSE" @@ -2026,10 +2009,10 @@ ;; presence of -0.0 and NaN. (define_insn "*ieee_smin<mode>3" - [(set (match_operand:VF 0 "register_operand" "=v,v") + [(set (match_operand:VF 0 "register_operand" "=x,v") (unspec:VF [(match_operand:VF 1 "register_operand" "0,v") - (match_operand:VF 2 "nonimmediate_operand" "vm,vm")] + (match_operand:VF 2 "vector_operand" "xBm,vm")] UNSPEC_IEEE_MIN))] "TARGET_SSE" "@ @@ -2041,10 +2024,10 @@ (set_attr "mode" "<MODE>")]) (define_insn "*ieee_smax<mode>3" - [(set (match_operand:VF 0 "register_operand" "=v,v") + [(set (match_operand:VF 0 "register_operand" "=x,v") (unspec:VF [(match_operand:VF 1 "register_operand" "0,v") - (match_operand:VF 2 "nonimmediate_operand" "vm,vm")] + (match_operand:VF 2 "vector_operand" "xBm,vm")] UNSPEC_IEEE_MAX))] "TARGET_SSE" "@ @@ -2074,7 +2057,7 @@ (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0,x") - (match_operand:V2DF 2 "nonimmediate_operand" "xm,xm")) + (match_operand:V2DF 2 "vector_operand" "xBm,xm")) (plus:V2DF (match_dup 1) (match_dup 2)) (const_int 1)))] "TARGET_SSE3" @@ -2106,7 +2089,7 @@ (vec_merge:V4SF (minus:V4SF (match_operand:V4SF 1 "register_operand" "0,x") - (match_operand:V4SF 2 "nonimmediate_operand" "xm,xm")) + (match_operand:V4SF 2 "vector_operand" "xBm,xm")) (plus:V4SF (match_dup 1) (match_dup 2)) (const_int 5)))] "TARGET_SSE3" @@ -2124,10 +2107,10 @@ (match_operator:VF_128_256 6 "addsub_vm_operator" [(minus:VF_128_256 (match_operand:VF_128_256 1 "register_operand") - (match_operand:VF_128_256 2 "nonimmediate_operand")) + (match_operand:VF_128_256 2 "vector_operand")) (plus:VF_128_256 - (match_operand:VF_128_256 3 "nonimmediate_operand") - (match_operand:VF_128_256 4 "nonimmediate_operand")) + (match_operand:VF_128_256 3 "vector_operand") + (match_operand:VF_128_256 4 "vector_operand")) (match_operand 5 "const_int_operand")]))] "TARGET_SSE3 && can_create_pseudo_p () @@ -2145,11 +2128,11 @@ [(set (match_operand:VF_128_256 0 "register_operand") (match_operator:VF_128_256 6 "addsub_vm_operator" [(plus:VF_128_256 - (match_operand:VF_128_256 1 "nonimmediate_operand") - (match_operand:VF_128_256 2 "nonimmediate_operand")) + (match_operand:VF_128_256 1 "vector_operand") + (match_operand:VF_128_256 2 "vector_operand")) (minus:VF_128_256 (match_operand:VF_128_256 3 "register_operand") - (match_operand:VF_128_256 4 "nonimmediate_operand")) + (match_operand:VF_128_256 4 "vector_operand")) (match_operand 5 "const_int_operand")]))] "TARGET_SSE3 && can_create_pseudo_p () @@ -2175,10 +2158,10 @@ [(vec_concat:<ssedoublemode> (minus:VF_128_256 (match_operand:VF_128_256 1 "register_operand") - (match_operand:VF_128_256 2 "nonimmediate_operand")) + (match_operand:VF_128_256 2 "vector_operand")) (plus:VF_128_256 - (match_operand:VF_128_256 3 "nonimmediate_operand") - (match_operand:VF_128_256 4 "nonimmediate_operand"))) + (match_operand:VF_128_256 3 "vector_operand") + (match_operand:VF_128_256 4 "vector_operand"))) (match_parallel 5 "addsub_vs_parallel" [(match_operand 6 "const_int_operand")])]))] "TARGET_SSE3 @@ -2208,11 +2191,11 @@ (match_operator:VF_128_256 7 "addsub_vs_operator" [(vec_concat:<ssedoublemode> (plus:VF_128_256 - (match_operand:VF_128_256 1 "nonimmediate_operand") - (match_operand:VF_128_256 2 "nonimmediate_operand")) + (match_operand:VF_128_256 1 "vector_operand") + (match_operand:VF_128_256 2 "vector_operand")) (minus:VF_128_256 (match_operand:VF_128_256 3 "register_operand") - (match_operand:VF_128_256 4 "nonimmediate_operand"))) + (match_operand:VF_128_256 4 "vector_operand"))) (match_parallel 5 "addsub_vs_parallel" [(match_operand 6 "const_int_operand")])]))] "TARGET_SSE3 @@ -2274,7 +2257,7 @@ (vec_select:DF (match_dup 1) (parallel [(const_int 1)]))) (plus:DF (vec_select:DF - (match_operand:V2DF 2 "nonimmediate_operand") + (match_operand:V2DF 2 "vector_operand") (parallel [(const_int 0)])) (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))] "TARGET_SSE3") @@ -2291,7 +2274,7 @@ (parallel [(match_operand:SI 4 "const_0_to_1_operand")]))) (plus:DF (vec_select:DF - (match_operand:V2DF 2 "nonimmediate_operand" "xm,xm") + (match_operand:V2DF 2 "vector_operand" "xBm,xm") (parallel [(match_operand:SI 5 "const_0_to_1_operand")])) (vec_select:DF (match_dup 2) @@ -2317,7 +2300,7 @@ (vec_select:DF (match_dup 1) (parallel [(const_int 1)]))) (minus:DF (vec_select:DF - (match_operand:V2DF 2 "nonimmediate_operand" "xm,xm") + (match_operand:V2DF 2 "vector_operand" "xBm,xm") (parallel [(const_int 0)])) (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))] "TARGET_SSE3" @@ -2424,7 +2407,7 @@ (vec_concat:V2SF (plusminus:SF (vec_select:SF - (match_operand:V4SF 2 "nonimmediate_operand" "xm,xm") + (match_operand:V4SF 2 "vector_operand" "xBm,xm") (parallel [(const_int 0)])) (vec_select:SF (match_dup 2) (parallel [(const_int 1)]))) (plusminus:SF @@ -2650,7 +2633,7 @@ [(set (match_operand:VF_128_256 0 "register_operand" "=x,x") (match_operator:VF_128_256 3 "sse_comparison_operator" [(match_operand:VF_128_256 1 "register_operand" "%0,x") - (match_operand:VF_128_256 2 "nonimmediate_operand" "xm,xm")]))] + (match_operand:VF_128_256 2 "vector_operand" "xBm,xm")]))] "TARGET_SSE && GET_RTX_CLASS (GET_CODE (operands[3])) == RTX_COMM_COMPARE" "@ @@ -2666,7 +2649,7 @@ [(set (match_operand:VF_128_256 0 "register_operand" "=x,x") (match_operator:VF_128_256 3 "sse_comparison_operator" [(match_operand:VF_128_256 1 "register_operand" "0,x") - (match_operand:VF_128_256 2 "nonimmediate_operand" "xm,xm")]))] + (match_operand:VF_128_256 2 "vector_operand" "xBm,xm")]))] "TARGET_SSE" "@ cmp%D3<ssemodesuffix>\t{%2, %0|%0, %2} @@ -2682,7 +2665,7 @@ (vec_merge:VF_128 (match_operator:VF_128 3 "sse_comparison_operator" [(match_operand:VF_128 1 "register_operand" "0,x") - (match_operand:VF_128 2 "nonimmediate_operand" "xm,xm")]) + (match_operand:VF_128 2 "vector_operand" "xBm,xm")]) (match_dup 1) (const_int 1)))] "TARGET_SSE" @@ -2815,7 +2798,7 @@ (match_operand:<ssevecmode> 0 "register_operand" "v") (parallel [(const_int 0)])) (vec_select:MODEF - (match_operand:<ssevecmode> 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") + (match_operand:<ssevecmode> 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") (parallel [(const_int 0)]))))] "SSE_FLOAT_MODE_P (<MODE>mode)" "%vcomi<ssemodesuffix>\t{<round_saeonly_op2>%1, %0|%0, %<iptr>1<round_saeonly_op2>}" @@ -2835,7 +2818,7 @@ (match_operand:<ssevecmode> 0 "register_operand" "v") (parallel [(const_int 0)])) (vec_select:MODEF - (match_operand:<ssevecmode> 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") + (match_operand:<ssevecmode> 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") (parallel [(const_int 0)]))))] "SSE_FLOAT_MODE_P (<MODE>mode)" "%vucomi<ssemodesuffix>\t{<round_saeonly_op2>%1, %0|%0, %<iptr>1<round_saeonly_op2>}" @@ -2888,7 +2871,7 @@ [(set (match_operand:<sseintvecmode> 0 "register_operand") (match_operator:<sseintvecmode> 1 "" [(match_operand:VI124_128 2 "register_operand") - (match_operand:VI124_128 3 "nonimmediate_operand")]))] + (match_operand:VI124_128 3 "vector_operand")]))] "TARGET_SSE2" { bool ok = ix86_expand_int_vec_cmp (operands); @@ -2900,7 +2883,7 @@ [(set (match_operand:V2DI 0 "register_operand") (match_operator:V2DI 1 "" [(match_operand:V2DI 2 "register_operand") - (match_operand:V2DI 3 "nonimmediate_operand")]))] + (match_operand:V2DI 3 "vector_operand")]))] "TARGET_SSE4_2" { bool ok = ix86_expand_int_vec_cmp (operands); @@ -2924,7 +2907,7 @@ [(set (match_operand:<sseintvecmode> 0 "register_operand") (match_operator:<sseintvecmode> 1 "" [(match_operand:VF_128 2 "register_operand") - (match_operand:VF_128 3 "nonimmediate_operand")]))] + (match_operand:VF_128 3 "vector_operand")]))] "TARGET_SSE" { bool ok = ix86_expand_fp_vec_cmp (operands); @@ -2972,7 +2955,7 @@ [(set (match_operand:<sseintvecmode> 0 "register_operand") (match_operator:<sseintvecmode> 1 "" [(match_operand:VI124_128 2 "register_operand") - (match_operand:VI124_128 3 "nonimmediate_operand")]))] + (match_operand:VI124_128 3 "vector_operand")]))] "TARGET_SSE2" { bool ok = ix86_expand_int_vec_cmp (operands); @@ -2984,7 +2967,7 @@ [(set (match_operand:V2DI 0 "register_operand") (match_operator:V2DI 1 "" [(match_operand:V2DI 2 "register_operand") - (match_operand:V2DI 3 "nonimmediate_operand")]))] + (match_operand:V2DI 3 "vector_operand")]))] "TARGET_SSE4_2" { bool ok = ix86_expand_int_vec_cmp (operands); @@ -3030,8 +3013,8 @@ [(set (match_operand:V_128 0 "register_operand") (if_then_else:V_128 (match_operator 3 "" - [(match_operand:VF_128 4 "nonimmediate_operand") - (match_operand:VF_128 5 "nonimmediate_operand")]) + [(match_operand:VF_128 4 "vector_operand") + (match_operand:VF_128 5 "vector_operand")]) (match_operand:V_128 1 "general_operand") (match_operand:V_128 2 "general_operand")))] "TARGET_SSE @@ -3075,7 +3058,7 @@ (define_expand "vcond_mask_<mode><sseintvecmodelower>" [(set (match_operand:VI124_128 0 "register_operand") (vec_merge:VI124_128 - (match_operand:VI124_128 1 "nonimmediate_operand") + (match_operand:VI124_128 1 "vector_operand") (match_operand:VI124_128 2 "vector_move_operand") (match_operand:<sseintvecmode> 3 "register_operand")))] "TARGET_SSE2" @@ -3088,7 +3071,7 @@ (define_expand "vcond_mask_v2div2di" [(set (match_operand:V2DI 0 "register_operand") (vec_merge:V2DI - (match_operand:V2DI 1 "nonimmediate_operand") + (match_operand:V2DI 1 "vector_operand") (match_operand:V2DI 2 "vector_move_operand") (match_operand:V2DI 3 "register_operand")))] "TARGET_SSE4_2" @@ -3114,7 +3097,7 @@ (define_expand "vcond_mask_<mode><sseintvecmodelower>" [(set (match_operand:VF_128 0 "register_operand") (vec_merge:VF_128 - (match_operand:VF_128 1 "nonimmediate_operand") + (match_operand:VF_128 1 "vector_operand") (match_operand:VF_128 2 "vector_move_operand") (match_operand:<sseintvecmode> 3 "register_operand")))] "TARGET_SSE" @@ -3135,7 +3118,7 @@ (and:VF_128_256 (not:VF_128_256 (match_operand:VF_128_256 1 "register_operand" "0,v")) - (match_operand:VF_128_256 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VF_128_256 2 "vector_operand" "xBm,vm")))] "TARGET_SSE && <mask_avx512vl_condition>" { static char buf[128]; @@ -3223,8 +3206,8 @@ (define_expand "<code><mode>3<mask_name>" [(set (match_operand:VF_128_256 0 "register_operand") (any_logic:VF_128_256 - (match_operand:VF_128_256 1 "nonimmediate_operand") - (match_operand:VF_128_256 2 "nonimmediate_operand")))] + (match_operand:VF_128_256 1 "vector_operand") + (match_operand:VF_128_256 2 "vector_operand")))] "TARGET_SSE && <mask_avx512vl_condition>" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") @@ -3239,8 +3222,8 @@ (define_insn "*<code><mode>3<mask_name>" [(set (match_operand:VF_128_256 0 "register_operand" "=x,v") (any_logic:VF_128_256 - (match_operand:VF_128_256 1 "nonimmediate_operand" "%0,v") - (match_operand:VF_128_256 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VF_128_256 1 "vector_operand" "%0,v") + (match_operand:VF_128_256 2 "vector_operand" "xBm,vm")))] "TARGET_SSE && <mask_avx512vl_condition> && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" { @@ -3328,10 +3311,10 @@ [(set (match_dup 4) (and:VF (not:VF (match_dup 3)) - (match_operand:VF 1 "nonimmediate_operand"))) + (match_operand:VF 1 "vector_operand"))) (set (match_dup 5) (and:VF (match_dup 3) - (match_operand:VF 2 "nonimmediate_operand"))) + (match_operand:VF 2 "vector_operand"))) (set (match_operand:VF 0 "register_operand") (ior:VF (match_dup 4) (match_dup 5)))] "TARGET_SSE" @@ -3393,7 +3376,7 @@ [(set (match_operand:TF 0 "register_operand" "=x,x") (and:TF (not:TF (match_operand:TF 1 "register_operand" "0,x")) - (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))] + (match_operand:TF 2 "vector_operand" "xBm,xm")))] "TARGET_SSE" { static char buf[32]; @@ -3480,16 +3463,16 @@ (define_expand "<code>tf3" [(set (match_operand:TF 0 "register_operand") (any_logic:TF - (match_operand:TF 1 "nonimmediate_operand") - (match_operand:TF 2 "nonimmediate_operand")))] + (match_operand:TF 1 "vector_operand") + (match_operand:TF 2 "vector_operand")))] "TARGET_SSE" "ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);") (define_insn "*<code>tf3" [(set (match_operand:TF 0 "register_operand" "=x,x") (any_logic:TF - (match_operand:TF 1 "nonimmediate_operand" "%0,x") - (match_operand:TF 2 "nonimmediate_operand" "xm,xm")))] + (match_operand:TF 1 "vector_operand" "%0,x") + (match_operand:TF 2 "vector_operand" "xBm,xm")))] "TARGET_SSE && ix86_binary_operator_ok (<CODE>, TFmode, operands)" { @@ -4269,7 +4252,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=x,x,v") (vec_merge:V4SF (vec_duplicate:V4SF - (float:SF (match_operand:SI 2 "<round_nimm_predicate>" "r,m,<round_constraint3>"))) + (float:SF (match_operand:SI 2 "<round_nimm_scalar_predicate>" "r,m,<round_constraint3>"))) (match_operand:V4SF 1 "register_operand" "0,0,v") (const_int 1)))] "TARGET_SSE" @@ -4291,7 +4274,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=x,x,v") (vec_merge:V4SF (vec_duplicate:V4SF - (float:SF (match_operand:DI 2 "<round_nimm_predicate>" "r,m,<round_constraint3>"))) + (float:SF (match_operand:DI 2 "<round_nimm_scalar_predicate>" "r,m,<round_constraint3>"))) (match_operand:V4SF 1 "register_operand" "0,0,v") (const_int 1)))] "TARGET_SSE && TARGET_64BIT" @@ -4314,7 +4297,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(vec_select:SF - (match_operand:V4SF 1 "<round_nimm_predicate>" "v,<round_constraint2>") + (match_operand:V4SF 1 "<round_nimm_scalar_predicate>" "v,<round_constraint2>") (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE" @@ -4344,7 +4327,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (unspec:DI [(vec_select:SF - (match_operand:V4SF 1 "<round_nimm_predicate>" "v,<round_constraint2>") + (match_operand:V4SF 1 "<round_nimm_scalar_predicate>" "v,<round_constraint2>") (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE && TARGET_64BIT" @@ -4374,7 +4357,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r") (fix:SI (vec_select:SF - (match_operand:V4SF 1 "<round_saeonly_nimm_predicate>" "v,<round_saeonly_constraint2>") + (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "v,<round_saeonly_constraint2>") (parallel [(const_int 0)]))))] "TARGET_SSE" "%vcvttss2si\t{<round_saeonly_op2>%1, %0|%0, %k1<round_saeonly_op2>}" @@ -4390,7 +4373,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (fix:DI (vec_select:SF - (match_operand:V4SF 1 "<round_saeonly_nimm_predicate>" "v,<round_saeonly_constraint>") + (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "v,<round_saeonly_constraint>") (parallel [(const_int 0)]))))] "TARGET_SSE && TARGET_64BIT" "%vcvttss2si{q}\t{<round_saeonly_op2>%1, %0|%0, %k1<round_saeonly_op2>}" @@ -4431,12 +4414,15 @@ (set_attr "mode" "<ssescalarmode>")]) (define_insn "float<sseintvecmodelower><mode>2<mask_name><round_name>" - [(set (match_operand:VF1 0 "register_operand" "=v") + [(set (match_operand:VF1 0 "register_operand" "=x,v") (float:VF1 - (match_operand:<sseintvecmode> 1 "<round_nimm_predicate>" "<round_constraint>")))] + (match_operand:<sseintvecmode> 1 "<round_nimm_predicate>" "xBm,<round_constraint>")))] "TARGET_SSE2 && <mask_mode512bit_condition> && <round_mode512bit_condition>" - "%vcvtdq2ps\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" - [(set_attr "type" "ssecvt") + "@ + cvtdq2ps\t{%1, %0|%0, %1} + vcvtdq2ps\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "ssecvt") (set_attr "prefix" "maybe_vex") (set_attr "mode" "<sseinsnmode>")]) @@ -4479,7 +4465,7 @@ (define_insn "<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode><mask_name>" [(set (match_operand:VI4_AVX 0 "register_operand" "=v") (unspec:VI4_AVX - [(match_operand:<ssePSmode> 1 "nonimmediate_operand" "vm")] + [(match_operand:<ssePSmode> 1 "vector_operand" "vBm")] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE2 && <mask_mode512bit_condition>" "%vcvtps2dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" @@ -4581,7 +4567,7 @@ (define_insn "fix_truncv4sfv4si2<mask_name>" [(set (match_operand:V4SI 0 "register_operand" "=v") - (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "vm")))] + (fix:V4SI (match_operand:V4SF 1 "vector_operand" "vBm")))] "TARGET_SSE2 && <mask_avx512vl_condition>" "%vcvttps2dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" [(set_attr "type" "ssecvt") @@ -4684,7 +4670,7 @@ [(set (match_operand:V2DF 0 "register_operand" "=x,x,v") (vec_merge:V2DF (vec_duplicate:V2DF - (float:DF (match_operand:DI 2 "<round_nimm_predicate>" "r,m,<round_constraint3>"))) + (float:DF (match_operand:DI 2 "<round_nimm_scalar_predicate>" "r,m,<round_constraint3>"))) (match_operand:V2DF 1 "register_operand" "0,0,v") (const_int 1)))] "TARGET_SSE2 && TARGET_64BIT" @@ -4732,7 +4718,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unsigned_fix:SI (vec_select:SF - (match_operand:V4SF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") + (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") (parallel [(const_int 0)]))))] "TARGET_AVX512F" "vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}" @@ -4744,7 +4730,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (unsigned_fix:DI (vec_select:SF - (match_operand:V4SF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") + (match_operand:V4SF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") (parallel [(const_int 0)]))))] "TARGET_AVX512F && TARGET_64BIT" "vcvttss2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}" @@ -4782,7 +4768,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unsigned_fix:SI (vec_select:DF - (match_operand:V2DF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") + (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") (parallel [(const_int 0)]))))] "TARGET_AVX512F" "vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}" @@ -4794,7 +4780,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (unsigned_fix:DI (vec_select:DF - (match_operand:V2DF 1 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>") + (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>") (parallel [(const_int 0)]))))] "TARGET_AVX512F && TARGET_64BIT" "vcvttsd2usi\t{<round_saeonly_op2>%1, %0|%0, %1<round_saeonly_op2>}" @@ -4806,7 +4792,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(vec_select:DF - (match_operand:V2DF 1 "<round_nimm_predicate>" "v,<round_constraint2>") + (match_operand:V2DF 1 "<round_nimm_scalar_predicate>" "v,<round_constraint2>") (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE2" @@ -4837,7 +4823,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (unspec:DI [(vec_select:DF - (match_operand:V2DF 1 "<round_nimm_predicate>" "v,<round_constraint2>") + (match_operand:V2DF 1 "<round_nimm_scalar_predicate>" "v,<round_constraint2>") (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE2 && TARGET_64BIT" @@ -4867,7 +4853,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r") (fix:SI (vec_select:DF - (match_operand:V2DF 1 "<round_saeonly_nimm_predicate>" "v,<round_saeonly_constraint2>") + (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "v,<round_saeonly_constraint2>") (parallel [(const_int 0)]))))] "TARGET_SSE2" "%vcvttsd2si\t{<round_saeonly_op2>%1, %0|%0, %q1<round_saeonly_op2>}" @@ -4884,7 +4870,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (fix:DI (vec_select:DF - (match_operand:V2DF 1 "<round_saeonly_nimm_predicate>" "v,<round_saeonly_constraint2>") + (match_operand:V2DF 1 "<round_saeonly_nimm_scalar_predicate>" "v,<round_saeonly_constraint2>") (parallel [(const_int 0)]))))] "TARGET_SSE2 && TARGET_64BIT" "%vcvttsd2si{q}\t{<round_saeonly_op2>%1, %0|%0, %q1<round_saeonly_op2>}" @@ -5081,7 +5067,7 @@ (define_insn "sse2_cvtpd2dq<mask_name>" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_concat:V4SI - (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "vm")] + (unspec:V2SI [(match_operand:V2DF 1 "vector_operand" "vBm")] UNSPEC_FIX_NOTRUNC) (const_vector:V2SI [(const_int 0) (const_int 0)])))] "TARGET_SSE2 && <mask_avx512vl_condition>" @@ -5242,7 +5228,7 @@ (define_insn "sse2_cvttpd2dq<mask_name>" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_concat:V4SI - (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vm")) + (fix:V2SI (match_operand:V2DF 1 "vector_operand" "vBm")) (const_vector:V2SI [(const_int 0) (const_int 0)])))] "TARGET_SSE2 && <mask_avx512vl_condition>" { @@ -5285,7 +5271,7 @@ (vec_merge:V2DF (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 2 "<round_saeonly_nimm_predicate>" "x,m,<round_saeonly_constraint>") + (match_operand:V4SF 2 "<round_saeonly_nimm_scalar_predicate>" "x,m,<round_saeonly_constraint>") (parallel [(const_int 0) (const_int 1)]))) (match_operand:V2DF 1 "register_operand" "0,0,v") (const_int 1)))] @@ -5328,7 +5314,7 @@ [(set (match_operand:V4SF 0 "register_operand") (vec_concat:V4SF (float_truncate:V2SF - (match_operand:V2DF 1 "nonimmediate_operand")) + (match_operand:V2DF 1 "vector_operand")) (match_dup 2)))] "TARGET_SSE2" "operands[2] = CONST0_RTX (V2SFmode);") @@ -5338,7 +5324,7 @@ (vec_merge:V4SF (vec_concat:V4SF (float_truncate:V2SF - (match_operand:V2DF 1 "nonimmediate_operand")) + (match_operand:V2DF 1 "vector_operand")) (match_dup 4)) (match_operand:V4SF 2 "register_operand") (match_operand:QI 3 "register_operand")))] @@ -5349,7 +5335,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_concat:V4SF (float_truncate:V2SF - (match_operand:V2DF 1 "nonimmediate_operand" "vm")) + (match_operand:V2DF 1 "vector_operand" "vBm")) (match_operand:V2SF 2 "const0_operand")))] "TARGET_SSE2 && <mask_avx512vl_condition>" { @@ -5478,7 +5464,7 @@ [(set (match_operand:V2DF 0 "register_operand" "=v") (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (match_operand:V4SF 1 "vector_operand" "vBm") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE2 && <mask_avx512vl_condition>" "%vcvtps2pd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}" @@ -5495,7 +5481,7 @@ (vec_select:V4SF (vec_concat:V8SF (match_dup 2) - (match_operand:V4SF 1 "nonimmediate_operand")) + (match_operand:V4SF 1 "vector_operand")) (parallel [(const_int 6) (const_int 7) (const_int 2) (const_int 3)]))) (set (match_operand:V2DF 0 "register_operand") @@ -5536,7 +5522,7 @@ [(set (match_operand:V2DF 0 "register_operand") (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 1 "nonimmediate_operand") + (match_operand:V4SF 1 "vector_operand") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE2") @@ -5608,7 +5594,7 @@ (define_expand "vec_unpacks_float_hi_v4si" [(set (match_dup 2) (vec_select:V4SI - (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:V4SI 1 "vector_operand") (parallel [(const_int 2) (const_int 3) (const_int 2) (const_int 3)]))) (set (match_operand:V2DF 0 "register_operand") @@ -5623,14 +5609,14 @@ [(set (match_operand:V2DF 0 "register_operand") (float:V2DF (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:V4SI 1 "vector_operand") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE2") (define_expand "vec_unpacks_float_hi_v8si" [(set (match_dup 2) (vec_select:V4SI - (match_operand:V8SI 1 "nonimmediate_operand") + (match_operand:V8SI 1 "vector_operand") (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))) (set (match_operand:V4DF 0 "register_operand") @@ -5676,7 +5662,7 @@ (define_expand "vec_unpacku_float_hi_v4si" [(set (match_dup 5) (vec_select:V4SI - (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:V4SI 1 "vector_operand") (parallel [(const_int 2) (const_int 3) (const_int 2) (const_int 3)]))) (set (match_dup 6) @@ -5713,7 +5699,7 @@ [(set (match_dup 5) (float:V2DF (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:V4SI 1 "vector_operand") (parallel [(const_int 0) (const_int 1)])))) (set (match_dup 6) (lt:V2DF (match_dup 5) (match_dup 3))) @@ -5855,8 +5841,8 @@ (define_expand "vec_pack_trunc_v2df" [(match_operand:V4SF 0 "register_operand") - (match_operand:V2DF 1 "nonimmediate_operand") - (match_operand:V2DF 2 "nonimmediate_operand")] + (match_operand:V2DF 1 "vector_operand") + (match_operand:V2DF 2 "vector_operand")] "TARGET_SSE2" { rtx tmp0, tmp1; @@ -5917,8 +5903,8 @@ (define_expand "vec_pack_sfix_trunc_v2df" [(match_operand:V4SI 0 "register_operand") - (match_operand:V2DF 1 "nonimmediate_operand") - (match_operand:V2DF 2 "nonimmediate_operand")] + (match_operand:V2DF 1 "vector_operand") + (match_operand:V2DF 2 "vector_operand")] "TARGET_SSE2" { rtx tmp0, tmp1, tmp2; @@ -6014,8 +6000,8 @@ (define_expand "vec_pack_sfix_v2df" [(match_operand:V4SI 0 "register_operand") - (match_operand:V2DF 1 "nonimmediate_operand") - (match_operand:V2DF 2 "nonimmediate_operand")] + (match_operand:V2DF 1 "vector_operand") + (match_operand:V2DF 2 "vector_operand")] "TARGET_SSE2" { rtx tmp0, tmp1, tmp2; @@ -6218,7 +6204,7 @@ (vec_select:V4SF (vec_concat:V8SF (match_operand:V4SF 1 "register_operand" "0,v") - (match_operand:V4SF 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V4SF 2 "vector_operand" "xBm,vm")) (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "TARGET_SSE && <mask_avx512vl_condition>" @@ -6323,7 +6309,7 @@ (vec_select:V4SF (vec_concat:V8SF (match_operand:V4SF 1 "register_operand" "0,x") - (match_operand:V4SF 2 "nonimmediate_operand" "xm,xm")) + (match_operand:V4SF 2 "vector_operand" "xBm,xm")) (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "TARGET_SSE" @@ -6357,7 +6343,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_select:V4SF (vec_concat:V8SF - (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (match_operand:V4SF 1 "vector_operand" "vBm") (match_dup 1)) (parallel [(const_int 1) (const_int 1) @@ -6410,7 +6396,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_select:V4SF (vec_concat:V8SF - (match_operand:V4SF 1 "nonimmediate_operand" "vm") + (match_operand:V4SF 1 "vector_operand" "vBm") (match_dup 1)) (parallel [(const_int 0) (const_int 0) @@ -6505,7 +6491,7 @@ (define_expand "sse_shufps<mask_expand4_name>" [(match_operand:V4SF 0 "register_operand") (match_operand:V4SF 1 "register_operand") - (match_operand:V4SF 2 "nonimmediate_operand") + (match_operand:V4SF 2 "vector_operand") (match_operand:SI 3 "const_int_operand")] "TARGET_SSE" { @@ -6555,7 +6541,7 @@ (vec_select:VI4F_128 (vec_concat:<ssedoublevecmode> (match_operand:VI4F_128 1 "register_operand" "0,x") - (match_operand:VI4F_128 2 "nonimmediate_operand" "xm,xm")) + (match_operand:VI4F_128 2 "vector_operand" "xBm,xm")) (parallel [(match_operand 3 "const_0_to_3_operand") (match_operand 4 "const_0_to_3_operand") (match_operand 5 "const_4_to_7_operand") @@ -6651,6 +6637,7 @@ %vmovaps\t{%1, %0|%0, %1} %vmovlps\t{%1, %d0|%d0, %q1}" [(set_attr "type" "ssemov") + (set_attr "ssememalign" "64") (set_attr "prefix" "maybe_vex") (set_attr "mode" "V2SF,V4SF,V2SF")]) @@ -6776,7 +6763,7 @@ (set_attr "mode" "V4SF,V4SF,V4SF,V4SF,V4SF,V4SF,SF,DI,DI")]) ;; ??? In theory we can match memory for the MMX alternative, but allowing -;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE +;; vector_operand for operand 2 and *not* allowing memory for the SSE ;; alternatives pretty much forces the MMX alternative to be chosen. (define_insn "*vec_concatv2sf_sse" [(set (match_operand:V2SF 0 "register_operand" "=x,x,*y,*y") @@ -8501,7 +8488,7 @@ (define_expand "sse2_shufpd<mask_expand4_name>" [(match_operand:V2DF 0 "register_operand") (match_operand:V2DF 1 "register_operand") - (match_operand:V2DF 2 "nonimmediate_operand") + (match_operand:V2DF 2 "vector_operand") (match_operand:SI 3 "const_int_operand")] "TARGET_SSE2" { @@ -8576,7 +8563,7 @@ (vec_select:V2DI (vec_concat:V4DI (match_operand:V2DI 1 "register_operand" "0,v") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V2DI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 1) (const_int 3)])))] "TARGET_SSE2 && <mask_avx512vl_condition>" @@ -8626,7 +8613,7 @@ (vec_select:V2DI (vec_concat:V4DI (match_operand:V2DI 1 "register_operand" "0,v") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V2DI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 0) (const_int 2)])))] "TARGET_SSE2 && <mask_avx512vl_condition>" @@ -8644,7 +8631,7 @@ (vec_select:VI8F_128 (vec_concat:<ssedoublevecmode> (match_operand:VI8F_128 1 "register_operand" "0,x") - (match_operand:VI8F_128 2 "nonimmediate_operand" "xm,xm")) + (match_operand:VI8F_128 2 "vector_operand" "xBm,xm")) (parallel [(match_operand 3 "const_0_to_1_operand") (match_operand 4 "const_2_to_3_operand")])))] "TARGET_SSE2" @@ -9615,15 +9602,15 @@ [(set (match_operand:VI_AVX2 0 "register_operand") (minus:VI_AVX2 (match_dup 2) - (match_operand:VI_AVX2 1 "nonimmediate_operand")))] + (match_operand:VI_AVX2 1 "vector_operand")))] "TARGET_SSE2" "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));") (define_expand "<plusminus_insn><mode>3" [(set (match_operand:VI_AVX2 0 "register_operand") (plusminus:VI_AVX2 - (match_operand:VI_AVX2 1 "nonimmediate_operand") - (match_operand:VI_AVX2 2 "nonimmediate_operand")))] + (match_operand:VI_AVX2 1 "vector_operand") + (match_operand:VI_AVX2 2 "vector_operand")))] "TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") @@ -9652,8 +9639,8 @@ (define_insn "*<plusminus_insn><mode>3" [(set (match_operand:VI_AVX2 0 "register_operand" "=x,v") (plusminus:VI_AVX2 - (match_operand:VI_AVX2 1 "nonimmediate_operand" "<comm>0,v") - (match_operand:VI_AVX2 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VI_AVX2 1 "vector_operand" "<comm>0,v") + (match_operand:VI_AVX2 2 "vector_operand" "xBm,vm")))] "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" "@ @@ -9697,16 +9684,16 @@ (define_expand "<sse2_avx2>_<plusminus_insn><mode>3<mask_name>" [(set (match_operand:VI12_AVX2 0 "register_operand") (sat_plusminus:VI12_AVX2 - (match_operand:VI12_AVX2 1 "nonimmediate_operand") - (match_operand:VI12_AVX2 2 "nonimmediate_operand")))] + (match_operand:VI12_AVX2 1 "vector_operand") + (match_operand:VI12_AVX2 2 "vector_operand")))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") (define_insn "*<sse2_avx2>_<plusminus_insn><mode>3<mask_name>" [(set (match_operand:VI12_AVX2 0 "register_operand" "=x,v") (sat_plusminus:VI12_AVX2 - (match_operand:VI12_AVX2 1 "nonimmediate_operand" "<comm>0,v") - (match_operand:VI12_AVX2 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VI12_AVX2 1 "vector_operand" "<comm>0,v") + (match_operand:VI12_AVX2 2 "vector_operand" "xBm,vm")))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition> && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" "@ @@ -9730,15 +9717,15 @@ (define_expand "mul<mode>3<mask_name>" [(set (match_operand:VI2_AVX2 0 "register_operand") - (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand") - (match_operand:VI2_AVX2 2 "nonimmediate_operand")))] + (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "vector_operand") + (match_operand:VI2_AVX2 2 "vector_operand")))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);") (define_insn "*mul<mode>3<mask_name>" [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v") - (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,v") - (match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,vm")))] + (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "vector_operand" "%0,v") + (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))] "TARGET_SSE2 && ix86_binary_operator_ok (MULT, <MODE>mode, operands) && <mask_mode512bit_condition> && <mask_avx512bw_condition>" @@ -9757,9 +9744,9 @@ (lshiftrt:<ssedoublemode> (mult:<ssedoublemode> (any_extend:<ssedoublemode> - (match_operand:VI2_AVX2 1 "nonimmediate_operand")) + (match_operand:VI2_AVX2 1 "vector_operand")) (any_extend:<ssedoublemode> - (match_operand:VI2_AVX2 2 "nonimmediate_operand"))) + (match_operand:VI2_AVX2 2 "vector_operand"))) (const_int 16))))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" @@ -9771,9 +9758,9 @@ (lshiftrt:<ssedoublemode> (mult:<ssedoublemode> (any_extend:<ssedoublemode> - (match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,v")) + (match_operand:VI2_AVX2 1 "vector_operand" "%0,v")) (any_extend:<ssedoublemode> - (match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,vm"))) + (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm"))) (const_int 16))))] "TARGET_SSE2 && ix86_binary_operator_ok (MULT, <MODE>mode, operands) @@ -9873,11 +9860,11 @@ (mult:V2DI (zero_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:V4SI 1 "vector_operand") (parallel [(const_int 0) (const_int 2)]))) (zero_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "nonimmediate_operand") + (match_operand:V4SI 2 "vector_operand") (parallel [(const_int 0) (const_int 2)])))))] "TARGET_SSE2 && <mask_avx512vl_condition>" "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);") @@ -9887,11 +9874,11 @@ (mult:V2DI (zero_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "%0,v") + (match_operand:V4SI 1 "vector_operand" "%0,v") (parallel [(const_int 0) (const_int 2)]))) (zero_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "nonimmediate_operand" "xm,vm") + (match_operand:V4SI 2 "vector_operand" "xBm,vm") (parallel [(const_int 0) (const_int 2)])))))] "TARGET_SSE2 && <mask_avx512vl_condition> && ix86_binary_operator_ok (MULT, V4SImode, operands)" @@ -9991,11 +9978,11 @@ (mult:V2DI (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:V4SI 1 "vector_operand") (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "nonimmediate_operand") + (match_operand:V4SI 2 "vector_operand") (parallel [(const_int 0) (const_int 2)])))))] "TARGET_SSE4_1 && <mask_avx512vl_condition>" "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);") @@ -10005,11 +9992,11 @@ (mult:V2DI (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "%0,0,v") + (match_operand:V4SI 1 "vector_operand" "%0,0,v") (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "nonimmediate_operand" "Yrm,*xm,vm") + (match_operand:V4SI 2 "vector_operand" "YrBm,*xBm,vm") (parallel [(const_int 0) (const_int 2)])))))] "TARGET_SSE4_1 && <mask_avx512vl_condition> && ix86_binary_operator_ok (MULT, V4SImode, operands)" @@ -10113,12 +10100,12 @@ (mult:V4SI (sign_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 1 "nonimmediate_operand") + (match_operand:V8HI 1 "vector_operand") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (sign_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 2 "nonimmediate_operand") + (match_operand:V8HI 2 "vector_operand") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))) (mult:V4SI @@ -10139,12 +10126,12 @@ (mult:V4SI (sign_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 1 "nonimmediate_operand" "%0,x") + (match_operand:V8HI 1 "vector_operand" "%0,x") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (sign_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm") + (match_operand:V8HI 2 "vector_operand" "xBm,xm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))) (mult:V4SI @@ -10187,9 +10174,9 @@ { if (TARGET_SSE4_1) { - if (!nonimmediate_operand (operands[1], <MODE>mode)) + if (!vector_operand (operands[1], <MODE>mode)) operands[1] = force_reg (<MODE>mode, operands[1]); - if (!nonimmediate_operand (operands[2], <MODE>mode)) + if (!vector_operand (operands[2], <MODE>mode)) operands[2] = force_reg (<MODE>mode, operands[2]); ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands); } @@ -10203,8 +10190,8 @@ (define_insn "*<sse4_1_avx2>_mul<mode>3<mask_name>" [(set (match_operand:VI4_AVX512F 0 "register_operand" "=Yr,*x,v") (mult:VI4_AVX512F - (match_operand:VI4_AVX512F 1 "nonimmediate_operand" "%0,0,v") - (match_operand:VI4_AVX512F 2 "nonimmediate_operand" "Yrm,*xm,vm")))] + (match_operand:VI4_AVX512F 1 "vector_operand" "%0,0,v") + (match_operand:VI4_AVX512F 2 "vector_operand" "YrBm,*xBm,vm")))] "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, <MODE>mode, operands) && <mask_mode512bit_condition>" "@ pmulld\t{%2, %0|%0, %2} @@ -10256,8 +10243,8 @@ ;; named patterns, but signed V4SI needs special help for plain SSE2. (define_expand "vec_widen_smult_even_v4si" [(match_operand:V2DI 0 "register_operand") - (match_operand:V4SI 1 "nonimmediate_operand") - (match_operand:V4SI 2 "nonimmediate_operand")] + (match_operand:V4SI 1 "vector_operand") + (match_operand:V4SI 2 "vector_operand")] "TARGET_SSE2" { ix86_expand_mul_widen_evenodd (operands[0], operands[1], operands[2], @@ -10313,8 +10300,8 @@ (define_expand "usadv16qi" [(match_operand:V4SI 0 "register_operand") (match_operand:V16QI 1 "register_operand") - (match_operand:V16QI 2 "nonimmediate_operand") - (match_operand:V4SI 3 "nonimmediate_operand")] + (match_operand:V16QI 2 "vector_operand") + (match_operand:V4SI 3 "vector_operand")] "TARGET_SSE2" { rtx t1 = gen_reg_rtx (V2DImode); @@ -10654,8 +10641,8 @@ (define_expand "<code><mode>3" [(set (match_operand:VI124_128 0 "register_operand") (smaxmin:VI124_128 - (match_operand:VI124_128 1 "nonimmediate_operand") - (match_operand:VI124_128 2 "nonimmediate_operand")))] + (match_operand:VI124_128 1 "vector_operand") + (match_operand:VI124_128 2 "vector_operand")))] "TARGET_SSE2" { if (TARGET_SSE4_1 || <MODE>mode == V8HImode) @@ -10693,8 +10680,8 @@ (define_insn "*sse4_1_<code><mode>3<mask_name>" [(set (match_operand:VI14_128 0 "register_operand" "=Yr,*x,v") (smaxmin:VI14_128 - (match_operand:VI14_128 1 "nonimmediate_operand" "%0,0,v") - (match_operand:VI14_128 2 "nonimmediate_operand" "Yrm,*xm,vm")))] + (match_operand:VI14_128 1 "vector_operand" "%0,0,v") + (match_operand:VI14_128 2 "vector_operand" "YrBm,*xBm,vm")))] "TARGET_SSE4_1 && <mask_mode512bit_condition> && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" @@ -10711,8 +10698,8 @@ (define_insn "*<code>v8hi3" [(set (match_operand:V8HI 0 "register_operand" "=x,x") (smaxmin:V8HI - (match_operand:V8HI 1 "nonimmediate_operand" "%0,x") - (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")))] + (match_operand:V8HI 1 "vector_operand" "%0,x") + (match_operand:V8HI 2 "vector_operand" "xBm,xm")))] "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)" "@ p<maxmin_int>w\t{%2, %0|%0, %2} @@ -10727,8 +10714,8 @@ (define_expand "<code><mode>3" [(set (match_operand:VI124_128 0 "register_operand") (umaxmin:VI124_128 - (match_operand:VI124_128 1 "nonimmediate_operand") - (match_operand:VI124_128 2 "nonimmediate_operand")))] + (match_operand:VI124_128 1 "vector_operand") + (match_operand:VI124_128 2 "vector_operand")))] "TARGET_SSE2" { if (TARGET_SSE4_1 || <MODE>mode == V16QImode) @@ -10777,8 +10764,8 @@ (define_insn "*sse4_1_<code><mode>3<mask_name>" [(set (match_operand:VI24_128 0 "register_operand" "=Yr,*x,v") (umaxmin:VI24_128 - (match_operand:VI24_128 1 "nonimmediate_operand" "%0,0,v") - (match_operand:VI24_128 2 "nonimmediate_operand" "Yrm,*xm,vm")))] + (match_operand:VI24_128 1 "vector_operand" "%0,0,v") + (match_operand:VI24_128 2 "vector_operand" "YrBm,*xBm,vm")))] "TARGET_SSE4_1 && <mask_mode512bit_condition> && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" @@ -10795,8 +10782,8 @@ (define_insn "*<code>v16qi3" [(set (match_operand:V16QI 0 "register_operand" "=x,x") (umaxmin:V16QI - (match_operand:V16QI 1 "nonimmediate_operand" "%0,x") - (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm")))] + (match_operand:V16QI 1 "vector_operand" "%0,x") + (match_operand:V16QI 2 "vector_operand" "xBm,xm")))] "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)" "@ p<maxmin_int>b\t{%2, %0|%0, %2} @@ -10881,8 +10868,8 @@ (define_insn "*sse4_1_eqv2di3" [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,x") (eq:V2DI - (match_operand:V2DI 1 "nonimmediate_operand" "%0,0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "Yrm,*xm,xm")))] + (match_operand:V2DI 1 "vector_operand" "%0,0,x") + (match_operand:V2DI 2 "vector_operand" "YrBm,*xBm,xm")))] "TARGET_SSE4_1 && ix86_binary_operator_ok (EQ, V2DImode, operands)" "@ pcmpeqq\t{%2, %0|%0, %2} @@ -10897,8 +10884,8 @@ (define_insn "*sse2_eq<mode>3" [(set (match_operand:VI124_128 0 "register_operand" "=x,x") (eq:VI124_128 - (match_operand:VI124_128 1 "nonimmediate_operand" "%0,x") - (match_operand:VI124_128 2 "nonimmediate_operand" "xm,xm")))] + (match_operand:VI124_128 1 "vector_operand" "%0,x") + (match_operand:VI124_128 2 "vector_operand" "xBm,xm")))] "TARGET_SSE2 && !TARGET_XOP && ix86_binary_operator_ok (EQ, <MODE>mode, operands)" "@ @@ -10913,16 +10900,16 @@ (define_expand "sse2_eq<mode>3" [(set (match_operand:VI124_128 0 "register_operand") (eq:VI124_128 - (match_operand:VI124_128 1 "nonimmediate_operand") - (match_operand:VI124_128 2 "nonimmediate_operand")))] + (match_operand:VI124_128 1 "vector_operand") + (match_operand:VI124_128 2 "vector_operand")))] "TARGET_SSE2 && !TARGET_XOP " "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);") (define_expand "sse4_1_eqv2di3" [(set (match_operand:V2DI 0 "register_operand") (eq:V2DI - (match_operand:V2DI 1 "nonimmediate_operand") - (match_operand:V2DI 2 "nonimmediate_operand")))] + (match_operand:V2DI 1 "vector_operand") + (match_operand:V2DI 2 "vector_operand")))] "TARGET_SSE4_1" "ix86_fixup_binary_operands_no_copy (EQ, V2DImode, operands);") @@ -10930,7 +10917,7 @@ [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,x") (gt:V2DI (match_operand:V2DI 1 "register_operand" "0,0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "Yrm,*xm,xm")))] + (match_operand:V2DI 2 "vector_operand" "YrBm,*xBm,xm")))] "TARGET_SSE4_2" "@ pcmpgtq\t{%2, %0|%0, %2} @@ -10982,7 +10969,7 @@ [(set (match_operand:VI124_128 0 "register_operand" "=x,x") (gt:VI124_128 (match_operand:VI124_128 1 "register_operand" "0,x") - (match_operand:VI124_128 2 "nonimmediate_operand" "xm,xm")))] + (match_operand:VI124_128 2 "vector_operand" "xBm,xm")))] "TARGET_SSE2 && !TARGET_XOP" "@ pcmpgt<ssemodesuffix>\t{%2, %0|%0, %2} @@ -11031,7 +11018,7 @@ [(set (match_operand:V_128 0 "register_operand") (if_then_else:V_128 (match_operator 3 "" - [(match_operand:VI124_128 4 "nonimmediate_operand") + [(match_operand:VI124_128 4 "vector_operand") (match_operand:VI124_128 5 "general_operand")]) (match_operand:V_128 1) (match_operand:V_128 2)))] @@ -11048,7 +11035,7 @@ [(set (match_operand:VI8F_128 0 "register_operand") (if_then_else:VI8F_128 (match_operator 3 "" - [(match_operand:V2DI 4 "nonimmediate_operand") + [(match_operand:V2DI 4 "vector_operand") (match_operand:V2DI 5 "general_operand")]) (match_operand:VI8F_128 1) (match_operand:VI8F_128 2)))] @@ -11097,8 +11084,8 @@ [(set (match_operand:V_128 0 "register_operand") (if_then_else:V_128 (match_operator 3 "" - [(match_operand:VI124_128 4 "nonimmediate_operand") - (match_operand:VI124_128 5 "nonimmediate_operand")]) + [(match_operand:VI124_128 4 "vector_operand") + (match_operand:VI124_128 5 "vector_operand")]) (match_operand:V_128 1 "general_operand") (match_operand:V_128 2 "general_operand")))] "TARGET_SSE2 @@ -11114,8 +11101,8 @@ [(set (match_operand:VI8F_128 0 "register_operand") (if_then_else:VI8F_128 (match_operator 3 "" - [(match_operand:V2DI 4 "nonimmediate_operand") - (match_operand:V2DI 5 "nonimmediate_operand")]) + [(match_operand:V2DI 4 "vector_operand") + (match_operand:V2DI 5 "vector_operand")]) (match_operand:VI8F_128 1 "general_operand") (match_operand:VI8F_128 2 "general_operand")))] "TARGET_SSE4_2" @@ -11177,7 +11164,7 @@ (define_expand "one_cmpl<mode>2" [(set (match_operand:VI 0 "register_operand") - (xor:VI (match_operand:VI 1 "nonimmediate_operand") + (xor:VI (match_operand:VI 1 "vector_operand") (match_dup 2)))] "TARGET_SSE" { @@ -11194,7 +11181,7 @@ [(set (match_operand:VI_AVX2 0 "register_operand") (and:VI_AVX2 (not:VI_AVX2 (match_operand:VI_AVX2 1 "register_operand")) - (match_operand:VI_AVX2 2 "nonimmediate_operand")))] + (match_operand:VI_AVX2 2 "vector_operand")))] "TARGET_SSE2") (define_expand "<sse2_avx2>_andnot<mode>3_mask" @@ -11223,7 +11210,7 @@ [(set (match_operand:VI 0 "register_operand" "=x,v") (and:VI (not:VI (match_operand:VI 1 "register_operand" "0,v")) - (match_operand:VI 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VI 2 "vector_operand" "xBm,vm")))] "TARGET_SSE" { static char buf[64]; @@ -11360,8 +11347,8 @@ (define_insn "<mask_codefor><code><mode>3<mask_name>" [(set (match_operand:VI48_AVX_AVX512F 0 "register_operand" "=x,v") (any_logic:VI48_AVX_AVX512F - (match_operand:VI48_AVX_AVX512F 1 "nonimmediate_operand" "%0,v") - (match_operand:VI48_AVX_AVX512F 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VI48_AVX_AVX512F 1 "vector_operand" "%0,v") + (match_operand:VI48_AVX_AVX512F 2 "vector_operand" "xBm,vm")))] "TARGET_SSE && <mask_mode512bit_condition> && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" { @@ -11456,8 +11443,8 @@ (define_insn "*<code><mode>3" [(set (match_operand:VI12_AVX_AVX512F 0 "register_operand" "=x,v") (any_logic: VI12_AVX_AVX512F - (match_operand:VI12_AVX_AVX512F 1 "nonimmediate_operand" "%0,v") - (match_operand:VI12_AVX_AVX512F 2 "nonimmediate_operand" "xm,vm")))] + (match_operand:VI12_AVX_AVX512F 1 "vector_operand" "%0,v") + (match_operand:VI12_AVX_AVX512F 2 "vector_operand" "xBm,vm")))] "TARGET_SSE && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" { static char buf[64]; @@ -11637,7 +11624,7 @@ (ss_truncate:<ssehalfvecmode> (match_operand:<sseunpackmode> 1 "register_operand" "0,v")) (ss_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,vm"))))] + (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,vm"))))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ packsswb\t{%2, %0|%0, %2} @@ -11654,7 +11641,7 @@ (ss_truncate:<ssehalfvecmode> (match_operand:<sseunpackmode> 1 "register_operand" "0,v")) (ss_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,vm"))))] + (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,vm"))))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ packssdw\t{%2, %0|%0, %2} @@ -11671,7 +11658,7 @@ (us_truncate:<ssehalfvecmode> (match_operand:<sseunpackmode> 1 "register_operand" "0,v")) (us_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "xm,vm"))))] + (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,vm"))))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ packuswb\t{%2, %0|%0, %2} @@ -11759,7 +11746,7 @@ (vec_select:V16QI (vec_concat:V32QI (match_operand:V16QI 1 "register_operand" "0,v") - (match_operand:V16QI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V16QI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 8) (const_int 24) (const_int 9) (const_int 25) (const_int 10) (const_int 26) @@ -11855,7 +11842,7 @@ (vec_select:V16QI (vec_concat:V32QI (match_operand:V16QI 1 "register_operand" "0,v") - (match_operand:V16QI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V16QI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 0) (const_int 16) (const_int 1) (const_int 17) (const_int 2) (const_int 18) @@ -11927,7 +11914,7 @@ (vec_select:V8HI (vec_concat:V16HI (match_operand:V8HI 1 "register_operand" "0,v") - (match_operand:V8HI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V8HI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13) (const_int 6) (const_int 14) @@ -11995,7 +11982,7 @@ (vec_select:V8HI (vec_concat:V16HI (match_operand:V8HI 1 "register_operand" "0,v") - (match_operand:V8HI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V8HI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9) (const_int 2) (const_int 10) @@ -12052,7 +12039,7 @@ (vec_select:V4SI (vec_concat:V8SI (match_operand:V4SI 1 "register_operand" "0,v") - (match_operand:V4SI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V4SI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "TARGET_SSE2 && <mask_avx512vl_condition>" @@ -12106,7 +12093,7 @@ (vec_select:V4SI (vec_concat:V8SI (match_operand:V4SI 1 "register_operand" "0,v") - (match_operand:V4SI 2 "nonimmediate_operand" "xm,vm")) + (match_operand:V4SI 2 "vector_operand" "xBm,vm")) (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "TARGET_SSE2 && <mask_avx512vl_condition>" @@ -12773,7 +12760,7 @@ (define_expand "sse2_pshufd" [(match_operand:V4SI 0 "register_operand") - (match_operand:V4SI 1 "nonimmediate_operand") + (match_operand:V4SI 1 "vector_operand") (match_operand:SI 2 "const_int_operand")] "TARGET_SSE2" { @@ -12789,7 +12776,7 @@ (define_insn "sse2_pshufd_1<mask_name>" [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_select:V4SI - (match_operand:V4SI 1 "nonimmediate_operand" "vm") + (match_operand:V4SI 1 "vector_operand" "vBm") (parallel [(match_operand 2 "const_0_to_3_operand") (match_operand 3 "const_0_to_3_operand") (match_operand 4 "const_0_to_3_operand") @@ -12925,7 +12912,7 @@ (define_expand "sse2_pshuflw" [(match_operand:V8HI 0 "register_operand") - (match_operand:V8HI 1 "nonimmediate_operand") + (match_operand:V8HI 1 "vector_operand") (match_operand:SI 2 "const_int_operand")] "TARGET_SSE2" { @@ -12941,7 +12928,7 @@ (define_insn "sse2_pshuflw_1<mask_name>" [(set (match_operand:V8HI 0 "register_operand" "=v") (vec_select:V8HI - (match_operand:V8HI 1 "nonimmediate_operand" "vm") + (match_operand:V8HI 1 "vector_operand" "vBm") (parallel [(match_operand 2 "const_0_to_3_operand") (match_operand 3 "const_0_to_3_operand") (match_operand 4 "const_0_to_3_operand") @@ -13082,7 +13069,7 @@ (define_expand "sse2_pshufhw" [(match_operand:V8HI 0 "register_operand") - (match_operand:V8HI 1 "nonimmediate_operand") + (match_operand:V8HI 1 "vector_operand") (match_operand:SI 2 "const_int_operand")] "TARGET_SSE2" { @@ -13098,7 +13085,7 @@ (define_insn "sse2_pshufhw_1<mask_name>" [(set (match_operand:V8HI 0 "register_operand" "=v") (vec_select:V8HI - (match_operand:V8HI 1 "nonimmediate_operand" "vm") + (match_operand:V8HI 1 "vector_operand" "vBm") (parallel [(const_int 0) (const_int 1) (const_int 2) @@ -13576,9 +13563,9 @@ (plus:<ssedoublemode> (plus:<ssedoublemode> (zero_extend:<ssedoublemode> - (match_operand:VI12_AVX2 1 "nonimmediate_operand")) + (match_operand:VI12_AVX2 1 "vector_operand")) (zero_extend:<ssedoublemode> - (match_operand:VI12_AVX2 2 "nonimmediate_operand"))) + (match_operand:VI12_AVX2 2 "vector_operand"))) (match_dup <mask_expand_op3>)) (const_int 1))))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" @@ -13603,9 +13590,9 @@ (plus:<ssedoublemode> (plus:<ssedoublemode> (zero_extend:<ssedoublemode> - (match_operand:VI12_AVX2 1 "nonimmediate_operand" "%0,v")) + (match_operand:VI12_AVX2 1 "vector_operand" "%0,v")) (zero_extend:<ssedoublemode> - (match_operand:VI12_AVX2 2 "nonimmediate_operand" "xm,vm"))) + (match_operand:VI12_AVX2 2 "vector_operand" "xBm,vm"))) (match_operand:VI12_AVX2 <mask_expand_op3> "const1_operand")) (const_int 1))))] "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition> @@ -13625,7 +13612,7 @@ [(set (match_operand:VI8_AVX2_AVX512BW 0 "register_operand" "=x,v") (unspec:VI8_AVX2_AVX512BW [(match_operand:<ssebytemode> 1 "register_operand" "0,v") - (match_operand:<ssebytemode> 2 "nonimmediate_operand" "xm,vm")] + (match_operand:<ssebytemode> 2 "vector_operand" "xBm,vm")] UNSPEC_PSADBW))] "TARGET_SSE2" "@ @@ -13891,7 +13878,7 @@ (vec_concat:V2HI (ssse3_plusminus:HI (vec_select:HI - (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm") + (match_operand:V8HI 2 "vector_operand" "xBm,xm") (parallel [(const_int 0)])) (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))) (ssse3_plusminus:HI @@ -14004,7 +13991,7 @@ (vec_concat:V2SI (plusminus:SI (vec_select:SI - (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm") + (match_operand:V4SI 2 "vector_operand" "xBm,xm") (parallel [(const_int 0)])) (vec_select:SI (match_dup 2) (parallel [(const_int 1)]))) (plusminus:SI @@ -14159,7 +14146,7 @@ (const_int 12) (const_int 14)]))) (sign_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm") + (match_operand:V16QI 2 "vector_operand" "xBm,xm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6) (const_int 8) (const_int 10) @@ -14274,9 +14261,9 @@ (lshiftrt:<ssedoublemode> (mult:<ssedoublemode> (sign_extend:<ssedoublemode> - (match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,v")) + (match_operand:VI2_AVX2 1 "vector_operand" "%0,v")) (sign_extend:<ssedoublemode> - (match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,vm"))) + (match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm"))) (const_int 14)) (match_operand:VI2_AVX2 3 "const1_operand")) (const_int 1))))] @@ -14317,7 +14304,7 @@ [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,v") (unspec:VI1_AVX512 [(match_operand:VI1_AVX512 1 "register_operand" "0,v") - (match_operand:VI1_AVX512 2 "nonimmediate_operand" "xm,vm")] + (match_operand:VI1_AVX512 2 "vector_operand" "xBm,vm")] UNSPEC_PSHUFB))] "TARGET_SSSE3 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ @@ -14347,7 +14334,7 @@ [(set (match_operand:VI124_AVX2 0 "register_operand" "=x,x") (unspec:VI124_AVX2 [(match_operand:VI124_AVX2 1 "register_operand" "0,x") - (match_operand:VI124_AVX2 2 "nonimmediate_operand" "xm,xm")] + (match_operand:VI124_AVX2 2 "vector_operand" "xBm,xm")] UNSPEC_PSIGN))] "TARGET_SSSE3" "@ @@ -14399,7 +14386,7 @@ [(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,v") (unspec:SSESCALARMODE [(match_operand:SSESCALARMODE 1 "register_operand" "0,v") - (match_operand:SSESCALARMODE 2 "nonimmediate_operand" "xm,vm") + (match_operand:SSESCALARMODE 2 "vector_operand" "xBm,vm") (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")] UNSPEC_PALIGNR))] "TARGET_SSSE3" @@ -14454,7 +14441,7 @@ (define_insn "*abs<mode>2" [(set (match_operand:VI1248_AVX512VL_AVX512BW 0 "register_operand" "=v") (abs:VI1248_AVX512VL_AVX512BW - (match_operand:VI1248_AVX512VL_AVX512BW 1 "nonimmediate_operand" "vm")))] + (match_operand:VI1248_AVX512VL_AVX512BW 1 "vector_operand" "vBm")))] "TARGET_SSSE3" "%vpabs<ssemodesuffix>\t{%1, %0|%0, %1}" [(set_attr "type" "sselog1") @@ -14492,7 +14479,7 @@ (define_expand "abs<mode>2" [(set (match_operand:VI1248_AVX512VL_AVX512BW 0 "register_operand") (abs:VI1248_AVX512VL_AVX512BW - (match_operand:VI1248_AVX512VL_AVX512BW 1 "nonimmediate_operand")))] + (match_operand:VI1248_AVX512VL_AVX512BW 1 "vector_operand")))] "TARGET_SSE2" { if (!TARGET_SSSE3) @@ -14606,7 +14593,7 @@ (define_insn "<sse4_1>_blend<ssemodesuffix><avxsizesuffix>" [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x") (vec_merge:VF_128_256 - (match_operand:VF_128_256 2 "nonimmediate_operand" "Yrm,*xm,xm") + (match_operand:VF_128_256 2 "vector_operand" "YrBm,*xBm,xm") (match_operand:VF_128_256 1 "register_operand" "0,0,x") (match_operand:SI 3 "const_0_to_<blendbits>_operand")))] "TARGET_SSE4_1" @@ -14626,7 +14613,7 @@ [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x") (unspec:VF_128_256 [(match_operand:VF_128_256 1 "register_operand" "0,0,x") - (match_operand:VF_128_256 2 "nonimmediate_operand" "Yrm,*xm,xm") + (match_operand:VF_128_256 2 "vector_operand" "YrBm,*xBm,xm") (match_operand:VF_128_256 3 "register_operand" "Yz,Yz,x")] UNSPEC_BLENDV))] "TARGET_SSE4_1" @@ -14646,8 +14633,8 @@ (define_insn "<sse4_1>_dp<ssemodesuffix><avxsizesuffix>" [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x") (unspec:VF_128_256 - [(match_operand:VF_128_256 1 "nonimmediate_operand" "%0,0,x") - (match_operand:VF_128_256 2 "nonimmediate_operand" "Yrm,*xm,xm") + [(match_operand:VF_128_256 1 "vector_operand" "%0,0,x") + (match_operand:VF_128_256 2 "vector_operand" "YrBm,*xBm,xm") (match_operand:SI 3 "const_0_to_255_operand" "n,n,n")] UNSPEC_DP))] "TARGET_SSE4_1" @@ -14684,7 +14671,7 @@ [(set (match_operand:VI1_AVX2 0 "register_operand" "=Yr,*x,x") (unspec:VI1_AVX2 [(match_operand:VI1_AVX2 1 "register_operand" "0,0,x") - (match_operand:VI1_AVX2 2 "nonimmediate_operand" "Yrm,*xm,xm") + (match_operand:VI1_AVX2 2 "vector_operand" "YrBm,*xBm,xm") (match_operand:SI 3 "const_0_to_255_operand" "n,n,n")] UNSPEC_MPSADBW))] "TARGET_SSE4_1" @@ -14707,7 +14694,7 @@ (us_truncate:<ssehalfvecmode> (match_operand:<sseunpackmode> 1 "register_operand" "0,0,v")) (us_truncate:<ssehalfvecmode> - (match_operand:<sseunpackmode> 2 "nonimmediate_operand" "Yrm,*xm,vm"))))] + (match_operand:<sseunpackmode> 2 "vector_operand" "YrBm,*xBm,vm"))))] "TARGET_SSE4_1 && <mask_mode512bit_condition> && <mask_avx512bw_condition>" "@ packusdw\t{%2, %0|%0, %2} @@ -14723,7 +14710,7 @@ [(set (match_operand:VI1_AVX2 0 "register_operand" "=Yr,*x,x") (unspec:VI1_AVX2 [(match_operand:VI1_AVX2 1 "register_operand" "0,0,x") - (match_operand:VI1_AVX2 2 "nonimmediate_operand" "Yrm,*xm,xm") + (match_operand:VI1_AVX2 2 "vector_operand" "YrBm,*xBm,xm") (match_operand:VI1_AVX2 3 "register_operand" "Yz,Yz,x")] UNSPEC_BLENDV))] "TARGET_SSE4_1" @@ -14742,7 +14729,7 @@ (define_insn "sse4_1_pblendw" [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,x") (vec_merge:V8HI - (match_operand:V8HI 2 "nonimmediate_operand" "Yrm,*xm,xm") + (match_operand:V8HI 2 "vector_operand" "YrBm,*xBm,xm") (match_operand:V8HI 1 "register_operand" "0,0,x") (match_operand:SI 3 "const_0_to_255_operand" "n,n,n")))] "TARGET_SSE4_1" @@ -14803,7 +14790,7 @@ (define_insn "sse4_1_phminposuw" [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x") - (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "Yrm,*xm")] + (unspec:V8HI [(match_operand:V8HI 1 "vector_operand" "YrBm,*xBm")] UNSPEC_PHMINPOSUW))] "TARGET_SSE4_1" "%vphminposuw\t{%1, %0|%0, %1}" @@ -15063,7 +15050,7 @@ (define_insn "<sse4_1>_ptest<mode>" [(set (reg:CC FLAGS_REG) (unspec:CC [(match_operand:V_AVX 0 "register_operand" "Yr, *x, x") - (match_operand:V_AVX 1 "nonimmediate_operand" "Yrm, *xm, xm")] + (match_operand:V_AVX 1 "vector_operand" "YrBm, *xBm, xm")] UNSPEC_PTEST))] "TARGET_SSE4_1" "%vptest\t{%1, %0|%0, %1}" @@ -15081,7 +15068,7 @@ (define_insn "<sse4_1>_round<ssemodesuffix><avxsizesuffix>" [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x") (unspec:VF_128_256 - [(match_operand:VF_128_256 1 "nonimmediate_operand" "Yrm,*xm") + [(match_operand:VF_128_256 1 "vector_operand" "YrBm,*xBm") (match_operand:SI 2 "const_0_to_15_operand" "n,n")] UNSPEC_ROUND))] "TARGET_ROUND" @@ -15099,7 +15086,7 @@ (define_expand "<sse4_1>_round<ssemodesuffix>_sfix<avxsizesuffix>" [(match_operand:<sseintvecmode> 0 "register_operand") - (match_operand:VF1_128_256 1 "nonimmediate_operand") + (match_operand:VF1_128_256 1 "vector_operand") (match_operand:SI 2 "const_0_to_15_operand")] "TARGET_ROUND" { @@ -15125,8 +15112,8 @@ (define_expand "<sse4_1>_round<ssemodesuffix>_vec_pack_sfix<avxsizesuffix>" [(match_operand:<ssepackfltmode> 0 "register_operand") - (match_operand:VF2 1 "nonimmediate_operand") - (match_operand:VF2 2 "nonimmediate_operand") + (match_operand:VF2 1 "vector_operand") + (match_operand:VF2 2 "vector_operand") (match_operand:SI 3 "const_0_to_15_operand")] "TARGET_ROUND" { @@ -15667,7 +15654,7 @@ (define_expand "avx512pf_gatherpf<mode>sf" [(unspec - [(match_operand:<avx512fmaskmode> 0 "register_or_constm1_operand") + [(match_operand:<avx512fmaskmode> 0 "register_operand") (mem:<GATHER_SCATTER_SF_MEM_MODE> (match_par_dup 5 [(match_operand 2 "vsib_address_operand") @@ -15709,37 +15696,10 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "*avx512pf_gatherpf<mode>sf" - [(unspec - [(const_int -1) - (match_operator:<GATHER_SCATTER_SF_MEM_MODE> 4 "vsib_mem_operator" - [(unspec:P - [(match_operand:P 1 "vsib_address_operand" "Tv") - (match_operand:VI48_512 0 "register_operand" "v") - (match_operand:SI 2 "const1248_operand" "n")] - UNSPEC_VSIBADDR)]) - (match_operand:SI 3 "const_2_to_3_operand" "n")] - UNSPEC_GATHER_PREFETCH)] - "TARGET_AVX512PF" -{ - switch (INTVAL (operands[3])) - { - case 3: - return "vgatherpf0<ssemodesuffix>ps\t{%4|%4}"; - case 2: - return "vgatherpf1<ssemodesuffix>ps\t{%4|%4}"; - default: - gcc_unreachable (); - } -} - [(set_attr "type" "sse") - (set_attr "prefix" "evex") - (set_attr "mode" "XI")]) - ;; Packed double variants (define_expand "avx512pf_gatherpf<mode>df" [(unspec - [(match_operand:<avx512fmaskmode> 0 "register_or_constm1_operand") + [(match_operand:<avx512fmaskmode> 0 "register_operand") (mem:V8DF (match_par_dup 5 [(match_operand 2 "vsib_address_operand") @@ -15781,37 +15741,10 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "*avx512pf_gatherpf<mode>df" - [(unspec - [(const_int -1) - (match_operator:V8DF 4 "vsib_mem_operator" - [(unspec:P - [(match_operand:P 1 "vsib_address_operand" "Tv") - (match_operand:VI4_256_8_512 0 "register_operand" "v") - (match_operand:SI 2 "const1248_operand" "n")] - UNSPEC_VSIBADDR)]) - (match_operand:SI 3 "const_2_to_3_operand" "n")] - UNSPEC_GATHER_PREFETCH)] - "TARGET_AVX512PF" -{ - switch (INTVAL (operands[3])) - { - case 3: - return "vgatherpf0<ssemodesuffix>pd\t{%4|%4}"; - case 2: - return "vgatherpf1<ssemodesuffix>pd\t{%4|%4}"; - default: - gcc_unreachable (); - } -} - [(set_attr "type" "sse") - (set_attr "prefix" "evex") - (set_attr "mode" "XI")]) - ;; Packed float variants (define_expand "avx512pf_scatterpf<mode>sf" [(unspec - [(match_operand:<avx512fmaskmode> 0 "register_or_constm1_operand") + [(match_operand:<avx512fmaskmode> 0 "register_operand") (mem:<GATHER_SCATTER_SF_MEM_MODE> (match_par_dup 5 [(match_operand 2 "vsib_address_operand") @@ -15855,39 +15788,10 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "*avx512pf_scatterpf<mode>sf" - [(unspec - [(const_int -1) - (match_operator:<GATHER_SCATTER_SF_MEM_MODE> 4 "vsib_mem_operator" - [(unspec:P - [(match_operand:P 1 "vsib_address_operand" "Tv") - (match_operand:VI48_512 0 "register_operand" "v") - (match_operand:SI 2 "const1248_operand" "n")] - UNSPEC_VSIBADDR)]) - (match_operand:SI 3 "const2367_operand" "n")] - UNSPEC_SCATTER_PREFETCH)] - "TARGET_AVX512PF" -{ - switch (INTVAL (operands[3])) - { - case 3: - case 7: - return "vscatterpf0<ssemodesuffix>ps\t{%4|%4}"; - case 2: - case 6: - return "vscatterpf1<ssemodesuffix>ps\t{%4|%4}"; - default: - gcc_unreachable (); - } -} - [(set_attr "type" "sse") - (set_attr "prefix" "evex") - (set_attr "mode" "XI")]) - ;; Packed double variants (define_expand "avx512pf_scatterpf<mode>df" [(unspec - [(match_operand:<avx512fmaskmode> 0 "register_or_constm1_operand") + [(match_operand:<avx512fmaskmode> 0 "register_operand") (mem:V8DF (match_par_dup 5 [(match_operand 2 "vsib_address_operand") @@ -15931,35 +15835,6 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "*avx512pf_scatterpf<mode>df" - [(unspec - [(const_int -1) - (match_operator:V8DF 4 "vsib_mem_operator" - [(unspec:P - [(match_operand:P 1 "vsib_address_operand" "Tv") - (match_operand:VI4_256_8_512 0 "register_operand" "v") - (match_operand:SI 2 "const1248_operand" "n")] - UNSPEC_VSIBADDR)]) - (match_operand:SI 3 "const2367_operand" "n")] - UNSPEC_SCATTER_PREFETCH)] - "TARGET_AVX512PF" -{ - switch (INTVAL (operands[3])) - { - case 3: - case 7: - return "vscatterpf0<ssemodesuffix>pd\t{%4|%4}"; - case 2: - case 6: - return "vscatterpf1<ssemodesuffix>pd\t{%4|%4}"; - default: - gcc_unreachable (); - } -} - [(set_attr "type" "sse") - (set_attr "prefix" "evex") - (set_attr "mode" "XI")]) - (define_insn "avx512er_exp2<mode><mask_name><round_saeonly_name>" [(set (match_operand:VF_512 0 "register_operand" "=v") (unspec:VF_512 @@ -16926,7 +16801,7 @@ (define_insn "aesenc" [(set (match_operand:V2DI 0 "register_operand" "=x,x") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")] + (match_operand:V2DI 2 "vector_operand" "xBm,xm")] UNSPEC_AESENC))] "TARGET_AES" "@ @@ -16942,7 +16817,7 @@ (define_insn "aesenclast" [(set (match_operand:V2DI 0 "register_operand" "=x,x") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")] + (match_operand:V2DI 2 "vector_operand" "xBm,xm")] UNSPEC_AESENCLAST))] "TARGET_AES" "@ @@ -16958,7 +16833,7 @@ (define_insn "aesdec" [(set (match_operand:V2DI 0 "register_operand" "=x,x") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")] + (match_operand:V2DI 2 "vector_operand" "xBm,xm")] UNSPEC_AESDEC))] "TARGET_AES" "@ @@ -16974,7 +16849,7 @@ (define_insn "aesdeclast" [(set (match_operand:V2DI 0 "register_operand" "=x,x") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")] + (match_operand:V2DI 2 "vector_operand" "xBm,xm")] UNSPEC_AESDECLAST))] "TARGET_AES" "@ @@ -16989,7 +16864,7 @@ (define_insn "aesimc" [(set (match_operand:V2DI 0 "register_operand" "=x") - (unspec:V2DI [(match_operand:V2DI 1 "nonimmediate_operand" "xm")] + (unspec:V2DI [(match_operand:V2DI 1 "vector_operand" "xBm")] UNSPEC_AESIMC))] "TARGET_AES" "%vaesimc\t{%1, %0|%0, %1}" @@ -17000,7 +16875,7 @@ (define_insn "aeskeygenassist" [(set (match_operand:V2DI 0 "register_operand" "=x") - (unspec:V2DI [(match_operand:V2DI 1 "nonimmediate_operand" "xm") + (unspec:V2DI [(match_operand:V2DI 1 "vector_operand" "xBm") (match_operand:SI 2 "const_0_to_255_operand" "n")] UNSPEC_AESKEYGENASSIST))] "TARGET_AES" @@ -17014,7 +16889,7 @@ (define_insn "pclmulqdq" [(set (match_operand:V2DI 0 "register_operand" "=x,x") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") - (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm") + (match_operand:V2DI 2 "vector_operand" "xBm,xm") (match_operand:SI 3 "const_0_to_255_operand" "n,n")] UNSPEC_PCLMUL))] "TARGET_PCLMUL" @@ -19152,7 +19027,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "nonimmediate_operand" "xm")] + (match_operand:V4SI 2 "vector_operand" "xBm")] UNSPEC_SHA1MSG1))] "TARGET_SHA" "sha1msg1\t{%2, %0|%0, %2}" @@ -19163,7 +19038,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "nonimmediate_operand" "xm")] + (match_operand:V4SI 2 "vector_operand" "xBm")] UNSPEC_SHA1MSG2))] "TARGET_SHA" "sha1msg2\t{%2, %0|%0, %2}" @@ -19174,7 +19049,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "nonimmediate_operand" "xm")] + (match_operand:V4SI 2 "vector_operand" "xBm")] UNSPEC_SHA1NEXTE))] "TARGET_SHA" "sha1nexte\t{%2, %0|%0, %2}" @@ -19185,7 +19060,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "nonimmediate_operand" "xm") + (match_operand:V4SI 2 "vector_operand" "xBm") (match_operand:SI 3 "const_0_to_3_operand" "n")] UNSPEC_SHA1RNDS4))] "TARGET_SHA" @@ -19198,7 +19073,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "nonimmediate_operand" "xm")] + (match_operand:V4SI 2 "vector_operand" "xBm")] UNSPEC_SHA256MSG1))] "TARGET_SHA" "sha256msg1\t{%2, %0|%0, %2}" @@ -19209,7 +19084,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "nonimmediate_operand" "xm")] + (match_operand:V4SI 2 "vector_operand" "xBm")] UNSPEC_SHA256MSG2))] "TARGET_SHA" "sha256msg2\t{%2, %0|%0, %2}" @@ -19220,7 +19095,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=x") (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") - (match_operand:V4SI 2 "nonimmediate_operand" "xm") + (match_operand:V4SI 2 "vector_operand" "xBm") (match_operand:V4SI 3 "register_operand" "Yz")] UNSPEC_SHA256RNDS2))] "TARGET_SHA" diff --git a/gcc/config/i386/ssemath.h b/gcc/config/i386/ssemath.h index 802e6017ff2..eeebeef5d7b 100644 --- a/gcc/config/i386/ssemath.h +++ b/gcc/config/i386/ssemath.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2010-2015 Free Software Foundation, Inc. +/* Copyright (C) 2010-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/stringop.def b/gcc/config/i386/stringop.def index 0d6a5fab672..b4abbd7ef52 100644 --- a/gcc/config/i386/stringop.def +++ b/gcc/config/i386/stringop.def @@ -1,5 +1,5 @@ /* Definitions for stringop strategy for IA-32. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/stringop.opt b/gcc/config/i386/stringop.opt index 6b6d1e0ff24..ad64f371436 100644 --- a/gcc/config/i386/stringop.opt +++ b/gcc/config/i386/stringop.opt @@ -1,5 +1,5 @@ /* Definitions for stringop option handling for IA-32. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index 1c5a541245f..e2f67c4a00c 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -1,5 +1,5 @@ ;; GCC machine description for AVX512F instructions -;; Copyright (C) 2013-2015 Free Software Foundation, Inc. +;; Copyright (C) 2013-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -123,7 +123,8 @@ (define_subst_attr "round_constraint" "round" "vm" "v") (define_subst_attr "round_constraint2" "round" "m" "v") (define_subst_attr "round_constraint3" "round" "rm" "r") -(define_subst_attr "round_nimm_predicate" "round" "nonimmediate_operand" "register_operand") +(define_subst_attr "round_nimm_predicate" "round" "vector_operand" "register_operand") +(define_subst_attr "round_nimm_scalar_predicate" "round" "nonimmediate_operand" "register_operand") (define_subst_attr "round_prefix" "round" "vex" "evex") (define_subst_attr "round_mode512bit_condition" "round" "1" "(<MODE>mode == V16SFmode || <MODE>mode == V8DFmode @@ -162,7 +163,8 @@ (define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "<round_saeonly_sd_mask_operand5>") (define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v") (define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v") -(define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "nonimmediate_operand" "register_operand") +(define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "vector_operand" "register_operand") +(define_subst_attr "round_saeonly_nimm_scalar_predicate" "round_saeonly" "nonimmediate_operand" "register_operand") (define_subst_attr "round_saeonly_mode512bit_condition" "round_saeonly" "1" "(<MODE>mode == V16SFmode || <MODE>mode == V8DFmode || <MODE>mode == V8DImode diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index 59573d40a99..85a2b9ad630 100644 --- a/gcc/config/i386/sync.md +++ b/gcc/config/i386/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for i386 synchronization instructions. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/i386/sysv4.h b/gcc/config/i386/sysv4.h index 9f945074056..35e91027bf5 100644 --- a/gcc/config/i386/sysv4.h +++ b/gcc/config/i386/sysv4.h @@ -1,5 +1,5 @@ /* Target definitions for GCC for Intel 80386 running System V.4 - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. Written by Ron Guilmette (rfg@netcom.com). diff --git a/gcc/config/i386/t-cygming b/gcc/config/i386/t-cygming index 7775e79e820..db724fdc12e 100644 --- a/gcc/config/i386/t-cygming +++ b/gcc/config/i386/t-cygming @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2015 Free Software Foundation, Inc. +# Copyright (C) 2003-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-djgpp b/gcc/config/i386/t-djgpp new file mode 100644 index 00000000000..dd3b32ac351 --- /dev/null +++ b/gcc/config/i386/t-djgpp @@ -0,0 +1,8 @@ + +EXTRA_OBJS += djgpp.o + +djgpp.o: $(srcdir)/config/i386/djgpp.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ + $(TM_H) $(RTL_H) $(REGS_H) hard-reg-set.h output.h $(TREE_H) flags.h \ + $(TM_P_H) $(HASH_TABLE_H) $(GGC_H) $(LTO_STREAMER_H) + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/i386/djgpp.c diff --git a/gcc/config/i386/t-i386 b/gcc/config/i386/t-i386 index 5bb1be0427b..a90097cf8ce 100644 --- a/gcc/config/i386/t-i386 +++ b/gcc/config/i386/t-i386 @@ -1,4 +1,4 @@ -# Copyright (C) 2008-2015 Free Software Foundation, Inc. +# Copyright (C) 2008-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-interix b/gcc/config/i386/t-interix index dd59b85088d..39edbe5ccb6 100644 --- a/gcc/config/i386/t-interix +++ b/gcc/config/i386/t-interix @@ -1,4 +1,4 @@ -# Copyright (C) 2011-2015 Free Software Foundation, Inc. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-linux64 b/gcc/config/i386/t-linux64 index f6dbb78ffcf..c0cc8a37246 100644 --- a/gcc/config/i386/t-linux64 +++ b/gcc/config/i386/t-linux64 @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-rtems b/gcc/config/i386/t-rtems index ed84021531a..4a68cd50b01 100644 --- a/gcc/config/i386/t-rtems +++ b/gcc/config/i386/t-rtems @@ -1,4 +1,4 @@ -# Copyright (C) 1999-2015 Free Software Foundation, Inc. +# Copyright (C) 1999-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/t-sol2 b/gcc/config/i386/t-sol2 index a00d52e9e42..4bd1dee9ddb 100644 --- a/gcc/config/i386/t-sol2 +++ b/gcc/config/i386/t-sol2 @@ -1,4 +1,4 @@ -# Copyright (C) 2004-2015 Free Software Foundation, Inc. +# Copyright (C) 2004-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/tbmintrin.h b/gcc/config/i386/tbmintrin.h index cc265bbba5f..d4b3588d15c 100644 --- a/gcc/config/i386/tbmintrin.h +++ b/gcc/config/i386/tbmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2010-2015 Free Software Foundation, Inc. +/* Copyright (C) 2010-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/tmmintrin.h b/gcc/config/i386/tmmintrin.h index ac2e343eddf..6ec867d464b 100644 --- a/gcc/config/i386/tmmintrin.h +++ b/gcc/config/i386/tmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2006-2015 Free Software Foundation, Inc. +/* Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/unix.h b/gcc/config/i386/unix.h index 3ccd031882c..e73ffb3de7e 100644 --- a/gcc/config/i386/unix.h +++ b/gcc/config/i386/unix.h @@ -1,5 +1,5 @@ /* Definitions for Unix assembler syntax for the Intel 80386. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/vxworks.h b/gcc/config/i386/vxworks.h index 6abdf837a73..b5960b1c658 100644 --- a/gcc/config/i386/vxworks.h +++ b/gcc/config/i386/vxworks.h @@ -1,5 +1,5 @@ /* IA32 VxWorks target definitions for GNU compiler. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. Updated by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/i386/vxworksae.h b/gcc/config/i386/vxworksae.h index c2ce8c8c576..4455298febb 100644 --- a/gcc/config/i386/vxworksae.h +++ b/gcc/config/i386/vxworksae.h @@ -1,5 +1,5 @@ /* IA32 VxWorks AE target definitions for GNU compiler. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/i386/winnt-cxx.c b/gcc/config/i386/winnt-cxx.c index 8cb1347061e..f156ba87271 100644 --- a/gcc/config/i386/winnt-cxx.c +++ b/gcc/config/i386/winnt-cxx.c @@ -1,6 +1,6 @@ /* Target support for C++ classes on Windows. Contributed by Danny Smith (dannysmith@users.sourceforge.net) - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/winnt-stubs.c b/gcc/config/i386/winnt-stubs.c index 95aa9f20e77..39955b799ac 100644 --- a/gcc/config/i386/winnt-stubs.c +++ b/gcc/config/i386/winnt-stubs.c @@ -1,6 +1,6 @@ /* Dummy subroutines for language-specific support on Windows. Contributed by Danny Smith (dannysmith@users.sourceforge.net) - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/winnt.c b/gcc/config/i386/winnt.c index ec670cf4bfe..53abf475bce 100644 --- a/gcc/config/i386/winnt.c +++ b/gcc/config/i386/winnt.c @@ -1,6 +1,6 @@ /* Subroutines for insn-output.c for Windows NT. Contributed by Douglas Rupp (drupp@cs.washington.edu) - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/wmmintrin.h b/gcc/config/i386/wmmintrin.h index 37eac1fb1c8..be79f4332a7 100644 --- a/gcc/config/i386/wmmintrin.h +++ b/gcc/config/i386/wmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2015 Free Software Foundation, Inc. +/* Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/x-mingw32 b/gcc/config/i386/x-mingw32 index f0884b8dfda..1d28a702a9d 100644 --- a/gcc/config/i386/x-mingw32 +++ b/gcc/config/i386/x-mingw32 @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2015 Free Software Foundation, Inc. +# Copyright (C) 2003-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/i386/x86-64.h b/gcc/config/i386/x86-64.h index a1e145ff29d..204f128d5b0 100644 --- a/gcc/config/i386/x86-64.h +++ b/gcc/config/i386/x86-64.h @@ -1,5 +1,5 @@ /* OS independent definitions for AMD x86-64. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Bo Thorsen <bo@suse.de>. This file is part of GCC. diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index b2d39219124..9d25e51d407 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -1,5 +1,5 @@ /* Definitions of x86 tunable features. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -550,3 +550,8 @@ DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", 0) unrolling small loop less important. For, such architectures we adjust the unroll factor so that the unrolled loop fits the loop buffer. */ DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4) + +/* X86_TUNE_ONE_IF_CONV_INSNS: Restrict a number of set insns to be + if-converted to one. */ +DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn", + m_SILVERMONT | m_KNL | m_INTEL | m_CORE_ALL | m_GENERIC) diff --git a/gcc/config/i386/x86intrin.h b/gcc/config/i386/x86intrin.h index 9b292b35434..e666c4ed635 100644 --- a/gcc/config/i386/x86intrin.h +++ b/gcc/config/i386/x86intrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2015 Free Software Foundation, Inc. +/* Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -95,6 +95,8 @@ #include <clzerointrin.h> +#include <pkuintrin.h> + #endif /* __iamcu__ */ #endif /* _X86INTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/xm-cygwin.h b/gcc/config/i386/xm-cygwin.h index e40d11defa2..92bd1087f93 100644 --- a/gcc/config/i386/xm-cygwin.h +++ b/gcc/config/i386/xm-cygwin.h @@ -1,6 +1,6 @@ /* Configuration for GCC for hosting on Windows NT. using a unix style C library. - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xm-djgpp.h b/gcc/config/i386/xm-djgpp.h index 626be2fcff0..94e6ff614a7 100644 --- a/gcc/config/i386/xm-djgpp.h +++ b/gcc/config/i386/xm-djgpp.h @@ -1,5 +1,5 @@ /* Configuration for GCC for Intel 80386 running DJGPP. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -22,6 +22,31 @@ along with GCC; see the file COPYING3. If not see #define HOST_EXECUTABLE_SUFFIX ".exe" +/* Define standard DJGPP installation paths. */ +/* We override default /usr or /usr/local part with /dev/env/DJDIR which */ +/* points to actual DJGPP installation directory. */ + +/* Native system include directory */ +#undef NATIVE_SYSTEM_HEADER_DIR +#define NATIVE_SYSTEM_HEADER_DIR "/dev/env/DJDIR/include/" + +/* Search for as.exe and ld.exe in DJGPP's binary directory. */ +#undef MD_EXEC_PREFIX +#define MD_EXEC_PREFIX "/dev/env/DJDIR/bin/" + +/* Standard DJGPP library and startup files */ +#undef STANDARD_STARTFILE_PREFIX_1 +#define STANDARD_STARTFILE_PREFIX_1 "/dev/env/DJDIR/lib/" + +/* Define STANDARD_STARTFILE_PREFIX_2 equal to STANDARD_STARTFILE_PREFIX_1 + to avoid gcc.c redefining it to /usr/lib */ +#undef STANDARD_STARTFILE_PREFIX_2 +#define STANDARD_STARTFILE_PREFIX_1 "/dev/env/DJDIR/lib/" + +/* Make sure that gcc will not look for .h files in /usr/local/include + unless user explicitly requests it. */ +#undef LOCAL_INCLUDE_DIR + /* System dependent initialization for collect2 to tell system() to act like Unix. */ #define COLLECT2_HOST_INITIALIZATION \ @@ -57,12 +82,12 @@ along with GCC; see the file COPYING3. If not see to try and figure out what's wrong. */ \ char *djgpp = getenv ("DJGPP"); \ if (djgpp == NULL) \ - fatal ("environment variable DJGPP not defined"); \ + fatal_error (UNKNOWN_LOCATION, "environment variable DJGPP not defined"); \ else if (access (djgpp, R_OK) == 0) \ - fatal ("environment variable DJGPP points to missing file '%s'", \ + fatal_error (UNKNOWN_LOCATION, "environment variable DJGPP points to missing file '%s'", \ djgpp); \ else \ - fatal ("environment variable DJGPP points to corrupt file '%s'", \ + fatal_error (UNKNOWN_LOCATION, "environment variable DJGPP points to corrupt file '%s'", \ djgpp); \ } \ } while (0) @@ -80,4 +105,11 @@ along with GCC; see the file COPYING3. If not see _fixpath ((PATH), fixed_path); \ strcat (fixed_path, "/"); \ (PATH) = xstrdup (fixed_path); \ - } + } + +#undef MAX_OFILE_ALIGNMENT +#define MAX_OFILE_ALIGNMENT 128 + +/* DJGPP versions up to current (2.05) have ftw.h but only ftw() not nftw(). + Disable use of ftw.h */ +#undef HAVE_FTW_H diff --git a/gcc/config/i386/xm-mingw32.h b/gcc/config/i386/xm-mingw32.h index 501cebdb963..5561e00343e 100644 --- a/gcc/config/i386/xm-mingw32.h +++ b/gcc/config/i386/xm-mingw32.h @@ -1,6 +1,6 @@ /* Configuration for GCC for hosting on Windows32. using GNU tools and the Windows32 API Library. - Copyright (C) 1997-2015 Free Software Foundation, Inc. + Copyright (C) 1997-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xmmintrin.h b/gcc/config/i386/xmmintrin.h index 9cd3fa7d079..ffe5771b1c5 100644 --- a/gcc/config/i386/xmmintrin.h +++ b/gcc/config/i386/xmmintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002-2015 Free Software Foundation, Inc. +/* Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xopintrin.h b/gcc/config/i386/xopintrin.h index 6573767e7b1..609cba04a6f 100644 --- a/gcc/config/i386/xopintrin.h +++ b/gcc/config/i386/xopintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2007-2015 Free Software Foundation, Inc. +/* Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xsavecintrin.h b/gcc/config/i386/xsavecintrin.h index f32dbe9e823..4757415bc3c 100644 --- a/gcc/config/i386/xsavecintrin.h +++ b/gcc/config/i386/xsavecintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2015 Free Software Foundation, Inc. +/* Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xsaveintrin.h b/gcc/config/i386/xsaveintrin.h index 614fcf6ef5b..53616b72281 100644 --- a/gcc/config/i386/xsaveintrin.h +++ b/gcc/config/i386/xsaveintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xsaveoptintrin.h b/gcc/config/i386/xsaveoptintrin.h index 7f71c014505..2569824bb81 100644 --- a/gcc/config/i386/xsaveoptintrin.h +++ b/gcc/config/i386/xsaveoptintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xsavesintrin.h b/gcc/config/i386/xsavesintrin.h index 48efc4c59e7..cc29e47dfec 100644 --- a/gcc/config/i386/xsavesintrin.h +++ b/gcc/config/i386/xsavesintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2014-2015 Free Software Foundation, Inc. +/* Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/xtestintrin.h b/gcc/config/i386/xtestintrin.h index 026e60b6aae..b5a84d49158 100644 --- a/gcc/config/i386/xtestintrin.h +++ b/gcc/config/i386/xtestintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2012-2015 Free Software Foundation, Inc. +/* Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/i386/znver1.md b/gcc/config/i386/znver1.md index d8c429c08c8..b7fcf6c7a1e 100644 --- a/gcc/config/i386/znver1.md +++ b/gcc/config/i386/znver1.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/ia64/constraints.md b/gcc/config/ia64/constraints.md index f58567d3f9e..7cfba36356d 100644 --- a/gcc/config/ia64/constraints.md +++ b/gcc/config/ia64/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for IA-64 -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/ia64/div.md b/gcc/config/ia64/div.md index 1fe4ebace1e..19e95c10fb8 100644 --- a/gcc/config/ia64/div.md +++ b/gcc/config/ia64/div.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/ia64/elf.h b/gcc/config/ia64/elf.h index c9f87ab971b..a65f3d89228 100644 --- a/gcc/config/ia64/elf.h +++ b/gcc/config/ia64/elf.h @@ -1,6 +1,6 @@ /* Definitions for embedded ia64-elf target. -Copyright (C) 2000-2015 Free Software Foundation, Inc. +Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/ia64/freebsd.h b/gcc/config/ia64/freebsd.h index a62479e0b97..bcce09ba416 100644 --- a/gcc/config/ia64/freebsd.h +++ b/gcc/config/ia64/freebsd.h @@ -1,5 +1,5 @@ /* Definitions for Intel IA-64 running FreeBSD using the ELF format - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by David E. O'Brien <obrien@FreeBSD.org> and BSDi. This file is part of GCC. diff --git a/gcc/config/ia64/hpux.h b/gcc/config/ia64/hpux.h index a497e444b21..8b90c99f44b 100644 --- a/gcc/config/ia64/hpux.h +++ b/gcc/config/ia64/hpux.h @@ -1,5 +1,5 @@ /* Definitions of target machine GNU compiler. IA-64 version. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by Steve Ellcey <sje@cup.hp.com> and Reva Cuthbertson <reva@cup.hp.com> diff --git a/gcc/config/ia64/ia64-c.c b/gcc/config/ia64/ia64-c.c index cc9e82bdaad..6aa2c5fcc4a 100644 --- a/gcc/config/ia64/ia64-c.c +++ b/gcc/config/ia64/ia64-c.c @@ -1,5 +1,5 @@ /* Definitions of C specific functions for GNU compiler. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Steve Ellcey <sje@cup.hp.com> This file is part of GCC. diff --git a/gcc/config/ia64/ia64-modes.def b/gcc/config/ia64/ia64-modes.def index 7f16d49ab9b..bee833480a8 100644 --- a/gcc/config/ia64/ia64-modes.def +++ b/gcc/config/ia64/ia64-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine GNU compiler. IA-64 version. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by James E. Wilson <wilson@cygnus.com> and David Mosberger <davidm@hpl.hp.com>. diff --git a/gcc/config/ia64/ia64-opts.h b/gcc/config/ia64/ia64-opts.h index 8aa634ff504..2d823735506 100644 --- a/gcc/config/ia64/ia64-opts.h +++ b/gcc/config/ia64/ia64-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for IA-64. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/ia64/ia64-protos.h b/gcc/config/ia64/ia64-protos.h index 29fc714100a..f23260422e7 100644 --- a/gcc/config/ia64/ia64-protos.h +++ b/gcc/config/ia64/ia64-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for IA-64. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index f48cebc4036..33ec7a74bee 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by James E. Wilson <wilson@cygnus.com> and David Mosberger <davidm@hpl.hp.com>. @@ -1105,6 +1105,15 @@ ia64_expand_load_address (rtx dest, rtx src) emit_insn (gen_load_fptr (dest, src)); else if (sdata_symbolic_operand (src, VOIDmode)) emit_insn (gen_load_gprel (dest, src)); + else if (local_symbolic_operand64 (src, VOIDmode)) + { + /* We want to use @gprel rather than @ltoff relocations for local + symbols: + - @gprel does not require dynamic linker + - and does not use .sdata section + https://gcc.gnu.org/bugzilla/60465 */ + emit_insn (gen_load_gprel64 (dest, src)); + } else { HOST_WIDE_INT addend = 0; diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h index 4b624237a48..4e1b7af6ab7 100644 --- a/gcc/config/ia64/ia64.h +++ b/gcc/config/ia64/ia64.h @@ -1,5 +1,5 @@ /* Definitions of target machine GNU compiler. IA-64 version. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by James E. Wilson <wilson@cygnus.com> and David Mosberger <davidm@hpl.hp.com>. diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index c343aca3030..7bc21fd8ca4 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -1,5 +1,5 @@ ;; IA-64 Machine description template -;; Copyright (C) 1999-2015 Free Software Foundation, Inc. +;; Copyright (C) 1999-2016 Free Software Foundation, Inc. ;; Contributed by James E. Wilson <wilson@cygnus.com> and ;; David Mosberger <davidm@hpl.hp.com>. diff --git a/gcc/config/ia64/ia64.opt b/gcc/config/ia64/ia64.opt index 4e0af4238ef..99f7a685577 100644 --- a/gcc/config/ia64/ia64.opt +++ b/gcc/config/ia64/ia64.opt @@ -1,4 +1,4 @@ -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/ia64/itanium2.md b/gcc/config/ia64/itanium2.md index f0fe07f31e3..cd318612db2 100644 --- a/gcc/config/ia64/itanium2.md +++ b/gcc/config/ia64/itanium2.md @@ -1,5 +1,5 @@ ;; Itanium2 DFA descriptions for insn scheduling and bundling. -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; Contributed by Vladimir Makarov <vmakarov@redhat.com>. ;; ;; This file is part of GCC. diff --git a/gcc/config/ia64/linux.h b/gcc/config/ia64/linux.h index f6ef6d70a67..e0395a693d0 100644 --- a/gcc/config/ia64/linux.h +++ b/gcc/config/ia64/linux.h @@ -1,6 +1,6 @@ /* Definitions for ia64-linux target. -Copyright (C) 2000-2015 Free Software Foundation, Inc. +Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md index 2aa7a780e02..02347f7823c 100644 --- a/gcc/config/ia64/predicates.md +++ b/gcc/config/ia64/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for IA-64. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -97,6 +97,32 @@ } }) +;; True if OP refers to a local symbol [+any offset]. +;; To be encoded as: +;; movl % = @gprel(symbol+offset) +;; add % = %, gp +(define_predicate "local_symbolic_operand64" + (match_code "symbol_ref,const") +{ + switch (GET_CODE (op)) + { + case CONST: + op = XEXP (op, 0); + if (GET_CODE (op) != PLUS + || GET_CODE (XEXP (op, 0)) != SYMBOL_REF + || GET_CODE (XEXP (op, 1)) != CONST_INT) + return false; + op = XEXP (op, 0); + /* FALLTHRU */ + + case SYMBOL_REF: + return SYMBOL_REF_LOCAL_P (op); + + default: + gcc_unreachable (); + } +}) + ;; True if OP refers to a symbol in the small address area. (define_predicate "small_addr_symbolic_operand" (match_code "symbol_ref,const") diff --git a/gcc/config/ia64/sync.md b/gcc/config/ia64/sync.md index 9c178b826b1..62335d76a21 100644 --- a/gcc/config/ia64/sync.md +++ b/gcc/config/ia64/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for IA-64 synchronization instructions. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/ia64/sysv4.h b/gcc/config/ia64/sysv4.h index e3b25037199..dc2f5c504d9 100644 --- a/gcc/config/ia64/sysv4.h +++ b/gcc/config/ia64/sysv4.h @@ -1,6 +1,6 @@ /* Override definitions in elfos.h to be correct for IA64. -Copyright (C) 2000-2015 Free Software Foundation, Inc. +Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/ia64/t-hpux b/gcc/config/ia64/t-hpux index 32ff4fead32..22d692d1bb8 100644 --- a/gcc/config/ia64/t-hpux +++ b/gcc/config/ia64/t-hpux @@ -1,4 +1,4 @@ -# Copyright (C) 2001-2015 Free Software Foundation, Inc. +# Copyright (C) 2001-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/ia64/t-ia64 b/gcc/config/ia64/t-ia64 index 3ac6768ab16..dd2bda173cd 100644 --- a/gcc/config/ia64/t-ia64 +++ b/gcc/config/ia64/t-ia64 @@ -1,4 +1,4 @@ -# Copyright (C) 2000-2015 Free Software Foundation, Inc. +# Copyright (C) 2000-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md index 9e75e9a8a29..82c881898ab 100644 --- a/gcc/config/ia64/vect.md +++ b/gcc/config/ia64/vect.md @@ -1,5 +1,5 @@ ;; IA-64 machine description for vector operations. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/ia64/vms.h b/gcc/config/ia64/vms.h index ee77f09af95..8a80a7edbe1 100644 --- a/gcc/config/ia64/vms.h +++ b/gcc/config/ia64/vms.h @@ -1,5 +1,5 @@ /* Definitions of target machine GNU compiler. IA64-VMS version. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. Contributed by Douglas B Rupp (rupp@gnat.com). This file is part of GCC. diff --git a/gcc/config/ia64/vms.opt b/gcc/config/ia64/vms.opt index 19ff9bcab93..5bb3f45230c 100644 --- a/gcc/config/ia64/vms.opt +++ b/gcc/config/ia64/vms.opt @@ -1,6 +1,6 @@ ; IA64 VMS options. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/initfini-array.h b/gcc/config/initfini-array.h index 59adedebf00..90202429b07 100644 --- a/gcc/config/initfini-array.h +++ b/gcc/config/initfini-array.h @@ -1,6 +1,6 @@ /* Definitions for ELF systems with .init_array/.fini_array section support. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/iq2000/abi b/gcc/config/iq2000/abi index 3497132e990..2303529872a 100644 --- a/gcc/config/iq2000/abi +++ b/gcc/config/iq2000/abi @@ -232,7 +232,7 @@ caller passing as a "hidden" first argument a pointer to space allocated to receive the return value. -Copyright (C) 2003-2015 Free Software Foundation, Inc. +Copyright (C) 2003-2016 Free Software Foundation, Inc. Copying and distribution of this file, with or without modification, are permitted in any medium without royalty provided the copyright diff --git a/gcc/config/iq2000/constraints.md b/gcc/config/iq2000/constraints.md index d89c4d998d4..b7f83bd675f 100644 --- a/gcc/config/iq2000/constraints.md +++ b/gcc/config/iq2000/constraints.md @@ -1,5 +1,5 @@ ;; Constraints for Vitesse IQ2000 processors -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/iq2000/iq2000-opts.h b/gcc/config/iq2000/iq2000-opts.h index 6ca98c834e6..46ba9c5e6df 100644 --- a/gcc/config/iq2000/iq2000-opts.h +++ b/gcc/config/iq2000/iq2000-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for Vitesse IQ2000 processors. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/iq2000/iq2000-protos.h b/gcc/config/iq2000/iq2000-protos.h index 29e27a99442..6a457e64310 100644 --- a/gcc/config/iq2000/iq2000-protos.h +++ b/gcc/config/iq2000/iq2000-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for iq2000. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c index 26b9e6741ff..73b9cdb3fe0 100644 --- a/gcc/config/iq2000/iq2000.c +++ b/gcc/config/iq2000/iq2000.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on Vitesse IQ2000 processors - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/iq2000/iq2000.h b/gcc/config/iq2000/iq2000.h index 73b1205db1c..3b9dceb6904 100644 --- a/gcc/config/iq2000/iq2000.h +++ b/gcc/config/iq2000/iq2000.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. Vitesse IQ2000 processors - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/iq2000/iq2000.md b/gcc/config/iq2000/iq2000.md index a0306616b86..ed93e0edc09 100644 --- a/gcc/config/iq2000/iq2000.md +++ b/gcc/config/iq2000/iq2000.md @@ -1,5 +1,5 @@ ;; iq2000.md Machine Description for Vitesse IQ2000 processors -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/iq2000/iq2000.opt b/gcc/config/iq2000/iq2000.opt index 721b0804be3..f43725549f0 100644 --- a/gcc/config/iq2000/iq2000.opt +++ b/gcc/config/iq2000/iq2000.opt @@ -1,6 +1,6 @@ ; Options for the Vitesse IQ2000 port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/iq2000/predicates.md b/gcc/config/iq2000/predicates.md index 1d0601b6ae4..11fed73956d 100644 --- a/gcc/config/iq2000/predicates.md +++ b/gcc/config/iq2000/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Vitesse IQ2000. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/kfreebsd-gnu.h b/gcc/config/kfreebsd-gnu.h index 96773674664..164231b4a02 100644 --- a/gcc/config/kfreebsd-gnu.h +++ b/gcc/config/kfreebsd-gnu.h @@ -1,5 +1,5 @@ /* Definitions for kFreeBSD-based GNU systems with ELF format - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/knetbsd-gnu.h b/gcc/config/knetbsd-gnu.h index 95f80bb0018..02b7488a07c 100644 --- a/gcc/config/knetbsd-gnu.h +++ b/gcc/config/knetbsd-gnu.h @@ -1,5 +1,5 @@ /* Definitions for kNetBSD-based GNU systems with ELF format - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/kopensolaris-gnu.h b/gcc/config/kopensolaris-gnu.h index 0a35a06adc3..080cab20d65 100644 --- a/gcc/config/kopensolaris-gnu.h +++ b/gcc/config/kopensolaris-gnu.h @@ -1,5 +1,5 @@ /* Definitions for kOpenSolaris-based GNU systems with ELF format - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. Contributed by Robert Millan. This file is part of GCC. diff --git a/gcc/config/linux-android.h b/gcc/config/linux-android.h index 7b3a1e5fd69..301a41ccdd8 100644 --- a/gcc/config/linux-android.h +++ b/gcc/config/linux-android.h @@ -1,5 +1,5 @@ /* Configuration file for Linux Android targets. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. Contributed by Doug Kwan (dougkwan@google.com) Rewritten by CodeSourcery, Inc. diff --git a/gcc/config/linux-android.opt b/gcc/config/linux-android.opt index 3e732ffe928..2c39f04f61b 100644 --- a/gcc/config/linux-android.opt +++ b/gcc/config/linux-android.opt @@ -1,6 +1,6 @@ ; Android specific options. -; Copyright (C) 2008-2015 Free Software Foundation, Inc. +; Copyright (C) 2008-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/linux-protos.h b/gcc/config/linux-protos.h index 786e668ea3f..87f1b0539af 100644 --- a/gcc/config/linux-protos.h +++ b/gcc/config/linux-protos.h @@ -1,5 +1,5 @@ /* Prototypes. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/linux.c b/gcc/config/linux.c index 2081e340688..250296bf425 100644 --- a/gcc/config/linux.c +++ b/gcc/config/linux.c @@ -1,5 +1,5 @@ /* Functions for Linux Android as target machine for GNU C compiler. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/linux.h b/gcc/config/linux.h index a2094ce7fa8..9aeeb948f55 100644 --- a/gcc/config/linux.h +++ b/gcc/config/linux.h @@ -2,7 +2,7 @@ MMU, using ELF at the compiler level but possibly FLT for final linked executables and shared libraries in some no-MMU cases, and possibly with a choice of libc implementations. - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. Contributed by Eric Youngdale. Modified for stabs-in-ELF by H.J. Lu (hjl@lucon.org). diff --git a/gcc/config/linux.opt b/gcc/config/linux.opt index 3f6115f46a0..6cadc52011b 100644 --- a/gcc/config/linux.opt +++ b/gcc/config/linux.opt @@ -1,6 +1,6 @@ ; Processor-independent options for GNU/Linux. ; -; Copyright (C) 2006-2015 Free Software Foundation, Inc. +; Copyright (C) 2006-2016 Free Software Foundation, Inc. ; Contributed by CodeSourcery. ; ; This file is part of GCC. diff --git a/gcc/config/lm32/constraints.md b/gcc/config/lm32/constraints.md index bfd0ec5f3e3..5d91a8ec295 100644 --- a/gcc/config/lm32/constraints.md +++ b/gcc/config/lm32/constraints.md @@ -1,7 +1,7 @@ ;; Constraint definitions for Lattice Mico32 architecture. ;; Contributed by Jon Beniston <jon@beniston.com> ;; -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/lm32/lm32-protos.h b/gcc/config/lm32/lm32-protos.h index 80c9398e4c7..e19c82f43a6 100644 --- a/gcc/config/lm32/lm32-protos.h +++ b/gcc/config/lm32/lm32-protos.h @@ -1,7 +1,7 @@ /* Prototypes of target machine functions, Lattice Mico32 architecture. Contributed by Jon Beniston <jon@beniston.com> - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/lm32/lm32.c b/gcc/config/lm32/lm32.c index 7a19a8204ca..4a8079f4a74 100644 --- a/gcc/config/lm32/lm32.c +++ b/gcc/config/lm32/lm32.c @@ -1,7 +1,7 @@ /* Subroutines used for code generation on the Lattice Mico32 architecture. Contributed by Jon Beniston <jon@beniston.com> - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/lm32/lm32.h b/gcc/config/lm32/lm32.h index c65538adcd8..e18e13693fb 100644 --- a/gcc/config/lm32/lm32.h +++ b/gcc/config/lm32/lm32.h @@ -1,7 +1,7 @@ /* Definitions of target machine for GNU compiler, Lattice Mico32 architecture. Contributed by Jon Beniston <jon@beniston.com> - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/lm32/lm32.md b/gcc/config/lm32/lm32.md index 5c87072cb67..5d06f2c16a7 100644 --- a/gcc/config/lm32/lm32.md +++ b/gcc/config/lm32/lm32.md @@ -1,7 +1,7 @@ ;; Machine description of the Lattice Mico32 architecture for GNU C compiler. ;; Contributed by Jon Beniston <jon@beniston.com> -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/lm32/lm32.opt b/gcc/config/lm32/lm32.opt index 4090b3db365..8106407613f 100644 --- a/gcc/config/lm32/lm32.opt +++ b/gcc/config/lm32/lm32.opt @@ -1,7 +1,7 @@ ; Options for the Lattice Mico32 port of the compiler. ; Contributed by Jon Beniston <jon@beniston.com> ; -; Copyright (C) 2009-2015 Free Software Foundation, Inc. +; Copyright (C) 2009-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/lm32/predicates.md b/gcc/config/lm32/predicates.md index 3edafbc3a59..6bb1037fc7b 100644 --- a/gcc/config/lm32/predicates.md +++ b/gcc/config/lm32/predicates.md @@ -1,7 +1,7 @@ ;; Predicate definitions for Lattice Mico32 architecture. ;; Contributed by Jon Beniston <jon@beniston.com> ;; -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/lm32/rtems.h b/gcc/config/lm32/rtems.h index 411297a6c10..5f3bd2a43e8 100644 --- a/gcc/config/lm32/rtems.h +++ b/gcc/config/lm32/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a lm32 using ELF. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/lm32/uclinux-elf.h b/gcc/config/lm32/uclinux-elf.h index fad3ab7b024..4a0862dca89 100644 --- a/gcc/config/lm32/uclinux-elf.h +++ b/gcc/config/lm32/uclinux-elf.h @@ -1,5 +1,5 @@ /* Definitions for LM32 running Linux-based GNU systems using ELF - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. Contributed by Philip Blundell <philb@gnu.org> This file is part of GCC. diff --git a/gcc/config/lynx.h b/gcc/config/lynx.h index ac3565e288b..fa180c77dc1 100644 --- a/gcc/config/lynx.h +++ b/gcc/config/lynx.h @@ -1,5 +1,5 @@ /* Target independent definitions for LynxOS. - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/lynx.opt b/gcc/config/lynx.opt index 39bf9ee26b1..415911164d4 100644 --- a/gcc/config/lynx.opt +++ b/gcc/config/lynx.opt @@ -1,6 +1,6 @@ ; Processor-independent options for LynxOS. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/m32c/addsub.md b/gcc/config/m32c/addsub.md index 74cbd3b7cbd..ac8a7f16495 100644 --- a/gcc/config/m32c/addsub.md +++ b/gcc/config/m32c/addsub.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/bitops.md b/gcc/config/m32c/bitops.md index e75e6712dde..8c512323733 100644 --- a/gcc/config/m32c/bitops.md +++ b/gcc/config/m32c/bitops.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/blkmov.md b/gcc/config/m32c/blkmov.md index 02ad3455bd1..39b0c427116 100644 --- a/gcc/config/m32c/blkmov.md +++ b/gcc/config/m32c/blkmov.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/cond.md b/gcc/config/m32c/cond.md index 366727c7d9c..696f7055be4 100644 --- a/gcc/config/m32c/cond.md +++ b/gcc/config/m32c/cond.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/constraints.md b/gcc/config/m32c/constraints.md index bf31a45592e..57c765ef241 100644 --- a/gcc/config/m32c/constraints.md +++ b/gcc/config/m32c/constraints.md @@ -1,5 +1,5 @@ ;; m32c constraints -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/m32c/jump.md b/gcc/config/m32c/jump.md index aff828d1f88..87e53ed4879 100644 --- a/gcc/config/m32c/jump.md +++ b/gcc/config/m32c/jump.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/m32c-modes.def b/gcc/config/m32c/m32c-modes.def index 16cecd9b26a..8e605c6c811 100644 --- a/gcc/config/m32c/m32c-modes.def +++ b/gcc/config/m32c/m32c-modes.def @@ -1,5 +1,5 @@ /* Target-Specific Modes for R8C/M16C/M32C - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/m32c/m32c-pragma.c b/gcc/config/m32c/m32c-pragma.c index 570b3baa672..66278f165af 100644 --- a/gcc/config/m32c/m32c-pragma.c +++ b/gcc/config/m32c/m32c-pragma.c @@ -1,5 +1,5 @@ /* M32C Pragma support - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/m32c/m32c-protos.h b/gcc/config/m32c/m32c-protos.h index 95b5258aefb..9c8a442d247 100644 --- a/gcc/config/m32c/m32c-protos.h +++ b/gcc/config/m32c/m32c-protos.h @@ -1,5 +1,5 @@ /* Target Prototypes for R8C/M16C/M32C - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/m32c/m32c.abi b/gcc/config/m32c/m32c.abi index f27617dde0d..f32d271a8a2 100644 --- a/gcc/config/m32c/m32c.abi +++ b/gcc/config/m32c/m32c.abi @@ -1,5 +1,5 @@ Target Definitions for R8C/M16C/M32C - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c index baf978f2ddf..6f6d7e4e45e 100644 --- a/gcc/config/m32c/m32c.c +++ b/gcc/config/m32c/m32c.c @@ -1,5 +1,5 @@ /* Target Code for R8C/M16C/M32C - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/m32c/m32c.h b/gcc/config/m32c/m32c.h index 7d5f2fca02f..fce3c73c8cd 100644 --- a/gcc/config/m32c/m32c.h +++ b/gcc/config/m32c/m32c.h @@ -1,5 +1,5 @@ /* Target Definitions for R8C/M16C/M32C - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/m32c/m32c.md b/gcc/config/m32c/m32c.md index c002ebb6011..3ceff8fecb5 100644 --- a/gcc/config/m32c/m32c.md +++ b/gcc/config/m32c/m32c.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/m32c.opt b/gcc/config/m32c/m32c.opt index 0ff13fa5ee1..881b2d3222a 100644 --- a/gcc/config/m32c/m32c.opt +++ b/gcc/config/m32c/m32c.opt @@ -1,5 +1,5 @@ ; Target Options for R8C/M16C/M32C -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; Contributed by Red Hat. ; ; This file is part of GCC. diff --git a/gcc/config/m32c/minmax.md b/gcc/config/m32c/minmax.md index 33aad68810a..da7bdcbb8aa 100644 --- a/gcc/config/m32c/minmax.md +++ b/gcc/config/m32c/minmax.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/mov.md b/gcc/config/m32c/mov.md index 356963add88..ec90cc7d160 100644 --- a/gcc/config/m32c/mov.md +++ b/gcc/config/m32c/mov.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/muldiv.md b/gcc/config/m32c/muldiv.md index a089a9d6e4f..59d471907b0 100644 --- a/gcc/config/m32c/muldiv.md +++ b/gcc/config/m32c/muldiv.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/predicates.md b/gcc/config/m32c/predicates.md index 1dadd392716..e991ed42ab1 100644 --- a/gcc/config/m32c/predicates.md +++ b/gcc/config/m32c/predicates.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/prologue.md b/gcc/config/m32c/prologue.md index 902d25b08e2..a2b4a765a16 100644 --- a/gcc/config/m32c/prologue.md +++ b/gcc/config/m32c/prologue.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/rtems.h b/gcc/config/m32c/rtems.h index 4b279abefaf..e8f6c5a70b2 100644 --- a/gcc/config/m32c/rtems.h +++ b/gcc/config/m32c/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a M32C using ELF. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/m32c/shift.md b/gcc/config/m32c/shift.md index a7495a46dbc..22320c09aea 100644 --- a/gcc/config/m32c/shift.md +++ b/gcc/config/m32c/shift.md @@ -1,5 +1,5 @@ ;; Machine Descriptions for R8C/M16C/M32C -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/m32c/t-m32c b/gcc/config/m32c/t-m32c index 4c8edfd69dc..888ff7ce5d8 100644 --- a/gcc/config/m32c/t-m32c +++ b/gcc/config/m32c/t-m32c @@ -1,5 +1,5 @@ # Target Makefile Fragment for R8C/M16C/M32C -# Copyright (C) 2005-2015 Free Software Foundation, Inc. +# Copyright (C) 2005-2016 Free Software Foundation, Inc. # Contributed by Red Hat. # # This file is part of GCC. diff --git a/gcc/config/m32r/constraints.md b/gcc/config/m32r/constraints.md index 193a7d8e304..5b616596108 100644 --- a/gcc/config/m32r/constraints.md +++ b/gcc/config/m32r/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Renesas M32R cpu for GNU C compiler -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/m32r/linux.h b/gcc/config/m32r/linux.h index 1bb62973d7a..5ac7ac50d48 100644 --- a/gcc/config/m32r/linux.h +++ b/gcc/config/m32r/linux.h @@ -1,5 +1,5 @@ /* Definitions for Renesas M32R running Linux-based GNU systems using ELF. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m32r/little.h b/gcc/config/m32r/little.h index 65b95b182a5..87f2d6b9dc3 100644 --- a/gcc/config/m32r/little.h +++ b/gcc/config/m32r/little.h @@ -1,5 +1,5 @@ /* Definitions for Renesas little endian M32R cpu. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m32r/m32r-opts.h b/gcc/config/m32r/m32r-opts.h index 567b6837270..8544d843a11 100644 --- a/gcc/config/m32r/m32r-opts.h +++ b/gcc/config/m32r/m32r-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for Renesas M32R cpu. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m32r/m32r-protos.h b/gcc/config/m32r/m32r-protos.h index 3cbca56850e..eda05f2816e 100644 --- a/gcc/config/m32r/m32r-protos.h +++ b/gcc/config/m32r/m32r-protos.h @@ -1,5 +1,5 @@ /* Prototypes for m32r.c functions used in the md file & elsewhere. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c index e4085daf6a5..b40c53ca189 100644 --- a/gcc/config/m32r/m32r.c +++ b/gcc/config/m32r/m32r.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on the Renesas M32R cpu. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h index fa061351f38..2ff4a459dc4 100644 --- a/gcc/config/m32r/m32r.h +++ b/gcc/config/m32r/m32r.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, Renesas M32R cpu. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md index b036800e39c..9529b4c58fa 100644 --- a/gcc/config/m32r/m32r.md +++ b/gcc/config/m32r/m32r.md @@ -1,5 +1,5 @@ ;; Machine description of the Renesas M32R cpu for GNU C compiler -;; Copyright (C) 1996-2015 Free Software Foundation, Inc. +;; Copyright (C) 1996-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/m32r/m32r.opt b/gcc/config/m32r/m32r.opt index c87b6875621..b68e5147950 100644 --- a/gcc/config/m32r/m32r.opt +++ b/gcc/config/m32r/m32r.opt @@ -1,6 +1,6 @@ ; Options for the Renesas M32R port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/m32r/predicates.md b/gcc/config/m32r/predicates.md index e3336ea9992..0c74bb531c7 100644 --- a/gcc/config/m32r/predicates.md +++ b/gcc/config/m32r/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Renesas M32R. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/m32r/rtems.h b/gcc/config/m32r/rtems.h index 6f38ed4d225..839b4e0980d 100644 --- a/gcc/config/m32r/rtems.h +++ b/gcc/config/m32r/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a M32R using ELF. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/m32r/t-linux b/gcc/config/m32r/t-linux index 5841e85cab0..70224d0576b 100644 --- a/gcc/config/m32r/t-linux +++ b/gcc/config/m32r/t-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2015 Free Software Foundation, Inc. +# Copyright (C) 2003-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/m32r/t-m32r b/gcc/config/m32r/t-m32r index 50ad75d4dfe..16055761b44 100644 --- a/gcc/config/m32r/t-m32r +++ b/gcc/config/m32r/t-m32r @@ -1,4 +1,4 @@ -# Copyright (C) 1997-2015 Free Software Foundation, Inc. +# Copyright (C) 1997-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/m68k/cf.md b/gcc/config/m68k/cf.md index 66273f5714f..14f0dd65751 100644 --- a/gcc/config/m68k/cf.md +++ b/gcc/config/m68k/cf.md @@ -1,5 +1,5 @@ ;; ColdFire V1, V2, V3 and V4/V4e DFA description. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; Contributed by CodeSourcery Inc., www.codesourcery.com ;; ;; This file is part of GCC. diff --git a/gcc/config/m68k/constraints.md b/gcc/config/m68k/constraints.md index 1223852570c..b6212089530 100644 --- a/gcc/config/m68k/constraints.md +++ b/gcc/config/m68k/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for m68k -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/m68k/genopt.sh b/gcc/config/m68k/genopt.sh index ffd9dc3a6f2..71a70596c7a 100755 --- a/gcc/config/m68k/genopt.sh +++ b/gcc/config/m68k/genopt.sh @@ -1,6 +1,6 @@ #!/bin/sh # Generate m68k-tables.opt from the lists in *.def. -# Copyright (C) 2011-2015 Free Software Foundation, Inc. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -23,7 +23,7 @@ cat <<EOF ; Generated automatically by genopt.sh from m68k-devices.def, ; m68k-isas.def and m68k-microarchs.def. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/m68k/ieee.opt b/gcc/config/m68k/ieee.opt index 24144072734..78428e9cb4b 100644 --- a/gcc/config/m68k/ieee.opt +++ b/gcc/config/m68k/ieee.opt @@ -1,6 +1,6 @@ ; Extra IEEE options for the Motorola 68000 port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/m68k/linux.h b/gcc/config/m68k/linux.h index 5c19d842a39..7a9e9344481 100644 --- a/gcc/config/m68k/linux.h +++ b/gcc/config/m68k/linux.h @@ -1,6 +1,6 @@ /* Definitions for Motorola 68k running Linux-based GNU systems with ELF format. - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68020-elf.h b/gcc/config/m68k/m68020-elf.h index 52fea946952..582fdd6a1e8 100644 --- a/gcc/config/m68k/m68020-elf.h +++ b/gcc/config/m68k/m68020-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. "naked" 68020, elf object files and debugging, version. - Copyright (C) 1987-2015 Free Software Foundation, Inc. + Copyright (C) 1987-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k-devices.def b/gcc/config/m68k/m68k-devices.def index 2134adb01f0..7d7d6670268 100644 --- a/gcc/config/m68k/m68k-devices.def +++ b/gcc/config/m68k/m68k-devices.def @@ -1,5 +1,5 @@ /* m68k device names -*- C -*- - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. Written by CodeSourcery This file is part of GCC. diff --git a/gcc/config/m68k/m68k-isas.def b/gcc/config/m68k/m68k-isas.def index 96100094bad..69369f2f840 100644 --- a/gcc/config/m68k/m68k-isas.def +++ b/gcc/config/m68k/m68k-isas.def @@ -1,5 +1,5 @@ /* m68k ISA names. - Copyright (C) 1987-2015 Free Software Foundation, Inc. + Copyright (C) 1987-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k-microarchs.def b/gcc/config/m68k/m68k-microarchs.def index 6d483310a95..c8998a7389e 100644 --- a/gcc/config/m68k/m68k-microarchs.def +++ b/gcc/config/m68k/m68k-microarchs.def @@ -1,5 +1,5 @@ /* m68k microarchitecture names. - Copyright (C) 1987-2015 Free Software Foundation, Inc. + Copyright (C) 1987-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k-modes.def b/gcc/config/m68k/m68k-modes.def index 3531de1a7e6..5d8a3b06293 100644 --- a/gcc/config/m68k/m68k-modes.def +++ b/gcc/config/m68k/m68k-modes.def @@ -1,5 +1,5 @@ /* M68k extra machine modes. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k-none.h b/gcc/config/m68k/m68k-none.h index 8cd245b521d..8dfc8c089bb 100644 --- a/gcc/config/m68k/m68k-none.h +++ b/gcc/config/m68k/m68k-none.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. "naked" 68020. - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k-opts.h b/gcc/config/m68k/m68k-opts.h index 31b9aa600ba..2bd57b9184a 100644 --- a/gcc/config/m68k/m68k-opts.h +++ b/gcc/config/m68k/m68k-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for Motorola 680x0/ColdFire. - Copyright (C) 1987-2015 Free Software Foundation, Inc. + Copyright (C) 1987-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k-protos.h b/gcc/config/m68k/m68k-protos.h index 4056cb6fee0..d6b81574e67 100644 --- a/gcc/config/m68k/m68k-protos.h +++ b/gcc/config/m68k/m68k-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. Sun 68000/68020 version. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k-tables.opt b/gcc/config/m68k/m68k-tables.opt index ff1ed32d324..414252a42ee 100644 --- a/gcc/config/m68k/m68k-tables.opt +++ b/gcc/config/m68k/m68k-tables.opt @@ -2,7 +2,7 @@ ; Generated automatically by genopt.sh from m68k-devices.def, ; m68k-isas.def and m68k-microarchs.def. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index 7a768d45c30..03f474e1b63 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for Motorola 68000 family. - Copyright (C) 1987-2015 Free Software Foundation, Inc. + Copyright (C) 1987-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h index b227c675226..2aa858fa23b 100644 --- a/gcc/config/m68k/m68k.h +++ b/gcc/config/m68k/m68k.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC for Motorola 680x0/ColdFire. - Copyright (C) 1987-2015 Free Software Foundation, Inc. + Copyright (C) 1987-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 444515aea68..5731780631f 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -1,5 +1,5 @@ ;;- Machine description for GNU compiler, Motorola 68000 Version -;; Copyright (C) 1987-2015 Free Software Foundation, Inc. +;; Copyright (C) 1987-2016 Free Software Foundation, Inc. ;; This file is part of GCC. @@ -7634,3 +7634,88 @@ (set (mem:QI (match_dup 5)) (const_int 0))] "operands[5] = (operands[0] == operands[3]) ? operands[4] : operands[3];") + +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "pow2_m1_operand" "")) + (set (cc0) (compare (match_operand:SI 2 "register_operand" "") + (match_operand:SI 3 "register_operand" ""))) + (set (pc) (if_then_else (gtu (cc0) (const_int 0)) + (match_operand 4 "pc_or_label_operand") + (match_operand 5 "pc_or_label_operand")))] + "INTVAL (operands[1]) <= 255 + && operands[0] == operands[3] + && peep2_reg_dead_p (2, operands[0]) + && peep2_reg_dead_p (2, operands[2]) + && (operands[4] == pc_rtx || operands[5] == pc_rtx) + && (optimize_size || TUNE_68040_60) + && DATA_REG_P (operands[2])" + [(set (match_dup 7) (lshiftrt:SI (match_dup 7) (match_dup 6))) + (set (cc0) (compare (match_dup 7) (const_int 0))) + (set (pc) (if_then_else (ne (cc0) (const_int 0)) + (match_dup 4) (match_dup 5)))] + " +{ + operands[6] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); + operands[7] = operands[2]; +}") + +(define_peephole2 + [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "pow2_m1_operand" ""))) + (set (pc) (if_then_else (gtu (cc0) (const_int 0)) + (match_operand 2 "pc_or_label_operand") + (match_operand 3 "pc_or_label_operand")))] + "INTVAL (operands[1]) <= 255 + && peep2_reg_dead_p (1, operands[0]) + && (operands[2] == pc_rtx || operands[3] == pc_rtx) + && (optimize_size || TUNE_68040_60) + && DATA_REG_P (operands[0])" + [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 4))) + (set (cc0) (compare (match_dup 0) (const_int 0))) + (set (pc) (if_then_else (ne (cc0) (const_int 0)) + (match_dup 2) (match_dup 3)))] + "{ operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); }") + +(define_peephole2 + [(set (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "pow2_m1_operand" "")) + (set (cc0) (compare (match_operand:SI 2 "register_operand" "") + (match_operand:SI 3 "register_operand" ""))) + (set (pc) (if_then_else (leu (cc0) (const_int 0)) + (match_operand 4 "pc_or_label_operand") + (match_operand 5 "pc_or_label_operand")))] + "INTVAL (operands[1]) <= 255 + && operands[0] == operands[3] + && peep2_reg_dead_p (2, operands[0]) + && peep2_reg_dead_p (2, operands[2]) + && (operands[4] == pc_rtx || operands[5] == pc_rtx) + && (optimize_size || TUNE_68040_60) + && DATA_REG_P (operands[2])" + [(set (match_dup 7) (lshiftrt:SI (match_dup 7) (match_dup 6))) + (set (cc0) (compare (match_dup 7) (const_int 0))) + (set (pc) (if_then_else (eq (cc0) (const_int 0)) + (match_dup 4) (match_dup 5)))] + " +{ + operands[6] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); + operands[7] = operands[2]; +}") + +(define_peephole2 + [(set (cc0) (compare (match_operand:SI 0 "register_operand" "") + (match_operand:SI 1 "pow2_m1_operand" ""))) + (set (pc) (if_then_else (leu (cc0) (const_int 0)) + (match_operand 2 "pc_or_label_operand") + (match_operand 3 "pc_or_label_operand")))] + "INTVAL (operands[1]) <= 255 + && peep2_reg_dead_p (1, operands[0]) + && (operands[2] == pc_rtx || operands[3] == pc_rtx) + && (optimize_size || TUNE_68040_60) + && DATA_REG_P (operands[0])" + [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 4))) + (set (cc0) (compare (match_dup 0) (const_int 0))) + (set (pc) (if_then_else (eq (cc0) (const_int 0)) + (match_dup 2) (match_dup 3)))] + "{ operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); }") + diff --git a/gcc/config/m68k/m68k.opt b/gcc/config/m68k/m68k.opt index 46010e50046..e44539f2b7a 100644 --- a/gcc/config/m68k/m68k.opt +++ b/gcc/config/m68k/m68k.opt @@ -1,6 +1,6 @@ ; Options for the Motorola 68000 port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/m68k/m68kelf.h b/gcc/config/m68k/m68kelf.h index e06f40b91c5..f0196f00b5a 100644 --- a/gcc/config/m68k/m68kelf.h +++ b/gcc/config/m68k/m68kelf.h @@ -1,7 +1,7 @@ /* m68kelf support, derived from m68kv4.h */ /* Target definitions for GNU compiler for mc680x0 running System V.4 - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. Written by Ron Guilmette (rfg@netcom.com) and Fred Fish (fnf@cygnus.com). diff --git a/gcc/config/m68k/m68kemb.h b/gcc/config/m68k/m68kemb.h index d02ae5b3e29..0d8d88c74ea 100644 --- a/gcc/config/m68k/m68kemb.h +++ b/gcc/config/m68k/m68kemb.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. "embedded" 68XXX. This is meant to be included after m68k.h. - Copyright (C) 1994-2015 Free Software Foundation, Inc. */ + Copyright (C) 1994-2016 Free Software Foundation, Inc. */ /* Override the SVR4 ABI for this target. */ diff --git a/gcc/config/m68k/netbsd-elf.h b/gcc/config/m68k/netbsd-elf.h index a180667bf3d..46dc2e8e4ae 100644 --- a/gcc/config/m68k/netbsd-elf.h +++ b/gcc/config/m68k/netbsd-elf.h @@ -1,7 +1,7 @@ /* Definitions of target machine for GNU compiler, for m68k (including m68010) NetBSD platforms using the ELF object format. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Wasabi Systems. Inc. This file is derived from <m68k/m68kv4.h>, <m68k/m68kelf.h>, diff --git a/gcc/config/m68k/openbsd.h b/gcc/config/m68k/openbsd.h index 379ca85f567..b22a23cfa81 100644 --- a/gcc/config/m68k/openbsd.h +++ b/gcc/config/m68k/openbsd.h @@ -1,5 +1,5 @@ /* Configuration file for an m68k OpenBSD target. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/predicates.md b/gcc/config/m68k/predicates.md index c652f109128..186436c42b7 100644 --- a/gcc/config/m68k/predicates.md +++ b/gcc/config/m68k/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Motorola 68000. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -253,7 +253,17 @@ (define_predicate "reg_or_pow2_m1_operand" (match_code "reg,const_int") { - return (REG_P (op) - || (GET_CODE (op) == CONST_INT - && exact_log2 (INTVAL (op) + 1) >= 0)); + return (REG_P (op) || pow2_m1_operand (op, VOIDmode)); }) + +;; Used to detect a constant that is all ones in its lower bits. +(define_predicate "pow2_m1_operand" + (match_code "const_int") +{ + return (GET_CODE (op) == CONST_INT && exact_log2 (INTVAL (op) + 1) >= 0); +}) + +;; Used to detect valid targets for conditional branches +;; Used to detect (pc) or (label_ref) in some jumping patterns to cut down +(define_predicate "pc_or_label_operand" + (match_code "pc,label_ref")) diff --git a/gcc/config/m68k/print-sysroot-suffix.sh b/gcc/config/m68k/print-sysroot-suffix.sh index 06885fbf81b..1f6af3ba1f4 100644 --- a/gcc/config/m68k/print-sysroot-suffix.sh +++ b/gcc/config/m68k/print-sysroot-suffix.sh @@ -1,5 +1,5 @@ #!/bin/sh -# Copyright (C) 2006-2015 Free Software Foundation, Inc. +# Copyright (C) 2006-2016 Free Software Foundation, Inc. # This file is part of GCC. # GCC is free software; you can redistribute it and/or modify diff --git a/gcc/config/m68k/rtemself.h b/gcc/config/m68k/rtemself.h index 48e73805d63..73c4f772a88 100644 --- a/gcc/config/m68k/rtemself.h +++ b/gcc/config/m68k/rtemself.h @@ -1,6 +1,6 @@ /* Definitions for rtems targeting a Motorola m68k using elf. Copyright (C) 1999, 2000, 2002 National Research Council of Canada. - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. Contributed by Charles-Antoine Gauthier (charles.gauthier@nrc.ca). This file is part of GCC. diff --git a/gcc/config/m68k/sync.md b/gcc/config/m68k/sync.md index 4914bb5b880..bc94bbe96b4 100644 --- a/gcc/config/m68k/sync.md +++ b/gcc/config/m68k/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for m68k synchronization instructions. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/m68k/t-linux b/gcc/config/m68k/t-linux index 74386dacaf4..1343cdb17c2 100644 --- a/gcc/config/m68k/t-linux +++ b/gcc/config/m68k/t-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2008-2015 Free Software Foundation, Inc. +# Copyright (C) 2008-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/m68k/t-mlibs b/gcc/config/m68k/t-mlibs index 1f6c94b6a4c..1639d16fe58 100644 --- a/gcc/config/m68k/t-mlibs +++ b/gcc/config/m68k/t-mlibs @@ -1,6 +1,6 @@ # multilibs -*- mode:Makefile -*- # -# Copyright (C) 2007-2015 Free Software Foundation, Inc. +# Copyright (C) 2007-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/m68k/t-uclinux b/gcc/config/m68k/t-uclinux index 58b1c72ac8a..ce6f8ac271e 100644 --- a/gcc/config/m68k/t-uclinux +++ b/gcc/config/m68k/t-uclinux @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2015 Free Software Foundation, Inc. +# Copyright (C) 2003-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/m68k/uclinux.h b/gcc/config/m68k/uclinux.h index ef6a3a0f504..6f64aed8ef8 100644 --- a/gcc/config/m68k/uclinux.h +++ b/gcc/config/m68k/uclinux.h @@ -2,7 +2,7 @@ using ELF objects with special linker post-processing to produce FLAT executables. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/m68k/uclinux.opt b/gcc/config/m68k/uclinux.opt index 12e659b6b32..a91ae8def64 100644 --- a/gcc/config/m68k/uclinux.opt +++ b/gcc/config/m68k/uclinux.opt @@ -1,6 +1,6 @@ ; m68k/ColdFire uClinux options. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/mcore/constraints.md b/gcc/config/mcore/constraints.md index f845c8da620..a0ee44c8dd0 100644 --- a/gcc/config/mcore/constraints.md +++ b/gcc/config/mcore/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for the Motorola MCore -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/mcore/mcore-elf.h b/gcc/config/mcore/mcore-elf.h index 59900cbaa48..5af690416e7 100644 --- a/gcc/config/mcore/mcore-elf.h +++ b/gcc/config/mcore/mcore-elf.h @@ -1,5 +1,5 @@ /* Definitions of MCore target. - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. Contributed by Cygnus Solutions. This file is part of GCC. diff --git a/gcc/config/mcore/mcore-protos.h b/gcc/config/mcore/mcore-protos.h index cbb519aec71..abdf02bf7bb 100644 --- a/gcc/config/mcore/mcore-protos.h +++ b/gcc/config/mcore/mcore-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in mcore.c - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Nick Clifton (nickc@redhat.com) This file is part of GCC. diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c index d28f2b71ffc..c9d0506afd5 100644 --- a/gcc/config/mcore/mcore.c +++ b/gcc/config/mcore/mcore.c @@ -1,5 +1,5 @@ /* Output routines for Motorola MCore processor - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h index 21952d1bcfb..6e0e4a34364 100644 --- a/gcc/config/mcore/mcore.h +++ b/gcc/config/mcore/mcore.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for Motorola M*CORE Processor. - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md index 6e7b02590d5..7d64b01a098 100644 --- a/gcc/config/mcore/mcore.md +++ b/gcc/config/mcore/mcore.md @@ -1,5 +1,5 @@ ;; Machine description the Motorola MCore -;; Copyright (C) 1993-2015 Free Software Foundation, Inc. +;; Copyright (C) 1993-2016 Free Software Foundation, Inc. ;; Contributed by Motorola. ;; This file is part of GCC. diff --git a/gcc/config/mcore/mcore.opt b/gcc/config/mcore/mcore.opt index 396f689be3d..a358c885310 100644 --- a/gcc/config/mcore/mcore.opt +++ b/gcc/config/mcore/mcore.opt @@ -1,6 +1,6 @@ ; Options for the Motorola MCore port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/mcore/predicates.md b/gcc/config/mcore/predicates.md index 5311575c9d3..9e73bb9eb32 100644 --- a/gcc/config/mcore/predicates.md +++ b/gcc/config/mcore/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Motorola MCore. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mcore/t-mcore b/gcc/config/mcore/t-mcore index f9c0b6d048b..1888b2b5007 100644 --- a/gcc/config/mcore/t-mcore +++ b/gcc/config/mcore/t-mcore @@ -1,4 +1,4 @@ -# Copyright (C) 2000-2015 Free Software Foundation, Inc. +# Copyright (C) 2000-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mep/constraints.md b/gcc/config/mep/constraints.md index b74c96e1237..a17a1f3f67d 100644 --- a/gcc/config/mep/constraints.md +++ b/gcc/config/mep/constraints.md @@ -1,5 +1,5 @@ ;; Toshiba Media Processor Machine constraints -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mep/mep-c5.cpu b/gcc/config/mep/mep-c5.cpu index 56525f358ba..865f1147434 100644 --- a/gcc/config/mep/mep-c5.cpu +++ b/gcc/config/mep/mep-c5.cpu @@ -1,5 +1,5 @@ ; Toshiba MeP C5 Core description. -*- scheme -*- -; Copyright (C) 2009-2015 Free Software Foundation, Inc. +; Copyright (C) 2009-2016 Free Software Foundation, Inc. ; Contributed by Red Hat, Inc. ; ; This file is part of GCC. diff --git a/gcc/config/mep/mep-core.cpu b/gcc/config/mep/mep-core.cpu index 826a63cc0fb..ef711882aad 100644 --- a/gcc/config/mep/mep-core.cpu +++ b/gcc/config/mep/mep-core.cpu @@ -1,5 +1,5 @@ ; Toshiba MeP Media Engine architecture description. -*- Scheme -*- -; Copyright (C) 2001-2015 Free Software Foundation, Inc. +; Copyright (C) 2001-2016 Free Software Foundation, Inc. ; Contributed by Red Hat, Inc. ; ; This file is part of GCC. diff --git a/gcc/config/mep/mep-default.cpu b/gcc/config/mep/mep-default.cpu index 9776c788233..f86445a552b 100644 --- a/gcc/config/mep/mep-default.cpu +++ b/gcc/config/mep/mep-default.cpu @@ -1,5 +1,5 @@ ; Toshiba MeP Media Engine architecture description. -*- Scheme -*- -; Copyright (C) 2001-2015 Free Software Foundation, Inc. +; Copyright (C) 2001-2016 Free Software Foundation, Inc. ; Contributed by Red Hat, Inc. ; ; This file is part of GCC. diff --git a/gcc/config/mep/mep-ext-cop.cpu b/gcc/config/mep/mep-ext-cop.cpu index f70d0e6fe5e..592d429ee6f 100644 --- a/gcc/config/mep/mep-ext-cop.cpu +++ b/gcc/config/mep/mep-ext-cop.cpu @@ -1,5 +1,5 @@ ; Toshiba MeP IVC2 Coprocessor description. -*- scheme -*- -; Copyright (C) 2003-2015 Free Software Foundation, Inc. +; Copyright (C) 2003-2016 Free Software Foundation, Inc. ; Contributed by Red Hat, Inc. ; ; This file is part of GCC. diff --git a/gcc/config/mep/mep-ivc2.cpu b/gcc/config/mep/mep-ivc2.cpu index 5ba204438e8..24966a6d7e7 100644 --- a/gcc/config/mep/mep-ivc2.cpu +++ b/gcc/config/mep/mep-ivc2.cpu @@ -1,5 +1,5 @@ ; Toshiba MeP IVC2 Coprocessor description. -*- scheme -*- -; Copyright (C) 2001-2015 Free Software Foundation, Inc. +; Copyright (C) 2001-2016 Free Software Foundation, Inc. ; Contributed by Red Hat, Inc. ; ; This file is part of GCC. diff --git a/gcc/config/mep/mep-pragma.c b/gcc/config/mep/mep-pragma.c index 95908d5bd38..bddce9f71a1 100644 --- a/gcc/config/mep/mep-pragma.c +++ b/gcc/config/mep/mep-pragma.c @@ -1,5 +1,5 @@ /* Definitions of Toshiba Media Processor - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/mep/mep-protos.h b/gcc/config/mep/mep-protos.h index b8706d8f0c6..b3828b99d75 100644 --- a/gcc/config/mep/mep-protos.h +++ b/gcc/config/mep/mep-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in mep.c - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Red Hat Inc (dj@redhat.com) This file is part of GCC. diff --git a/gcc/config/mep/mep.c b/gcc/config/mep/mep.c index 5ab56bd1c64..9c4cd860ac2 100644 --- a/gcc/config/mep/mep.c +++ b/gcc/config/mep/mep.c @@ -1,5 +1,5 @@ /* Definitions for Toshiba Media Processor - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/mep/mep.cpu b/gcc/config/mep/mep.cpu index 33053947e41..cedbdf44602 100644 --- a/gcc/config/mep/mep.cpu +++ b/gcc/config/mep/mep.cpu @@ -1,5 +1,5 @@ ; Toshiba MeP Media Engine description. -*- Scheme -*- -; Copyright (C) 2009-2015 Free Software Foundation, Inc. +; Copyright (C) 2009-2016 Free Software Foundation, Inc. ; Contributed by Red Hat, Inc. ; ; This file is part of GCC. diff --git a/gcc/config/mep/mep.h b/gcc/config/mep/mep.h index 4d335b05adf..e5508048ef9 100644 --- a/gcc/config/mep/mep.h +++ b/gcc/config/mep/mep.h @@ -1,5 +1,5 @@ /* Definitions for Toshiba Media Processor - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/mep/mep.md b/gcc/config/mep/mep.md index bcaab563563..f5d21cf383f 100644 --- a/gcc/config/mep/mep.md +++ b/gcc/config/mep/mep.md @@ -1,5 +1,5 @@ ;; Toshiba Media Processor Machine description template -;; Copyright (C) 2001-2015 Free Software Foundation, Inc. +;; Copyright (C) 2001-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat Inc ;; ;; This file is part of GCC. diff --git a/gcc/config/mep/mep.opt b/gcc/config/mep/mep.opt index 64864419e92..e089d152f46 100644 --- a/gcc/config/mep/mep.opt +++ b/gcc/config/mep/mep.opt @@ -1,5 +1,5 @@ ; Target specific command line options for the MEP port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; Contributed by Red Hat Inc. ; ; GCC is free software; you can redistribute it and/or modify it under diff --git a/gcc/config/mep/predicates.md b/gcc/config/mep/predicates.md index 22802ecd1e3..24972e01f49 100644 --- a/gcc/config/mep/predicates.md +++ b/gcc/config/mep/predicates.md @@ -1,5 +1,5 @@ ;; Toshiba Media Processor Machine predicates -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat Inc. ;; This file is part of GCC. diff --git a/gcc/config/mep/t-mep b/gcc/config/mep/t-mep index 8b70a9dd76b..dd0742fbc60 100644 --- a/gcc/config/mep/t-mep +++ b/gcc/config/mep/t-mep @@ -1,6 +1,6 @@ # -*- makefile -*- # GCC makefile fragment for MeP -# Copyright (C) 2001-2015 Free Software Foundation, Inc. +# Copyright (C) 2001-2016 Free Software Foundation, Inc. # Contributed by Red Hat Inc # # This file is part of GCC. diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md index 5dd04ea3025..fea67c695bc 100644 --- a/gcc/config/microblaze/constraints.md +++ b/gcc/config/microblaze/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Xilinx MicroBlaze processors. -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Michael Eager <eager@eagercon.com>. diff --git a/gcc/config/microblaze/linux.h b/gcc/config/microblaze/linux.h index a8a3f3e3bd7..ae8523c19c3 100644 --- a/gcc/config/microblaze/linux.h +++ b/gcc/config/microblaze/linux.h @@ -1,5 +1,5 @@ /* Definitions for MicroBlaze running Linux. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c index b596cbfc300..69af960760d 100644 --- a/gcc/config/microblaze/microblaze-c.c +++ b/gcc/config/microblaze/microblaze-c.c @@ -1,5 +1,5 @@ /* Subroutines used for the C front end for Xilinx MicroBlaze. - Copyright (C) 2010-2015 Free Software Foundation, Inc. + Copyright (C) 2010-2016 Free Software Foundation, Inc. Contributed by Michael Eager <eager@eagercon.com>. diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h index 3ece34e086f..1cfaf08c1c6 100644 --- a/gcc/config/microblaze/microblaze-protos.h +++ b/gcc/config/microblaze/microblaze-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for Xilinx MicroBlaze. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c index aebbc3b0380..4e778e7d762 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on Xilinx MicroBlaze. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by Michael Eager <eager@eagercon.com>. diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h index 482c4a25d20..e115c42839b 100644 --- a/gcc/config/microblaze/microblaze.h +++ b/gcc/config/microblaze/microblaze.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for Xilinx MicroBlaze. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by Michael Eager <eager@eagercon.com>. diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md index 596968d5b56..287c5c97a99 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -1,5 +1,5 @@ ;; microblaze.md -- Machine description for Xilinx MicroBlaze processors. -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by Michael Eager <eager@eagercon.com>. diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt index 360a8d57e5b..039ae96c850 100644 --- a/gcc/config/microblaze/microblaze.opt +++ b/gcc/config/microblaze/microblaze.opt @@ -1,6 +1,6 @@ ; Options for the MicroBlaze port of the compiler ; -; Copyright (C) 2009-2015 Free Software Foundation, Inc. +; Copyright (C) 2009-2016 Free Software Foundation, Inc. ; ; Contributed by Michael Eager <eager@eagercon.com>. ; diff --git a/gcc/config/microblaze/predicates.md b/gcc/config/microblaze/predicates.md index dadf6486961..2dbb5fa8f07 100644 --- a/gcc/config/microblaze/predicates.md +++ b/gcc/config/microblaze/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Xilinx MicroBlaze -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; ;; Contributed by Michael Eager <eager@eagercon.com>. ;; diff --git a/gcc/config/microblaze/rtems.h b/gcc/config/microblaze/rtems.h index c8d42db045e..68aa381b370 100644 --- a/gcc/config/microblaze/rtems.h +++ b/gcc/config/microblaze/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a microblaze using ELF. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md index 9de24f1a901..f944fca9c74 100644 --- a/gcc/config/microblaze/sync.md +++ b/gcc/config/microblaze/sync.md @@ -1,5 +1,5 @@ ;; Machine description for Xilinx MicroBlaze synchronization instructions. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/10000.md b/gcc/config/mips/10000.md index 975d149742d..a2d2664c74a 100644 --- a/gcc/config/mips/10000.md +++ b/gcc/config/mips/10000.md @@ -1,5 +1,5 @@ ;; DFA-based pipeline description for the VR1x000. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/20kc.md b/gcc/config/mips/20kc.md index 2affa50a6a9..0a3db1fe5cc 100644 --- a/gcc/config/mips/20kc.md +++ b/gcc/config/mips/20kc.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/24k.md b/gcc/config/mips/24k.md index a8e27c60fab..b4148aef7fa 100644 --- a/gcc/config/mips/24k.md +++ b/gcc/config/mips/24k.md @@ -8,7 +8,7 @@ ;; References: ;; "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04." ;; -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/3000.md b/gcc/config/mips/3000.md index bfe6b511399..2bc10087c3f 100644 --- a/gcc/config/mips/3000.md +++ b/gcc/config/mips/3000.md @@ -1,5 +1,5 @@ ;; R3000 and TX39 pipeline description. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/4000.md b/gcc/config/mips/4000.md index dd1ac8f6dc4..e1ac02963ab 100644 --- a/gcc/config/mips/4000.md +++ b/gcc/config/mips/4000.md @@ -1,5 +1,5 @@ ;; R4000 pipeline description. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/4100.md b/gcc/config/mips/4100.md index 7160edd848a..ad93a9832bb 100644 --- a/gcc/config/mips/4100.md +++ b/gcc/config/mips/4100.md @@ -1,5 +1,5 @@ ;; VR4100 and VR4120 pipeline description. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/4130.md b/gcc/config/mips/4130.md index 78bf504c098..ce6be200f9c 100644 --- a/gcc/config/mips/4130.md +++ b/gcc/config/mips/4130.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/4300.md b/gcc/config/mips/4300.md index b377450b260..a0708357de4 100644 --- a/gcc/config/mips/4300.md +++ b/gcc/config/mips/4300.md @@ -1,5 +1,5 @@ ;; VR4300 pipeline description. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/4600.md b/gcc/config/mips/4600.md index f9601a3ba6f..1d934b7f125 100644 --- a/gcc/config/mips/4600.md +++ b/gcc/config/mips/4600.md @@ -1,5 +1,5 @@ ;; R4600, R4650, and R4700 pipeline description. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/4k.md b/gcc/config/mips/4k.md index ab936701e2f..4baa09a8ab2 100644 --- a/gcc/config/mips/4k.md +++ b/gcc/config/mips/4k.md @@ -10,7 +10,7 @@ ;; 4km - pipelined multiplier and block address translator (BAT) ;; 4kp - non-pipelined multiplier and block address translator (BAT) ;; -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/5000.md b/gcc/config/mips/5000.md index 573331251b3..b4f75bf292a 100644 --- a/gcc/config/mips/5000.md +++ b/gcc/config/mips/5000.md @@ -1,5 +1,5 @@ ;; VR5000 pipeline description. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/5400.md b/gcc/config/mips/5400.md index 6f929c908e6..116cbcd6455 100644 --- a/gcc/config/mips/5400.md +++ b/gcc/config/mips/5400.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/5500.md b/gcc/config/mips/5500.md index 583948d0816..851d7f742cc 100644 --- a/gcc/config/mips/5500.md +++ b/gcc/config/mips/5500.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/5k.md b/gcc/config/mips/5k.md index 65eeaef7061..352fc05e72c 100644 --- a/gcc/config/mips/5k.md +++ b/gcc/config/mips/5k.md @@ -10,7 +10,7 @@ ;; 5kf - Separate floating point pipe which can dual-issue with the ;; integer pipe. ;; -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/6000.md b/gcc/config/mips/6000.md index 8fd09db81e5..551e2b4c0f0 100644 --- a/gcc/config/mips/6000.md +++ b/gcc/config/mips/6000.md @@ -1,5 +1,5 @@ ;; R6000 pipeline description. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/7000.md b/gcc/config/mips/7000.md index 27b976467c2..37f06e3b23f 100644 --- a/gcc/config/mips/7000.md +++ b/gcc/config/mips/7000.md @@ -1,5 +1,5 @@ ;; DFA-based pipeline description for the RM7000. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/74k.md b/gcc/config/mips/74k.md index 11c3340e5a1..b07d870e839 100644 --- a/gcc/config/mips/74k.md +++ b/gcc/config/mips/74k.md @@ -5,7 +5,7 @@ ;; "MIPS32 74K Microarchitecure Specification Rev. 01.02 Jun 15, 2006" ;; "MIPS32 74Kf Processor Core Datasheet Jun 2, 2006" ;; -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/9000.md b/gcc/config/mips/9000.md index ae252ad18ec..cdace4faf84 100644 --- a/gcc/config/mips/9000.md +++ b/gcc/config/mips/9000.md @@ -1,5 +1,5 @@ ;; DFA-based pipeline description for the RM9000. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md index 7d1a8baeaaa..133e346a8fc 100644 --- a/gcc/config/mips/constraints.md +++ b/gcc/config/mips/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for MIPS. -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/driver-native.c b/gcc/config/mips/driver-native.c index 8983dab16bc..7cc01f009b1 100644 --- a/gcc/config/mips/driver-native.c +++ b/gcc/config/mips/driver-native.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/elf.h b/gcc/config/mips/elf.h index e3562aab790..4094d2a35e5 100644 --- a/gcc/config/mips/elf.h +++ b/gcc/config/mips/elf.h @@ -1,5 +1,5 @@ /* Target macros for mips*-elf targets. - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/elfoabi.h b/gcc/config/mips/elfoabi.h index 695bf418206..334191ec993 100644 --- a/gcc/config/mips/elfoabi.h +++ b/gcc/config/mips/elfoabi.h @@ -1,6 +1,6 @@ /* Target macros for mips*-elf targets that selected between o32 and o64 based on the target architecture. - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/elforion.h b/gcc/config/mips/elforion.h index 7cbe6f55d66..154652b0e89 100644 --- a/gcc/config/mips/elforion.h +++ b/gcc/config/mips/elforion.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. MIPS ORION version. - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/frame-header-opt.c b/gcc/config/mips/frame-header-opt.c index b80aa4db032..cc51577751b 100644 --- a/gcc/config/mips/frame-header-opt.c +++ b/gcc/config/mips/frame-header-opt.c @@ -4,7 +4,7 @@ targets, if a frame header is required, it is allocated by the callee. - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/generic.md b/gcc/config/mips/generic.md index ce2a72f8ec5..b25613127ac 100644 --- a/gcc/config/mips/generic.md +++ b/gcc/config/mips/generic.md @@ -1,5 +1,5 @@ ;; Generic DFA-based pipeline description for MIPS targets -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/genopt.sh b/gcc/config/mips/genopt.sh index 75f57631720..e11c5cfe0f0 100755 --- a/gcc/config/mips/genopt.sh +++ b/gcc/config/mips/genopt.sh @@ -1,6 +1,6 @@ #!/bin/sh # Generate mips-tables.opt from the list of CPUs in mips-cpus.def. -# Copyright (C) 2011-2015 Free Software Foundation, Inc. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -22,7 +22,7 @@ cat <<EOF ; -*- buffer-read-only: t -*- ; Generated automatically by genopt.sh from mips-cpus.def. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/mips/gnu-user.h b/gcc/config/mips/gnu-user.h index dd4cf11377e..15b549c087c 100644 --- a/gcc/config/mips/gnu-user.h +++ b/gcc/config/mips/gnu-user.h @@ -1,5 +1,5 @@ /* Definitions for MIPS systems using GNU userspace. - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/i6400.md b/gcc/config/mips/i6400.md index a32086f65b7..0f8230d6426 100644 --- a/gcc/config/mips/i6400.md +++ b/gcc/config/mips/i6400.md @@ -1,6 +1,6 @@ ;; DFA-based pipeline description for I6400. ;; -;; Copyright (C) 2015 Free Software Foundation, Inc. +;; Copyright (C) 2015-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/linux-common.h b/gcc/config/mips/linux-common.h index d98ffa4eb07..8429a7ca2fb 100644 --- a/gcc/config/mips/linux-common.h +++ b/gcc/config/mips/linux-common.h @@ -1,5 +1,5 @@ /* Definitions for MIPS running Linux-based GNU systems with ELF format. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h index fb358e25ff0..fa253b65313 100644 --- a/gcc/config/mips/linux.h +++ b/gcc/config/mips/linux.h @@ -1,5 +1,5 @@ /* Definitions for MIPS running Linux-based GNU systems with ELF format. - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/loongson.h b/gcc/config/mips/loongson.h index af84bfb828e..543ae546c37 100644 --- a/gcc/config/mips/loongson.h +++ b/gcc/config/mips/loongson.h @@ -1,6 +1,6 @@ /* Intrinsics for ST Microelectronics Loongson-2E/2F SIMD operations. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. Contributed by CodeSourcery. This file is part of GCC. diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson.md index b8489ab5ab9..4bd2926a574 100644 --- a/gcc/config/mips/loongson.md +++ b/gcc/config/mips/loongson.md @@ -1,6 +1,6 @@ ;; Machine description for Loongson-specific patterns, such as ;; ST Microelectronics Loongson-2E/2F etc. -;; Copyright (C) 2008-2015 Free Software Foundation, Inc. +;; Copyright (C) 2008-2016 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; ;; This file is part of GCC. diff --git a/gcc/config/mips/loongson2ef.md b/gcc/config/mips/loongson2ef.md index 95167e8f166..18a443cc717 100644 --- a/gcc/config/mips/loongson2ef.md +++ b/gcc/config/mips/loongson2ef.md @@ -1,6 +1,6 @@ ;; Pipeline model for ST Microelectronics Loongson-2E/2F cores. -;; Copyright (C) 2008-2015 Free Software Foundation, Inc. +;; Copyright (C) 2008-2016 Free Software Foundation, Inc. ;; Contributed by CodeSourcery. ;; ;; GCC is free software; you can redistribute it and/or modify diff --git a/gcc/config/mips/loongson3a.md b/gcc/config/mips/loongson3a.md index 06f7b283f30..2b136c27928 100644 --- a/gcc/config/mips/loongson3a.md +++ b/gcc/config/mips/loongson3a.md @@ -1,6 +1,6 @@ ;; Pipeline model for Loongson-3A cores. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/m5100.md b/gcc/config/mips/m5100.md index f860eb211f8..f69fc7fc609 100644 --- a/gcc/config/mips/m5100.md +++ b/gcc/config/mips/m5100.md @@ -1,6 +1,6 @@ ;; DFA-based pipeline description for MIPS32 models M5100. ;; -;; Copyright (C) 2015 Free Software Foundation, Inc. +;; Copyright (C) 2015-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/micromips.md b/gcc/config/mips/micromips.md index ef9920f4776..2104255e6e8 100644 --- a/gcc/config/mips/micromips.md +++ b/gcc/config/mips/micromips.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2013-2015 Free Software Foundation, Inc. +;; Copyright (C) 2013-2016 Free Software Foundation, Inc. ;; ;; micromips.md Machine Description for the microMIPS instruction set ;; This file is part of GCC. diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index e0c77f8f4c9..17034f2ea95 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -1,5 +1,5 @@ /* MIPS CPU names. - Copyright (C) 1989-2015 Free Software Foundation, Inc. + Copyright (C) 1989-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/mips-dsp.md b/gcc/config/mips/mips-dsp.md index a852b6d85f2..573e2a3f7a3 100644 --- a/gcc/config/mips/mips-dsp.md +++ b/gcc/config/mips/mips-dsp.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/mips-dspr2.md b/gcc/config/mips/mips-dspr2.md index 78b2f1fb3de..8c20c9a52e8 100644 --- a/gcc/config/mips/mips-dspr2.md +++ b/gcc/config/mips/mips-dspr2.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/mips-fixed.md b/gcc/config/mips/mips-fixed.md index 3d5bb060eed..0583e4277ad 100644 --- a/gcc/config/mips/mips-fixed.md +++ b/gcc/config/mips/mips-fixed.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/mips-ftypes.def b/gcc/config/mips/mips-ftypes.def index d56accc32e3..7fe1c06eb00 100644 --- a/gcc/config/mips/mips-ftypes.def +++ b/gcc/config/mips/mips-ftypes.def @@ -1,5 +1,5 @@ /* Definitions of prototypes for MIPS built-in functions. -*- C -*- - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -42,6 +42,7 @@ DEF_MIPS_FTYPE (3, (DI, DI, SI, SI)) DEF_MIPS_FTYPE (3, (DI, DI, USI, USI)) DEF_MIPS_FTYPE (3, (DI, DI, V2HI, V2HI)) DEF_MIPS_FTYPE (3, (DI, DI, V4QI, V4QI)) +DEF_MIPS_FTYPE (2, (DI, POINTER, SI)) DEF_MIPS_FTYPE (2, (DI, SI, SI)) DEF_MIPS_FTYPE (2, (DI, USI, USI)) @@ -50,9 +51,12 @@ DEF_MIPS_FTYPE (2, (INT, SF, SF)) DEF_MIPS_FTYPE (2, (INT, V2SF, V2SF)) DEF_MIPS_FTYPE (4, (INT, V2SF, V2SF, V2SF, V2SF)) +DEF_MIPS_FTYPE (1, (SF, SF)) +DEF_MIPS_FTYPE (2, (SF, SF, SF)) +DEF_MIPS_FTYPE (1, (SF, V2SF)) + DEF_MIPS_FTYPE (2, (SI, DI, SI)) DEF_MIPS_FTYPE (2, (SI, POINTER, SI)) -DEF_MIPS_FTYPE (2, (DI, POINTER, SI)) DEF_MIPS_FTYPE (1, (SI, SI)) DEF_MIPS_FTYPE (2, (SI, SI, SI)) DEF_MIPS_FTYPE (3, (SI, SI, SI, SI)) @@ -62,10 +66,6 @@ DEF_MIPS_FTYPE (1, (SI, V4QI)) DEF_MIPS_FTYPE (2, (SI, V4QI, V4QI)) DEF_MIPS_FTYPE (1, (SI, VOID)) -DEF_MIPS_FTYPE (1, (SF, SF)) -DEF_MIPS_FTYPE (2, (SF, SF, SF)) -DEF_MIPS_FTYPE (1, (SF, V2SF)) - DEF_MIPS_FTYPE (2, (UDI, UDI, UDI)) DEF_MIPS_FTYPE (2, (UDI, UV2SI, UV2SI)) @@ -76,9 +76,9 @@ DEF_MIPS_FTYPE (2, (UV2SI, UV2SI, UV2SI)) DEF_MIPS_FTYPE (2, (UV4HI, UV4HI, UQI)) DEF_MIPS_FTYPE (2, (UV4HI, UV4HI, USI)) +DEF_MIPS_FTYPE (2, (UV4HI, UV4HI, UV4HI)) DEF_MIPS_FTYPE (3, (UV4HI, UV4HI, UV4HI, UQI)) DEF_MIPS_FTYPE (3, (UV4HI, UV4HI, UV4HI, USI)) -DEF_MIPS_FTYPE (2, (UV4HI, UV4HI, UV4HI)) DEF_MIPS_FTYPE (1, (UV4HI, UV8QI)) DEF_MIPS_FTYPE (2, (UV4HI, UV8QI, UV8QI)) diff --git a/gcc/config/mips/mips-modes.def b/gcc/config/mips/mips-modes.def index b655eb15668..08d713243d9 100644 --- a/gcc/config/mips/mips-modes.def +++ b/gcc/config/mips/mips-modes.def @@ -1,5 +1,5 @@ /* MIPS extra machine modes. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/mips-opts.h b/gcc/config/mips/mips-opts.h index 3c2c6590e3d..40aa006bc4e 100644 --- a/gcc/config/mips/mips-opts.h +++ b/gcc/config/mips/mips-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for MIPS. - Copyright (C) 1989-2015 Free Software Foundation, Inc. + Copyright (C) 1989-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index 43774facdbe..01aad8295b3 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -1,5 +1,5 @@ /* Prototypes of target machine for GNU compiler. MIPS version. - Copyright (C) 1989-2015 Free Software Foundation, Inc. + Copyright (C) 1989-2016 Free Software Foundation, Inc. Contributed by A. Lichnewsky (lich@inria.inria.fr). Changed by Michael Meissner (meissner@osf.org). 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and diff --git a/gcc/config/mips/mips-ps-3d.md b/gcc/config/mips/mips-ps-3d.md index 8bc760879ae..3da85090da5 100644 --- a/gcc/config/mips/mips-ps-3d.md +++ b/gcc/config/mips/mips-ps-3d.md @@ -1,5 +1,5 @@ ;; MIPS Paired-Single Floating and MIPS-3D Instructions. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -371,13 +371,17 @@ [(set_attr "type" "fadd") (set_attr "mode" "SF")]) -(define_insn "reduc_splus_v2sf" - [(set (match_operand:V2SF 0 "register_operand" "=f") - (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") - (match_dup 1)] - UNSPEC_ADDR_PS))] +(define_expand "reduc_plus_scal_v2sf" + [(match_operand:SF 0 "register_operand" "=f") + (match_operand:V2SF 1 "register_operand" "f")] "TARGET_HARD_FLOAT && TARGET_MIPS3D" - "") + { + rtx temp = gen_reg_rtx (V2SFmode); + emit_insn (gen_mips_addr_ps (temp, operands[1], operands[1])); + rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; + emit_insn (gen_vec_extractv2sf (operands[0], temp, lane)); + DONE; + }) ; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word (define_insn "mips_cvt_pw_ps" @@ -745,20 +749,26 @@ DONE; }) -(define_expand "reduc_smin_v2sf" - [(match_operand:V2SF 0 "register_operand") +(define_expand "reduc_smin_scal_v2sf" + [(match_operand:SF 0 "register_operand") (match_operand:V2SF 1 "register_operand")] "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { - mips_expand_vec_reduc (operands[0], operands[1], gen_sminv2sf3); + rtx temp = gen_reg_rtx (V2SFmode); + mips_expand_vec_reduc (temp, operands[1], gen_sminv2sf3); + rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; + emit_insn (gen_vec_extractv2sf (operands[0], temp, lane)); DONE; }) -(define_expand "reduc_smax_v2sf" - [(match_operand:V2SF 0 "register_operand") +(define_expand "reduc_smax_scal_v2sf" + [(match_operand:SF 0 "register_operand") (match_operand:V2SF 1 "register_operand")] "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" { - mips_expand_vec_reduc (operands[0], operands[1], gen_smaxv2sf3); + rtx temp = gen_reg_rtx (V2SFmode); + mips_expand_vec_reduc (temp, operands[1], gen_smaxv2sf3); + rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; + emit_insn (gen_vec_extractv2sf (operands[0], temp, lane)); DONE; }) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index b2196f32413..34c12bd4444 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -1,7 +1,7 @@ ; -*- buffer-read-only: t -*- ; Generated automatically by genopt.sh from mips-cpus.def. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 7744d193337..ea18ad643e4 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -1,5 +1,5 @@ /* Subroutines used for MIPS code generation. - Copyright (C) 1989-2015 Free Software Foundation, Inc. + Copyright (C) 1989-2016 Free Software Foundation, Inc. Contributed by A. Lichnewsky, lich@inria.inria.fr. Changes by Michael Meissner, meissner@osf.org. 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 7a4a0ba59a0..803ab98e760 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. MIPS version. - Copyright (C) 1989-2015 Free Software Foundation, Inc. + Copyright (C) 1989-2016 Free Software Foundation, Inc. Contributed by A. Lichnewsky (lich@inria.inria.fr). Changed by Michael Meissner (meissner@osf.org). 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and @@ -1014,9 +1014,10 @@ struct mips_cpu_info { #define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4 /* ISA has paired-single instructions. */ -#define ISA_HAS_PAIRED_SINGLE (ISA_MIPS64 \ - || (mips_isa_rev >= 2 \ - && mips_isa_rev <= 5)) +#define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \ + || (mips_isa_rev >= 2 \ + && mips_isa_rev <= 5)) \ + && !TARGET_OCTEON) /* ISA has conditional trap instructions. */ #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index d24dcfeeefe..188308aae83 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1,5 +1,5 @@ ;; Mips.md Machine Description for MIPS based processors -;; Copyright (C) 1989-2015 Free Software Foundation, Inc. +;; Copyright (C) 1989-2016 Free Software Foundation, Inc. ;; Contributed by A. Lichnewsky, lich@inria.inria.fr ;; Changes by Michael Meissner, meissner@osf.org ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 53fca28b660..ebd67e4bdb9 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -1,6 +1,6 @@ ; Options for the MIPS port of the compiler ; -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/mips/mti-elf.h b/gcc/config/mips/mti-elf.h index 1075180983d..e804f6ab645 100644 --- a/gcc/config/mips/mti-elf.h +++ b/gcc/config/mips/mti-elf.h @@ -1,5 +1,5 @@ /* Target macros for mips*-mti-elf targets. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/mti-linux.h b/gcc/config/mips/mti-linux.h index b497625802a..d84ad1842b2 100644 --- a/gcc/config/mips/mti-linux.h +++ b/gcc/config/mips/mti-linux.h @@ -1,5 +1,5 @@ /* Target macros for mips*-mti-linux* targets. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/n32-elf.h b/gcc/config/mips/n32-elf.h index f450271e925..73b232deaaa 100644 --- a/gcc/config/mips/n32-elf.h +++ b/gcc/config/mips/n32-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. n32 for embedded systems. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/netbsd.h b/gcc/config/mips/netbsd.h index 2d4b8f4a2ff..fcfd17ed037 100644 --- a/gcc/config/mips/netbsd.h +++ b/gcc/config/mips/netbsd.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for MIPS NetBSD systems. - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/octeon.md b/gcc/config/mips/octeon.md index 09c6cd976ee..75cdcb78601 100644 --- a/gcc/config/mips/octeon.md +++ b/gcc/config/mips/octeon.md @@ -1,5 +1,5 @@ ;; Octeon pipeline description. -;; Copyright (C) 2008-2015 Free Software Foundation, Inc. +;; Copyright (C) 2008-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/mips/p5600.md b/gcc/config/mips/p5600.md index b7e32878815..35e8749e8da 100644 --- a/gcc/config/mips/p5600.md +++ b/gcc/config/mips/p5600.md @@ -1,6 +1,6 @@ ;; DFA-based pipeline description for P5600. ;; -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/predicates.md b/gcc/config/mips/predicates.md index 3259232bb89..cbeace9d640 100644 --- a/gcc/config/mips/predicates.md +++ b/gcc/config/mips/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for MIPS. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/r3900.h b/gcc/config/mips/r3900.h index b2ee9ce6593..0c123064dda 100644 --- a/gcc/config/mips/r3900.h +++ b/gcc/config/mips/r3900.h @@ -1,7 +1,7 @@ /* Definitions of MIPS sub target machine for GNU compiler. Toshiba r3900. You should include mips.h after this. - Copyright (C) 1989-2015 Free Software Foundation, Inc. + Copyright (C) 1989-2016 Free Software Foundation, Inc. Contributed by Gavin Koch (gavin@cygnus.com). This file is part of GCC. diff --git a/gcc/config/mips/rtems.h b/gcc/config/mips/rtems.h index 1eba611de72..41b575a0bb4 100644 --- a/gcc/config/mips/rtems.h +++ b/gcc/config/mips/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a MIPS using ELF. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/mips/sb1.md b/gcc/config/mips/sb1.md index e8d1f1b2da8..dd863a5397d 100644 --- a/gcc/config/mips/sb1.md +++ b/gcc/config/mips/sb1.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/sde.h b/gcc/config/mips/sde.h index 3cb64b09656..4136f666ac4 100644 --- a/gcc/config/mips/sde.h +++ b/gcc/config/mips/sde.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. MIPS SDE version. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/sde.opt b/gcc/config/mips/sde.opt index 847231d9f0c..e3e07e9ee21 100644 --- a/gcc/config/mips/sde.opt +++ b/gcc/config/mips/sde.opt @@ -1,6 +1,6 @@ ; MIPS SDE options. ; -; Copyright (C) 2010-2015 Free Software Foundation, Inc. +; Copyright (C) 2010-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/mips/sdemtk.h b/gcc/config/mips/sdemtk.h index 6029f3971e2..ccc22f235fb 100644 --- a/gcc/config/mips/sdemtk.h +++ b/gcc/config/mips/sdemtk.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. MIPS SDE version, for use with the SDE C library rather than newlib. - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/sr71k.md b/gcc/config/mips/sr71k.md index 073b606026a..f4be95d011a 100644 --- a/gcc/config/mips/sr71k.md +++ b/gcc/config/mips/sr71k.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mips/st.h b/gcc/config/mips/st.h index cf7f6b58f1a..6f71a237739 100644 --- a/gcc/config/mips/st.h +++ b/gcc/config/mips/st.h @@ -1,5 +1,5 @@ /* ST 2e / 2f GNU/Linux Configuration. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/sync.md b/gcc/config/mips/sync.md index a4f8376441f..5da74ce9c69 100644 --- a/gcc/config/mips/sync.md +++ b/gcc/config/mips/sync.md @@ -1,6 +1,6 @@ ;; Machine Description for MIPS based processor synchronization ;; instructions. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/mips/t-elf b/gcc/config/mips/t-elf index fefaf898220..ce907e83991 100644 --- a/gcc/config/mips/t-elf +++ b/gcc/config/mips/t-elf @@ -1,4 +1,4 @@ -# Copyright (C) 1999-2015 Free Software Foundation, Inc. +# Copyright (C) 1999-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-img-elf b/gcc/config/mips/t-img-elf index 7e7b2d57e31..eca0a2e64da 100644 --- a/gcc/config/mips/t-img-elf +++ b/gcc/config/mips/t-img-elf @@ -1,4 +1,4 @@ -# Copyright (C) 2014-2015 Free Software Foundation, Inc. +# Copyright (C) 2014-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-img-linux b/gcc/config/mips/t-img-linux index 93d81920679..8a7e0411e4f 100644 --- a/gcc/config/mips/t-img-linux +++ b/gcc/config/mips/t-img-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2014-2015 Free Software Foundation, Inc. +# Copyright (C) 2014-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-isa3264 b/gcc/config/mips/t-isa3264 index dcd1e9dcc7d..edd2a3eb24e 100644 --- a/gcc/config/mips/t-isa3264 +++ b/gcc/config/mips/t-isa3264 @@ -1,4 +1,4 @@ -# Copyright (C) 2001-2015 Free Software Foundation, Inc. +# Copyright (C) 2001-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-linux64 b/gcc/config/mips/t-linux64 index 7e96406065f..16c8adf85ca 100644 --- a/gcc/config/mips/t-linux64 +++ b/gcc/config/mips/t-linux64 @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2015 Free Software Foundation, Inc. +# Copyright (C) 2003-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-mips b/gcc/config/mips/t-mips index a8938411420..330f8fa204d 100644 --- a/gcc/config/mips/t-mips +++ b/gcc/config/mips/t-mips @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-mti-elf b/gcc/config/mips/t-mti-elf index c0dcbf07e83..d997661f84d 100644 --- a/gcc/config/mips/t-mti-elf +++ b/gcc/config/mips/t-mti-elf @@ -1,4 +1,4 @@ -# Copyright (C) 2012-2015 Free Software Foundation, Inc. +# Copyright (C) 2012-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-mti-linux b/gcc/config/mips/t-mti-linux index 3dd7e71d862..67b88abbb22 100644 --- a/gcc/config/mips/t-mti-linux +++ b/gcc/config/mips/t-mti-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2012-2015 Free Software Foundation, Inc. +# Copyright (C) 2012-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-r3900 b/gcc/config/mips/t-r3900 index c73894b3829..df1eddf05de 100644 --- a/gcc/config/mips/t-r3900 +++ b/gcc/config/mips/t-r3900 @@ -1,4 +1,4 @@ -# Copyright (C) 1998-2015 Free Software Foundation, Inc. +# Copyright (C) 1998-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-rtems b/gcc/config/mips/t-rtems index 65ce695bd64..f5b92cfbaed 100644 --- a/gcc/config/mips/t-rtems +++ b/gcc/config/mips/t-rtems @@ -1,6 +1,6 @@ # Custom multilibs for RTEMS # -# Copyright (C) 2003-2015 Free Software Foundation, Inc. +# Copyright (C) 2003-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-sb1 b/gcc/config/mips/t-sb1 index 8ba9fb9dc5d..5102b7e581b 100644 --- a/gcc/config/mips/t-sb1 +++ b/gcc/config/mips/t-sb1 @@ -1,4 +1,4 @@ -# Copyright (C) 2006-2015 Free Software Foundation, Inc. +# Copyright (C) 2006-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-sde b/gcc/config/mips/t-sde index 93166836a9b..78985ea1766 100644 --- a/gcc/config/mips/t-sde +++ b/gcc/config/mips/t-sde @@ -1,4 +1,4 @@ -# Copyright (C) 2007-2015 Free Software Foundation, Inc. +# Copyright (C) 2007-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-sdemtk b/gcc/config/mips/t-sdemtk index 8d280898b52..58fe7a33ebc 100644 --- a/gcc/config/mips/t-sdemtk +++ b/gcc/config/mips/t-sdemtk @@ -1,4 +1,4 @@ -# Copyright (C) 2007-2015 Free Software Foundation, Inc. +# Copyright (C) 2007-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-sr71k b/gcc/config/mips/t-sr71k index 0c244a80927..acb73b9cc07 100644 --- a/gcc/config/mips/t-sr71k +++ b/gcc/config/mips/t-sr71k @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-st b/gcc/config/mips/t-st index 9f6a8816241..617ae516be0 100644 --- a/gcc/config/mips/t-st +++ b/gcc/config/mips/t-st @@ -1,4 +1,4 @@ -# Copyright (C) 2008-2015 Free Software Foundation, Inc. +# Copyright (C) 2008-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-vr b/gcc/config/mips/t-vr index 53a1a8a9bb9..93dd716e101 100644 --- a/gcc/config/mips/t-vr +++ b/gcc/config/mips/t-vr @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/t-vxworks b/gcc/config/mips/t-vxworks index 06d74e997ee..4cf851397e3 100644 --- a/gcc/config/mips/t-vxworks +++ b/gcc/config/mips/t-vxworks @@ -1,4 +1,4 @@ -# Copyright (C) 2003-2015 Free Software Foundation, Inc. +# Copyright (C) 2003-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mips/vr.h b/gcc/config/mips/vr.h index b9afd4747d5..e31086c9342 100644 --- a/gcc/config/mips/vr.h +++ b/gcc/config/mips/vr.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. NEC VR Series Processors - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/mips/vxworks.h b/gcc/config/mips/vxworks.h index 0fa40b0d7d6..d776eca8e6c 100644 --- a/gcc/config/mips/vxworks.h +++ b/gcc/config/mips/vxworks.h @@ -1,4 +1,4 @@ -/* Copyright (C) 1999-2015 Free Software Foundation, Inc. +/* Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mips/xlp.md b/gcc/config/mips/xlp.md index 6b9445fd4cf..0e54639f069 100644 --- a/gcc/config/mips/xlp.md +++ b/gcc/config/mips/xlp.md @@ -1,5 +1,5 @@ ;; DFA-based pipeline description for the XLP. -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; xlp.md Machine Description for the Broadcom XLP Microprocessor ;; This file is part of GCC. diff --git a/gcc/config/mips/xlr.md b/gcc/config/mips/xlr.md index b1dce741161..cdb2eca5541 100644 --- a/gcc/config/mips/xlr.md +++ b/gcc/config/mips/xlr.md @@ -1,5 +1,5 @@ ;; DFA-based pipeline description for the XLR. -;; Copyright (C) 2008-2015 Free Software Foundation, Inc. +;; Copyright (C) 2008-2016 Free Software Foundation, Inc. ;; ;; xlr.md Machine Description for the RMI XLR Microprocessor ;; This file is part of GCC. diff --git a/gcc/config/mmix/constraints.md b/gcc/config/mmix/constraints.md index f2721f7427f..8db520cdc59 100644 --- a/gcc/config/mmix/constraints.md +++ b/gcc/config/mmix/constraints.md @@ -1,5 +1,5 @@ ;; MMIX constraints -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mmix/mmix-modes.def b/gcc/config/mmix/mmix-modes.def index aa0a62a5c9a..841db9b7e49 100644 --- a/gcc/config/mmix/mmix-modes.def +++ b/gcc/config/mmix/mmix-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for MMIX. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Hans-Peter Nilsson (hp@bitrange.com) This file is part of GCC. diff --git a/gcc/config/mmix/mmix-protos.h b/gcc/config/mmix/mmix-protos.h index 9c089630e49..21e83ed1774 100644 --- a/gcc/config/mmix/mmix-protos.h +++ b/gcc/config/mmix/mmix-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in mmix.c - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Hans-Peter Nilsson (hp@bitrange.com) This file is part of GCC. diff --git a/gcc/config/mmix/mmix.c b/gcc/config/mmix/mmix.c index 4cafc02d2f3..3fffdc2e9af 100644 --- a/gcc/config/mmix/mmix.c +++ b/gcc/config/mmix/mmix.c @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for MMIX. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Hans-Peter Nilsson (hp@bitrange.com) This file is part of GCC. diff --git a/gcc/config/mmix/mmix.h b/gcc/config/mmix/mmix.h index d15d90e54a3..e2f24381328 100644 --- a/gcc/config/mmix/mmix.h +++ b/gcc/config/mmix/mmix.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for MMIX. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Hans-Peter Nilsson (hp@bitrange.com) This file is part of GCC. diff --git a/gcc/config/mmix/mmix.md b/gcc/config/mmix/mmix.md index 0b431e73ddc..9f4c6cb2a6d 100644 --- a/gcc/config/mmix/mmix.md +++ b/gcc/config/mmix/mmix.md @@ -1,5 +1,5 @@ ;; GCC machine description for MMIX -;; Copyright (C) 2000-2015 Free Software Foundation, Inc. +;; Copyright (C) 2000-2016 Free Software Foundation, Inc. ;; Contributed by Hans-Peter Nilsson (hp@bitrange.com) ;; This file is part of GCC. diff --git a/gcc/config/mmix/mmix.opt b/gcc/config/mmix/mmix.opt index 1093179f82a..04eea19291c 100644 --- a/gcc/config/mmix/mmix.opt +++ b/gcc/config/mmix/mmix.opt @@ -1,6 +1,6 @@ ; Options for the MMIX port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/mmix/predicates.md b/gcc/config/mmix/predicates.md index eb26cae2ae1..8e920c24a02 100644 --- a/gcc/config/mmix/predicates.md +++ b/gcc/config/mmix/predicates.md @@ -1,5 +1,5 @@ ;; Operand and operator predicates for the GCC MMIX port. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; This file is part of GCC. ;; diff --git a/gcc/config/mmix/t-mmix b/gcc/config/mmix/t-mmix index 863918946e3..e43ad65e4fa 100644 --- a/gcc/config/mmix/t-mmix +++ b/gcc/config/mmix/t-mmix @@ -1,4 +1,4 @@ -# Copyright (C) 2001-2015 Free Software Foundation, Inc. +# Copyright (C) 2001-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/mn10300/constraints.md b/gcc/config/mn10300/constraints.md index 0d4e9c5a46d..b93a29b3666 100644 --- a/gcc/config/mn10300/constraints.md +++ b/gcc/config/mn10300/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for the MN10300. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mn10300/linux.h b/gcc/config/mn10300/linux.h index e78f4a09f91..f43aee31aad 100644 --- a/gcc/config/mn10300/linux.h +++ b/gcc/config/mn10300/linux.h @@ -1,6 +1,6 @@ /* Definitions of taret machine for GNU compiler. Matsushita AM33/2.0 - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Alexandre Oliva <aoliva@redhat.com> This file is part of GCC. diff --git a/gcc/config/mn10300/mn10300-modes.def b/gcc/config/mn10300/mn10300-modes.def index f126ee48a05..00f31d9a65d 100644 --- a/gcc/config/mn10300/mn10300-modes.def +++ b/gcc/config/mn10300/mn10300-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for MN10300. - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. Contributed by Red Hat Inc. This file is part of GCC. diff --git a/gcc/config/mn10300/mn10300-opts.h b/gcc/config/mn10300/mn10300-opts.h index a8c0ef7963b..ac76d082324 100644 --- a/gcc/config/mn10300/mn10300-opts.h +++ b/gcc/config/mn10300/mn10300-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for Matsushita MN10300 series. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/mn10300/mn10300-protos.h b/gcc/config/mn10300/mn10300-protos.h index ecda6c76b9f..46f4a1f65ba 100644 --- a/gcc/config/mn10300/mn10300-protos.h +++ b/gcc/config/mn10300/mn10300-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. Matsushita MN10300 series - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Jeff Law (law@cygnus.com). This file is part of GCC. diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c index 2f191e416fe..71815d665c5 100644 --- a/gcc/config/mn10300/mn10300.c +++ b/gcc/config/mn10300/mn10300.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for Matsushita MN10300 series - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Jeff Law (law@cygnus.com). This file is part of GCC. diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h index dbedb18e40c..714c6a0f900 100644 --- a/gcc/config/mn10300/mn10300.h +++ b/gcc/config/mn10300/mn10300.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler. Matsushita MN10300 series - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Jeff Law (law@cygnus.com). This file is part of GCC. diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md index 7cd5306187a..decda0ea786 100644 --- a/gcc/config/mn10300/mn10300.md +++ b/gcc/config/mn10300/mn10300.md @@ -1,5 +1,5 @@ ;; GCC machine description for Matsushita MN10300 -;; Copyright (C) 1996-2015 Free Software Foundation, Inc. +;; Copyright (C) 1996-2016 Free Software Foundation, Inc. ;; Contributed by Jeff Law (law@cygnus.com). ;; This file is part of GCC. diff --git a/gcc/config/mn10300/mn10300.opt b/gcc/config/mn10300/mn10300.opt index 1ae07b0a832..8a577250522 100644 --- a/gcc/config/mn10300/mn10300.opt +++ b/gcc/config/mn10300/mn10300.opt @@ -1,6 +1,6 @@ ; Options for the Matsushita MN10300 port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/mn10300/predicates.md b/gcc/config/mn10300/predicates.md index 3e8d42f2f74..a5b8871d574 100644 --- a/gcc/config/mn10300/predicates.md +++ b/gcc/config/mn10300/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Matsushita MN10300. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/mn10300/t-mn10300 b/gcc/config/mn10300/t-mn10300 index 4da0938853a..e16bf373939 100644 --- a/gcc/config/mn10300/t-mn10300 +++ b/gcc/config/mn10300/t-mn10300 @@ -1,4 +1,4 @@ -# Copyright (C) 1996-2015 Free Software Foundation, Inc. +# Copyright (C) 1996-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/moxie/constraints.md b/gcc/config/moxie/constraints.md index 78451105cc4..58c8323db58 100644 --- a/gcc/config/moxie/constraints.md +++ b/gcc/config/moxie/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Moxie -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by Anthony Green <green@moxielogic.com> ;; This file is part of GCC. diff --git a/gcc/config/moxie/moxie-protos.h b/gcc/config/moxie/moxie-protos.h index cc452af6810..ff5f09784cb 100644 --- a/gcc/config/moxie/moxie-protos.h +++ b/gcc/config/moxie/moxie-protos.h @@ -1,5 +1,5 @@ /* Prototypes for moxie.c functions used in the md file & elsewhere. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/moxie/moxie.c b/gcc/config/moxie/moxie.c index 756e2f74e2d..4e38a57f828 100644 --- a/gcc/config/moxie/moxie.c +++ b/gcc/config/moxie/moxie.c @@ -1,5 +1,5 @@ /* Target Code for moxie - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. Contributed by Anthony Green. This file is part of GCC. diff --git a/gcc/config/moxie/moxie.h b/gcc/config/moxie/moxie.h index 1dc7a097ac8..b9cb38bf139 100644 --- a/gcc/config/moxie/moxie.h +++ b/gcc/config/moxie/moxie.h @@ -1,5 +1,5 @@ /* Target Definitions for moxie. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. Contributed by Anthony Green. This file is part of GCC. diff --git a/gcc/config/moxie/moxie.md b/gcc/config/moxie/moxie.md index d09f3b19e69..49f96c48c55 100644 --- a/gcc/config/moxie/moxie.md +++ b/gcc/config/moxie/moxie.md @@ -1,5 +1,5 @@ ;; Machine description for Moxie -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by Anthony Green <green@moxielogic.com> ;; This file is part of GCC. diff --git a/gcc/config/moxie/moxie.opt b/gcc/config/moxie/moxie.opt index 2fbc9c11460..0e371450cc4 100644 --- a/gcc/config/moxie/moxie.opt +++ b/gcc/config/moxie/moxie.opt @@ -1,6 +1,6 @@ ; Options for the moxie compiler port. -; Copyright (C) 2012-2015 Free Software Foundation, Inc. +; Copyright (C) 2012-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/moxie/moxiebox.h b/gcc/config/moxie/moxiebox.h index 4dfa5ec4987..f67bfd67d85 100644 --- a/gcc/config/moxie/moxiebox.h +++ b/gcc/config/moxie/moxiebox.h @@ -1,5 +1,5 @@ /* Definitions for the moxiebox. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by Anthony Green (green@moxielogic.com) This file is part of GCC. diff --git a/gcc/config/moxie/predicates.md b/gcc/config/moxie/predicates.md index 2f28206608f..d109e8201fb 100644 --- a/gcc/config/moxie/predicates.md +++ b/gcc/config/moxie/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Moxie -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by Anthony Green <green@moxielogic.com> ;; This file is part of GCC. diff --git a/gcc/config/moxie/rtems.h b/gcc/config/moxie/rtems.h index b24779914aa..3e723e88138 100644 --- a/gcc/config/moxie/rtems.h +++ b/gcc/config/moxie/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting the Moxie core. - Copyright (C) 2010-2015 Free Software Foundation, Inc. + Copyright (C) 2010-2016 Free Software Foundation, Inc. Contributed by Anthony Green (green@moxielogic.com) This file is part of GCC. diff --git a/gcc/config/moxie/t-moxie b/gcc/config/moxie/t-moxie index 44a592dfd09..dc37ea7975a 100644 --- a/gcc/config/moxie/t-moxie +++ b/gcc/config/moxie/t-moxie @@ -1,5 +1,5 @@ # Target Makefile Fragment for moxie -# Copyright (C) 2008-2015 Free Software Foundation, Inc. +# Copyright (C) 2008-2016 Free Software Foundation, Inc. # Contributed by Anthony Green. # # This file is part of GCC. diff --git a/gcc/config/moxie/uclinux.h b/gcc/config/moxie/uclinux.h index 0f9bd4b00a6..f10d229a5a8 100644 --- a/gcc/config/moxie/uclinux.h +++ b/gcc/config/moxie/uclinux.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2009-2015 Free Software Foundation, Inc. +/* Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/msp430/constraints.md b/gcc/config/msp430/constraints.md index dfda1528a04..7e3e30ff83f 100644 --- a/gcc/config/msp430/constraints.md +++ b/gcc/config/msp430/constraints.md @@ -1,5 +1,5 @@ ;; Machine Description for TI MSP43* processors -;; Copyright (C) 2013-2015 Free Software Foundation, Inc. +;; Copyright (C) 2013-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/msp430/driver-msp430.c b/gcc/config/msp430/driver-msp430.c index 0557aac5e97..69b7a73f028 100644 --- a/gcc/config/msp430/driver-msp430.c +++ b/gcc/config/msp430/driver-msp430.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. Contributed by Georg-Johann Lay <avr@gjlay.de> This file is part of GCC. diff --git a/gcc/config/msp430/msp430-c.c b/gcc/config/msp430/msp430-c.c index d2ca1491568..ea241d4896f 100644 --- a/gcc/config/msp430/msp430-c.c +++ b/gcc/config/msp430/msp430-c.c @@ -1,5 +1,5 @@ /* MSP430 C-specific support - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/msp430/msp430-opts.h b/gcc/config/msp430/msp430-opts.h index 258dccbd29c..d009d10de50 100644 --- a/gcc/config/msp430/msp430-opts.h +++ b/gcc/config/msp430/msp430-opts.h @@ -1,5 +1,5 @@ /* GCC option-handling definitions for the TI MSP430 - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/msp430/msp430-protos.h b/gcc/config/msp430/msp430-protos.h index b4fd58721f3..862a8919f9b 100644 --- a/gcc/config/msp430/msp430-protos.h +++ b/gcc/config/msp430/msp430-protos.h @@ -1,5 +1,5 @@ /* Exported function prototypes from the TI MSP430 backend. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c index 88301c808ea..182ca59a1c1 100644 --- a/gcc/config/msp430/msp430.c +++ b/gcc/config/msp430/msp430.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on TI MSP430 processors. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/msp430/msp430.h b/gcc/config/msp430/msp430.h index c638f2f0dbc..b2f0764565f 100644 --- a/gcc/config/msp430/msp430.h +++ b/gcc/config/msp430/msp430.h @@ -1,5 +1,5 @@ /* GCC backend definitions for the TI MSP430 Processor - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md index 4b48d6aef5e..bcf5dac1ad3 100644 --- a/gcc/config/msp430/msp430.md +++ b/gcc/config/msp430/msp430.md @@ -1,5 +1,5 @@ ;; Machine Description for TI MSP43* processors -;; Copyright (C) 2013-2015 Free Software Foundation, Inc. +;; Copyright (C) 2013-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/msp430/predicates.md b/gcc/config/msp430/predicates.md index 5902339be97..0931bdf53b4 100644 --- a/gcc/config/msp430/predicates.md +++ b/gcc/config/msp430/predicates.md @@ -1,5 +1,5 @@ ;; Machine Description for TI MSP43* processors -;; Copyright (C) 2013-2015 Free Software Foundation, Inc. +;; Copyright (C) 2013-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/msp430/t-msp430 b/gcc/config/msp430/t-msp430 index 01e6d4cfa34..62cc0b41676 100644 --- a/gcc/config/msp430/t-msp430 +++ b/gcc/config/msp430/t-msp430 @@ -1,5 +1,5 @@ # Makefile fragment for building GCC for the TI MSP430 target. -# Copyright (C) 2012-2015 Free Software Foundation, Inc. +# Copyright (C) 2012-2016 Free Software Foundation, Inc. # Contributed by Red Hat. # # This file is part of GCC. diff --git a/gcc/config/nds32/constants.md b/gcc/config/nds32/constants.md index ea1cd4cf52b..bea42ee75a9 100644 --- a/gcc/config/nds32/constants.md +++ b/gcc/config/nds32/constants.md @@ -1,5 +1,5 @@ ;; Constant defintions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/constraints.md b/gcc/config/nds32/constraints.md index d84583b2645..1f44a1ada98 100644 --- a/gcc/config/nds32/constraints.md +++ b/gcc/config/nds32/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/iterators.md b/gcc/config/nds32/iterators.md index 892b4e0b470..ab0f10375a5 100644 --- a/gcc/config/nds32/iterators.md +++ b/gcc/config/nds32/iterators.md @@ -1,6 +1,6 @@ ;; Code and mode itertator and attribute definitions ;; of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-cost.c b/gcc/config/nds32/nds32-cost.c index 5bc622e51a1..e6a29fc9dbf 100644 --- a/gcc/config/nds32/nds32-cost.c +++ b/gcc/config/nds32/nds32-cost.c @@ -1,5 +1,5 @@ /* Subroutines used for calculate rtx costs of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-doubleword.md b/gcc/config/nds32/nds32-doubleword.md index f98dc7992b2..23a9f2592b5 100644 --- a/gcc/config/nds32/nds32-doubleword.md +++ b/gcc/config/nds32/nds32-doubleword.md @@ -1,5 +1,5 @@ ;; DImode/DFmode patterns description of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-fp-as-gp.c b/gcc/config/nds32/nds32-fp-as-gp.c index 3fdbd966df1..f8b2738ced6 100644 --- a/gcc/config/nds32/nds32-fp-as-gp.c +++ b/gcc/config/nds32/nds32-fp-as-gp.c @@ -1,5 +1,5 @@ /* The fp-as-gp pass of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-intrinsic.c b/gcc/config/nds32/nds32-intrinsic.c index 93e4225e7d0..fabf262e3cb 100644 --- a/gcc/config/nds32/nds32-intrinsic.c +++ b/gcc/config/nds32/nds32-intrinsic.c @@ -1,5 +1,5 @@ /* Intrinsic functions of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-intrinsic.md b/gcc/config/nds32/nds32-intrinsic.md index db4f8cef4db..53876c596c7 100644 --- a/gcc/config/nds32/nds32-intrinsic.md +++ b/gcc/config/nds32/nds32-intrinsic.md @@ -1,5 +1,5 @@ ;; Intrinsic patterns description of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-isr.c b/gcc/config/nds32/nds32-isr.c index a2c79757113..79be27e41c1 100644 --- a/gcc/config/nds32/nds32-isr.c +++ b/gcc/config/nds32/nds32-isr.c @@ -1,5 +1,5 @@ /* Subroutines used for ISR of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-md-auxiliary.c b/gcc/config/nds32/nds32-md-auxiliary.c index 53ad24ea1fa..def8eda417e 100644 --- a/gcc/config/nds32/nds32-md-auxiliary.c +++ b/gcc/config/nds32/nds32-md-auxiliary.c @@ -1,6 +1,6 @@ /* Auxiliary functions for output asm template or expand rtl pattern of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-memory-manipulation.c b/gcc/config/nds32/nds32-memory-manipulation.c index 690e68c0f75..4c26dcc7bbc 100644 --- a/gcc/config/nds32/nds32-memory-manipulation.c +++ b/gcc/config/nds32/nds32-memory-manipulation.c @@ -1,6 +1,6 @@ /* Auxiliary functions for expand movmem, setmem, cmpmem, load_multiple and store_multiple pattern of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-modes.def b/gcc/config/nds32/nds32-modes.def index cfd0fe76d6c..f2d0e6c2760 100644 --- a/gcc/config/nds32/nds32-modes.def +++ b/gcc/config/nds32/nds32-modes.def @@ -1,5 +1,5 @@ /* Extra machine modes of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-multiple.md b/gcc/config/nds32/nds32-multiple.md index 977a144bb21..babc7f2a230 100644 --- a/gcc/config/nds32/nds32-multiple.md +++ b/gcc/config/nds32/nds32-multiple.md @@ -1,5 +1,5 @@ ;; Load/Store Multiple patterns description of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation.for NDS32. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-opts.h b/gcc/config/nds32/nds32-opts.h index 1aa0d31dff4..25c4081a668 100644 --- a/gcc/config/nds32/nds32-opts.h +++ b/gcc/config/nds32/nds32-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-peephole2.md b/gcc/config/nds32/nds32-peephole2.md index df391cc0088..07e3a2b8c43 100644 --- a/gcc/config/nds32/nds32-peephole2.md +++ b/gcc/config/nds32/nds32-peephole2.md @@ -1,5 +1,5 @@ ;; define_peephole2 optimization patterns of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32-pipelines-auxiliary.c b/gcc/config/nds32/nds32-pipelines-auxiliary.c index a0e24ed167d..a396fffbea4 100644 --- a/gcc/config/nds32/nds32-pipelines-auxiliary.c +++ b/gcc/config/nds32/nds32-pipelines-auxiliary.c @@ -1,6 +1,6 @@ /* Auxiliary functions for pipeline descriptions pattern of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-predicates.c b/gcc/config/nds32/nds32-predicates.c index aa300a2d742..361d0018627 100644 --- a/gcc/config/nds32/nds32-predicates.c +++ b/gcc/config/nds32/nds32-predicates.c @@ -1,5 +1,5 @@ /* Predicate functions of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32-protos.h b/gcc/config/nds32/nds32-protos.h index 199e7037458..d66749d8f92 100644 --- a/gcc/config/nds32/nds32-protos.h +++ b/gcc/config/nds32/nds32-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c index 1bdb518a02e..c47c122a817 100644 --- a/gcc/config/nds32/nds32.c +++ b/gcc/config/nds32/nds32.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h index 126b5861d80..eb4558ce57d 100644 --- a/gcc/config/nds32/nds32.h +++ b/gcc/config/nds32/nds32.h @@ -1,5 +1,5 @@ /* Definitions of target machine of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md index 3dc1ce8f962..5cdd8b24aae 100644 --- a/gcc/config/nds32/nds32.md +++ b/gcc/config/nds32/nds32.md @@ -1,5 +1,5 @@ ;; Machine description of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/nds32.opt b/gcc/config/nds32/nds32.opt index 0d573daa548..938136f8a19 100644 --- a/gcc/config/nds32/nds32.opt +++ b/gcc/config/nds32/nds32.opt @@ -1,5 +1,5 @@ ; Options of Andes NDS32 cpu for GNU compiler -; Copyright (C) 2012-2015 Free Software Foundation, Inc. +; Copyright (C) 2012-2016 Free Software Foundation, Inc. ; Contributed by Andes Technology Corporation. ; ; This file is part of GCC. diff --git a/gcc/config/nds32/nds32_intrinsic.h b/gcc/config/nds32/nds32_intrinsic.h index 5993eadc142..3e868dc8e02 100644 --- a/gcc/config/nds32/nds32_intrinsic.h +++ b/gcc/config/nds32/nds32_intrinsic.h @@ -1,5 +1,5 @@ /* Intrinsic definitions of Andes NDS32 cpu for GNU compiler - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Andes Technology Corporation. This file is part of GCC. diff --git a/gcc/config/nds32/pipelines.md b/gcc/config/nds32/pipelines.md index cf017358180..f7e2fa8cf41 100644 --- a/gcc/config/nds32/pipelines.md +++ b/gcc/config/nds32/pipelines.md @@ -1,5 +1,5 @@ ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/predicates.md b/gcc/config/nds32/predicates.md index 6ee1a06ab80..05a039d2390 100644 --- a/gcc/config/nds32/predicates.md +++ b/gcc/config/nds32/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions of Andes NDS32 cpu for GNU compiler -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Andes Technology Corporation. ;; ;; This file is part of GCC. diff --git a/gcc/config/nds32/t-mlibs b/gcc/config/nds32/t-mlibs index d9e5ba4b952..5cb13f7a494 100644 --- a/gcc/config/nds32/t-mlibs +++ b/gcc/config/nds32/t-mlibs @@ -1,5 +1,5 @@ # The multilib settings of Andes NDS32 cpu for GNU compiler -# Copyright (C) 2012-2015 Free Software Foundation, Inc. +# Copyright (C) 2012-2016 Free Software Foundation, Inc. # Contributed by Andes Technology Corporation. # # This file is part of GCC. diff --git a/gcc/config/nds32/t-nds32 b/gcc/config/nds32/t-nds32 index ea36cc71b64..cf3aea67018 100644 --- a/gcc/config/nds32/t-nds32 +++ b/gcc/config/nds32/t-nds32 @@ -1,5 +1,5 @@ # General rules that all nds32/ targets must have. -# Copyright (C) 2012-2015 Free Software Foundation, Inc. +# Copyright (C) 2012-2016 Free Software Foundation, Inc. # Contributed by Andes Technology Corporation. # # This file is part of GCC. diff --git a/gcc/config/netbsd-elf.h b/gcc/config/netbsd-elf.h index a679bbde238..7182da9bf00 100644 --- a/gcc/config/netbsd-elf.h +++ b/gcc/config/netbsd-elf.h @@ -1,5 +1,5 @@ /* Common configuration file for NetBSD ELF targets. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. This file is part of GCC. diff --git a/gcc/config/netbsd-elf.opt b/gcc/config/netbsd-elf.opt index 6ff2c7e7c47..c90f4a2f521 100644 --- a/gcc/config/netbsd-elf.opt +++ b/gcc/config/netbsd-elf.opt @@ -1,6 +1,6 @@ ; NetBSD ELF-only options. -; Copyright (C) 2010-2015 Free Software Foundation, Inc. +; Copyright (C) 2010-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/netbsd.h b/gcc/config/netbsd.h index 5aa7aba4594..f2d6cc6a101 100644 --- a/gcc/config/netbsd.h +++ b/gcc/config/netbsd.h @@ -1,5 +1,5 @@ /* Base configuration file for all NetBSD targets. - Copyright (C) 1997-2015 Free Software Foundation, Inc. + Copyright (C) 1997-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/netbsd.opt b/gcc/config/netbsd.opt index 0478fb72fff..ee585d26a91 100644 --- a/gcc/config/netbsd.opt +++ b/gcc/config/netbsd.opt @@ -1,6 +1,6 @@ ; NetBSD options. -; Copyright (C) 2010-2015 Free Software Foundation, Inc. +; Copyright (C) 2010-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/newlib-stdint.h b/gcc/config/newlib-stdint.h index eb99556bef0..04ed457ef24 100644 --- a/gcc/config/newlib-stdint.h +++ b/gcc/config/newlib-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using newlib. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/nios2/constraints.md b/gcc/config/nios2/constraints.md index 6f7afa4358f..06b5137a2b7 100644 --- a/gcc/config/nios2/constraints.md +++ b/gcc/config/nios2/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Altera Nios II. -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Chung-Lin Tang <cltang@codesourcery.com> ;; ;; This file is part of GCC. diff --git a/gcc/config/nios2/elf.h b/gcc/config/nios2/elf.h index 84b44d42258..314a12a3191 100644 --- a/gcc/config/nios2/elf.h +++ b/gcc/config/nios2/elf.h @@ -1,5 +1,5 @@ /* Definitions of ELF target support for Altera Nios II. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Jonah Graham (jgraham@altera.com), Will Reece (wreece@altera.com), and Jeff DaSilva (jdasilva@altera.com). Contributed by Mentor Graphics, Inc. diff --git a/gcc/config/nios2/elf.opt b/gcc/config/nios2/elf.opt index 2887dca098d..888ebd16a61 100644 --- a/gcc/config/nios2/elf.opt +++ b/gcc/config/nios2/elf.opt @@ -1,5 +1,5 @@ ; Options for the Altera Nios II port of the compiler. -; Copyright (C) 2012-2015 Free Software Foundation, Inc. +; Copyright (C) 2012-2016 Free Software Foundation, Inc. ; Contributed by Altera and Mentor Graphics, Inc. ; ; This file is part of GCC. diff --git a/gcc/config/nios2/ldstwm.md b/gcc/config/nios2/ldstwm.md index 828bf494c69..5fdf4270281 100644 --- a/gcc/config/nios2/ldstwm.md +++ b/gcc/config/nios2/ldstwm.md @@ -2,7 +2,7 @@ This file was automatically generated using nios2-ldstwm.sml. Please do not edit manually. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by Mentor Graphics. This file is part of GCC. diff --git a/gcc/config/nios2/linux.h b/gcc/config/nios2/linux.h index f43f655e860..4ef55b58886 100644 --- a/gcc/config/nios2/linux.h +++ b/gcc/config/nios2/linux.h @@ -1,6 +1,6 @@ /* Definitions of target support for Altera Nios II systems running GNU/Linux with ELF format. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Mentor Graphics, Inc. This file is part of GCC. diff --git a/gcc/config/nios2/nios2-ldstwm.sml b/gcc/config/nios2/nios2-ldstwm.sml index baff780b050..f32ebb3c70e 100644 --- a/gcc/config/nios2/nios2-ldstwm.sml +++ b/gcc/config/nios2/nios2-ldstwm.sml @@ -1,5 +1,5 @@ (* Auto-generate Nios II R2 CDX ldwm/stwm/push.n/pop.n patterns - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by Mentor Graphics. This file is part of GCC. @@ -233,7 +233,7 @@ print " This file was automatically generated using nios2-ldstwm.sml.\n" ^ " Please do not edit manually.\n" ^ "\n" ^ - " Copyright (C) 2014-2015 Free Software Foundation, Inc.\n" ^ + " Copyright (C) 2014-2016 Free Software Foundation, Inc.\n" ^ " Contributed by Mentor Graphics.\n" ^ "\n" ^ " This file is part of GCC.\n" ^ diff --git a/gcc/config/nios2/nios2-opts.h b/gcc/config/nios2/nios2-opts.h index 062642438aa..c17c091b146 100644 --- a/gcc/config/nios2/nios2-opts.h +++ b/gcc/config/nios2/nios2-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for Nios II. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/nios2/nios2-protos.h b/gcc/config/nios2/nios2-protos.h index 897a23fdc2a..4d837e79ef3 100644 --- a/gcc/config/nios2/nios2-protos.h +++ b/gcc/config/nios2/nios2-protos.h @@ -1,5 +1,5 @@ /* Subroutine declarations for Altera Nios II target support. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Jonah Graham (jgraham@altera.com). Contributed by Mentor Graphics, Inc. diff --git a/gcc/config/nios2/nios2.c b/gcc/config/nios2/nios2.c index f9daa3fedeb..18fcbb3266e 100644 --- a/gcc/config/nios2/nios2.c +++ b/gcc/config/nios2/nios2.c @@ -1,5 +1,5 @@ /* Target machine subroutines for Altera Nios II. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Jonah Graham (jgraham@altera.com), Will Reece (wreece@altera.com), and Jeff DaSilva (jdasilva@altera.com). Contributed by Mentor Graphics, Inc. diff --git a/gcc/config/nios2/nios2.h b/gcc/config/nios2/nios2.h index ff25ade9372..abc676f4249 100644 --- a/gcc/config/nios2/nios2.h +++ b/gcc/config/nios2/nios2.h @@ -1,5 +1,5 @@ /* Definitions of target machine for Altera Nios II. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Jonah Graham (jgraham@altera.com), Will Reece (wreece@altera.com), and Jeff DaSilva (jdasilva@altera.com). Contributed by Mentor Graphics, Inc. diff --git a/gcc/config/nios2/nios2.md b/gcc/config/nios2/nios2.md index 88e689b00bf..3c5ba5345e0 100644 --- a/gcc/config/nios2/nios2.md +++ b/gcc/config/nios2/nios2.md @@ -1,5 +1,5 @@ ;; Machine Description for Altera Nios II. -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Jonah Graham (jgraham@altera.com) and ;; Will Reece (wreece@altera.com). ;; Contributed by Mentor Graphics, Inc. diff --git a/gcc/config/nios2/nios2.opt b/gcc/config/nios2/nios2.opt index 41afe4d87ab..510ec0acf14 100644 --- a/gcc/config/nios2/nios2.opt +++ b/gcc/config/nios2/nios2.opt @@ -1,5 +1,5 @@ ; Options for the Altera Nios II port of the compiler. -; Copyright (C) 2012-2015 Free Software Foundation, Inc. +; Copyright (C) 2012-2016 Free Software Foundation, Inc. ; Contributed by Altera and Mentor Graphics, Inc. ; ; This file is part of GCC. diff --git a/gcc/config/nios2/predicates.md b/gcc/config/nios2/predicates.md index f1de2f4edb3..bfbfb391290 100644 --- a/gcc/config/nios2/predicates.md +++ b/gcc/config/nios2/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Altera Nios II. -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Chung-Lin Tang <cltang@codesourcery.com> ;; ;; This file is part of GCC. diff --git a/gcc/config/nios2/rtems.h b/gcc/config/nios2/rtems.h index af3fa93c9ba..0772260aecc 100644 --- a/gcc/config/nios2/rtems.h +++ b/gcc/config/nios2/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a NIOS2 using ELF. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Chris Johns (chrisj@rtems.org). diff --git a/gcc/config/nios2/sync.md b/gcc/config/nios2/sync.md index 405aa38e9aa..04ae31f5bdd 100644 --- a/gcc/config/nios2/sync.md +++ b/gcc/config/nios2/sync.md @@ -1,5 +1,5 @@ ;; Machine Description for Altera Nios II synchronization primitives. -;; Copyright (C) 2014-2015 Free Software Foundation, Inc. +;; Copyright (C) 2014-2016 Free Software Foundation, Inc. ;; Contributed by Mentor Graphics, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/nios2/t-nios2 b/gcc/config/nios2/t-nios2 index 2e94a8255da..554177a56f1 100644 --- a/gcc/config/nios2/t-nios2 +++ b/gcc/config/nios2/t-nios2 @@ -1,5 +1,5 @@ # Target Makefile Fragment for Altera Nios II. -# Copyright (C) 2013-2015 Free Software Foundation, Inc. +# Copyright (C) 2013-2016 Free Software Foundation, Inc. # Contributed by Altera and Mentor Graphics, Inc. # # This file is part of GCC. diff --git a/gcc/config/nvptx/mkoffload.c b/gcc/config/nvptx/mkoffload.c index 3829f691188..c8eed451078 100644 --- a/gcc/config/nvptx/mkoffload.c +++ b/gcc/config/nvptx/mkoffload.c @@ -1,6 +1,6 @@ /* Offload image generation tool for PTX. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by Nathan Sidwell <nathan@codesourcery.com> and Bernd Schmidt <bernds@codesourcery.com>. diff --git a/gcc/config/nvptx/nvptx-protos.h b/gcc/config/nvptx/nvptx-protos.h index 7e0c296e3f0..ec4588e6dc0 100644 --- a/gcc/config/nvptx/nvptx-protos.h +++ b/gcc/config/nvptx/nvptx-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in nvptx.c. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by Bernd Schmidt <bernds@codesourcery.com> This file is part of GCC. @@ -41,7 +41,5 @@ extern const char *nvptx_ptx_type_from_mode (machine_mode, bool); extern const char *nvptx_output_mov_insn (rtx, rtx); extern const char *nvptx_output_call_insn (rtx_insn *, rtx, rtx); extern const char *nvptx_output_return (void); -extern bool nvptx_hard_regno_mode_ok (int, machine_mode); -extern rtx nvptx_maybe_convert_symbolic_operand (rtx); #endif #endif diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c index bb4c384a5d2..15a04399c4a 100644 --- a/gcc/config/nvptx/nvptx.c +++ b/gcc/config/nvptx/nvptx.c @@ -1,5 +1,5 @@ /* Target code for NVPTX. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by Bernd Schmidt <bernds@codesourcery.com> This file is part of GCC. @@ -128,14 +128,12 @@ static GTY((cache)) hash_table<tree_hasher> *needed_fndecls_htab; shared across TUs (taking the largest size). */ static unsigned worker_bcast_size; static unsigned worker_bcast_align; -#define worker_bcast_name "__worker_bcast" static GTY(()) rtx worker_bcast_sym; /* Buffer needed for worker reductions. This has to be distinct from the worker broadcast array, as both may be live concurrently. */ static unsigned worker_red_size; static unsigned worker_red_align; -#define worker_red_name "__worker_red" static GTY(()) rtx worker_red_sym; /* Global lock variable, needed for 128bit worker & gang reductions. */ @@ -147,7 +145,7 @@ static struct machine_function * nvptx_init_machine_status (void) { struct machine_function *p = ggc_cleared_alloc<machine_function> (); - p->ret_reg_mode = VOIDmode; + p->return_mode = VOIDmode; return p; } @@ -161,6 +159,13 @@ nvptx_option_override (void) flag_toplevel_reorder = 1; /* Assumes that it will see only hard registers. */ flag_var_tracking = 0; + + if (write_symbols == DBX_DEBUG) + /* The stabs testcases want to know stabs isn't supported. */ + sorry ("stabs debug format not supported"); + + /* Actually we don't have any debug format, but don't be + unneccesarily noisy. */ write_symbols = NO_DEBUG; debug_info_level = DINFO_LEVEL_NONE; @@ -172,11 +177,11 @@ nvptx_option_override (void) declared_libfuncs_htab = hash_table<declared_libfunc_hasher>::create_ggc (17); - worker_bcast_sym = gen_rtx_SYMBOL_REF (Pmode, worker_bcast_name); + worker_bcast_sym = gen_rtx_SYMBOL_REF (Pmode, "__worker_bcast"); SET_SYMBOL_DATA_AREA (worker_bcast_sym, DATA_AREA_SHARED); worker_bcast_align = GET_MODE_ALIGNMENT (SImode) / BITS_PER_UNIT; - worker_red_sym = gen_rtx_SYMBOL_REF (Pmode, worker_red_name); + worker_red_sym = gen_rtx_SYMBOL_REF (Pmode, "__worker_red"); SET_SYMBOL_DATA_AREA (worker_red_sym, DATA_AREA_SHARED); worker_red_align = GET_MODE_ALIGNMENT (SImode) / BITS_PER_UNIT; } @@ -366,17 +371,6 @@ nvptx_emit_joining (unsigned mask, bool is_call) } -/* Perform a mode promotion for a function argument with MODE. Return - the promoted mode. */ - -static machine_mode -arg_promotion (machine_mode mode) -{ - if (mode == QImode || mode == HImode) - return SImode; - return mode; -} - /* Determine whether MODE and TYPE (possibly NULL) should be passed or returned in memory. Integer and floating types supported by the machine are passed in registers, everything else is passed in @@ -498,7 +492,7 @@ nvptx_strict_argument_naming (cumulative_args_t cum_v) static rtx nvptx_libcall_value (machine_mode mode, const_rtx) { - if (cfun->machine->start_call == NULL_RTX) + if (!cfun->machine->doing_call) /* Pretend to return in a hard reg for early uses before pseudos can be generated. */ return gen_rtx_REG (mode, NVPTX_RETURN_REGNUM); @@ -516,7 +510,10 @@ nvptx_function_value (const_tree type, const_tree ARG_UNUSED (func), machine_mode mode = promote_return (TYPE_MODE (type)); if (outgoing) - return gen_rtx_REG (mode, NVPTX_RETURN_REGNUM); + { + cfun->machine->return_mode = mode; + return gen_rtx_REG (mode, NVPTX_RETURN_REGNUM); + } return nvptx_libcall_value (mode, NULL_RTX); } @@ -533,8 +530,9 @@ nvptx_function_value_regno_p (const unsigned int regno) reference in memory. */ static bool -nvptx_pass_by_reference (cumulative_args_t ARG_UNUSED (cum), machine_mode mode, - const_tree type, bool ARG_UNUSED (named)) +nvptx_pass_by_reference (cumulative_args_t ARG_UNUSED (cum), + machine_mode mode, const_tree type, + bool ARG_UNUSED (named)) { return pass_in_memory (mode, type, false); } @@ -557,18 +555,6 @@ nvptx_promote_function_mode (const_tree type, machine_mode mode, return promote_arg (mode, for_return || !type || TYPE_ARG_TYPES (funtype)); } -/* Implement TARGET_STATIC_CHAIN. */ - -static rtx -nvptx_static_chain (const_tree fndecl, bool incoming_p) -{ - if (!DECL_STATIC_CHAIN (fndecl)) - return NULL; - - return gen_rtx_REG (Pmode, (incoming_p ? STATIC_CHAIN_REGNUM - : OUTGOING_STATIC_CHAIN_REGNUM)); -} - /* Helper for write_arg. Emit a single PTX argument of MODE, either in a prototype, or as copy in a function prologue. ARGNO is the index of this argument in the PTX function. FOR_REG is negative, @@ -577,7 +563,8 @@ nvptx_static_chain (const_tree fndecl, bool incoming_p) copying to a specific hard register. */ static int -write_one_arg (std::stringstream &s, int for_reg, int argno, machine_mode mode) +write_arg_mode (std::stringstream &s, int for_reg, int argno, + machine_mode mode) { const char *ptx_type = nvptx_ptx_type_from_mode (mode, false); @@ -597,18 +584,21 @@ write_one_arg (std::stringstream &s, int for_reg, int argno, machine_mode mode) else s << "%ar" << argno; s << ";\n"; - s << "\tld.param" << ptx_type << " "; - if (for_reg) - s << reg_names[for_reg]; - else - s << "%ar" << argno; - s << ", [%in_ar" << argno << "];\n"; + if (argno >= 0) + { + s << "\tld.param" << ptx_type << " "; + if (for_reg) + s << reg_names[for_reg]; + else + s << "%ar" << argno; + s << ", [%in_ar" << argno << "];\n"; + } } return argno + 1; } /* Process function parameter TYPE to emit one or more PTX - arguments. S, FOR_REG and ARGNO as for write_one_arg. PROTOTYPED + arguments. S, FOR_REG and ARGNO as for write_arg_mode. PROTOTYPED is true, if this is a prototyped function, rather than an old-style C declaration. Returns the next argument number to use. @@ -616,8 +606,8 @@ write_one_arg (std::stringstream &s, int for_reg, int argno, machine_mode mode) parameter marshalling machinery. */ static int -write_arg (std::stringstream &s, int for_reg, int argno, - tree type, bool prototyped) +write_arg_type (std::stringstream &s, int for_reg, int argno, + tree type, bool prototyped) { machine_mode mode = TYPE_MODE (type); @@ -634,27 +624,41 @@ write_arg (std::stringstream &s, int for_reg, int argno, { /* Complex types are sent as two separate args. */ type = TREE_TYPE (type); - mode = TYPE_MODE (type); + mode = TYPE_MODE (type); prototyped = true; } mode = promote_arg (mode, prototyped); if (split) - argno = write_one_arg (s, for_reg, argno, mode); + argno = write_arg_mode (s, for_reg, argno, mode); } - return write_one_arg (s, for_reg, argno, mode); + return write_arg_mode (s, for_reg, argno, mode); +} + +/* Emit a PTX return as a prototype or function prologue declaration + for MODE. */ + +static void +write_return_mode (std::stringstream &s, bool for_proto, machine_mode mode) +{ + const char *ptx_type = nvptx_ptx_type_from_mode (mode, false); + const char *pfx = "\t.reg"; + const char *sfx = ";\n"; + + if (for_proto) + pfx = "(.param", sfx = "_out) "; + + s << pfx << ptx_type << " " << reg_names[NVPTX_RETURN_REGNUM] << sfx; } /* Process a function return TYPE to emit a PTX return as a prototype - or function prologue declaration. DECL_RESULT is the decl result - of the function and needed for determining named result - behaviour. Returns true if return is via an additional pointer - parameter. The promotion behaviour here must match the regular GCC - function return mashalling. */ + or function prologue declaration. Returns true if return is via an + additional pointer parameter. The promotion behaviour here must + match the regular GCC function return mashalling. */ static bool -write_return (std::stringstream &s, bool for_proto, tree type) +write_return_type (std::stringstream &s, bool for_proto, tree type) { machine_mode mode = TYPE_MODE (type); @@ -673,22 +677,18 @@ write_return (std::stringstream &s, bool for_proto, tree type) optimization-level specific, so no caller can make use of this data, but more importantly for us, we must ensure it doesn't change the PTX prototype. */ - mode = (machine_mode) cfun->machine->ret_reg_mode; + mode = (machine_mode) cfun->machine->return_mode; if (mode == VOIDmode) return return_in_mem; - /* Clear ret_reg_mode to inhibit copy of retval to non-existent + /* Clear return_mode to inhibit copy of retval to non-existent retval parameter. */ - cfun->machine->ret_reg_mode = VOIDmode; + cfun->machine->return_mode = VOIDmode; } else mode = promote_return (mode); - const char *ptx_type = nvptx_ptx_type_from_mode (mode, false); - if (for_proto) - s << "(.param" << ptx_type << " %out_retval) "; - else - s << "\t.reg" << ptx_type << " %retval;\n"; + write_return_mode (s, for_proto, mode); return return_in_mem; } @@ -761,7 +761,7 @@ write_fn_proto (std::stringstream &s, bool is_defn, tree result_type = TREE_TYPE (fntype); /* Declare the result. */ - bool return_in_mem = write_return (s, true, result_type); + bool return_in_mem = write_return_type (s, true, result_type); s << name; @@ -769,7 +769,7 @@ write_fn_proto (std::stringstream &s, bool is_defn, /* Emit argument list. */ if (return_in_mem) - argno = write_arg (s, -1, argno, ptr_type_node, true); + argno = write_arg_type (s, -1, argno, ptr_type_node, true); /* We get: NULL in TYPE_ARG_TYPES, for old-style functions @@ -788,19 +788,19 @@ write_fn_proto (std::stringstream &s, bool is_defn, { tree type = prototyped ? TREE_VALUE (args) : TREE_TYPE (args); - argno = write_arg (s, -1, argno, type, prototyped); + argno = write_arg_type (s, -1, argno, type, prototyped); } if (stdarg_p (fntype)) - argno = write_arg (s, -1, argno, ptr_type_node, true); + argno = write_arg_type (s, -1, argno, ptr_type_node, true); if (DECL_STATIC_CHAIN (decl)) - argno = write_arg (s, -1, argno, ptr_type_node, true); + argno = write_arg_type (s, -1, argno, ptr_type_node, true); if (!argno && strcmp (name, "main") == 0) { - argno = write_arg (s, -1, argno, integer_type_node, true); - argno = write_arg (s, -1, argno, ptr_type_node, true); + argno = write_arg_type (s, -1, argno, integer_type_node, true); + argno = write_arg_type (s, -1, argno, ptr_type_node, true); } if (argno) @@ -833,28 +833,19 @@ write_fn_proto_from_insn (std::stringstream &s, const char *name, } if (result != NULL_RTX) - s << "(.param" - << nvptx_ptx_type_from_mode (arg_promotion (GET_MODE (result)), false) - << " %rval) "; + write_return_mode (s, true, GET_MODE (result)); s << name; - const char *sep = " ("; int arg_end = XVECLEN (pat, 0); for (int i = 1; i < arg_end; i++) { - /* We don't have to deal with mode splitting here, as that was - already done when generating the call sequence. */ + /* We don't have to deal with mode splitting & promotion here, + as that was already done when generating the call + sequence. */ machine_mode mode = GET_MODE (XEXP (XVECEXP (pat, 0, i), 0)); - s << sep - << ".param" - << nvptx_ptx_type_from_mode (mode, false) - << " %arg" - << i; - if (mode == QImode || mode == HImode) - s << "[1]"; - sep = ", "; + write_arg_mode (s, -1, i - 1, mode); } if (arg_end != 1) s << ")"; @@ -923,6 +914,24 @@ nvptx_maybe_record_fnsym (rtx sym) nvptx_record_needed_fndecl (decl); } +/* Emit a local array to hold some part of a conventional stack frame + and initialize REGNO to point to it. If the size is zero, it'll + never be valid to dereference, so we can simply initialize to + zero. */ + +static void +init_frame (FILE *file, int regno, unsigned align, unsigned size) +{ + if (size) + fprintf (file, "\t.local .align %d .b8 %s_ar[%u];\n", + align, reg_names[regno], size); + fprintf (file, "\t.reg.u%d %s;\n", + POINTER_SIZE, reg_names[regno]); + fprintf (file, (size ? "\tcvta.local.u%d %s, %s_ar;\n" + : "\tmov.u%d %s, 0;\n"), + POINTER_SIZE, reg_names[regno], reg_names[regno]); +} + /* Emit code to initialize the REGNO predicate register to indicate whether we are not lane zero on the NAME axis. */ @@ -953,9 +962,9 @@ nvptx_declare_function_name (FILE *file, const char *name, const_tree decl) write_fn_proto (s, true, name, decl); s << "{\n"; - bool return_in_mem = write_return (s, false, result_type); + bool return_in_mem = write_return_type (s, false, result_type); if (return_in_mem) - argno = write_arg (s, 0, argno, ptr_type_node, true); + argno = write_arg_type (s, 0, argno, ptr_type_node, true); /* Declare and initialize incoming arguments. */ tree args = TYPE_ARG_TYPES (fntype); @@ -970,20 +979,31 @@ nvptx_declare_function_name (FILE *file, const char *name, const_tree decl) { tree type = prototyped ? TREE_VALUE (args) : TREE_TYPE (args); - argno = write_arg (s, 0, argno, type, prototyped); + argno = write_arg_type (s, 0, argno, type, prototyped); } if (stdarg_p (fntype)) - argno = write_arg (s, ARG_POINTER_REGNUM, argno, ptr_type_node, true); + argno = write_arg_type (s, ARG_POINTER_REGNUM, argno, ptr_type_node, + true); - if (DECL_STATIC_CHAIN (decl)) - argno = write_arg (s, STATIC_CHAIN_REGNUM, argno, ptr_type_node, true); + if (DECL_STATIC_CHAIN (decl) || cfun->machine->has_chain) + write_arg_type (s, STATIC_CHAIN_REGNUM, + DECL_STATIC_CHAIN (decl) ? argno : -1, ptr_type_node, + true); fprintf (file, "%s", s.str().c_str()); - fprintf (file, "\t.reg.u%d %s;\n", GET_MODE_BITSIZE (Pmode), - reg_names[OUTGOING_STATIC_CHAIN_REGNUM]); - + /* Declare a local var for outgoing varargs. */ + if (cfun->machine->has_varadic) + init_frame (file, STACK_POINTER_REGNUM, + UNITS_PER_WORD, crtl->outgoing_args_size); + + /* Declare a local variable for the frame. */ + HOST_WIDE_INT sz = get_frame_size (); + if (sz || cfun->machine->has_chain) + init_frame (file, FRAME_POINTER_REGNUM, + crtl->stack_alignment_needed / BITS_PER_UNIT, sz); + /* Declare the pseudos we have as ptx registers. */ int maxregs = max_reg_num (); for (int i = LAST_VIRTUAL_REGISTER + 1; i < maxregs; i++) @@ -1001,36 +1021,6 @@ nvptx_declare_function_name (FILE *file, const char *name, const_tree decl) } } - /* The only reason we might be using outgoing args is if we call a stdargs - function. Allocate the space for this. If we called varargs functions - without passing any variadic arguments, we'll see a reference to outargs - even with a zero outgoing_args_size. */ - HOST_WIDE_INT sz = crtl->outgoing_args_size; - if (sz == 0) - sz = 1; - if (cfun->machine->has_call_with_varargs) - { - fprintf (file, "\t.reg.u%d %%outargs;\n" - "\t.local.align 8 .b8 %%outargs_ar[" - HOST_WIDE_INT_PRINT_DEC"];\n", - BITS_PER_WORD, sz); - fprintf (file, "\tcvta.local.u%d %%outargs, %%outargs_ar;\n", - BITS_PER_WORD); - } - - /* Declare a local variable for the frame. */ - sz = get_frame_size (); - if (sz > 0 || cfun->machine->has_call_with_sc) - { - int alignment = crtl->stack_alignment_needed / BITS_PER_UNIT; - - fprintf (file, "\t.reg.u%d %%frame;\n" - "\t.local.align %d .b8 %%farray[" HOST_WIDE_INT_PRINT_DEC"];\n", - BITS_PER_WORD, alignment, sz == 0 ? 1 : sz); - fprintf (file, "\tcvta.local.u%d %%frame, %%farray;\n", - BITS_PER_WORD); - } - /* Emit axis predicates. */ if (cfun->machine->axis_predicate[0]) nvptx_init_axis_predicate (file, @@ -1046,14 +1036,13 @@ nvptx_declare_function_name (FILE *file, const char *name, const_tree decl) const char * nvptx_output_return (void) { - machine_mode mode = (machine_mode)cfun->machine->ret_reg_mode; + machine_mode mode = (machine_mode)cfun->machine->return_mode; if (mode != VOIDmode) - { - mode = arg_promotion (mode); - fprintf (asm_out_file, "\tst.param%s\t[%%out_retval], %%retval;\n", - nvptx_ptx_type_from_mode (mode, false)); - } + fprintf (asm_out_file, "\tst.param%s\t[%s_out], %s;\n", + nvptx_ptx_type_from_mode (mode, false), + reg_names[NVPTX_RETURN_REGNUM], + reg_names[NVPTX_RETURN_REGNUM]); return "ret;"; } @@ -1087,20 +1076,28 @@ nvptx_get_drap_rtx (void) argument to the next call. */ static void -nvptx_call_args (rtx arg, tree funtype) +nvptx_call_args (rtx arg, tree fntype) { - if (cfun->machine->start_call == NULL_RTX) + if (!cfun->machine->doing_call) { - cfun->machine->call_args = NULL; - cfun->machine->funtype = funtype; - cfun->machine->start_call = const0_rtx; + cfun->machine->doing_call = true; + cfun->machine->is_varadic = false; + cfun->machine->num_args = 0; + + if (fntype && stdarg_p (fntype)) + { + cfun->machine->is_varadic = true; + cfun->machine->has_varadic = true; + cfun->machine->num_args++; + } } - if (arg == pc_rtx) - return; - rtx_expr_list *args_so_far = cfun->machine->call_args; - if (REG_P (arg)) - cfun->machine->call_args = alloc_EXPR_LIST (VOIDmode, arg, args_so_far); + if (REG_P (arg) && arg != pc_rtx) + { + cfun->machine->num_args++; + cfun->machine->call_args = alloc_EXPR_LIST (VOIDmode, arg, + cfun->machine->call_args); + } } /* Implement the corresponding END_CALL_ARGS hook. Clear and free the @@ -1109,7 +1106,7 @@ nvptx_call_args (rtx arg, tree funtype) static void nvptx_end_call_args (void) { - cfun->machine->start_call = NULL_RTX; + cfun->machine->doing_call = false; free_EXPR_LIST_list (&cfun->machine->call_args); } @@ -1122,16 +1119,10 @@ nvptx_end_call_args (void) void nvptx_expand_call (rtx retval, rtx address) { - int nargs = 0; rtx callee = XEXP (address, 0); - rtx pat, t; - rtvec vec; rtx varargs = NULL_RTX; unsigned parallel = 0; - for (t = cfun->machine->call_args; t; t = XEXP (t, 1)) - nargs++; - if (!call_insn_operand (callee, Pmode)) { callee = force_reg (Pmode, callee); @@ -1144,7 +1135,7 @@ nvptx_expand_call (rtx retval, rtx address) if (decl != NULL_TREE) { if (DECL_STATIC_CHAIN (decl)) - cfun->machine->has_call_with_sc = true; + cfun->machine->has_chain = true; tree attr = get_oacc_fn_attrib (decl); if (attr) @@ -1165,40 +1156,31 @@ nvptx_expand_call (rtx retval, rtx address) } } - if (cfun->machine->funtype - /* It's possible to construct testcases where we call a variable. - See compile/20020129-1.c. stdarg_p will crash so avoid calling it - in such a case. */ - && (TREE_CODE (cfun->machine->funtype) == FUNCTION_TYPE - || TREE_CODE (cfun->machine->funtype) == METHOD_TYPE) - && stdarg_p (cfun->machine->funtype)) + unsigned nargs = cfun->machine->num_args; + if (cfun->machine->is_varadic) { varargs = gen_reg_rtx (Pmode); emit_move_insn (varargs, stack_pointer_rtx); - cfun->machine->has_call_with_varargs = true; } - vec = rtvec_alloc (nargs + 1 + (varargs ? 1 : 0)); - pat = gen_rtx_PARALLEL (VOIDmode, vec); + rtvec vec = rtvec_alloc (nargs + 1); + rtx pat = gen_rtx_PARALLEL (VOIDmode, vec); int vec_pos = 0; - + + rtx call = gen_rtx_CALL (VOIDmode, address, const0_rtx); rtx tmp_retval = retval; - t = gen_rtx_CALL (VOIDmode, address, const0_rtx); - if (retval != NULL_RTX) + if (retval) { if (!nvptx_register_operand (retval, GET_MODE (retval))) tmp_retval = gen_reg_rtx (GET_MODE (retval)); - t = gen_rtx_SET (tmp_retval, t); + call = gen_rtx_SET (tmp_retval, call); } - XVECEXP (pat, 0, vec_pos++) = t; + XVECEXP (pat, 0, vec_pos++) = call; /* Construct the call insn, including a USE for each argument pseudo register. These will be used when printing the insn. */ for (rtx arg = cfun->machine->call_args; arg; arg = XEXP (arg, 1)) - { - rtx this_arg = XEXP (arg, 0); - XVECEXP (pat, 0, vec_pos++) = gen_rtx_USE (VOIDmode, this_arg); - } + XVECEXP (pat, 0, vec_pos++) = gen_rtx_USE (VOIDmode, XEXP (arg, 0)); if (varargs) XVECEXP (pat, 0, vec_pos++) = gen_rtx_USE (VOIDmode, varargs); @@ -1406,7 +1388,6 @@ nvptx_gen_wcast (rtx reg, propagate_mask pm, unsigned rep, wcast_data_t *data) } addr = gen_rtx_MEM (mode, addr); - addr = gen_rtx_UNSPEC (mode, gen_rtvec (1, addr), UNSPEC_SHARED_DATA); if (pm == PM_read) res = gen_rtx_SET (addr, reg); else if (pm == PM_write) @@ -1433,39 +1414,6 @@ nvptx_gen_wcast (rtx reg, propagate_mask pm, unsigned rep, wcast_data_t *data) } return res; } - -/* When loading an operand ORIG_OP, verify whether an address space - conversion to generic is required, and if so, perform it. Check - for SYMBOL_REFs and record them if needed. Return either the - original operand, or the converted one. */ - -rtx -nvptx_maybe_convert_symbolic_operand (rtx op) -{ - if (GET_MODE (op) != Pmode) - return op; - - rtx sym = op; - if (GET_CODE (sym) == CONST) - sym = XEXP (sym, 0); - if (GET_CODE (sym) == PLUS) - sym = XEXP (sym, 0); - - if (GET_CODE (sym) != SYMBOL_REF) - return op; - - nvptx_maybe_record_fnsym (sym); - - nvptx_data_area area = SYMBOL_DATA_AREA (sym); - if (area == DATA_AREA_GENERIC) - return op; - - rtx dest = gen_reg_rtx (Pmode); - emit_insn (gen_rtx_SET (dest, - gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), - UNSPEC_TO_GENERIC))); - return dest; -} /* Returns true if X is a valid address for use in a memory reference. */ @@ -1493,18 +1441,6 @@ nvptx_legitimate_address_p (machine_mode, rtx x, bool) return false; } } - -/* Implement HARD_REGNO_MODE_OK. We barely use hard regs, but we want - to ensure that the return register's mode isn't changed. */ - -bool -nvptx_hard_regno_mode_ok (int regno, machine_mode mode) -{ - if (regno != NVPTX_RETURN_REGNUM - || cfun == NULL || cfun->machine->ret_reg_mode == VOIDmode) - return true; - return mode == cfun->machine->ret_reg_mode; -} /* Machinery to output constant initializers. When beginning an initializer, we decide on a fragment size (which is visible in ptx @@ -1783,6 +1719,11 @@ nvptx_globalize_label (FILE *, const char *) static void nvptx_assemble_undefined_decl (FILE *file, const char *name, const_tree decl) { + /* The middle end can place constant pool decls into the varpool as + undefined. Until that is fixed, catch the problem here. */ + if (DECL_IN_CONSTANT_POOL (decl)) + return; + write_var_marker (file, false, TREE_PUBLIC (decl), name); fprintf (file, "\t.extern "); @@ -1790,7 +1731,7 @@ nvptx_assemble_undefined_decl (FILE *file, const char *name, const_tree decl) nvptx_assemble_decl_begin (file, name, section_for_decl (decl), TREE_TYPE (decl), size ? tree_to_shwi (size) : 0, DECL_ALIGN (decl)); - fprintf (file, ";\n"); + nvptx_assemble_decl_end (); } /* Output a pattern for a move instruction. */ @@ -1804,11 +1745,15 @@ nvptx_output_mov_insn (rtx dst, rtx src) machine_mode src_inner = (GET_CODE (src) == SUBREG ? GET_MODE (XEXP (src, 0)) : dst_mode); - if (REG_P (dst) && REGNO (dst) == NVPTX_RETURN_REGNUM && dst_mode == HImode) - /* Special handling for the return register. It's never really an - HI object, and only occurs as the destination of a move - insn. */ - dst_inner = SImode; + rtx sym = src; + if (GET_CODE (sym) == CONST) + sym = XEXP (XEXP (sym, 0), 0); + if (SYMBOL_REF_P (sym)) + { + if (SYMBOL_DATA_AREA (sym) != DATA_AREA_GENERIC) + return "%.\tcvta%D1%t0\t%0, %1;"; + nvptx_maybe_record_fnsym (sym); + } if (src_inner == dst_inner) return "%.\tmov%t0\t%0, %1;"; @@ -1840,9 +1785,9 @@ nvptx_output_call_insn (rtx_insn *insn, rtx result, rtx callee) fprintf (asm_out_file, "\t{\n"); if (result != NULL) - fprintf (asm_out_file, "\t\t.param%s %%retval_in;\n", - nvptx_ptx_type_from_mode (arg_promotion (GET_MODE (result)), - false)); + fprintf (asm_out_file, "\t\t.param%s %s_in;\n", + nvptx_ptx_type_from_mode (GET_MODE (result), false), + reg_names[NVPTX_RETURN_REGNUM]); /* Ensure we have a ptx declaration in the output if necessary. */ if (GET_CODE (callee) == SYMBOL_REF) @@ -1869,20 +1814,20 @@ nvptx_output_call_insn (rtx_insn *insn, rtx result, rtx callee) { rtx t = XEXP (XVECEXP (pat, 0, argno), 0); machine_mode mode = GET_MODE (t); + const char *ptx_type = nvptx_ptx_type_from_mode (mode, false); /* Mode splitting has already been done. */ - fprintf (asm_out_file, "\t\t.param%s %%out_arg%d%s;\n", - nvptx_ptx_type_from_mode (mode, false), argno, - mode == QImode || mode == HImode ? "[1]" : ""); - fprintf (asm_out_file, "\t\tst.param%s [%%out_arg%d], %%r%d;\n", - nvptx_ptx_type_from_mode (mode, false), argno, - REGNO (t)); + fprintf (asm_out_file, "\t\t.param%s %%out_arg%d;\n" + "\t\tst.param%s [%%out_arg%d], ", + ptx_type, argno, ptx_type, argno); + output_reg (asm_out_file, REGNO (t), VOIDmode); + fprintf (asm_out_file, ";\n"); } fprintf (asm_out_file, "\t\tcall "); if (result != NULL_RTX) - fprintf (asm_out_file, "(%%retval_in), "); - + fprintf (asm_out_file, "(%s_in), ", reg_names[NVPTX_RETURN_REGNUM]); + if (decl) { const char *name = get_fnname_from_decl (decl); @@ -1900,8 +1845,7 @@ nvptx_output_call_insn (rtx_insn *insn, rtx result, rtx callee) } if (decl && DECL_STATIC_CHAIN (decl)) { - fprintf (asm_out_file, ", %s%s", open, - reg_names [OUTGOING_STATIC_CHAIN_REGNUM]); + fprintf (asm_out_file, ", %s%s", open, reg_names [STATIC_CHAIN_REGNUM]); open = ""; } if (!open[0]) @@ -1921,7 +1865,18 @@ nvptx_output_call_insn (rtx_insn *insn, rtx result, rtx callee) trap, which it does grok. */ fprintf (asm_out_file, "\t\ttrap; // (noreturn)\n"); - return result != NULL_RTX ? "\tld.param%t0\t%0, [%%retval_in];\n\t}" : "}"; + if (result) + { + static char rval[sizeof ("\tld.param%%t0\t%%0, [%%%s_in];\n\t}") + 8]; + + if (!rval[0]) + /* We must escape the '%' that starts RETURN_REGNUM. */ + sprintf (rval, "\tld.param%%t0\t%%0, [%%%s_in];\n\t}", + reg_names[NVPTX_RETURN_REGNUM]); + return rval; + } + + return "}"; } /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ @@ -3390,7 +3345,7 @@ nvptx_wpropagate (bool pre_p, basic_block block, rtx_insn *insn) /* Stuff was emitted, initialize the base pointer now. */ rtx init = gen_rtx_SET (data.base, worker_bcast_sym); emit_insn_after (init, insn); - + if (worker_bcast_size < data.offset) worker_bcast_size = data.offset; } @@ -3954,6 +3909,18 @@ nvptx_file_start (void) fputs ("// END PREAMBLE\n", asm_out_file); } +/* Emit a declaration for a worker-level buffer in .shared memory. */ + +static void +write_worker_buffer (FILE *file, rtx sym, unsigned align, unsigned size) +{ + const char *name = XSTR (sym, 0); + + write_var_marker (file, true, false, name); + fprintf (file, ".shared .align %d .u8 %s[%d];\n", + align, name, size); +} + /* Write out the function declarations we've collected and declare storage for the broadcast buffer. */ @@ -3967,30 +3934,12 @@ nvptx_file_end (void) fputs (func_decls.str().c_str(), asm_out_file); if (worker_bcast_size) - { - /* Define the broadcast buffer. */ - - worker_bcast_size = (worker_bcast_size + worker_bcast_align - 1) - & ~(worker_bcast_align - 1); - - write_var_marker (asm_out_file, true, false, worker_bcast_name); - fprintf (asm_out_file, ".shared .align %d .u8 %s[%d];\n", - worker_bcast_align, - worker_bcast_name, worker_bcast_size); - } + write_worker_buffer (asm_out_file, worker_bcast_sym, + worker_bcast_align, worker_bcast_size); if (worker_red_size) - { - /* Define the reduction buffer. */ - - worker_red_size = ((worker_red_size + worker_red_align - 1) - & ~(worker_red_align - 1)); - - write_var_marker (asm_out_file, true, false, worker_red_name); - fprintf (asm_out_file, ".shared .align %d .u8 %s[%d];\n", - worker_red_align, - worker_red_name, worker_red_size); - } + write_worker_buffer (asm_out_file, worker_red_sym, + worker_red_align, worker_red_size); } /* Expander for the shuffle builtins. */ @@ -4804,7 +4753,7 @@ nvptx_goacc_reduction_teardown (gcall *call) /* NVPTX reduction expander. */ -void +static void nvptx_goacc_reduction (gcall *call) { unsigned code = (unsigned)TREE_INT_CST_LOW (gimple_call_arg (call, 0)); @@ -4870,9 +4819,6 @@ nvptx_goacc_reduction (gcall *call) #define TARGET_OMIT_STRUCT_RETURN_REG true #undef TARGET_STRICT_ARGUMENT_NAMING #define TARGET_STRICT_ARGUMENT_NAMING nvptx_strict_argument_naming -#undef TARGET_STATIC_CHAIN -#define TARGET_STATIC_CHAIN nvptx_static_chain - #undef TARGET_CALL_ARGS #define TARGET_CALL_ARGS nvptx_call_args #undef TARGET_END_CALL_ARGS diff --git a/gcc/config/nvptx/nvptx.h b/gcc/config/nvptx/nvptx.h index ed0f28e0dd8..565026f97ee 100644 --- a/gcc/config/nvptx/nvptx.h +++ b/gcc/config/nvptx/nvptx.h @@ -1,5 +1,5 @@ /* Target Definitions for NVPTX. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. Contributed by Bernd Schmidt <bernds@codesourcery.com> This file is part of GCC. @@ -78,53 +78,28 @@ #define PTRDIFF_TYPE (TARGET_ABI64 ? "long int" : "int") #define POINTER_SIZE (TARGET_ABI64 ? 64 : 32) - #define Pmode (TARGET_ABI64 ? DImode : SImode) /* Registers. Since ptx is a virtual target, we just define a few - hard registers for special purposes and leave pseudos unallocated. */ - + hard registers for special purposes and leave pseudos unallocated. + We have to have some available hard registers, to keep gcc setup + happy. */ #define FIRST_PSEUDO_REGISTER 16 -#define FIXED_REGISTERS \ - { 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1 } -#define CALL_USED_REGISTERS \ - { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } +#define FIXED_REGISTERS { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } +#define CALL_USED_REGISTERS { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } #define HARD_REGNO_NREGS(regno, mode) ((void)(regno), (void)(mode), 1) #define CANNOT_CHANGE_MODE_CLASS(M1, M2, CLS) ((CLS) == RETURN_REG) #define HARD_REGNO_MODE_OK(REG, MODE) nvptx_hard_regno_mode_ok (REG, MODE) /* Register Classes. */ - -enum reg_class - { - NO_REGS, - RETURN_REG, - ALL_REGS, - LIM_REG_CLASSES - }; - +enum reg_class { NO_REGS, ALL_REGS, LIM_REG_CLASSES }; +#define REG_CLASS_NAMES { "NO_REGS", "ALL_REGS" } +#define REG_CLASS_CONTENTS { { 0x0000 }, { 0xFFFF } } #define N_REG_CLASSES (int) LIM_REG_CLASSES -#define REG_CLASS_NAMES { \ - "RETURN_REG", \ - "NO_REGS", \ - "ALL_REGS" } - -#define REG_CLASS_CONTENTS \ -{ \ - /* NO_REGS. */ \ - { 0x0000 }, \ - /* RETURN_REG. */ \ - { 0x0008 }, \ - /* ALL_REGS. */ \ - { 0xFFFF }, \ -} - #define GENERAL_REGS ALL_REGS - -#define REGNO_REG_CLASS(R) ((R) == 4 ? RETURN_REG : ALL_REGS) - +#define REGNO_REG_CLASS(R) ((void)(R), ALL_REGS) #define BASE_REG_CLASS ALL_REGS #define INDEX_REG_CLASS NO_REGS @@ -137,10 +112,11 @@ enum reg_class #define MODES_TIEABLE_P(M1, M2) false #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ - if (GET_MODE_CLASS (MODE) == MODE_INT \ - && GET_MODE_SIZE (MODE) < GET_MODE_SIZE (SImode)) \ + if ((MODE) == QImode || (MODE) == HImode) \ { \ (MODE) = SImode; \ + (void)(UNSIGNEDP); \ + (void)(TYPE); \ } /* Stack and Calling. */ @@ -149,14 +125,17 @@ enum reg_class #define FRAME_GROWS_DOWNWARD 0 #define STACK_GROWS_DOWNWARD 1 +#define NVPTX_RETURN_REGNUM 0 #define STACK_POINTER_REGNUM 1 -#define HARD_FRAME_POINTER_REGNUM 2 -#define NVPTX_RETURN_REGNUM 4 -#define FRAME_POINTER_REGNUM 15 -#define ARG_POINTER_REGNUM 14 +#define FRAME_POINTER_REGNUM 2 +#define ARG_POINTER_REGNUM 3 +#define STATIC_CHAIN_REGNUM 4 -#define STATIC_CHAIN_REGNUM 12 -#define OUTGOING_STATIC_CHAIN_REGNUM 10 +#define REGISTER_NAMES \ + { \ + "%value", "%stack", "%frame", "%args", "%chain", "%hr5", "%hr6", "%hr7", \ + "%hr8", "%hr9", "%hr10", "%hr11", "%hr12", "%hr13", "%hr14", "%hr15" \ + } #define FIRST_PARM_OFFSET(FNDECL) ((void)(FNDECL), 0) #define PUSH_ARGS_REVERSED 1 @@ -170,15 +149,13 @@ struct nvptx_args { tree fntype; /* Number of arguments passed in registers so far. */ int count; - /* Offset into the stdarg area so far. */ - HOST_WIDE_INT off; }; #endif #define CUMULATIVE_ARGS struct nvptx_args #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ - ((CUM).fntype = (FNTYPE), (CUM).count = 0, (CUM).off = 0, (void)0) + ((CUM).fntype = (FNTYPE), (CUM).count = 0, (void)0) #define FUNCTION_ARG_REGNO_P(r) 0 @@ -196,8 +173,7 @@ struct nvptx_args { expand_builtin_setjmp_receiver from generating invalid insns. */ #define ELIMINABLE_REGS \ { \ - { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ - { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} \ + { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM} \ } /* Define the offset between two registers, one to be eliminated, and the other @@ -216,14 +192,15 @@ struct nvptx_args { #if defined HOST_WIDE_INT struct GTY(()) machine_function { - rtx_expr_list *call_args; - rtx start_call; - tree funtype; - bool has_call_with_varargs; - bool has_call_with_sc; - HOST_WIDE_INT outgoing_stdarg_size; - int ret_reg_mode; /* machine_mode not defined yet. */ - rtx axis_predicate[2]; + rtx_expr_list *call_args; /* Arg list for the current call. */ + bool doing_call; /* Within a CALL_ARGS ... CALL_ARGS_END sequence. */ + bool is_varadic; /* This call is varadic */ + bool has_varadic; /* Current function has a varadic call. */ + bool has_chain; /* Current function has outgoing static chain. */ + int num_args; /* Number of args of current call. */ + int return_mode; /* Return mode of current fn. + (machine_mode not defined yet.) */ + rtx axis_predicate[2]; /* Neutering predicates. */ }; #endif @@ -250,12 +227,6 @@ struct GTY(()) machine_function #undef ASM_APP_OFF #define ASM_APP_OFF "\t// #NO_APP \n" -#define REGISTER_NAMES \ - { \ - "%hr0", "%outargs", "%hfp", "%hr3", "%retval", "%hr5", "%hr6", "%hr7", \ - "%hr8", "%hr9", "%chain_out", "%hr11", "%chain_in", "%hr13", "%argp", "%frame" \ - } - #define DBX_REGISTER_NUMBER(N) N #define TEXT_SECTION_ASM_OP "" diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md index b0da63e389a..33a4862b98e 100644 --- a/gcc/config/nvptx/nvptx.md +++ b/gcc/config/nvptx/nvptx.md @@ -1,5 +1,5 @@ ;; Machine description for NVPTX. -;; Copyright (C) 2014-2015 Free Software Foundation, Inc. +;; Copyright (C) 2014-2016 Free Software Foundation, Inc. ;; Contributed by Bernd Schmidt <bernds@codesourcery.com> ;; ;; This file is part of GCC. @@ -20,7 +20,6 @@ (define_c_enum "unspec" [ UNSPEC_ARG_REG - UNSPEC_TO_GENERIC UNSPEC_COPYSIGN UNSPEC_LOG2 @@ -39,8 +38,6 @@ UNSPEC_DIM_SIZE - UNSPEC_SHARED_DATA - UNSPEC_BIT_CONV UNSPEC_SHUFFLE @@ -63,68 +60,27 @@ (define_attr "subregs_ok" "false,true" (const_string "false")) +;; The nvptx operand predicates, in general, don't permit subregs and +;; only literal constants, which differ from the generic ones, which +;; permit subregs and symbolc constants (as appropriate) (define_predicate "nvptx_register_operand" - (match_code "reg,subreg") + (match_code "reg") { - if (REG_P (op)) - return !HARD_REGISTER_P (op); - if (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))) - return false; - if (GET_CODE (op) == SUBREG) - return false; return register_operand (op, mode); }) -(define_predicate "nvptx_reg_or_mem_operand" - (match_code "mem,reg,subreg") +(define_predicate "nvptx_nonimmediate_operand" + (match_code "mem,reg") { - if (REG_P (op)) - return !HARD_REGISTER_P (op); - if (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))) - return false; - if (GET_CODE (op) == SUBREG) - return false; - return memory_operand (op, mode) || register_operand (op, mode); + return (REG_P (op) ? register_operand (op, mode) + : memory_operand (op, mode)); }) -;; Allow symbolic constants. -(define_predicate "symbolic_operand" - (match_code "symbol_ref,const")) - -;; Registers or constants for normal instructions. Does not allow symbolic -;; constants. (define_predicate "nvptx_nonmemory_operand" - (match_code "reg,subreg,const_int,const_double") + (match_code "reg,const_int,const_double") { - if (REG_P (op)) - return !HARD_REGISTER_P (op); - if (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))) - return false; - if (GET_CODE (op) == SUBREG) - return false; - return nonmemory_operand (op, mode); -}) - -;; A source operand for a move instruction. This is the only predicate we use -;; that accepts symbolic constants. -(define_predicate "nvptx_general_operand" - (match_code "reg,subreg,mem,const,symbol_ref,label_ref,const_int,const_double") -{ - if (REG_P (op)) - return !HARD_REGISTER_P (op); - return general_operand (op, mode); -}) - -;; A destination operand for a move instruction. This is the only destination -;; predicate that accepts the return register since it requires special handling. -(define_predicate "nvptx_nonimmediate_operand" - (match_code "reg,subreg,mem") -{ - if (REG_P (op)) - return (op != frame_pointer_rtx - && op != arg_pointer_rtx - && op != stack_pointer_rtx); - return nonimmediate_operand (op, mode); + return (REG_P (op) ? register_operand (op, mode) + : immediate_operand (op, mode)); }) (define_predicate "const0_operand" @@ -145,18 +101,10 @@ (match_code "eq,ne,le,ge,lt,gt,uneq,unle,unge,unlt,ungt,unordered,ordered")) ;; Test for a valid operand for a call instruction. -(define_special_predicate "call_insn_operand" +(define_predicate "call_insn_operand" (match_code "symbol_ref,reg") { - if (GET_CODE (op) == SYMBOL_REF) - { - tree decl = SYMBOL_REF_DECL (op); - /* This happens for libcalls. */ - if (decl == NULL_TREE) - return true; - return TREE_CODE (SYMBOL_REF_DECL (op)) == FUNCTION_DECL; - } - return true; + return REG_P (op) || SYMBOL_REF_FUNCTION_P (op); }) ;; Return true if OP is a call with parallel USEs of the argument @@ -170,11 +118,7 @@ { rtx elt = XVECEXP (op, 0, i); - if (GET_CODE (elt) != USE - || GET_CODE (XEXP (elt, 0)) != REG - || XEXP (elt, 0) == frame_pointer_rtx - || XEXP (elt, 0) == arg_pointer_rtx - || XEXP (elt, 0) == stack_pointer_rtx) + if (GET_CODE (elt) != USE || !REG_P (XEXP (elt, 0))) return false; } return true; @@ -232,10 +176,9 @@ %.\\tsetp.eq.u32\\t%0, 1, 1;") (define_insn "*mov<mode>_insn" - [(set (match_operand:QHSDIM 0 "nvptx_nonimmediate_operand" "=R,R,m") + [(set (match_operand:QHSDIM 0 "nonimmediate_operand" "=R,R,m") (match_operand:QHSDIM 1 "general_operand" "Ri,m,R"))] - "!MEM_P (operands[0]) - || (REG_P (operands[1]) && REGNO (operands[1]) > LAST_VIRTUAL_REGISTER)" + "!MEM_P (operands[0]) || REG_P (operands[1])" { if (which_alternative == 1) return "%.\\tld%A1%u1\\t%0, %1;"; @@ -247,7 +190,7 @@ [(set_attr "subregs_ok" "true")]) (define_insn "*mov<mode>_insn" - [(set (match_operand:SDFM 0 "nvptx_nonimmediate_operand" "=R,R,m") + [(set (match_operand:SDFM 0 "nonimmediate_operand" "=R,R,m") (match_operand:SDFM 1 "general_operand" "RF,m,R"))] "!MEM_P (operands[0]) || REG_P (operands[1])" { @@ -275,27 +218,11 @@ "%.\\tmov%t0\\t%0, %%ar%1;") (define_expand "mov<mode>" - [(set (match_operand:QHSDISDFM 0 "nvptx_nonimmediate_operand" "") + [(set (match_operand:QHSDISDFM 0 "nonimmediate_operand" "") (match_operand:QHSDISDFM 1 "general_operand" ""))] "" { - operands[1] = nvptx_maybe_convert_symbolic_operand (operands[1]); - /* Record the mode of the return register so that we can prevent - later optimization passes from changing it. */ - if (REG_P (operands[0]) && REGNO (operands[0]) == NVPTX_RETURN_REGNUM - && cfun) - { - if (cfun->machine->ret_reg_mode == VOIDmode) - cfun->machine->ret_reg_mode = GET_MODE (operands[0]); - else - gcc_assert (cfun->machine->ret_reg_mode == GET_MODE (operands[0])); - } - - /* Hard registers are often actually symbolic operands on this target. - Don't allow them when storing to memory. */ - if (MEM_P (operands[0]) - && (!REG_P (operands[1]) - || REGNO (operands[1]) <= LAST_VIRTUAL_REGISTER)) + if (MEM_P (operands[0]) && !REG_P (operands[1])) { rtx tmp = gen_reg_rtx (<MODE>mode); emit_move_insn (tmp, operands[1]); @@ -306,7 +233,7 @@ (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "nvptx_register_operand" "=R,R") - (zero_extend:HI (match_operand:QI 1 "nvptx_reg_or_mem_operand" "R,m")))] + (zero_extend:HI (match_operand:QI 1 "nvptx_nonimmediate_operand" "R,m")))] "" "@ %.\\tcvt.u16.u%T1\\t%0, %1; @@ -315,7 +242,7 @@ (define_insn "zero_extend<mode>si2" [(set (match_operand:SI 0 "nvptx_register_operand" "=R,R") - (zero_extend:SI (match_operand:QHIM 1 "nvptx_reg_or_mem_operand" "R,m")))] + (zero_extend:SI (match_operand:QHIM 1 "nvptx_nonimmediate_operand" "R,m")))] "" "@ %.\\tcvt.u32.u%T1\\t%0, %1; @@ -324,7 +251,7 @@ (define_insn "zero_extend<mode>di2" [(set (match_operand:DI 0 "nvptx_register_operand" "=R,R") - (zero_extend:DI (match_operand:QHSIM 1 "nvptx_reg_or_mem_operand" "R,m")))] + (zero_extend:DI (match_operand:QHSIM 1 "nvptx_nonimmediate_operand" "R,m")))] "" "@ %.\\tcvt.u64.u%T1\\t%0, %1; @@ -333,7 +260,7 @@ (define_insn "extend<mode>si2" [(set (match_operand:SI 0 "nvptx_register_operand" "=R,R") - (sign_extend:SI (match_operand:QHIM 1 "nvptx_reg_or_mem_operand" "R,m")))] + (sign_extend:SI (match_operand:QHIM 1 "nvptx_nonimmediate_operand" "R,m")))] "" "@ %.\\tcvt.s32.s%T1\\t%0, %1; @@ -342,7 +269,7 @@ (define_insn "extend<mode>di2" [(set (match_operand:DI 0 "nvptx_register_operand" "=R,R") - (sign_extend:DI (match_operand:QHSIM 1 "nvptx_reg_or_mem_operand" "R,m")))] + (sign_extend:DI (match_operand:QHSIM 1 "nvptx_nonimmediate_operand" "R,m")))] "" "@ %.\\tcvt.s64.s%T1\\t%0, %1; @@ -350,7 +277,7 @@ [(set_attr "subregs_ok" "true")]) (define_insn "trunchiqi2" - [(set (match_operand:QI 0 "nvptx_reg_or_mem_operand" "=R,m") + [(set (match_operand:QI 0 "nvptx_nonimmediate_operand" "=R,m") (truncate:QI (match_operand:HI 1 "nvptx_register_operand" "R,R")))] "" "@ @@ -359,7 +286,7 @@ [(set_attr "subregs_ok" "true")]) (define_insn "truncsi<mode>2" - [(set (match_operand:QHIM 0 "nvptx_reg_or_mem_operand" "=R,m") + [(set (match_operand:QHIM 0 "nvptx_nonimmediate_operand" "=R,m") (truncate:QHIM (match_operand:SI 1 "nvptx_register_operand" "R,R")))] "" "@ @@ -368,7 +295,7 @@ [(set_attr "subregs_ok" "true")]) (define_insn "truncdi<mode>2" - [(set (match_operand:QHSIM 0 "nvptx_reg_or_mem_operand" "=R,m") + [(set (match_operand:QHSIM 0 "nvptx_nonimmediate_operand" "=R,m") (truncate:QHSIM (match_operand:DI 1 "nvptx_register_operand" "R,R")))] "" "@ @@ -376,14 +303,6 @@ %.\\tst%A0.u%T0\\t%0, %1;" [(set_attr "subregs_ok" "true")]) -;; Pointer address space conversion -(define_insn "convaddr_<mode>" - [(set (match_operand:P 0 "nvptx_register_operand" "=R") - (unspec:P [(match_operand:P 1 "symbolic_operand" "s")] - UNSPEC_TO_GENERIC))] - "" - "%.\\tcvta%D1%t0\\t%0, %1;") - ;; Integer arithmetic (define_insn "add<mode>3" @@ -763,7 +682,7 @@ (define_insn "call_insn" [(match_parallel 2 "call_operation" - [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "Rs")) + [(call (mem:QI (match_operand 0 "call_insn_operand" "Rs")) (match_operand 1))])] "" { @@ -773,7 +692,7 @@ (define_insn "call_value_insn" [(match_parallel 3 "call_operation" [(set (match_operand 0 "nvptx_register_operand" "=R") - (call (mem:QI (match_operand:SI 1 "call_insn_operand" "Rs")) + (call (mem:QI (match_operand 1 "call_insn_operand" "Rs")) (match_operand 2)))])] "" { @@ -1169,7 +1088,7 @@ (define_expand "oacc_fork" [(set (match_operand:SI 0 "nvptx_nonmemory_operand" "") - (match_operand:SI 1 "nvptx_general_operand" "")) + (match_operand:SI 1 "general_operand" "")) (unspec_volatile:SI [(match_operand:SI 2 "const_int_operand" "")] UNSPECV_FORKED)] "" @@ -1182,7 +1101,7 @@ (define_expand "oacc_join" [(set (match_operand:SI 0 "nvptx_nonmemory_operand" "") - (match_operand:SI 1 "nvptx_general_operand" "")) + (match_operand:SI 1 "general_operand" "")) (unspec_volatile:SI [(match_operand:SI 2 "const_int_operand" "")] UNSPECV_JOIN)] "" @@ -1223,20 +1142,6 @@ "" "%.\\tmov.b64\\t%0, {%1,%2};") -(define_insn "worker_load<mode>" - [(set (match_operand:SDISDFM 0 "nvptx_register_operand" "=R") - (unspec:SDISDFM [(match_operand:SDISDFM 1 "memory_operand" "m")] - UNSPEC_SHARED_DATA))] - "" - "%.\\tld.shared%u0\\t%0, %1;") - -(define_insn "worker_store<mode>" - [(set (unspec:SDISDFM [(match_operand:SDISDFM 1 "memory_operand" "=m")] - UNSPEC_SHARED_DATA) - (match_operand:SDISDFM 0 "nvptx_register_operand" "R"))] - "" - "%.\\tst.shared%u1\\t%1, %0;") - ;; Atomic insns. (define_expand "atomic_compare_and_swap<mode>" diff --git a/gcc/config/nvptx/nvptx.opt b/gcc/config/nvptx/nvptx.opt index 342915d8095..056b9b2d003 100644 --- a/gcc/config/nvptx/nvptx.opt +++ b/gcc/config/nvptx/nvptx.opt @@ -1,5 +1,5 @@ ; Options for the NVPTX port -; Copyright (C) 2014-2015 Free Software Foundation, Inc. +; Copyright (C) 2014-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/nvptx/offload.h b/gcc/config/nvptx/offload.h index 9a749a29ef6..f3fdd294caa 100644 --- a/gcc/config/nvptx/offload.h +++ b/gcc/config/nvptx/offload.h @@ -1,6 +1,6 @@ /* Support for Nvidia PTX offloading. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/openbsd-libpthread.h b/gcc/config/openbsd-libpthread.h index e070223eb05..83993bcbffe 100644 --- a/gcc/config/openbsd-libpthread.h +++ b/gcc/config/openbsd-libpthread.h @@ -1,6 +1,6 @@ /* LIB_SPEC appropriate for OpenBSD. Include -lpthread if -pthread is specified on the command line. */ -/* Copyright (C) 2004-2015 Free Software Foundation, Inc. +/* Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/openbsd-oldgas.h b/gcc/config/openbsd-oldgas.h index 5cef1eb0b9d..34e88bfe0a4 100644 --- a/gcc/config/openbsd-oldgas.h +++ b/gcc/config/openbsd-oldgas.h @@ -1,5 +1,5 @@ /* Generic settings for a.out OpenBSD systems. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by David E. O'Brien <obrien@FreeBSD.org>. This file is part of GCC. diff --git a/gcc/config/openbsd.h b/gcc/config/openbsd.h index cf6654898eb..37ecfc43f94 100644 --- a/gcc/config/openbsd.h +++ b/gcc/config/openbsd.h @@ -1,5 +1,5 @@ /* Base configuration file for all OpenBSD targets. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/openbsd.opt b/gcc/config/openbsd.opt index 9fc149ff384..ce0604f946a 100644 --- a/gcc/config/openbsd.opt +++ b/gcc/config/openbsd.opt @@ -1,6 +1,6 @@ ; OpenBSD options. -; Copyright (C) 2010-2015 Free Software Foundation, Inc. +; Copyright (C) 2010-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pa/constraints.md b/gcc/config/pa/constraints.md index fed0b58af81..b90e8f6ddd8 100644 --- a/gcc/config/pa/constraints.md +++ b/gcc/config/pa/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for pa -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/pa/elf.h b/gcc/config/pa/elf.h index 7975cccb5bf..c091ed43b04 100644 --- a/gcc/config/pa/elf.h +++ b/gcc/config/pa/elf.h @@ -1,5 +1,5 @@ /* Definitions for ELF assembler support. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-64.h b/gcc/config/pa/pa-64.h index dec8688afa6..afe001b4228 100644 --- a/gcc/config/pa/pa-64.h +++ b/gcc/config/pa/pa-64.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for HPs using the 64bit runtime model. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-hpux.h b/gcc/config/pa/pa-hpux.h index d605f3c9adc..ac433c646e1 100644 --- a/gcc/config/pa/pa-hpux.h +++ b/gcc/config/pa/pa-hpux.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for HP-UX. - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-hpux.opt b/gcc/config/pa/pa-hpux.opt index 1ce6998a82c..cf9feb0d3de 100644 --- a/gcc/config/pa/pa-hpux.opt +++ b/gcc/config/pa/pa-hpux.opt @@ -1,6 +1,6 @@ ; Options for the HP PA-RISC port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pa/pa-hpux10.h b/gcc/config/pa/pa-hpux10.h index 1731ddc8b4d..ebb21962e96 100644 --- a/gcc/config/pa/pa-hpux10.h +++ b/gcc/config/pa/pa-hpux10.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for HP PA-RISC - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. Contributed by Tim Moore (moore@defmacro.cs.utah.edu) This file is part of GCC. diff --git a/gcc/config/pa/pa-hpux10.opt b/gcc/config/pa/pa-hpux10.opt index ce0ae84e5c1..cd26baeabad 100644 --- a/gcc/config/pa/pa-hpux10.opt +++ b/gcc/config/pa/pa-hpux10.opt @@ -1,6 +1,6 @@ ; Options specific to HP-UX 10. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pa/pa-hpux1010.h b/gcc/config/pa/pa-hpux1010.h index b446647f0f4..ebb27c6a410 100644 --- a/gcc/config/pa/pa-hpux1010.h +++ b/gcc/config/pa/pa-hpux1010.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for HP PA-RISC - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-hpux1010.opt b/gcc/config/pa/pa-hpux1010.opt index 0ae6224d688..38d07a38b24 100644 --- a/gcc/config/pa/pa-hpux1010.opt +++ b/gcc/config/pa/pa-hpux1010.opt @@ -1,6 +1,6 @@ ; Options for the HP PA-RISC port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pa/pa-hpux11.h b/gcc/config/pa/pa-hpux11.h index 31a66f4a0f7..3e5207a669d 100644 --- a/gcc/config/pa/pa-hpux11.h +++ b/gcc/config/pa/pa-hpux11.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for HP PA-RISC - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-hpux1111.h b/gcc/config/pa/pa-hpux1111.h index 4ededf38867..7e5bf77f030 100644 --- a/gcc/config/pa/pa-hpux1111.h +++ b/gcc/config/pa/pa-hpux1111.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for HP PA-RISC - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-hpux1111.opt b/gcc/config/pa/pa-hpux1111.opt index 6623182a23e..05ee5bba61e 100644 --- a/gcc/config/pa/pa-hpux1111.opt +++ b/gcc/config/pa/pa-hpux1111.opt @@ -1,6 +1,6 @@ ; Options for the HP PA-RISC port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pa/pa-hpux1131.h b/gcc/config/pa/pa-hpux1131.h index ffdb97f8dac..c81e711a838 100644 --- a/gcc/config/pa/pa-hpux1131.h +++ b/gcc/config/pa/pa-hpux1131.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for HP PA-RISC - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-hpux1131.opt b/gcc/config/pa/pa-hpux1131.opt index fefd441d033..92717797bc4 100644 --- a/gcc/config/pa/pa-hpux1131.opt +++ b/gcc/config/pa/pa-hpux1131.opt @@ -1,6 +1,6 @@ ; Options for the HP PA-RISC port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pa/pa-linux.h b/gcc/config/pa/pa-linux.h index 957a274249b..f3fd2940e79 100644 --- a/gcc/config/pa/pa-linux.h +++ b/gcc/config/pa/pa-linux.h @@ -1,5 +1,5 @@ /* Definitions for PA_RISC with ELF format - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-modes.def b/gcc/config/pa/pa-modes.def index 4456ce2b9e0..3b0a756e2fa 100644 --- a/gcc/config/pa/pa-modes.def +++ b/gcc/config/pa/pa-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for the HP Spectrum. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for Software Science at the University of Utah. diff --git a/gcc/config/pa/pa-openbsd.h b/gcc/config/pa/pa-openbsd.h index 0f2e5cf6e62..701840d9ef7 100644 --- a/gcc/config/pa/pa-openbsd.h +++ b/gcc/config/pa/pa-openbsd.h @@ -1,5 +1,5 @@ /* Definitions for PA_RISC with ELF format - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-opts.h b/gcc/config/pa/pa-opts.h index 3a425eb2a35..44fb9935727 100644 --- a/gcc/config/pa/pa-opts.h +++ b/gcc/config/pa/pa-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for HP PA. - Copyright (C) 1992-2015 Free Software Foundation, Inc. + Copyright (C) 1992-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa-protos.h b/gcc/config/pa/pa-protos.h index 82ca9b2cc30..a341be673e6 100644 --- a/gcc/config/pa/pa-protos.h +++ b/gcc/config/pa/pa-protos.h @@ -1,5 +1,5 @@ /* Prototypes for pa.c functions used in the md file & elsewhere. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 50424c769b7..8b1c8327c79 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for HPPA. - Copyright (C) 1992-2015 Free Software Foundation, Inc. + Copyright (C) 1992-2016 Free Software Foundation, Inc. Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c This file is part of GCC. @@ -1681,38 +1681,60 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg) /* Handle secondary reloads for loads/stores of FP registers from REG+D addresses where D does not fit in 5 or 14 bits, including - (subreg (mem (addr))) cases. */ + (subreg (mem (addr))) cases, and reloads for other unsupported + memory operands. */ if (scratch_reg && FP_REG_P (operand0) && (MEM_P (operand1) || (GET_CODE (operand1) == SUBREG && MEM_P (XEXP (operand1, 0))))) { - if (GET_CODE (operand1) == SUBREG) - operand1 = XEXP (operand1, 0); + rtx op1 = operand1; - /* SCRATCH_REG will hold an address and maybe the actual data. We want - it in WORD_MODE regardless of what mode it was originally given - to us. */ - scratch_reg = force_mode (word_mode, scratch_reg); + if (GET_CODE (op1) == SUBREG) + op1 = XEXP (op1, 0); - /* D might not fit in 14 bits either; for such cases load D into - scratch reg. */ - if (reg_plus_base_memory_operand (operand1, GET_MODE (operand1)) - && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))) + if (reg_plus_base_memory_operand (op1, GET_MODE (op1))) { - emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); - emit_move_insn (scratch_reg, - gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), - Pmode, - XEXP (XEXP (operand1, 0), 0), - scratch_reg)); + if (!(TARGET_PA_20 + && !TARGET_ELF32 + && INT_14_BITS (XEXP (XEXP (op1, 0), 1))) + && !INT_5_BITS (XEXP (XEXP (op1, 0), 1))) + { + /* SCRATCH_REG will hold an address and maybe the actual data. + We want it in WORD_MODE regardless of what mode it was + originally given to us. */ + scratch_reg = force_mode (word_mode, scratch_reg); + + /* D might not fit in 14 bits either; for such cases load D + into scratch reg. */ + if (!INT_14_BITS (XEXP (XEXP (op1, 0), 1))) + { + emit_move_insn (scratch_reg, XEXP (XEXP (op1, 0), 1)); + emit_move_insn (scratch_reg, + gen_rtx_fmt_ee (GET_CODE (XEXP (op1, 0)), + Pmode, + XEXP (XEXP (op1, 0), 0), + scratch_reg)); + } + else + emit_move_insn (scratch_reg, XEXP (op1, 0)); + emit_insn (gen_rtx_SET (operand0, + replace_equiv_address (op1, scratch_reg))); + return 1; + } + } + else if ((!INT14_OK_STRICT && symbolic_memory_operand (op1, VOIDmode)) + || IS_LO_SUM_DLT_ADDR_P (XEXP (op1, 0)) + || IS_INDEX_ADDR_P (XEXP (op1, 0))) + { + /* Load memory address into SCRATCH_REG. */ + scratch_reg = force_mode (word_mode, scratch_reg); + emit_move_insn (scratch_reg, XEXP (op1, 0)); + emit_insn (gen_rtx_SET (operand0, + replace_equiv_address (op1, scratch_reg))); + return 1; } - else - emit_move_insn (scratch_reg, XEXP (operand1, 0)); - emit_insn (gen_rtx_SET (operand0, - replace_equiv_address (operand1, scratch_reg))); - return 1; } else if (scratch_reg && FP_REG_P (operand1) @@ -1720,32 +1742,52 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg) || (GET_CODE (operand0) == SUBREG && MEM_P (XEXP (operand0, 0))))) { - if (GET_CODE (operand0) == SUBREG) - operand0 = XEXP (operand0, 0); + rtx op0 = operand0; - /* SCRATCH_REG will hold an address and maybe the actual data. We want - it in WORD_MODE regardless of what mode it was originally given - to us. */ - scratch_reg = force_mode (word_mode, scratch_reg); + if (GET_CODE (op0) == SUBREG) + op0 = XEXP (op0, 0); - /* D might not fit in 14 bits either; for such cases load D into - scratch reg. */ - if (reg_plus_base_memory_operand (operand0, GET_MODE (operand0)) - && !INT_14_BITS (XEXP (XEXP (operand0, 0), 1))) + if (reg_plus_base_memory_operand (op0, GET_MODE (op0))) { - emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); - emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, - 0)), - Pmode, - XEXP (XEXP (operand0, 0), - 0), - scratch_reg)); + if (!(TARGET_PA_20 + && !TARGET_ELF32 + && INT_14_BITS (XEXP (XEXP (op0, 0), 1))) + && !INT_5_BITS (XEXP (XEXP (op0, 0), 1))) + { + /* SCRATCH_REG will hold an address and maybe the actual data. + We want it in WORD_MODE regardless of what mode it was + originally given to us. */ + scratch_reg = force_mode (word_mode, scratch_reg); + + /* D might not fit in 14 bits either; for such cases load D + into scratch reg. */ + if (!INT_14_BITS (XEXP (XEXP (op0, 0), 1))) + { + emit_move_insn (scratch_reg, XEXP (XEXP (op0, 0), 1)); + emit_move_insn (scratch_reg, + gen_rtx_fmt_ee (GET_CODE (XEXP (op0, 0)), + Pmode, + XEXP (XEXP (op0, 0), 0), + scratch_reg)); + } + else + emit_move_insn (scratch_reg, XEXP (op0, 0)); + emit_insn (gen_rtx_SET (replace_equiv_address (op0, scratch_reg), + operand1)); + return 1; + } + } + else if ((!INT14_OK_STRICT && symbolic_memory_operand (op0, VOIDmode)) + || IS_LO_SUM_DLT_ADDR_P (XEXP (op0, 0)) + || IS_INDEX_ADDR_P (XEXP (op0, 0))) + { + /* Load memory address into SCRATCH_REG. */ + scratch_reg = force_mode (word_mode, scratch_reg); + emit_move_insn (scratch_reg, XEXP (op0, 0)); + emit_insn (gen_rtx_SET (replace_equiv_address (op0, scratch_reg), + operand1)); + return 1; } - else - emit_move_insn (scratch_reg, XEXP (operand0, 0)); - emit_insn (gen_rtx_SET (replace_equiv_address (operand0, scratch_reg), - operand1)); - return 1; } /* Handle secondary reloads for loads of FP registers from constant expressions by forcing the constant into memory. For the most part, @@ -1754,7 +1796,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg) Use scratch_reg to hold the address of the memory location. */ else if (scratch_reg && CONSTANT_P (operand1) - && fp_reg_operand (operand0, mode)) + && FP_REG_P (operand0)) { rtx const_mem, xoperands[2]; @@ -1830,8 +1872,9 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg) emit_move_insn (operand0, scratch_reg); return 1; } + /* Handle the most common case: storing into a register. */ - else if (register_operand (operand0, mode)) + if (register_operand (operand0, mode)) { /* Legitimize TLS symbol references. This happens for references that aren't a legitimate constant. */ diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 511ea810de6..e1d826730fd 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for the HP Spectrum. - Copyright (C) 1992-2015 Free Software Foundation, Inc. + Copyright (C) 1992-2016 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for Software Science at the University of Utah. diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 36efb84806a..dd4daa4a907 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -1,5 +1,5 @@ ;;- Machine description for HP PA-RISC architecture for GCC compiler -;; Copyright (C) 1992-2015 Free Software Foundation, Inc. +;; Copyright (C) 1992-2016 Free Software Foundation, Inc. ;; Contributed by the Center for Software Science at the University ;; of Utah. @@ -692,237 +692,6 @@ (include "predicates.md") (include "constraints.md") -;; Atomic instructions - -;; All memory loads and stores access storage atomically except -;; for one exception. The STORE BYTES, STORE DOUBLE BYTES, and -;; doubleword loads and stores are not guaranteed to be atomic -;; when referencing the I/O address space. - -;; The kernel cmpxchg operation on linux is not atomic with respect to -;; memory stores on SMP machines, so we must do stores using a cmpxchg -;; operation. - -;; Implement atomic QImode store using exchange. - -(define_expand "atomic_storeqi" - [(match_operand:QI 0 "memory_operand") ;; memory - (match_operand:QI 1 "register_operand") ;; val out - (match_operand:SI 2 "const_int_operand")] ;; model - "" -{ - if (TARGET_SYNC_LIBCALL) - { - rtx mem = operands[0]; - rtx val = operands[1]; - if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val)) - DONE; - } - FAIL; -}) - -;; Implement atomic HImode stores using exchange. - -(define_expand "atomic_storehi" - [(match_operand:HI 0 "memory_operand") ;; memory - (match_operand:HI 1 "register_operand") ;; val out - (match_operand:SI 2 "const_int_operand")] ;; model - "" -{ - if (TARGET_SYNC_LIBCALL) - { - rtx mem = operands[0]; - rtx val = operands[1]; - if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val)) - DONE; - } - FAIL; -}) - -;; Implement atomic SImode store using exchange. - -(define_expand "atomic_storesi" - [(match_operand:SI 0 "memory_operand") ;; memory - (match_operand:SI 1 "register_operand") ;; val out - (match_operand:SI 2 "const_int_operand")] ;; model - "" -{ - if (TARGET_SYNC_LIBCALL) - { - rtx mem = operands[0]; - rtx val = operands[1]; - if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val)) - DONE; - } - FAIL; -}) - -;; Implement atomic SFmode store using exchange. - -(define_expand "atomic_storesf" - [(match_operand:SF 0 "memory_operand") ;; memory - (match_operand:SF 1 "register_operand") ;; val out - (match_operand:SI 2 "const_int_operand")] ;; model - "" -{ - if (TARGET_SYNC_LIBCALL) - { - rtx mem = operands[0]; - rtx val = operands[1]; - if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val)) - DONE; - } - FAIL; -}) - -;; Implement atomic DImode load using 64-bit floating point load. - -(define_expand "atomic_loaddi" - [(match_operand:DI 0 "register_operand") ;; val out - (match_operand:DI 1 "memory_operand") ;; memory - (match_operand:SI 2 "const_int_operand")] ;; model - "" -{ - enum memmodel model; - - if (TARGET_64BIT || TARGET_SOFT_FLOAT) - FAIL; - - model = memmodel_from_int (INTVAL (operands[2])); - operands[1] = force_reg (SImode, XEXP (operands[1], 0)); - expand_mem_thread_fence (model); - emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); - if (is_mm_seq_cst (model)) - expand_mem_thread_fence (model); - DONE; -}) - -(define_insn "atomic_loaddi_1" - [(set (match_operand:DI 0 "register_operand" "=f,r") - (mem:DI (match_operand:SI 1 "register_operand" "r,r"))) - (clobber (match_scratch:DI 2 "=X,f"))] - "!TARGET_64BIT && !TARGET_SOFT_FLOAT" - "@ - {fldds|fldd} 0(%1),%0 - {fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0" - [(set_attr "type" "move,move") - (set_attr "length" "4,16")]) - -;; Implement atomic DImode store. - -(define_expand "atomic_storedi" - [(match_operand:DI 0 "memory_operand") ;; memory - (match_operand:DI 1 "register_operand") ;; val out - (match_operand:SI 2 "const_int_operand")] ;; model - "" -{ - enum memmodel model; - - if (TARGET_SYNC_LIBCALL) - { - rtx mem = operands[0]; - rtx val = operands[1]; - if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val)) - DONE; - } - - if (TARGET_64BIT || TARGET_SOFT_FLOAT) - FAIL; - - model = memmodel_from_int (INTVAL (operands[2])); - operands[0] = force_reg (SImode, XEXP (operands[0], 0)); - expand_mem_thread_fence (model); - emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); - if (is_mm_seq_cst (model)) - expand_mem_thread_fence (model); - DONE; -}) - -(define_insn "atomic_storedi_1" - [(set (mem:DI (match_operand:SI 0 "register_operand" "r,r")) - (match_operand:DI 1 "register_operand" "f,r")) - (clobber (match_scratch:DI 2 "=X,f"))] - "!TARGET_64BIT && !TARGET_SOFT_FLOAT && !TARGET_SYNC_LIBCALL" - "@ - {fstds|fstd} %1,0(%0) - {stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)" - [(set_attr "type" "move,move") - (set_attr "length" "4,16")]) - -;; Implement atomic DFmode load using 64-bit floating point load. - -(define_expand "atomic_loaddf" - [(match_operand:DF 0 "register_operand") ;; val out - (match_operand:DF 1 "memory_operand") ;; memory - (match_operand:SI 2 "const_int_operand")] ;; model - "" -{ - enum memmodel model; - - if (TARGET_64BIT || TARGET_SOFT_FLOAT) - FAIL; - - model = memmodel_from_int (INTVAL (operands[2])); - operands[1] = force_reg (SImode, XEXP (operands[1], 0)); - expand_mem_thread_fence (model); - emit_insn (gen_atomic_loaddf_1 (operands[0], operands[1])); - if (is_mm_seq_cst (model)) - expand_mem_thread_fence (model); - DONE; -}) - -(define_insn "atomic_loaddf_1" - [(set (match_operand:DF 0 "register_operand" "=f,r") - (mem:DF (match_operand:SI 1 "register_operand" "r,r"))) - (clobber (match_scratch:DF 2 "=X,f"))] - "!TARGET_64BIT && !TARGET_SOFT_FLOAT" - "@ - {fldds|fldd} 0(%1),%0 - {fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0" - [(set_attr "type" "move,move") - (set_attr "length" "4,16")]) - -;; Implement atomic DFmode store using 64-bit floating point store. - -(define_expand "atomic_storedf" - [(match_operand:DF 0 "memory_operand") ;; memory - (match_operand:DF 1 "register_operand") ;; val out - (match_operand:SI 2 "const_int_operand")] ;; model - "" -{ - enum memmodel model; - - if (TARGET_SYNC_LIBCALL) - { - rtx mem = operands[0]; - rtx val = operands[1]; - if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val)) - DONE; - } - - if (TARGET_64BIT || TARGET_SOFT_FLOAT) - FAIL; - - model = memmodel_from_int (INTVAL (operands[2])); - operands[0] = force_reg (SImode, XEXP (operands[0], 0)); - expand_mem_thread_fence (model); - emit_insn (gen_atomic_storedf_1 (operands[0], operands[1])); - if (is_mm_seq_cst (model)) - expand_mem_thread_fence (model); - DONE; -}) - -(define_insn "atomic_storedf_1" - [(set (mem:DF (match_operand:SI 0 "register_operand" "r,r")) - (match_operand:DF 1 "register_operand" "f,r")) - (clobber (match_scratch:DF 2 "=X,f"))] - "!TARGET_64BIT && !TARGET_SOFT_FLOAT" - "@ - {fstds|fstd} %1,0(%0) - {stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)" - [(set_attr "type" "move,move") - (set_attr "length" "4,16")]) - ;; Compare instructions. ;; This controls RTL generation and register allocation. @@ -9930,3 +9699,238 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0" [(set_attr "type" "multi") (set_attr "length" "8")]) + +;; Atomic instructions + +;; All memory loads and stores access storage atomically except +;; for one exception. The STORE BYTES, STORE DOUBLE BYTES, and +;; doubleword loads and stores are not guaranteed to be atomic +;; when referencing the I/O address space. + +;; The kernel cmpxchg operation on linux is not atomic with respect to +;; memory stores on SMP machines, so we must do stores using a cmpxchg +;; operation. + +;; These patterns are at the bottom so the non atomic versions are preferred. + +;; Implement atomic QImode store using exchange. + +(define_expand "atomic_storeqi" + [(match_operand:QI 0 "memory_operand") ;; memory + (match_operand:QI 1 "register_operand") ;; val out + (match_operand:SI 2 "const_int_operand")] ;; model + "" +{ + if (TARGET_SYNC_LIBCALL) + { + rtx mem = operands[0]; + rtx val = operands[1]; + if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val)) + DONE; + } + FAIL; +}) + +;; Implement atomic HImode stores using exchange. + +(define_expand "atomic_storehi" + [(match_operand:HI 0 "memory_operand") ;; memory + (match_operand:HI 1 "register_operand") ;; val out + (match_operand:SI 2 "const_int_operand")] ;; model + "" +{ + if (TARGET_SYNC_LIBCALL) + { + rtx mem = operands[0]; + rtx val = operands[1]; + if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val)) + DONE; + } + FAIL; +}) + +;; Implement atomic SImode store using exchange. + +(define_expand "atomic_storesi" + [(match_operand:SI 0 "memory_operand") ;; memory + (match_operand:SI 1 "register_operand") ;; val out + (match_operand:SI 2 "const_int_operand")] ;; model + "" +{ + if (TARGET_SYNC_LIBCALL) + { + rtx mem = operands[0]; + rtx val = operands[1]; + if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val)) + DONE; + } + FAIL; +}) + +;; Implement atomic SFmode store using exchange. + +(define_expand "atomic_storesf" + [(match_operand:SF 0 "memory_operand") ;; memory + (match_operand:SF 1 "register_operand") ;; val out + (match_operand:SI 2 "const_int_operand")] ;; model + "" +{ + if (TARGET_SYNC_LIBCALL) + { + rtx mem = operands[0]; + rtx val = operands[1]; + if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val)) + DONE; + } + FAIL; +}) + +;; Implement atomic DImode load using 64-bit floating point load. + +(define_expand "atomic_loaddi" + [(match_operand:DI 0 "register_operand") ;; val out + (match_operand:DI 1 "memory_operand") ;; memory + (match_operand:SI 2 "const_int_operand")] ;; model + "" +{ + enum memmodel model; + + if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT) + FAIL; + + model = memmodel_from_int (INTVAL (operands[2])); + operands[1] = force_reg (SImode, XEXP (operands[1], 0)); + expand_mem_thread_fence (model); + emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); + if (is_mm_seq_cst (model)) + expand_mem_thread_fence (model); + DONE; +}) + +(define_insn "atomic_loaddi_1" + [(set (match_operand:DI 0 "register_operand" "=f,r") + (mem:DI (match_operand:SI 1 "register_operand" "r,r"))) + (clobber (match_scratch:DI 2 "=X,f"))] + "!TARGET_64BIT && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT" + "@ + {fldds|fldd} 0(%1),%0 + {fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0" + [(set_attr "type" "move,move") + (set_attr "length" "4,16")]) + +;; Implement atomic DImode store. + +(define_expand "atomic_storedi" + [(match_operand:DI 0 "memory_operand") ;; memory + (match_operand:DI 1 "register_operand") ;; val out + (match_operand:SI 2 "const_int_operand")] ;; model + "" +{ + enum memmodel model; + + if (TARGET_SYNC_LIBCALL) + { + rtx mem = operands[0]; + rtx val = operands[1]; + if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val)) + DONE; + } + + if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT) + FAIL; + + model = memmodel_from_int (INTVAL (operands[2])); + operands[0] = force_reg (SImode, XEXP (operands[0], 0)); + expand_mem_thread_fence (model); + emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); + if (is_mm_seq_cst (model)) + expand_mem_thread_fence (model); + DONE; +}) + +(define_insn "atomic_storedi_1" + [(set (mem:DI (match_operand:SI 0 "register_operand" "r,r")) + (match_operand:DI 1 "register_operand" "f,r")) + (clobber (match_scratch:DI 2 "=X,f"))] + "!TARGET_64BIT && !TARGET_DISABLE_FPREGS + && !TARGET_SOFT_FLOAT && !TARGET_SYNC_LIBCALL" + "@ + {fstds|fstd} %1,0(%0) + {stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)" + [(set_attr "type" "move,move") + (set_attr "length" "4,16")]) + +;; Implement atomic DFmode load using 64-bit floating point load. + +(define_expand "atomic_loaddf" + [(match_operand:DF 0 "register_operand") ;; val out + (match_operand:DF 1 "memory_operand") ;; memory + (match_operand:SI 2 "const_int_operand")] ;; model + "" +{ + enum memmodel model; + + if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT) + FAIL; + + model = memmodel_from_int (INTVAL (operands[2])); + operands[1] = force_reg (SImode, XEXP (operands[1], 0)); + expand_mem_thread_fence (model); + emit_insn (gen_atomic_loaddf_1 (operands[0], operands[1])); + if (is_mm_seq_cst (model)) + expand_mem_thread_fence (model); + DONE; +}) + +(define_insn "atomic_loaddf_1" + [(set (match_operand:DF 0 "register_operand" "=f,r") + (mem:DF (match_operand:SI 1 "register_operand" "r,r"))) + (clobber (match_scratch:DF 2 "=X,f"))] + "!TARGET_64BIT && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT" + "@ + {fldds|fldd} 0(%1),%0 + {fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0" + [(set_attr "type" "move,move") + (set_attr "length" "4,16")]) + +;; Implement atomic DFmode store using 64-bit floating point store. + +(define_expand "atomic_storedf" + [(match_operand:DF 0 "memory_operand") ;; memory + (match_operand:DF 1 "register_operand") ;; val out + (match_operand:SI 2 "const_int_operand")] ;; model + "" +{ + enum memmodel model; + + if (TARGET_SYNC_LIBCALL) + { + rtx mem = operands[0]; + rtx val = operands[1]; + if (pa_maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val)) + DONE; + } + + if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT) + FAIL; + + model = memmodel_from_int (INTVAL (operands[2])); + operands[0] = force_reg (SImode, XEXP (operands[0], 0)); + expand_mem_thread_fence (model); + emit_insn (gen_atomic_storedf_1 (operands[0], operands[1])); + if (is_mm_seq_cst (model)) + expand_mem_thread_fence (model); + DONE; +}) + +(define_insn "atomic_storedf_1" + [(set (mem:DF (match_operand:SI 0 "register_operand" "r,r")) + (match_operand:DF 1 "register_operand" "f,r")) + (clobber (match_scratch:DF 2 "=X,f"))] + "!TARGET_64BIT && !TARGET_DISABLE_FPREGS + && !TARGET_SOFT_FLOAT && !TARGET_SYNC_LIBCALL" + "@ + {fstds|fstd} %1,0(%0) + {stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)" + [(set_attr "type" "move,move") + (set_attr "length" "4,16")]) diff --git a/gcc/config/pa/pa.opt b/gcc/config/pa/pa.opt index 055c5697e55..9370b40ae80 100644 --- a/gcc/config/pa/pa.opt +++ b/gcc/config/pa/pa.opt @@ -1,6 +1,6 @@ ; Options for the HP PA-RISC port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pa/pa32-linux.h b/gcc/config/pa/pa32-linux.h index 5d9a72f2b38..9c3ec00dcb9 100644 --- a/gcc/config/pa/pa32-linux.h +++ b/gcc/config/pa/pa32-linux.h @@ -1,5 +1,5 @@ /* Definitions for PA_RISC with ELF-32 format - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa32-openbsd.h b/gcc/config/pa/pa32-openbsd.h index 8a84cdc95bc..b96697e1d0b 100644 --- a/gcc/config/pa/pa32-openbsd.h +++ b/gcc/config/pa/pa32-openbsd.h @@ -1,5 +1,5 @@ /* Definitions for PA_RISC with ELF-32 format - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h index 6c9fd7b856b..19c04fce677 100644 --- a/gcc/config/pa/pa32-regs.h +++ b/gcc/config/pa/pa32-regs.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2000-2015 Free Software Foundation, Inc. +/* Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa64-hpux.h b/gcc/config/pa/pa64-hpux.h index 0af5c1703bc..a5ccb4aaec7 100644 --- a/gcc/config/pa/pa64-hpux.h +++ b/gcc/config/pa/pa64-hpux.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for HPs running HPUX using the 64bit runtime model. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa64-hpux.opt b/gcc/config/pa/pa64-hpux.opt index 8e65a41b971..eb720af1366 100644 --- a/gcc/config/pa/pa64-hpux.opt +++ b/gcc/config/pa/pa64-hpux.opt @@ -1,6 +1,6 @@ ; Options for the HP PA-RISC port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pa/pa64-linux.h b/gcc/config/pa/pa64-linux.h index ff153b22d58..540bfa64c6c 100644 --- a/gcc/config/pa/pa64-linux.h +++ b/gcc/config/pa/pa64-linux.h @@ -1,5 +1,5 @@ /* Definitions for PA_RISC with ELF format on 64-bit Linux - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h index 731ec08dc00..b3a58a67d0d 100644 --- a/gcc/config/pa/pa64-regs.h +++ b/gcc/config/pa/pa64-regs.h @@ -1,5 +1,5 @@ /* Configuration for GCC-compiler for PA-RISC. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pa/predicates.md b/gcc/config/pa/predicates.md index bbbaa852b25..fbef6aee14b 100644 --- a/gcc/config/pa/predicates.md +++ b/gcc/config/pa/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for HP PA-RISC. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/pa/som.h b/gcc/config/pa/som.h index 8a0146a0c21..96145399eee 100644 --- a/gcc/config/pa/som.h +++ b/gcc/config/pa/som.h @@ -1,5 +1,5 @@ /* Definitions for SOM assembler support. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/pdp11/constraints.md b/gcc/config/pdp11/constraints.md index 09e55190c63..781e37f5309 100644 --- a/gcc/config/pdp11/constraints.md +++ b/gcc/config/pdp11/constraints.md @@ -1,5 +1,5 @@ ;;- Constraint definitions for the pdp11 for GNU C compiler -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). ;; This file is part of GCC. diff --git a/gcc/config/pdp11/pdp11-modes.def b/gcc/config/pdp11/pdp11-modes.def index fc31485549f..b42dadcd240 100644 --- a/gcc/config/pdp11/pdp11-modes.def +++ b/gcc/config/pdp11/pdp11-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for the pdp-11 - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). This file is part of GCC. diff --git a/gcc/config/pdp11/pdp11-protos.h b/gcc/config/pdp11/pdp11-protos.h index aca3d828e0b..dc934ef4bdc 100644 --- a/gcc/config/pdp11/pdp11-protos.h +++ b/gcc/config/pdp11/pdp11-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for the pdp-11 - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). This file is part of GCC. diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c index 9a1aaebb6b5..ec3d61a03ed 100644 --- a/gcc/config/pdp11/pdp11.c +++ b/gcc/config/pdp11/pdp11.c @@ -1,5 +1,5 @@ /* Subroutines for gcc2 for pdp11. - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). This file is part of GCC. diff --git a/gcc/config/pdp11/pdp11.h b/gcc/config/pdp11/pdp11.h index 8339f1c8dc9..e93d59b2da9 100644 --- a/gcc/config/pdp11/pdp11.h +++ b/gcc/config/pdp11/pdp11.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for the pdp-11 - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). This file is part of GCC. diff --git a/gcc/config/pdp11/pdp11.md b/gcc/config/pdp11/pdp11.md index 8af2fd5b9f8..3f24b51477f 100644 --- a/gcc/config/pdp11/pdp11.md +++ b/gcc/config/pdp11/pdp11.md @@ -1,5 +1,5 @@ ;;- Machine description for the pdp11 for GNU C compiler -;; Copyright (C) 1994-2015 Free Software Foundation, Inc. +;; Copyright (C) 1994-2016 Free Software Foundation, Inc. ;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). ;; This file is part of GCC. diff --git a/gcc/config/pdp11/pdp11.opt b/gcc/config/pdp11/pdp11.opt index ff27a9f4b42..6992003a113 100644 --- a/gcc/config/pdp11/pdp11.opt +++ b/gcc/config/pdp11/pdp11.opt @@ -1,6 +1,6 @@ ; Options for the PDP11 port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/pdp11/predicates.md b/gcc/config/pdp11/predicates.md index 8e2a3d2f2c5..93199d52425 100644 --- a/gcc/config/pdp11/predicates.md +++ b/gcc/config/pdp11/predicates.md @@ -1,5 +1,5 @@ ;;- Predicate definitions for the pdp11 for GNU C compiler -;; Copyright (C) 1994-2015 Free Software Foundation, Inc. +;; Copyright (C) 1994-2016 Free Software Foundation, Inc. ;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). ;; This file is part of GCC. diff --git a/gcc/config/pdp11/t-pdp11 b/gcc/config/pdp11/t-pdp11 index 518739c0f9f..f63657e5da1 100644 --- a/gcc/config/pdp11/t-pdp11 +++ b/gcc/config/pdp11/t-pdp11 @@ -1,4 +1,4 @@ -# Copyright (C) 1995-2015 Free Software Foundation, Inc. +# Copyright (C) 1995-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/print-sysroot-suffix.sh b/gcc/config/print-sysroot-suffix.sh index 3f8bd94d794..f764a8288fa 100644 --- a/gcc/config/print-sysroot-suffix.sh +++ b/gcc/config/print-sysroot-suffix.sh @@ -3,7 +3,7 @@ # Arguments are MULTILIB_OSDIRNAMES, MULTILIB_OPTIONS, MULTILIB_MATCHES, # and MULTILIB_REUSE. -# Copyright (C) 2009-2015 Free Software Foundation, Inc. +# Copyright (C) 2009-2016 Free Software Foundation, Inc. # This file is part of GCC. diff --git a/gcc/config/rl78/constraints.md b/gcc/config/rl78/constraints.md index 93c5f32ad47..f0eb85f5cbf 100644 --- a/gcc/config/rl78/constraints.md +++ b/gcc/config/rl78/constraints.md @@ -1,5 +1,5 @@ ;; Machine Description for Renesas RL78 processors -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/rl78/predicates.md b/gcc/config/rl78/predicates.md index 66e7e44827d..b01e94ebb44 100644 --- a/gcc/config/rl78/predicates.md +++ b/gcc/config/rl78/predicates.md @@ -1,5 +1,5 @@ ;; Machine Description for Renesas RL78 processors -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/rl78/rl78-c.c b/gcc/config/rl78/rl78-c.c index 53568c69178..226d728e7ff 100644 --- a/gcc/config/rl78/rl78-c.c +++ b/gcc/config/rl78/rl78-c.c @@ -1,5 +1,5 @@ /* RL78 C-specific support - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/rl78/rl78-expand.md b/gcc/config/rl78/rl78-expand.md index 67e6620bdf6..331eec1e902 100644 --- a/gcc/config/rl78/rl78-expand.md +++ b/gcc/config/rl78/rl78-expand.md @@ -1,5 +1,5 @@ ;; Machine Description for Renesas RL78 processors -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/rl78/rl78-opts.h b/gcc/config/rl78/rl78-opts.h index 826a1734555..9fe1f2b5fef 100644 --- a/gcc/config/rl78/rl78-opts.h +++ b/gcc/config/rl78/rl78-opts.h @@ -1,5 +1,5 @@ /* GCC option-handling definitions for the Renesas RL78 processor. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rl78/rl78-protos.h b/gcc/config/rl78/rl78-protos.h index 7a8b4c9e238..c4860df69c4 100644 --- a/gcc/config/rl78/rl78-protos.h +++ b/gcc/config/rl78/rl78-protos.h @@ -1,5 +1,5 @@ /* Prototypes for Renesas RL78 processors - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/rl78/rl78-real.md b/gcc/config/rl78/rl78-real.md index 8deb1bd20c2..aacaefff9e8 100644 --- a/gcc/config/rl78/rl78-real.md +++ b/gcc/config/rl78/rl78-real.md @@ -1,5 +1,5 @@ ;; Machine Description for Renesas RL78 processors -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/rl78/rl78-virt.md b/gcc/config/rl78/rl78-virt.md index a26aa1da85d..e2e7f4750e2 100644 --- a/gcc/config/rl78/rl78-virt.md +++ b/gcc/config/rl78/rl78-virt.md @@ -1,5 +1,5 @@ ;; Machine Description for Renesas RL78 processors -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c index 0735d277cb9..13c22539268 100644 --- a/gcc/config/rl78/rl78.c +++ b/gcc/config/rl78/rl78.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on Renesas RL78 processors. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/rl78/rl78.h b/gcc/config/rl78/rl78.h index 6c72fac938b..ff9e7646a44 100644 --- a/gcc/config/rl78/rl78.h +++ b/gcc/config/rl78/rl78.h @@ -1,5 +1,5 @@ /* GCC backend definitions for the Renesas RL78 processor. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/rl78/rl78.md b/gcc/config/rl78/rl78.md index 735c19f81ee..739f6057b92 100644 --- a/gcc/config/rl78/rl78.md +++ b/gcc/config/rl78/rl78.md @@ -1,5 +1,5 @@ ;; Machine Description for Renesas RL78 processors -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/rl78/rl78.opt b/gcc/config/rl78/rl78.opt index 9d7292b2528..a8e53ee0735 100644 --- a/gcc/config/rl78/rl78.opt +++ b/gcc/config/rl78/rl78.opt @@ -1,5 +1,5 @@ ; Command line options for the Renesas RL78 port of GCC. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; Contributed by Red Hat. ; ; This file is part of GCC. diff --git a/gcc/config/rl78/t-rl78 b/gcc/config/rl78/t-rl78 index bd8fab430e0..d90cc788b0b 100644 --- a/gcc/config/rl78/t-rl78 +++ b/gcc/config/rl78/t-rl78 @@ -1,5 +1,5 @@ # Makefile fragment for building GCC for the Renesas RL78 target. -# Copyright (C) 2011-2015 Free Software Foundation, Inc. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. # Contributed by Red Hat. # # This file is part of GCC. diff --git a/gcc/config/rpath.opt b/gcc/config/rpath.opt index f5c580bdb34..e211f559598 100644 --- a/gcc/config/rpath.opt +++ b/gcc/config/rpath.opt @@ -1,6 +1,6 @@ ; -rpath option to the driver. -; Copyright (C) 2010-2015 Free Software Foundation, Inc. +; Copyright (C) 2010-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md index eb308f3ff0e..91e5cffaa32 100644 --- a/gcc/config/rs6000/40x.md +++ b/gcc/config/rs6000/40x.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM PowerPC 403 and PowerPC 405 processors. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md index 8df19dfef40..6d07ef3ea3c 100644 --- a/gcc/config/rs6000/440.md +++ b/gcc/config/rs6000/440.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM PowerPC 440 processor. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/rs6000/476.h b/gcc/config/rs6000/476.h index 563653df928..da9eb1f8ac8 100644 --- a/gcc/config/rs6000/476.h +++ b/gcc/config/rs6000/476.h @@ -1,5 +1,5 @@ /* Enable IBM PowerPC 476 support. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Peter Bergner (bergner@vnet.ibm.com) This file is part of GCC. diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md index cbf8d4d72ea..8c266b992da 100644 --- a/gcc/config/rs6000/476.md +++ b/gcc/config/rs6000/476.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM PowerPC 476 processor. -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by Peter Bergner (bergner@vnet.ibm.com). ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/476.opt b/gcc/config/rs6000/476.opt index 329f71d92e8..52562439e49 100644 --- a/gcc/config/rs6000/476.opt +++ b/gcc/config/rs6000/476.opt @@ -1,6 +1,6 @@ ; IBM PowerPC 476 options. ; -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; Contributed by Peter Bergner (bergner@vnet.ibm.com) ; ; This file is part of GCC. diff --git a/gcc/config/rs6000/601.md b/gcc/config/rs6000/601.md index 95dc045b7d5..e34c9bf20f1 100644 --- a/gcc/config/rs6000/601.md +++ b/gcc/config/rs6000/601.md @@ -1,5 +1,5 @@ ;; Scheduling description for PowerPC 601 processor. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md index 2776049c76f..3b07461bf0e 100644 --- a/gcc/config/rs6000/603.md +++ b/gcc/config/rs6000/603.md @@ -1,5 +1,5 @@ ;; Scheduling description for PowerPC 603 processor. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/6xx.md b/gcc/config/rs6000/6xx.md index b36c09ce350..29893aeeefd 100644 --- a/gcc/config/rs6000/6xx.md +++ b/gcc/config/rs6000/6xx.md @@ -1,6 +1,6 @@ ;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620, ;; and PowerPC 630 processors. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md index b5282093f42..81463693999 100644 --- a/gcc/config/rs6000/7450.md +++ b/gcc/config/rs6000/7450.md @@ -1,5 +1,5 @@ ;; Scheduling description for Motorola PowerPC 7450 processor. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/750cl.h b/gcc/config/rs6000/750cl.h index 1b0a782c68a..b19f89c7fb5 100644 --- a/gcc/config/rs6000/750cl.h +++ b/gcc/config/rs6000/750cl.h @@ -1,5 +1,5 @@ /* Enable 750cl paired single support. - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. Contributed by Revital Eres (eres@il.ibm.com) This file is part of GCC. diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md index 84dff6f4b14..1da48b77fd9 100644 --- a/gcc/config/rs6000/7xx.md +++ b/gcc/config/rs6000/7xx.md @@ -1,5 +1,5 @@ ;; Scheduling description for Motorola PowerPC 750 and PowerPC 7400 processors. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/8540.md b/gcc/config/rs6000/8540.md index bfc38342719..ae4e45f89bb 100644 --- a/gcc/config/rs6000/8540.md +++ b/gcc/config/rs6000/8540.md @@ -1,5 +1,5 @@ ;; Pipeline description for Motorola PowerPC 8540 processor. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/a2.md b/gcc/config/rs6000/a2.md index da62cd893a5..1fcf1cfb204 100644 --- a/gcc/config/rs6000/a2.md +++ b/gcc/config/rs6000/a2.md @@ -1,5 +1,5 @@ ;; Scheduling description for PowerPC A2 processors. -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by Ben Elliston (bje@au.ibm.com) ;; This file is part of GCC. diff --git a/gcc/config/rs6000/aix-stdint.h b/gcc/config/rs6000/aix-stdint.h index 0e4572d0f98..21032a8f6e6 100644 --- a/gcc/config/rs6000/aix-stdint.h +++ b/gcc/config/rs6000/aix-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on systems using AIX. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/aix.h b/gcc/config/rs6000/aix.h index 375a13edb27..b2542360e79 100644 --- a/gcc/config/rs6000/aix.h +++ b/gcc/config/rs6000/aix.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000 POWER running AIX. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/aix43.h b/gcc/config/rs6000/aix43.h index 5bcd40fdd49..30eb47eb195 100644 --- a/gcc/config/rs6000/aix43.h +++ b/gcc/config/rs6000/aix43.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000 POWER running AIX version 4.3. - Copyright (C) 1998-2015 Free Software Foundation, Inc. + Copyright (C) 1998-2016 Free Software Foundation, Inc. Contributed by David Edelsohn (edelsohn@gnu.org). This file is part of GCC. diff --git a/gcc/config/rs6000/aix51.h b/gcc/config/rs6000/aix51.h index 12666265db2..b128219708a 100644 --- a/gcc/config/rs6000/aix51.h +++ b/gcc/config/rs6000/aix51.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000 POWER running AIX V5. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by David Edelsohn (edelsohn@gnu.org). This file is part of GCC. diff --git a/gcc/config/rs6000/aix52.h b/gcc/config/rs6000/aix52.h index ac365b7e158..f1893c70b0d 100644 --- a/gcc/config/rs6000/aix52.h +++ b/gcc/config/rs6000/aix52.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000 POWER running AIX V5.2. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by David Edelsohn (edelsohn@gnu.org). This file is part of GCC. diff --git a/gcc/config/rs6000/aix53.h b/gcc/config/rs6000/aix53.h index d9aa3c20f75..50e77e79051 100644 --- a/gcc/config/rs6000/aix53.h +++ b/gcc/config/rs6000/aix53.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000 POWER running AIX V5.3. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by David Edelsohn (edelsohn@gnu.org). This file is part of GCC. diff --git a/gcc/config/rs6000/aix61.h b/gcc/config/rs6000/aix61.h index 46bdcf50035..0c9e7f0829b 100644 --- a/gcc/config/rs6000/aix61.h +++ b/gcc/config/rs6000/aix61.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000 POWER running AIX V6.1. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by David Edelsohn (edelsohn@gnu.org). This file is part of GCC. diff --git a/gcc/config/rs6000/aix64.opt b/gcc/config/rs6000/aix64.opt index c07bd54c6d9..2e8e3895bdd 100644 --- a/gcc/config/rs6000/aix64.opt +++ b/gcc/config/rs6000/aix64.opt @@ -1,6 +1,6 @@ ; Options for the 64-bit flavor of AIX. ; -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; Contributed by Aldy Hernandez <aldy@quesejoda.com>. ; ; This file is part of GCC. diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index 2e676b0f3e0..132cb6bb28e 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000 POWER running AIX V7.1. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by David Edelsohn (edelsohn@gnu.org). This file is part of GCC. diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index 1c00099c78d..ea6af8d192d 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -1,5 +1,5 @@ /* PowerPC AltiVec include file. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldyh@redhat.com). Rewritten by Paolo Bonzini (bonzini@gnu.org). diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 5f6c0f5540e..d1f6acff977 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1,5 +1,5 @@ ;; AltiVec patterns. -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; Contributed by Aldy Hernandez (aldy@quesejoda.com) ;; This file is part of GCC. @@ -1933,10 +1933,10 @@ [(set_attr "type" "vecfloat")]) (define_expand "altivec_vperm_<mode>" - [(set (match_operand:VM 0 "register_operand" "=v") - (unspec:VM [(match_operand:VM 1 "register_operand" "v") - (match_operand:VM 2 "register_operand" "v") - (match_operand:V16QI 3 "register_operand" "v")] + [(set (match_operand:VM 0 "register_operand" "") + (unspec:VM [(match_operand:VM 1 "register_operand" "") + (match_operand:VM 2 "register_operand" "") + (match_operand:V16QI 3 "register_operand" "")] UNSPEC_VPERM))] "TARGET_ALTIVEC" { @@ -1947,31 +1947,40 @@ } }) +;; Slightly prefer vperm, since the target does not overlap the source (define_insn "*altivec_vperm_<mode>_internal" - [(set (match_operand:VM 0 "register_operand" "=v") - (unspec:VM [(match_operand:VM 1 "register_operand" "v") - (match_operand:VM 2 "register_operand" "v") - (match_operand:V16QI 3 "register_operand" "v")] + [(set (match_operand:VM 0 "register_operand" "=v,?wo,?&wo") + (unspec:VM [(match_operand:VM 1 "register_operand" "v,0,wo") + (match_operand:VM 2 "register_operand" "v,wo,wo") + (match_operand:V16QI 3 "register_operand" "v,wo,wo")] UNSPEC_VPERM))] "TARGET_ALTIVEC" - "vperm %0,%1,%2,%3" - [(set_attr "type" "vecperm")]) + "@ + vperm %0,%1,%2,%3 + xxperm %x0,%x2,%x3 + xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3" + [(set_attr "type" "vecperm") + (set_attr "length" "4,4,8")]) (define_insn "altivec_vperm_v8hiv16qi" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:V16QI 3 "register_operand" "v")] + [(set (match_operand:V16QI 0 "register_operand" "=v,?wo,?&wo") + (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,0,wo") + (match_operand:V8HI 2 "register_operand" "v,wo,wo") + (match_operand:V16QI 3 "register_operand" "v,wo,wo")] UNSPEC_VPERM))] "TARGET_ALTIVEC" - "vperm %0,%1,%2,%3" - [(set_attr "type" "vecperm")]) + "@ + vperm %0,%1,%2,%3 + xxperm %x0,%x2,%x3 + xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3" + [(set_attr "type" "vecperm") + (set_attr "length" "4,4,8")]) (define_expand "altivec_vperm_<mode>_uns" - [(set (match_operand:VM 0 "register_operand" "=v") - (unspec:VM [(match_operand:VM 1 "register_operand" "v") - (match_operand:VM 2 "register_operand" "v") - (match_operand:V16QI 3 "register_operand" "v")] + [(set (match_operand:VM 0 "register_operand" "") + (unspec:VM [(match_operand:VM 1 "register_operand" "") + (match_operand:VM 2 "register_operand" "") + (match_operand:V16QI 3 "register_operand" "")] UNSPEC_VPERM_UNS))] "TARGET_ALTIVEC" { @@ -1983,14 +1992,18 @@ }) (define_insn "*altivec_vperm_<mode>_uns_internal" - [(set (match_operand:VM 0 "register_operand" "=v") - (unspec:VM [(match_operand:VM 1 "register_operand" "v") - (match_operand:VM 2 "register_operand" "v") - (match_operand:V16QI 3 "register_operand" "v")] + [(set (match_operand:VM 0 "register_operand" "=v,?wo,?&wo") + (unspec:VM [(match_operand:VM 1 "register_operand" "v,0,wo") + (match_operand:VM 2 "register_operand" "v,wo,wo") + (match_operand:V16QI 3 "register_operand" "v,wo,wo")] UNSPEC_VPERM_UNS))] "TARGET_ALTIVEC" - "vperm %0,%1,%2,%3" - [(set_attr "type" "vecperm")]) + "@ + vperm %0,%1,%2,%3 + xxperm %x0,%x2,%x3 + xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3" + [(set_attr "type" "vecperm") + (set_attr "length" "4,4,8")]) (define_expand "vec_permv16qi" [(set (match_operand:V16QI 0 "register_operand" "") @@ -2778,24 +2791,32 @@ "") (define_insn "vperm_v8hiv4si" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v") - (match_operand:V16QI 3 "register_operand" "v")] + [(set (match_operand:V4SI 0 "register_operand" "=v,?wo,?&wo") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,0,wo") + (match_operand:V4SI 2 "register_operand" "v,wo,wo") + (match_operand:V16QI 3 "register_operand" "v,wo,wo")] UNSPEC_VPERMSI))] "TARGET_ALTIVEC" - "vperm %0,%1,%2,%3" - [(set_attr "type" "vecperm")]) + "@ + vperm %0,%1,%2,%3 + xxperm %x0,%x2,%x3 + xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3" + [(set_attr "type" "vecperm") + (set_attr "length" "4,4,8")]) (define_insn "vperm_v16qiv8hi" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:V16QI 3 "register_operand" "v")] + [(set (match_operand:V8HI 0 "register_operand" "=v,?wo,?&wo") + (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,0,wo") + (match_operand:V8HI 2 "register_operand" "v,wo,wo") + (match_operand:V16QI 3 "register_operand" "v,wo,wo")] UNSPEC_VPERMHI))] "TARGET_ALTIVEC" - "vperm %0,%1,%2,%3" - [(set_attr "type" "vecperm")]) + "@ + vperm %0,%1,%2,%3 + xxperm %x0,%x2,%x3 + xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3" + [(set_attr "type" "vecperm") + (set_attr "length" "4,4,8")]) (define_expand "vec_unpacku_hi_v16qi" diff --git a/gcc/config/rs6000/biarch64.h b/gcc/config/rs6000/biarch64.h index 4477c679991..31df6db096b 100644 --- a/gcc/config/rs6000/biarch64.h +++ b/gcc/config/rs6000/biarch64.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for 32/64 bit powerpc. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md index 68f2d695140..b780f09efe0 100644 --- a/gcc/config/rs6000/cell.md +++ b/gcc/config/rs6000/cell.md @@ -1,5 +1,5 @@ ;; Scheduling description for cell processor. -;; Copyright (C) 2001-2015 Free Software Foundation, Inc. +;; Copyright (C) 2001-2016 Free Software Foundation, Inc. ;; Contributed by Sony Computer Entertainment, Inc., diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 1e7f27b7d6f..9eca7572c44 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for RS6000 -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -99,7 +99,8 @@ ;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode (define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).") -;; wo is not currently used +(define_register_constraint "wo" "rs6000_constraints[RS6000_CONSTRAINT_wo]" + "VSX register if the -mpower9-vector option was used or NO_REGS.") (define_register_constraint "wp" "rs6000_constraints[RS6000_CONSTRAINT_wp]" "VSX register to use for IEEE 128-bit fp TFmode, or NO_REGS.") diff --git a/gcc/config/rs6000/crypto.md b/gcc/config/rs6000/crypto.md index 6a2cfc60f47..43015f01acb 100644 --- a/gcc/config/rs6000/crypto.md +++ b/gcc/config/rs6000/crypto.md @@ -1,5 +1,5 @@ ;; Cryptographic instructions added in ISA 2.07 -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Michael Meissner (meissner@linux.vnet.ibm.com) ;; This file is part of GCC. diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index 82fcad21e94..baac3e63a68 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -1,5 +1,5 @@ /* Target definitions for PowerPC running Darwin (Mac OS X). - Copyright (C) 1997-2015 Free Software Foundation, Inc. + Copyright (C) 1997-2016 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/darwin.md b/gcc/config/rs6000/darwin.md index ba1d3d864cb..57ce30e0cd1 100644 --- a/gcc/config/rs6000/darwin.md +++ b/gcc/config/rs6000/darwin.md @@ -1,5 +1,5 @@ /* Machine description patterns for PowerPC running Darwin (Mac OS X). - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/darwin.opt b/gcc/config/rs6000/darwin.opt index 9dbec3dd6a3..0508227caa1 100644 --- a/gcc/config/rs6000/darwin.opt +++ b/gcc/config/rs6000/darwin.opt @@ -1,6 +1,6 @@ ; Darwin options for PPC port. ; -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; Contributed by Aldy Hernandez <aldy@quesejoda.com>. ; ; This file is part of GCC. diff --git a/gcc/config/rs6000/darwin64.h b/gcc/config/rs6000/darwin64.h index d6d9ec6f629..2bcce05ceae 100644 --- a/gcc/config/rs6000/darwin64.h +++ b/gcc/config/rs6000/darwin64.h @@ -1,5 +1,5 @@ /* Target definitions for PowerPC running Darwin (Mac OS X). - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. Contributed by Apple Computer Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/darwin7.h b/gcc/config/rs6000/darwin7.h index e7338886ce0..546225b6d2f 100644 --- a/gcc/config/rs6000/darwin7.h +++ b/gcc/config/rs6000/darwin7.h @@ -1,5 +1,5 @@ /* Target definitions for Darwin 7.x (Mac OS X) systems. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/darwin8.h b/gcc/config/rs6000/darwin8.h index cc7c5b900b0..f8da90d45cc 100644 --- a/gcc/config/rs6000/darwin8.h +++ b/gcc/config/rs6000/darwin8.h @@ -1,5 +1,5 @@ /* Target definitions for Darwin 8.0 and above (Mac OS X) systems. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h index 7a29672a1ea..90b4ee17994 100644 --- a/gcc/config/rs6000/default64.h +++ b/gcc/config/rs6000/default64.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for 64 bit powerpc linux defaulting to -m64. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index cce0c3b2ead..a631ff5fd9e 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -1,5 +1,5 @@ ;; Decimal Floating Point (DFP) patterns. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner ;; (bergner@vnet.ibm.com). diff --git a/gcc/config/rs6000/driver-rs6000.c b/gcc/config/rs6000/driver-rs6000.c index af324712b20..30905886502 100644 --- a/gcc/config/rs6000/driver-rs6000.c +++ b/gcc/config/rs6000/driver-rs6000.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md index 3c825efc028..5865e95e2d2 100644 --- a/gcc/config/rs6000/e300c2c3.md +++ b/gcc/config/rs6000/e300c2c3.md @@ -1,5 +1,5 @@ ;; Pipeline description for Motorola PowerPC e300c3 core. -;; Copyright (C) 2008-2015 Free Software Foundation, Inc. +;; Copyright (C) 2008-2016 Free Software Foundation, Inc. ;; Contributed by Edmar Wienskoski (edmar@freescale.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/e500.h b/gcc/config/rs6000/e500.h index 871a8508645..4d5e98bce70 100644 --- a/gcc/config/rs6000/e500.h +++ b/gcc/config/rs6000/e500.h @@ -1,5 +1,5 @@ /* Enable E500 support. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. GCC is free software; you can redistribute it and/or modify it diff --git a/gcc/config/rs6000/e500mc.md b/gcc/config/rs6000/e500mc.md index ed56f383f27..d28f9d40422 100644 --- a/gcc/config/rs6000/e500mc.md +++ b/gcc/config/rs6000/e500mc.md @@ -1,5 +1,5 @@ ;; Pipeline description for Motorola PowerPC e500mc core. -;; Copyright (C) 2008-2015 Free Software Foundation, Inc. +;; Copyright (C) 2008-2016 Free Software Foundation, Inc. ;; Contributed by Edmar Wienskoski (edmar@freescale.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/e500mc64.md b/gcc/config/rs6000/e500mc64.md index 60d28e951ee..9b9704d0a21 100644 --- a/gcc/config/rs6000/e500mc64.md +++ b/gcc/config/rs6000/e500mc64.md @@ -1,5 +1,5 @@ ;; Pipeline description for Freescale PowerPC e500mc64 core. -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by Edmar Wienskoski (edmar@freescale.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/e5500.md b/gcc/config/rs6000/e5500.md index 614dbe600fb..0167e40b4c7 100644 --- a/gcc/config/rs6000/e5500.md +++ b/gcc/config/rs6000/e5500.md @@ -1,5 +1,5 @@ ;; Pipeline description for Freescale PowerPC e5500 core. -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Edmar Wienskoski (edmar@freescale.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md index e1f7aa45323..428222d14bf 100644 --- a/gcc/config/rs6000/e6500.md +++ b/gcc/config/rs6000/e6500.md @@ -1,5 +1,5 @@ ;; Pipeline description for Freescale PowerPC e6500 core. -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Edmar Wienskoski (edmar@freescale.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/eabi.h b/gcc/config/rs6000/eabi.h index f9eea013596..f515f1273cb 100644 --- a/gcc/config/rs6000/eabi.h +++ b/gcc/config/rs6000/eabi.h @@ -1,6 +1,6 @@ /* Core target definitions for GNU compiler for IBM RS/6000 PowerPC targeted to embedded ELF systems. - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. Contributed by Cygnus Support. This file is part of GCC. diff --git a/gcc/config/rs6000/eabialtivec.h b/gcc/config/rs6000/eabialtivec.h index 468d411424b..498603b7b10 100644 --- a/gcc/config/rs6000/eabialtivec.h +++ b/gcc/config/rs6000/eabialtivec.h @@ -1,6 +1,6 @@ /* Core target definitions for GNU compiler for PowerPC targeted systems with AltiVec support. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldyh@redhat.com). This file is part of GCC. diff --git a/gcc/config/rs6000/eabisim.h b/gcc/config/rs6000/eabisim.h index a1a326f7fa8..d95c7c59b45 100644 --- a/gcc/config/rs6000/eabisim.h +++ b/gcc/config/rs6000/eabisim.h @@ -1,6 +1,6 @@ /* Support for GCC on simulated PowerPC systems targeted to embedded ELF systems. - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. Contributed by Cygnus Support. This file is part of GCC. diff --git a/gcc/config/rs6000/eabispe.h b/gcc/config/rs6000/eabispe.h index 34196901a94..6b3b5dfb023 100644 --- a/gcc/config/rs6000/eabispe.h +++ b/gcc/config/rs6000/eabispe.h @@ -1,6 +1,6 @@ /* Core target definitions for GNU compiler for PowerPC embedded targeted systems with SPE support. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldyh@redhat.com). This file is part of GCC. diff --git a/gcc/config/rs6000/freebsd.h b/gcc/config/rs6000/freebsd.h index 21bfc0ca407..26941dd6c9c 100644 --- a/gcc/config/rs6000/freebsd.h +++ b/gcc/config/rs6000/freebsd.h @@ -1,5 +1,5 @@ /* Definitions for PowerPC running FreeBSD using the ELF format - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by David E. O'Brien <obrien@FreeBSD.org> and BSDi. This file is part of GCC. diff --git a/gcc/config/rs6000/freebsd64.h b/gcc/config/rs6000/freebsd64.h index aec1c348900..899b858d821 100644 --- a/gcc/config/rs6000/freebsd64.h +++ b/gcc/config/rs6000/freebsd64.h @@ -1,5 +1,5 @@ /* Definitions for 64-bit PowerPC running FreeBSD using the ELF format - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -167,22 +167,7 @@ extern int dot_symbols; { "link_os_freebsd_spec32", LINK_OS_FREEBSD_SPEC32 }, \ { "link_os_freebsd_spec64", LINK_OS_FREEBSD_SPEC64 }, -#define FREEBSD_DYNAMIC_LINKER32 "/libexec/ld-elf32.so.1" -#define FREEBSD_DYNAMIC_LINKER64 "/libexec/ld-elf.so.1" - -#define LINK_OS_FREEBSD_SPEC_DEF32 "\ - %{p:%nconsider using `-pg' instead of `-p' with gprof(1)} \ - %{v:-V} \ - %{assert*} %{R*} %{rpath*} %{defsym*} \ - %{shared:-Bshareable %{h*} %{soname*}} \ - %{!shared: \ - %{!static: \ - %{rdynamic: -export-dynamic} \ - %{!dynamic-linker:-dynamic-linker " FREEBSD_DYNAMIC_LINKER32 "}} \ - %{static:-Bstatic}} \ - %{symbolic:-Bsymbolic}" - -#define LINK_OS_FREEBSD_SPEC_DEF64 "\ +#define LINK_OS_FREEBSD_SPEC_DEF "\ %{p:%nconsider using `-pg' instead of `-p' with gprof(1)} \ %{v:-V} \ %{assert*} %{R*} %{rpath*} %{defsym*} \ @@ -190,13 +175,13 @@ extern int dot_symbols; %{!shared: \ %{!static: \ %{rdynamic: -export-dynamic} \ - %{!dynamic-linker:-dynamic-linker " FREEBSD_DYNAMIC_LINKER64 "}} \ + %{!dynamic-linker:-dynamic-linker " FBSD_DYNAMIC_LINKER "}} \ %{static:-Bstatic}} \ %{symbolic:-Bsymbolic}" -#define LINK_OS_FREEBSD_SPEC32 "-melf32ppc_fbsd " LINK_OS_FREEBSD_SPEC_DEF32 +#define LINK_OS_FREEBSD_SPEC32 "-melf32ppc_fbsd " LINK_OS_FREEBSD_SPEC_DEF -#define LINK_OS_FREEBSD_SPEC64 "-melf64ppc_fbsd " LINK_OS_FREEBSD_SPEC_DEF64 +#define LINK_OS_FREEBSD_SPEC64 "-melf64ppc_fbsd " LINK_OS_FREEBSD_SPEC_DEF #undef MULTILIB_DEFAULTS #define MULTILIB_DEFAULTS { "m64" } diff --git a/gcc/config/rs6000/genopt.sh b/gcc/config/rs6000/genopt.sh index 13ce5ead2a7..42bbd0e5bda 100755 --- a/gcc/config/rs6000/genopt.sh +++ b/gcc/config/rs6000/genopt.sh @@ -1,6 +1,6 @@ #!/bin/sh # Generate rs6000-tables.opt from the list of CPUs in rs6000-cpus.def. -# Copyright (C) 2011-2015 Free Software Foundation, Inc. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. # # This file is part of GCC. # @@ -22,7 +22,7 @@ cat <<EOF ; -*- buffer-read-only: t -*- ; Generated automatically by genopt.sh from rs6000-cpus.def. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/rs6000/host-darwin.c b/gcc/config/rs6000/host-darwin.c index efcecbcd528..add2bc7b0d4 100644 --- a/gcc/config/rs6000/host-darwin.c +++ b/gcc/config/rs6000/host-darwin.c @@ -1,5 +1,5 @@ /* Darwin/powerpc host-specific hook definitions. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/host-ppc64-darwin.c b/gcc/config/rs6000/host-ppc64-darwin.c index 3399d163299..ad058780af5 100644 --- a/gcc/config/rs6000/host-ppc64-darwin.c +++ b/gcc/config/rs6000/host-ppc64-darwin.c @@ -1,5 +1,5 @@ /* ppc64-darwin host-specific hook definitions. - Copyright (C) 2006-2015 Free Software Foundation, Inc. + Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/htm.md b/gcc/config/rs6000/htm.md index 098723f6308..0d0823824a8 100644 --- a/gcc/config/rs6000/htm.md +++ b/gcc/config/rs6000/htm.md @@ -1,5 +1,5 @@ ;; Hardware Transactional Memory (HTM) patterns. -;; Copyright (C) 2013-2015 Free Software Foundation, Inc. +;; Copyright (C) 2013-2016 Free Software Foundation, Inc. ;; Contributed by Peter Bergner <bergner@vnet.ibm.com>. ;; This file is part of GCC. diff --git a/gcc/config/rs6000/htmintrin.h b/gcc/config/rs6000/htmintrin.h index 7ce53ea90ca..717664140d7 100644 --- a/gcc/config/rs6000/htmintrin.h +++ b/gcc/config/rs6000/htmintrin.h @@ -1,5 +1,5 @@ /* Hardware Transactional Memory (HTM) intrinsics. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. Contributed by Peter Bergner <bergner@vnet.ibm.com>. This file is free software; you can redistribute it and/or modify it under diff --git a/gcc/config/rs6000/htmxlintrin.h b/gcc/config/rs6000/htmxlintrin.h index a10771cd4fc..5431c90930d 100644 --- a/gcc/config/rs6000/htmxlintrin.h +++ b/gcc/config/rs6000/htmxlintrin.h @@ -1,5 +1,5 @@ /* XL compiler Hardware Transactional Memory (HTM) execution intrinsics. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. Contributed by Peter Bergner <bergner@vnet.ibm.com>. This file is free software; you can redistribute it and/or modify it under diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h index a68ff6982af..ac9296d79ec 100644 --- a/gcc/config/rs6000/linux.h +++ b/gcc/config/rs6000/linux.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for PowerPC machines running Linux. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Michael Meissner (meissner@cygnus.com). This file is part of GCC. diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h index 810d2f8b0d8..20077e1aa71 100644 --- a/gcc/config/rs6000/linux64.h +++ b/gcc/config/rs6000/linux64.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for 64 bit PowerPC linux. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/linux64.opt b/gcc/config/rs6000/linux64.opt index 47c049bbdb2..045d442122f 100644 --- a/gcc/config/rs6000/linux64.opt +++ b/gcc/config/rs6000/linux64.opt @@ -1,6 +1,6 @@ ; Options for 64-bit PowerPC Linux. ; -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; Contributed by Aldy Hernandez <aldy@quesejoda.com>. ; ; This file is part of GCC. diff --git a/gcc/config/rs6000/linuxaltivec.h b/gcc/config/rs6000/linuxaltivec.h index 7a3fd7aef4d..9409f33e51c 100644 --- a/gcc/config/rs6000/linuxaltivec.h +++ b/gcc/config/rs6000/linuxaltivec.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for AltiVec enhanced PowerPC machines running GNU/Linux. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldyh@redhat.com). This file is part of GCC. diff --git a/gcc/config/rs6000/linuxspe.h b/gcc/config/rs6000/linuxspe.h index 51c2a5170da..35623cd29d6 100644 --- a/gcc/config/rs6000/linuxspe.h +++ b/gcc/config/rs6000/linuxspe.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for PowerPC e500 machines running GNU/Linux. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldy@quesejoda.com). This file is part of GCC. diff --git a/gcc/config/rs6000/lynx.h b/gcc/config/rs6000/lynx.h index 32d993e870c..d9cff7cd3d2 100644 --- a/gcc/config/rs6000/lynx.h +++ b/gcc/config/rs6000/lynx.h @@ -1,5 +1,5 @@ /* Definitions for Rs6000 running LynxOS. - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. Contributed by David Henkel-Wallace, Cygnus Support (gumby@cygnus.com) Rewritten by Adam Nemet, LynuxWorks Inc. diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md index e5c43bf5874..010dc9444e0 100644 --- a/gcc/config/rs6000/mpc.md +++ b/gcc/config/rs6000/mpc.md @@ -1,5 +1,5 @@ ;; Scheduling description for Motorola PowerPC processor cores. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/rs6000/netbsd.h b/gcc/config/rs6000/netbsd.h index 471a221f98d..0ca35d3ae42 100644 --- a/gcc/config/rs6000/netbsd.h +++ b/gcc/config/rs6000/netbsd.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for PowerPC NetBSD systems. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/option-defaults.h b/gcc/config/rs6000/option-defaults.h index 95a14720618..0c15a0fec85 100644 --- a/gcc/config/rs6000/option-defaults.h +++ b/gcc/config/rs6000/option-defaults.h @@ -1,5 +1,5 @@ /* Definitions of default options for config/rs6000 configurations. - Copyright (C) 1992-2015 Free Software Foundation, Inc. + Copyright (C) 1992-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/paired.h b/gcc/config/rs6000/paired.h index ccac6f315d2..be7964fc34a 100644 --- a/gcc/config/rs6000/paired.h +++ b/gcc/config/rs6000/paired.h @@ -1,5 +1,5 @@ /* PowerPC 750CL user include file. - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. Contributed by Revital Eres (eres@il.ibm.com). This file is part of GCC. diff --git a/gcc/config/rs6000/paired.md b/gcc/config/rs6000/paired.md index 5d094fbbff5..224081b83c3 100644 --- a/gcc/config/rs6000/paired.md +++ b/gcc/config/rs6000/paired.md @@ -1,5 +1,5 @@ ;; PowerPC paired single and double hummer description -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; Contributed by David Edelsohn <edelsohn@gnu.org> and Revital Eres ;; <eres@il.ibm.com> @@ -421,45 +421,62 @@ DONE; }) -(define_expand "reduc_smax_v2sf" - [(match_operand:V2SF 0 "gpc_reg_operand" "=f") +(define_expand "reduc_smax_scal_v2sf" + [(match_operand:SF 0 "gpc_reg_operand" "=f") (match_operand:V2SF 1 "gpc_reg_operand" "f")] "TARGET_PAIRED_FLOAT" { rtx tmp_swap = gen_reg_rtx (V2SFmode); rtx tmp = gen_reg_rtx (V2SFmode); + rtx vec_res = gen_reg_rtx (V2SFmode); + rtx di_res = gen_reg_rtx (DImode); emit_insn (gen_paired_merge10 (tmp_swap, operands[1], operands[1])); emit_insn (gen_subv2sf3 (tmp, operands[1], tmp_swap)); - emit_insn (gen_selv2sf4 (operands[0], tmp, operands[1], tmp_swap, CONST0_RTX (SFmode))); + emit_insn (gen_selv2sf4 (vec_res, tmp, operands[1], tmp_swap, + CONST0_RTX (SFmode))); + emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0)); + emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode, + BYTES_BIG_ENDIAN ? 4 : 0)); DONE; }) -(define_expand "reduc_smin_v2sf" - [(match_operand:V2SF 0 "gpc_reg_operand" "=f") +(define_expand "reduc_smin_scal_v2sf" + [(match_operand:SF 0 "gpc_reg_operand" "=f") (match_operand:V2SF 1 "gpc_reg_operand" "f")] "TARGET_PAIRED_FLOAT" { rtx tmp_swap = gen_reg_rtx (V2SFmode); rtx tmp = gen_reg_rtx (V2SFmode); + rtx vec_res = gen_reg_rtx (V2SFmode); + rtx di_res = gen_reg_rtx (DImode); emit_insn (gen_paired_merge10 (tmp_swap, operands[1], operands[1])); emit_insn (gen_subv2sf3 (tmp, operands[1], tmp_swap)); - emit_insn (gen_selv2sf4 (operands[0], tmp, tmp_swap, operands[1], CONST0_RTX (SFmode))); + emit_insn (gen_selv2sf4 (vec_res, tmp, tmp_swap, operands[1], + CONST0_RTX (SFmode))); + emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0)); + emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode, + BYTES_BIG_ENDIAN ? 4 : 0)); DONE; }) -(define_expand "reduc_splus_v2sf" - [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") +(define_expand "reduc_plus_scal_v2sf" + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (match_operand:V2SF 1 "gpc_reg_operand" "f"))] "TARGET_PAIRED_FLOAT" - " { - emit_insn (gen_paired_sum1 (operands[0], operands[1], operands[1], operands[1])); + rtx vec_res = gen_reg_rtx (V2SFmode); + rtx di_res = gen_reg_rtx (DImode); + + emit_insn (gen_paired_sum1 (vec_res, operands[1], operands[1], operands[1])); + emit_move_insn (di_res, simplify_gen_subreg (DImode, vec_res, V2SFmode, 0)); + emit_move_insn (operands[0], simplify_gen_subreg (SFmode, di_res, DImode, + BYTES_BIG_ENDIAN ? 4 : 0)); DONE; -}") +}) (define_expand "movmisalignv2sf" [(set (match_operand:V2SF 0 "nonimmediate_operand" "") diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md index e28b1015a26..7b0ccbedaac 100644 --- a/gcc/config/rs6000/power4.md +++ b/gcc/config/rs6000/power4.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM Power4 and PowerPC 970 processors. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md index be0075580d9..2d7c15e59c0 100644 --- a/gcc/config/rs6000/power5.md +++ b/gcc/config/rs6000/power5.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM POWER5 processor. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/rs6000/power6.md b/gcc/config/rs6000/power6.md index 82651497b26..15d31eb81a2 100644 --- a/gcc/config/rs6000/power6.md +++ b/gcc/config/rs6000/power6.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM POWER6 processor. -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; Contributed by Peter Steinmetz (steinmtz@us.ibm.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/power7.md b/gcc/config/rs6000/power7.md index 0884974a938..9c6326dd26b 100644 --- a/gcc/config/rs6000/power7.md +++ b/gcc/config/rs6000/power7.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM POWER7 processor. -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthaugen@us.ibm.com). diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md index c88d66a453a..6b6f0ffb8de 100644 --- a/gcc/config/rs6000/power8.md +++ b/gcc/config/rs6000/power8.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM POWER8 processor. -;; Copyright (C) 2013-2015 Free Software Foundation, Inc. +;; Copyright (C) 2013-2016 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthaugen@us.ibm.com). diff --git a/gcc/config/rs6000/ppc-asm.h b/gcc/config/rs6000/ppc-asm.h index 7da8c5f5386..1234db65f8d 100644 --- a/gcc/config/rs6000/ppc-asm.h +++ b/gcc/config/rs6000/ppc-asm.h @@ -1,6 +1,6 @@ /* PowerPC asm definitions for GNU C. -Copyright (C) 2002-2015 Free Software Foundation, Inc. +Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/ppu_intrinsics.h b/gcc/config/rs6000/ppu_intrinsics.h index 8e4ec34d02a..65f74574754 100644 --- a/gcc/config/rs6000/ppu_intrinsics.h +++ b/gcc/config/rs6000/ppu_intrinsics.h @@ -1,5 +1,5 @@ /* PPU intrinsics as defined by the C/C++ Language extension for Cell BEA. - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 362188f1d16..5adc4de6a31 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for POWER and PowerPC. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 85082ec0ee2..709992b3772 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -1,5 +1,5 @@ /* Builtin functions for rs6000/powerpc. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by Michael Meissner (meissner@linux.vnet.ibm.com) This file is part of GCC. diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index a1b4fd4d17e..b6e42f6ecad 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -1,5 +1,5 @@ /* Subroutines for the C front end on the PowerPC architecture. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Zack Weinberg <zack@codesourcery.com> and Paolo Bonzini <bonzini@gnu.org> @@ -412,6 +412,8 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile) builtin_define ("__RSQRTEF__"); if (TARGET_FLOAT128) builtin_define ("__FLOAT128__"); + if (TARGET_FLOAT128_HW) + builtin_define ("__FLOAT128_HARDWARE__"); if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM) { diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index fc2b0f11353..92fb71aed21 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -1,5 +1,5 @@ /* IBM RS/6000 CPU names.. - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. @@ -67,6 +67,7 @@ | OPTION_MASK_ISEL \ | OPTION_MASK_MODULO \ | OPTION_MASK_P9_FUSION \ + | OPTION_MASK_P9_DFORM \ | OPTION_MASK_P9_VECTOR) #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) diff --git a/gcc/config/rs6000/rs6000-linux.c b/gcc/config/rs6000/rs6000-linux.c index 16416ba12c1..9f3bd2d586b 100644 --- a/gcc/config/rs6000/rs6000-linux.c +++ b/gcc/config/rs6000/rs6000-linux.c @@ -1,5 +1,5 @@ /* Functions for Linux on PowerPC. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def index 1cd3b94eee7..075819dd465 100644 --- a/gcc/config/rs6000/rs6000-modes.def +++ b/gcc/config/rs6000/rs6000-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index 012c0db42fc..44e584a746a 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -1,6 +1,6 @@ /* Definitions of target machine needed for option handling for GNU compiler, for IBM RS/6000. - Copyright (C) 2010-2015 Free Software Foundation, Inc. + Copyright (C) 2010-2016 Free Software Foundation, Inc. Contributed by Michael Meissner (meissner@linux.vnet.ibm.com) This file is part of GCC. diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index d9c7a79af39..d9a6b1f784b 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index 2529ff1ca91..545875a8de2 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -1,7 +1,7 @@ ; -*- buffer-read-only: t -*- ; Generated automatically by genopt.sh from rs6000-cpus.def. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 6b22f93e0ff..c589118a797 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on IBM RS/6000. - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. @@ -2284,6 +2284,7 @@ rs6000_debug_reg_global (void) "wk reg_class = %s\n" "wl reg_class = %s\n" "wm reg_class = %s\n" + "wo reg_class = %s\n" "wp reg_class = %s\n" "wq reg_class = %s\n" "wr reg_class = %s\n" @@ -2311,6 +2312,7 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wo]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]], @@ -3019,7 +3021,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) if (TARGET_P9_DFORM) rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS; - /* Support for new direct moves. */ + /* Support for ISA 3.0 (power9) vectors. */ + if (TARGET_P9_VECTOR) + rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS; + + /* Support for new direct moves (ISA 3.0 + 64bit). */ if (TARGET_DIRECT_MOVE_128) rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS; @@ -8829,8 +8835,9 @@ rs6000_const_vec (machine_mode mode) rtx rs6000_gen_le_vsx_permute (rtx source, machine_mode mode) { - /* Use ROTATE instead of VEC_SELECT on IEEE 128-bit floating point. */ - if (FLOAT128_VECTOR_P (mode)) + /* Use ROTATE instead of VEC_SELECT on IEEE 128-bit floating point, and + 128-bit integers if they are allowed in VSX registers. */ + if (FLOAT128_VECTOR_P (mode) || mode == TImode) return gen_rtx_ROTATE (mode, source, GEN_INT (64)); else { @@ -8903,6 +8910,7 @@ rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode) { gcc_assert (!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode) + && !TARGET_P9_VECTOR && !gpr_or_gpr_p (dest, source) && (MEM_P (source) ^ MEM_P (dest))); @@ -16499,8 +16507,6 @@ init_float128_ieee (machine_mode mode) set_optab_libfunc (lt_optab, mode, "__ltkf2"); set_optab_libfunc (le_optab, mode, "__lekf2"); set_optab_libfunc (unord_optab, mode, "__unordkf2"); - set_optab_libfunc (cmp_optab, mode, "__cmpokf2"); /* fcmpo */ - set_optab_libfunc (ucmp_optab, mode, "__cmpukf2"); /* fcmpu */ set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2"); set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2"); @@ -20295,7 +20301,9 @@ rs6000_generate_compare (rtx cmp, machine_mode mode) rtx op0 = XEXP (cmp, 0); rtx op1 = XEXP (cmp, 1); - if (FLOAT_MODE_P (mode)) + if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode)) + comp_mode = CCmode; + else if (FLOAT_MODE_P (mode)) comp_mode = CCFPmode; else if (code == GTU || code == LTU || code == GEU || code == LEU) @@ -20501,106 +20509,77 @@ rs6000_generate_compare (rtx cmp, machine_mode mode) emit_insn (cmp); } - /* IEEE 128-bit support in VSX registers. If we do not have IEEE 128-bit - hardware, the comparison functions (__cmpokf2 and __cmpukf2) returns 0..15 - that is laid out the same way as the PowerPC CR register would for a - normal floating point comparison from the fcmpo and fcmpu - instructions. */ - else if (!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)) + /* IEEE 128-bit support in VSX registers when we do not have hardware + support. */ + else if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode)) { - rtx and_reg = gen_reg_rtx (SImode); + rtx libfunc = NULL_RTX; + bool uneq_or_ltgt = false; rtx dest = gen_reg_rtx (SImode); - rtx libfunc = optab_libfunc (ucmp_optab, mode); - HOST_WIDE_INT mask_value = 0; - - /* Values that __cmpokf2/__cmpukf2 returns. */ -#define PPC_CMP_UNORDERED 0x1 /* isnan (a) || isnan (b). */ -#define PPC_CMP_EQUAL 0x2 /* a == b. */ -#define PPC_CMP_GREATER_THEN 0x4 /* a > b. */ -#define PPC_CMP_LESS_THEN 0x8 /* a < b. */ switch (code) { case EQ: - mask_value = PPC_CMP_EQUAL; - code = NE; - break; - case NE: - mask_value = PPC_CMP_EQUAL; - code = EQ; + libfunc = optab_libfunc (eq_optab, mode); break; case GT: - mask_value = PPC_CMP_GREATER_THEN; - code = NE; - break; - case GE: - mask_value = PPC_CMP_GREATER_THEN | PPC_CMP_EQUAL; - code = NE; + libfunc = optab_libfunc (ge_optab, mode); break; case LT: - mask_value = PPC_CMP_LESS_THEN; - code = NE; - break; - case LE: - mask_value = PPC_CMP_LESS_THEN | PPC_CMP_EQUAL; - code = NE; + libfunc = optab_libfunc (le_optab, mode); break; - case UNLE: - mask_value = PPC_CMP_GREATER_THEN; - code = EQ; - break; - - case UNLT: - mask_value = PPC_CMP_GREATER_THEN | PPC_CMP_EQUAL; - code = EQ; + case UNORDERED: + case ORDERED: + libfunc = optab_libfunc (unord_optab, mode); + code = (code == UNORDERED) ? NE : EQ; break; case UNGE: - mask_value = PPC_CMP_LESS_THEN; - code = EQ; + case UNGT: + libfunc = optab_libfunc (le_optab, mode); + code = (code == UNGE) ? GE : GT; break; - case UNGT: - mask_value = PPC_CMP_LESS_THEN | PPC_CMP_EQUAL; - code = EQ; + case UNLE: + case UNLT: + libfunc = optab_libfunc (ge_optab, mode); + code = (code == UNLE) ? LE : LT; break; case UNEQ: - mask_value = PPC_CMP_EQUAL | PPC_CMP_UNORDERED; - code = NE; - case LTGT: - mask_value = PPC_CMP_EQUAL | PPC_CMP_UNORDERED; - code = EQ; - break; - - case UNORDERED: - mask_value = PPC_CMP_UNORDERED; - code = NE; - break; - - case ORDERED: - mask_value = PPC_CMP_UNORDERED; - code = EQ; + libfunc = optab_libfunc (le_optab, mode); + uneq_or_ltgt = true; + code = (code = UNEQ) ? NE : EQ; break; default: gcc_unreachable (); } - gcc_assert (mask_value != 0); - and_reg = emit_library_call_value (libfunc, and_reg, LCT_CONST, SImode, 2, - op0, mode, op1, mode); + gcc_assert (libfunc); + dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, + SImode, 2, op0, mode, op1, mode); - emit_insn (gen_andsi3 (dest, and_reg, GEN_INT (mask_value))); - compare_result = gen_reg_rtx (CCmode); - comp_mode = CCmode; + /* If this is UNEQ or LTGT, we call __lekf2, which returns -1 for less + than, 0 for equal, +1 for greater, and +2 for nan. We add 1, to give + a value of 0..3, and then do and AND immediate of 1 to isolate whether + it is 0/Nan (i.e. bottom bit is 0), or less than/greater than + (i.e. bottom bit is 1). */ + if (uneq_or_ltgt) + { + rtx add_result = gen_reg_rtx (SImode); + rtx and_result = gen_reg_rtx (SImode); + emit_insn (gen_addsi3 (add_result, dest, GEN_INT (1))); + emit_insn (gen_andsi3 (and_result, add_result, GEN_INT (1))); + dest = and_result; + } emit_insn (gen_rtx_SET (compare_result, gen_rtx_COMPARE (comp_mode, dest, const0_rtx))); @@ -20704,24 +20683,29 @@ rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED, mode2 = GET_MODE_INNER (mode2); /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended - double to intermix. */ + double to intermix unless -mfloat128-convert. */ if (mode1 == mode2) return NULL; - if ((mode1 == KFmode && mode2 == IFmode) - || (mode1 == IFmode && mode2 == KFmode)) - return N_("__float128 and __ibm128 cannot be used in the same expression"); + if (!TARGET_FLOAT128_CVT) + { + if ((mode1 == KFmode && mode2 == IFmode) + || (mode1 == IFmode && mode2 == KFmode)) + return N_("__float128 and __ibm128 cannot be used in the same " + "expression"); - if (TARGET_IEEEQUAD - && ((mode1 == IFmode && mode2 == TFmode) - || (mode1 == TFmode && mode2 == IFmode))) - return N_("__ibm128 and long double cannot be used in the same expression"); + if (TARGET_IEEEQUAD + && ((mode1 == IFmode && mode2 == TFmode) + || (mode1 == TFmode && mode2 == IFmode))) + return N_("__ibm128 and long double cannot be used in the same " + "expression"); - if (!TARGET_IEEEQUAD - && ((mode1 == KFmode && mode2 == TFmode) - || (mode1 == TFmode && mode2 == KFmode))) - return N_("__float128 and long double cannot be used in the same " - "expression"); + if (!TARGET_IEEEQUAD + && ((mode1 == KFmode && mode2 == TFmode) + || (mode1 == TFmode && mode2 == KFmode))) + return N_("__float128 and long double cannot be used in the same " + "expression"); + } return NULL; } @@ -32785,29 +32769,6 @@ rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a) emit_move_insn (target, dst); } -/* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */ - -static void -rs6000_emit_msub (rtx target, rtx m1, rtx m2, rtx a) -{ - machine_mode mode = GET_MODE (target); - rtx dst; - - /* Altivec does not support fms directly; - generate in terms of fma in that case. */ - if (optab_handler (fms_optab, mode) != CODE_FOR_nothing) - dst = expand_ternary_op (mode, fms_optab, m1, m2, a, target, 0); - else - { - a = expand_unop (mode, neg_optab, a, NULL_RTX, 0); - dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0); - } - gcc_assert (dst != NULL); - - if (dst != target) - emit_move_insn (target, dst); -} - /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */ static void @@ -32906,15 +32867,16 @@ rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p) add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d)); } -/* Newton-Raphson approximation of single/double-precision floating point - rsqrt. Assumes no trapping math and finite arguments. */ +/* Goldschmidt's Algorithm for single/double-precision floating point + sqrt and rsqrt. Assumes no trapping math and finite arguments. */ void rs6000_emit_swsqrt (rtx dst, rtx src, bool recip) { machine_mode mode = GET_MODE (src); - rtx x0 = gen_reg_rtx (mode); - rtx y = gen_reg_rtx (mode); + rtx e = gen_reg_rtx (mode); + rtx g = gen_reg_rtx (mode); + rtx h = gen_reg_rtx (mode); /* Low precision estimates guarantee 5 bits of accuracy. High precision estimates guarantee 14 bits of accuracy. SFmode @@ -32925,55 +32887,68 @@ rs6000_emit_swsqrt (rtx dst, rtx src, bool recip) if (mode == DFmode || mode == V2DFmode) passes++; - REAL_VALUE_TYPE dconst3_2; int i; - rtx halfthree; + rtx mhalf; enum insn_code code = optab_handler (smul_optab, mode); insn_gen_fn gen_mul = GEN_FCN (code); gcc_assert (code != CODE_FOR_nothing); - /* Load up the constant 1.5 either as a scalar, or as a vector. */ - real_from_integer (&dconst3_2, VOIDmode, 3, SIGNED); - SET_REAL_EXP (&dconst3_2, REAL_EXP (&dconst3_2) - 1); + mhalf = rs6000_load_constant_and_splat (mode, dconsthalf); - halfthree = rs6000_load_constant_and_splat (mode, dconst3_2); - - /* x0 = rsqrt estimate */ - emit_insn (gen_rtx_SET (x0, gen_rtx_UNSPEC (mode, gen_rtvec (1, src), - UNSPEC_RSQRT))); + /* e = rsqrt estimate */ + emit_insn (gen_rtx_SET (e, gen_rtx_UNSPEC (mode, gen_rtvec (1, src), + UNSPEC_RSQRT))); /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */ if (!recip) { rtx zero = force_reg (mode, CONST0_RTX (mode)); - rtx target = emit_conditional_move (x0, GT, src, zero, mode, - x0, zero, mode, 0); - if (target != x0) - emit_move_insn (x0, target); + rtx target = emit_conditional_move (e, GT, src, zero, mode, + e, zero, mode, 0); + if (target != e) + emit_move_insn (e, target); } - /* y = 0.5 * src = 1.5 * src - src -> fewer constants */ - rs6000_emit_msub (y, src, halfthree, src); + /* g = sqrt estimate. */ + emit_insn (gen_mul (g, e, src)); + /* h = 1/(2*sqrt) estimate. */ + emit_insn (gen_mul (h, e, mhalf)); - for (i = 0; i < passes; i++) + if (recip) { - rtx x1 = gen_reg_rtx (mode); - rtx u = gen_reg_rtx (mode); - rtx v = gen_reg_rtx (mode); + if (passes == 1) + { + rtx t = gen_reg_rtx (mode); + rs6000_emit_nmsub (t, g, h, mhalf); + /* Apply correction directly to 1/rsqrt estimate. */ + rs6000_emit_madd (dst, e, t, e); + } + else + { + for (i = 0; i < passes; i++) + { + rtx t1 = gen_reg_rtx (mode); + rtx g1 = gen_reg_rtx (mode); + rtx h1 = gen_reg_rtx (mode); - /* x1 = x0 * (1.5 - y * (x0 * x0)) */ - emit_insn (gen_mul (u, x0, x0)); - rs6000_emit_nmsub (v, y, u, halfthree); - emit_insn (gen_mul (x1, x0, v)); - x0 = x1; - } + rs6000_emit_nmsub (t1, g, h, mhalf); + rs6000_emit_madd (g1, g, t1, g); + rs6000_emit_madd (h1, h, t1, h); - /* If not reciprocal, multiply by src to produce sqrt. */ - if (!recip) - emit_insn (gen_mul (dst, src, x0)); + g = g1; + h = h1; + } + /* Multiply by 2 for 1/rsqrt. */ + emit_insn (gen_add3_insn (dst, h, h)); + } + } else - emit_move_insn (dst, x0); + { + rtx t = gen_reg_rtx (mode); + rs6000_emit_nmsub (t, g, h, mhalf); + rs6000_emit_madd (dst, g, t, g); + } return; } @@ -36664,6 +36639,44 @@ const_load_sequence_p (swap_web_entry *insn_entry, rtx insn) return true; } +/* Return TRUE iff OP matches a V2DF reduction pattern. See the + definition of vsx_reduc_<VEC_reduc_name>_v2df in vsx.md. */ +static bool +v2df_reduction_p (rtx op) +{ + if (GET_MODE (op) != V2DFmode) + return false; + + enum rtx_code code = GET_CODE (op); + if (code != PLUS && code != SMIN && code != SMAX) + return false; + + rtx concat = XEXP (op, 0); + if (GET_CODE (concat) != VEC_CONCAT) + return false; + + rtx select0 = XEXP (concat, 0); + rtx select1 = XEXP (concat, 1); + if (GET_CODE (select0) != VEC_SELECT || GET_CODE (select1) != VEC_SELECT) + return false; + + rtx reg0 = XEXP (select0, 0); + rtx reg1 = XEXP (select1, 0); + if (!rtx_equal_p (reg0, reg1) || !REG_P (reg0)) + return false; + + rtx parallel0 = XEXP (select0, 1); + rtx parallel1 = XEXP (select1, 1); + if (GET_CODE (parallel0) != PARALLEL || GET_CODE (parallel1) != PARALLEL) + return false; + + if (!rtx_equal_p (XVECEXP (parallel0, 0, 0), const1_rtx) + || !rtx_equal_p (XVECEXP (parallel1, 0, 0), const0_rtx)) + return false; + + return true; +} + /* Return 1 iff OP is an operand that will not be affected by having vector doublewords swapped in memory. */ static unsigned int @@ -36735,6 +36748,8 @@ rtx_is_swappable_p (rtx op, unsigned int *special) *special = SH_XXPERMDI; return 1; } + else if (v2df_reduction_p (op)) + return 1; else return 0; @@ -36799,6 +36814,9 @@ rtx_is_swappable_p (rtx op, unsigned int *special) case UNSPEC_VSPLT_DIRECT: *special = SH_SPLAT; return 1; + case UNSPEC_REDUC_PLUS: + case UNSPEC_REDUC: + return 1; } } @@ -36923,6 +36941,15 @@ insn_is_swappable_p (swap_web_entry *insn_entry, rtx insn, return 1; } + /* V2DF reductions are always swappable. */ + if (GET_CODE (body) == PARALLEL) + { + rtx expr = XVECEXP (body, 0, 0); + if (GET_CODE (expr) == SET + && v2df_reduction_p (SET_SRC (expr))) + return 1; + } + /* An UNSPEC_VPERM is ok if the mask operand is loaded from the constant pool. */ if (GET_CODE (body) == SET @@ -37792,7 +37819,7 @@ public: virtual bool gate (function *) { return (optimize > 0 && !BYTES_BIG_ENDIAN && TARGET_VSX - && rs6000_optimize_swaps); + && !TARGET_P9_VECTOR && rs6000_optimize_swaps); } virtual unsigned int execute (function *fun) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index dafe3acf912..6b0e64e693d 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000. - Copyright (C) 1992-2015 Free Software Foundation, Inc. + Copyright (C) 1992-2016 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GCC. @@ -128,6 +128,7 @@ %{mcpu=power9: %(asm_cpu_power9)} \ %{mcpu=a2: -ma2} \ %{mcpu=powerpc: -mppc} \ +%{mcpu=powerpc64le: %(asm_cpu_power8)} \ %{mcpu=rs64a: -mppc64} \ %{mcpu=401: -mppc} \ %{mcpu=403: -m403} \ @@ -1534,6 +1535,7 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ RS6000_CONSTRAINT_wm, /* VSX register for direct move */ + RS6000_CONSTRAINT_wo, /* VSX register for power9 vector. */ RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */ RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 35685a92e1a..d8834a27314 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1,5 +1,5 @@ ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler -;; Copyright (C) 1990-2015 Free Software Foundation, Inc. +;; Copyright (C) 1990-2016 Free Software Foundation, Inc. ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) ;; This file is part of GCC. @@ -4444,6 +4444,7 @@ && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))" { if (<MODE>mode == SFmode + && TARGET_RECIP_PRECISION && RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode) && !optimize_function_for_size_p (cfun) && flag_finite_math_only && !flag_trapping_math @@ -13352,6 +13353,40 @@ "xscvdpqp %0,%1" [(set_attr "type" "vecfloat")]) +;; Conversion between KFmode and TFmode if TFmode is ieee 128-bit floating +;; point is a simple copy. +(define_insn_and_split "extendkftf2" + [(set (match_operand:TF 0 "vsx_register_operand" "=wa,?wa") + (float_extend:TF (match_operand:KF 1 "vsx_register_operand" "0,wa")))] + "TARGET_FLOAT128 && TARGET_IEEEQUAD" + "@ + # + xxlor %x0,%x1,%x1" + "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" + [(const_int 0)] +{ + emit_note (NOTE_INSN_DELETED); + DONE; +} + [(set_attr "type" "*,vecsimple") + (set_attr "length" "0,4")]) + +(define_insn_and_split "trunctfkf2" + [(set (match_operand:KF 0 "vsx_register_operand" "=wa,?wa") + (float_extend:KF (match_operand:TF 1 "vsx_register_operand" "0,wa")))] + "TARGET_FLOAT128 && TARGET_IEEEQUAD" + "@ + # + xxlor %x0,%x1,%x1" + "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" + [(const_int 0)] +{ + emit_note (NOTE_INSN_DELETED); + DONE; +} + [(set_attr "type" "*,vecsimple") + (set_attr "length" "0,4")]) + (define_insn "trunc<mode>df2_hw" [(set (match_operand:DF 0 "altivec_register_operand" "=v") (float_truncate:DF @@ -13476,7 +13511,7 @@ "xscv<su>dqp %0,%1" [(set_attr "type" "vecfloat")]) -(define_insn "*ieee128_mfvsrd" +(define_insn "*ieee128_mfvsrd_64bit" [(set (match_operand:DI 0 "reg_or_indexed_operand" "=wr,Z,wi") (unspec:DI [(match_operand:V2DI 1 "altivec_register_operand" "v,v,v")] UNSPEC_IEEE128_MOVE))] @@ -13487,6 +13522,17 @@ xxlor %x0,%x1,%x1" [(set_attr "type" "mftgpr,vecsimple,fpstore")]) + +(define_insn "*ieee128_mfvsrd_32bit" + [(set (match_operand:DI 0 "reg_or_indexed_operand" "=Z,wi") + (unspec:DI [(match_operand:V2DI 1 "altivec_register_operand" "v,v")] + UNSPEC_IEEE128_MOVE))] + "TARGET_FLOAT128_HW && !TARGET_POWERPC64" + "@ + stxsdx %x1,%y0 + xxlor %x0,%x1,%x1" + [(set_attr "type" "vecsimple,fpstore")]) + (define_insn "*ieee128_mfvsrwz" [(set (match_operand:SI 0 "reg_or_indexed_operand" "=r,Z") (unspec:SI [(match_operand:V2DI 1 "altivec_register_operand" "v,v")] @@ -13512,17 +13558,27 @@ [(set_attr "type" "mffgpr,fpload,mffgpr,fpload")]) -(define_insn "*ieee128_mtvsrd" +(define_insn "*ieee128_mtvsrd_64bit" [(set (match_operand:V2DI 0 "altivec_register_operand" "=v,v,v") (unspec:V2DI [(match_operand:DI 1 "nonimmediate_operand" "wr,Z,wi")] UNSPEC_IEEE128_MOVE))] - "TARGET_FLOAT128_HW" + "TARGET_FLOAT128_HW && TARGET_POWERPC64" "@ mtvsrd %x0,%1 lxsdx %x0,%y1 xxlor %x0,%x1,%x1" [(set_attr "type" "mffgpr,fpload,vecsimple")]) +(define_insn "*ieee128_mtvsrd_32bit" + [(set (match_operand:V2DI 0 "altivec_register_operand" "=v,v") + (unspec:V2DI [(match_operand:DI 1 "nonimmediate_operand" "Z,wi")] + UNSPEC_IEEE128_MOVE))] + "TARGET_FLOAT128_HW && !TARGET_POWERPC64" + "@ + lxsdx %x0,%y1 + xxlor %x0,%x1,%x1" + [(set_attr "type" "fpload,vecsimple")]) + ;; IEEE 128-bit instructions with round to odd semantics (define_insn "*trunc<mode>df2_odd" [(set (match_operand:DF 0 "vsx_register_operand" "=v") diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 61e3c8a323e..9a155ce0e05 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -1,6 +1,6 @@ ; Options for the rs6000 port of the compiler ; -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; Contributed by Aldy Hernandez <aldy@quesejoda.com>. ; ; This file is part of GCC. @@ -632,3 +632,7 @@ Enable/disable IEEE 128-bit floating point via the __float128 keyword. mfloat128-hardware Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags) Enable/disable using IEEE 128-bit floating point instructions. + +mfloat128-convert +Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags) +Enable/disable default conversions between __float128 & long double. diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md index 0d180c38ccd..b730aa82ec4 100644 --- a/gcc/config/rs6000/rs64.md +++ b/gcc/config/rs6000/rs64.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM RS64 processors. -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/rtems.h b/gcc/config/rs6000/rtems.h index b3ee387eaa3..1f1fec47ee7 100644 --- a/gcc/config/rs6000/rtems.h +++ b/gcc/config/rs6000/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a PowerPC using elf. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/rs6000/secureplt.h b/gcc/config/rs6000/secureplt.h index 77edf2aefae..78322065aa1 100644 --- a/gcc/config/rs6000/secureplt.h +++ b/gcc/config/rs6000/secureplt.h @@ -1,5 +1,5 @@ /* Default to -msecure-plt. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/si2vmx.h b/gcc/config/rs6000/si2vmx.h index e2c6f719bca..d5cc0086a48 100644 --- a/gcc/config/rs6000/si2vmx.h +++ b/gcc/config/rs6000/si2vmx.h @@ -1,5 +1,5 @@ /* Cell BEA specific SPU intrinsics to PPU/VMX intrinsics - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/rs6000/singlefp.h b/gcc/config/rs6000/singlefp.h index 7096d73efbb..23756e5c889 100644 --- a/gcc/config/rs6000/singlefp.h +++ b/gcc/config/rs6000/singlefp.h @@ -1,7 +1,7 @@ /* Definitions for PowerPC single-precision floating point unit such as Xilinx PowerPC 405/440 APU. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. Contributed by Michael Eager (eager@eagercon.com) This file is part of GCC. diff --git a/gcc/config/rs6000/spe.h b/gcc/config/rs6000/spe.h index 62208e6fe91..c4371e21d0d 100644 --- a/gcc/config/rs6000/spe.h +++ b/gcc/config/rs6000/spe.h @@ -1,5 +1,5 @@ /* PowerPC E500 user include file. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Aldy Hernandez (aldyh@redhat.com). This file is part of GCC. diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index d65dcf3121b..87fb787a1c1 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -1,5 +1,5 @@ ;; e500 SPE description -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; Contributed by Aldy Hernandez (aldy@quesejoda.com) ;; This file is part of GCC. diff --git a/gcc/config/rs6000/spu2vmx.h b/gcc/config/rs6000/spu2vmx.h index dc795a08bae..477cff1c4e3 100644 --- a/gcc/config/rs6000/spu2vmx.h +++ b/gcc/config/rs6000/spu2vmx.h @@ -1,5 +1,5 @@ /* Cell SPU 2 VMX intrinsics header - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md index d97df8b67fa..ee6e68d6e97 100644 --- a/gcc/config/rs6000/sync.md +++ b/gcc/config/rs6000/sync.md @@ -1,5 +1,5 @@ ;; Machine description for PowerPC synchronization instructions. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Geoffrey Keating. ;; This file is part of GCC. diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h index 20fa3eb07c5..cbf909722da 100644 --- a/gcc/config/rs6000/sysv4.h +++ b/gcc/config/rs6000/sysv4.h @@ -1,5 +1,5 @@ /* Target definitions for GNU compiler for PowerPC running System V.4 - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. Contributed by Cygnus Support. This file is part of GCC. diff --git a/gcc/config/rs6000/sysv4.opt b/gcc/config/rs6000/sysv4.opt index addc9db0a4c..581fcde4c55 100644 --- a/gcc/config/rs6000/sysv4.opt +++ b/gcc/config/rs6000/sysv4.opt @@ -1,6 +1,6 @@ ; SYSV4 options for PPC port. ; -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; Contributed by Aldy Hernandez <aldy@quesejoda.com>. ; ; This file is part of GCC. diff --git a/gcc/config/rs6000/sysv4le.h b/gcc/config/rs6000/sysv4le.h index f00e8b0b832..6b19b634c2b 100644 --- a/gcc/config/rs6000/sysv4le.h +++ b/gcc/config/rs6000/sysv4le.h @@ -1,6 +1,6 @@ /* Target definitions for GCC for a little endian PowerPC running System V.4 - Copyright (C) 1995-2015 Free Software Foundation, Inc. + Copyright (C) 1995-2016 Free Software Foundation, Inc. Contributed by Cygnus Support. This file is part of GCC. diff --git a/gcc/config/rs6000/t-aix43 b/gcc/config/rs6000/t-aix43 index 7e8e468e5bc..c3791076b4c 100644 --- a/gcc/config/rs6000/t-aix43 +++ b/gcc/config/rs6000/t-aix43 @@ -1,4 +1,4 @@ -# Copyright (C) 1998-2015 Free Software Foundation, Inc. +# Copyright (C) 1998-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-aix52 b/gcc/config/rs6000/t-aix52 index 6dca4b27012..cd11716952f 100644 --- a/gcc/config/rs6000/t-aix52 +++ b/gcc/config/rs6000/t-aix52 @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-fprules b/gcc/config/rs6000/t-fprules index dc345ad9e84..23544d15787 100644 --- a/gcc/config/rs6000/t-fprules +++ b/gcc/config/rs6000/t-fprules @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-freebsd64 b/gcc/config/rs6000/t-freebsd64 index e0c347cb369..fb7214f493a 100644 --- a/gcc/config/rs6000/t-freebsd64 +++ b/gcc/config/rs6000/t-freebsd64 @@ -1,6 +1,6 @@ #rs6000/t-freebsd64 -# Copyright (C) 2012-2015 Free Software Foundation, Inc. +# Copyright (C) 2012-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-linux64 b/gcc/config/rs6000/t-linux64 index b6b351d79a5..fa7550b2aff 100644 --- a/gcc/config/rs6000/t-linux64 +++ b/gcc/config/rs6000/t-linux64 @@ -1,6 +1,6 @@ #rs6000/t-linux64 -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-lynx b/gcc/config/rs6000/t-lynx index dcf982f1a27..611be0842e7 100644 --- a/gcc/config/rs6000/t-lynx +++ b/gcc/config/rs6000/t-lynx @@ -1,4 +1,4 @@ -# Copyright (C) 2004-2015 Free Software Foundation, Inc. +# Copyright (C) 2004-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-netbsd b/gcc/config/rs6000/t-netbsd index d431f7b39e2..c86daff7b80 100644 --- a/gcc/config/rs6000/t-netbsd +++ b/gcc/config/rs6000/t-netbsd @@ -1,6 +1,6 @@ # Support for NetBSD PowerPC ELF targets (SVR4 ABI). # -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-ppccomm b/gcc/config/rs6000/t-ppccomm index c05ba0a6cdb..6d144bb2975 100644 --- a/gcc/config/rs6000/t-ppccomm +++ b/gcc/config/rs6000/t-ppccomm @@ -1,6 +1,6 @@ # Common support for PowerPC ELF targets (both EABI and SVR4). # -# Copyright (C) 1996-2015 Free Software Foundation, Inc. +# Copyright (C) 1996-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-ppcendian b/gcc/config/rs6000/t-ppcendian index 352c7a49e41..1af3bf06ec7 100644 --- a/gcc/config/rs6000/t-ppcendian +++ b/gcc/config/rs6000/t-ppcendian @@ -1,6 +1,6 @@ # Multilibs for powerpc embedded ELF targets with altivec. # -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-ppcgas b/gcc/config/rs6000/t-ppcgas index ad2ae1b6615..204a5222bb1 100644 --- a/gcc/config/rs6000/t-ppcgas +++ b/gcc/config/rs6000/t-ppcgas @@ -1,6 +1,6 @@ # Multilibs for powerpc embedded ELF targets. # -# Copyright (C) 1995-2015 Free Software Foundation, Inc. +# Copyright (C) 1995-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000 index 1fe5a53ff8e..0ba0af0666c 100644 --- a/gcc/config/rs6000/t-rs6000 +++ b/gcc/config/rs6000/t-rs6000 @@ -1,6 +1,6 @@ # General rules that all rs6000/ targets must have. # -# Copyright (C) 1995-2015 Free Software Foundation, Inc. +# Copyright (C) 1995-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-rtems b/gcc/config/rs6000/t-rtems index 893321604ea..3baa94e25b8 100644 --- a/gcc/config/rs6000/t-rtems +++ b/gcc/config/rs6000/t-rtems @@ -1,6 +1,6 @@ # Multilibs for powerpc RTEMS targets. # -# Copyright (C) 2004-2015 Free Software Foundation, Inc. +# Copyright (C) 2004-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-spe b/gcc/config/rs6000/t-spe index 757008045c2..ffaf635a55e 100644 --- a/gcc/config/rs6000/t-spe +++ b/gcc/config/rs6000/t-spe @@ -1,6 +1,6 @@ # Multilibs for e500 # -# Copyright (C) 2003-2015 Free Software Foundation, Inc. +# Copyright (C) 2003-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-vxworks b/gcc/config/rs6000/t-vxworks index 97b70331c99..5a4dea5f36a 100644 --- a/gcc/config/rs6000/t-vxworks +++ b/gcc/config/rs6000/t-vxworks @@ -1,6 +1,6 @@ # Multilibs for VxWorks. # -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/rs6000/t-xilinx b/gcc/config/rs6000/t-xilinx index ff99be95a0c..b039ea65f94 100644 --- a/gcc/config/rs6000/t-xilinx +++ b/gcc/config/rs6000/t-xilinx @@ -1,6 +1,6 @@ # Multilibs for Xilinx powerpc embedded ELF targets. # -# Copyright (C) 2009-2015 Free Software Foundation, Inc. +# Copyright (C) 2009-2016 Free Software Foundation, Inc. # Contributed by Michael Eager, eager@eagercon.com # # This file is part of GCC. diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md index 736329cf498..74389534b45 100644 --- a/gcc/config/rs6000/titan.md +++ b/gcc/config/rs6000/titan.md @@ -1,5 +1,5 @@ ;; Pipeline description for the AppliedMicro Titan core. -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Theobroma Systems Design und Consulting GmbH ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/vec_types.h b/gcc/config/rs6000/vec_types.h index 7c674bcf75d..bb84236844c 100644 --- a/gcc/config/rs6000/vec_types.h +++ b/gcc/config/rs6000/vec_types.h @@ -1,5 +1,5 @@ /* Cell single token vector types - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index d8699c8a032..7eca7ce9755 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -3,7 +3,7 @@ ;; expander, and the actual vector instructions will be in altivec.md and ;; vsx.md -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com> ;; This file is part of GCC. @@ -113,6 +113,7 @@ } if (!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode) + && !TARGET_P9_VECTOR && !gpr_or_gpr_p (operands[0], operands[1]) && (memory_operand (operands[0], <MODE>mode) ^ memory_operand (operands[1], <MODE>mode))) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 2b92d451a54..997ff31aef3 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1,5 +1,5 @@ ;; VSX patterns. -;; Copyright (C) 2009-2015 Free Software Foundation, Inc. +;; Copyright (C) 2009-2016 Free Software Foundation, Inc. ;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com> ;; This file is part of GCC. @@ -26,15 +26,13 @@ ;; Iterator for the 2 64-bit vector types + 128-bit types that are loaded with ;; lxvd2x to properly handle swapping words on little endian -(define_mode_iterator VSX_LE [V2DF - V2DI - V1TI - (TI "VECTOR_MEM_VSX_P (TImode)")]) +(define_mode_iterator VSX_LE [V2DF V2DI V1TI]) ;; Mode iterator to handle swapping words on little endian for the 128-bit ;; types that goes in a single vector register. (define_mode_iterator VSX_LE_128 [(KF "FLOAT128_VECTOR_P (KFmode)") - (TF "FLOAT128_VECTOR_P (TFmode)")]) + (TF "FLOAT128_VECTOR_P (TFmode)") + (TI "TARGET_VSX_TIMODE")]) ;; Iterator for the 2 32-bit vector types (define_mode_iterator VSX_W [V4SF V4SI]) @@ -303,6 +301,24 @@ UNSPEC_VSX_XVCVDPUXDS ]) +;; VSX (P9) moves + +(define_insn "*p9_vecload_<mode>" + [(set (match_operand:VSX_M2 0 "vsx_register_operand" "=<VSa>") + (match_operand:VSX_M2 1 "memory_operand" "Z"))] + "TARGET_P9_VECTOR" + "lxvx %x0,%y1" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "*p9_vecstore_<mode>" + [(set (match_operand:VSX_M2 0 "memory_operand" "=Z") + (match_operand:VSX_M2 1 "vsx_register_operand" "<VSa>"))] + "TARGET_P9_VECTOR" + "stxvx %x1,%y0" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + ;; VSX moves ;; The patterns for LE permuted loads and stores come before the general @@ -310,9 +326,9 @@ (define_insn_and_split "*vsx_le_perm_load_<mode>" [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>") (match_operand:VSX_LE 1 "memory_operand" "Z"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" [(set (match_dup 2) (vec_select:<MODE> (match_dup 1) @@ -333,9 +349,9 @@ (define_insn_and_split "*vsx_le_perm_load_<mode>" [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>") (match_operand:VSX_W 1 "memory_operand" "Z"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" [(set (match_dup 2) (vec_select:<MODE> (match_dup 1) @@ -358,9 +374,9 @@ (define_insn_and_split "*vsx_le_perm_load_v8hi" [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa") (match_operand:V8HI 1 "memory_operand" "Z"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" [(set (match_dup 2) (vec_select:V8HI (match_dup 1) @@ -387,9 +403,9 @@ (define_insn_and_split "*vsx_le_perm_load_v16qi" [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") (match_operand:V16QI 1 "memory_operand" "Z"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" [(set (match_dup 2) (vec_select:V16QI (match_dup 1) @@ -424,7 +440,7 @@ (define_insn "*vsx_le_perm_store_<mode>" [(set (match_operand:VSX_LE 0 "memory_operand" "=Z") (match_operand:VSX_LE 1 "vsx_register_operand" "+<VSa>"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") (set_attr "length" "12")]) @@ -432,7 +448,7 @@ (define_split [(set (match_operand:VSX_LE 0 "memory_operand" "") (match_operand:VSX_LE 1 "vsx_register_operand" ""))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) (vec_select:<MODE> (match_dup 1) @@ -451,7 +467,7 @@ (define_split [(set (match_operand:VSX_LE 0 "memory_operand" "") (match_operand:VSX_LE 1 "vsx_register_operand" ""))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) (vec_select:<MODE> (match_dup 1) @@ -469,7 +485,7 @@ (define_insn "*vsx_le_perm_store_<mode>" [(set (match_operand:VSX_W 0 "memory_operand" "=Z") (match_operand:VSX_W 1 "vsx_register_operand" "+<VSa>"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") (set_attr "length" "12")]) @@ -477,7 +493,7 @@ (define_split [(set (match_operand:VSX_W 0 "memory_operand" "") (match_operand:VSX_W 1 "vsx_register_operand" ""))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) (vec_select:<MODE> (match_dup 1) @@ -498,7 +514,7 @@ (define_split [(set (match_operand:VSX_W 0 "memory_operand" "") (match_operand:VSX_W 1 "vsx_register_operand" ""))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) (vec_select:<MODE> (match_dup 1) @@ -519,7 +535,7 @@ (define_insn "*vsx_le_perm_store_v8hi" [(set (match_operand:V8HI 0 "memory_operand" "=Z") (match_operand:V8HI 1 "vsx_register_operand" "+wa"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") (set_attr "length" "12")]) @@ -527,7 +543,7 @@ (define_split [(set (match_operand:V8HI 0 "memory_operand" "") (match_operand:V8HI 1 "vsx_register_operand" ""))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) (vec_select:V8HI (match_dup 1) @@ -552,7 +568,7 @@ (define_split [(set (match_operand:V8HI 0 "memory_operand" "") (match_operand:V8HI 1 "vsx_register_operand" ""))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) (vec_select:V8HI (match_dup 1) @@ -579,7 +595,7 @@ (define_insn "*vsx_le_perm_store_v16qi" [(set (match_operand:V16QI 0 "memory_operand" "=Z") (match_operand:V16QI 1 "vsx_register_operand" "+wa"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") (set_attr "length" "12")]) @@ -587,7 +603,7 @@ (define_split [(set (match_operand:V16QI 0 "memory_operand" "") (match_operand:V16QI 1 "vsx_register_operand" ""))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed" [(set (match_dup 2) (vec_select:V16QI (match_dup 1) @@ -620,7 +636,7 @@ (define_split [(set (match_operand:V16QI 0 "memory_operand" "") (match_operand:V16QI 1 "vsx_register_operand" ""))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed" [(set (match_dup 1) (vec_select:V16QI (match_dup 1) @@ -664,7 +680,7 @@ (rotate:VSX_LE_128 (match_operand:VSX_LE_128 1 "input_operand" "<VSa>,Z,<VSa>") (const_int 64)))] - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "@ xxpermdi %x0,%x1,%x1,2 lxvd2x %x0,%y1 @@ -698,9 +714,9 @@ (define_insn_and_split "*vsx_le_perm_load_<mode>" [(set (match_operand:VSX_LE_128 0 "vsx_register_operand" "=<VSa>") (match_operand:VSX_LE_128 1 "memory_operand" "Z"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" [(set (match_dup 2) (rotate:VSX_LE_128 (match_dup 1) (const_int 64))) @@ -719,7 +735,7 @@ (define_insn "*vsx_le_perm_store_<mode>" [(set (match_operand:VSX_LE_128 0 "memory_operand" "=Z") (match_operand:VSX_LE_128 1 "vsx_register_operand" "+<VSa>"))] - "!BYTES_BIG_ENDIAN && TARGET_VSX" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") (set_attr "length" "12")]) @@ -727,7 +743,7 @@ (define_split [(set (match_operand:VSX_LE_128 0 "memory_operand" "") (match_operand:VSX_LE_128 1 "vsx_register_operand" ""))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed" + "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed && !TARGET_P9_VECTOR" [(set (match_dup 2) (rotate:VSX_LE_128 (match_dup 1) (const_int 64))) @@ -739,12 +755,27 @@ : operands[0]; }) +;; Peephole to catch memory to memory transfers for TImode if TImode landed in +;; VSX registers on a little endian system. The vector types and IEEE 128-bit +;; floating point are handled by the more generic swap elimination pass. +(define_peephole2 + [(set (match_operand:TI 0 "vsx_register_operand" "") + (rotate:TI (match_operand:TI 1 "vsx_register_operand" "") + (const_int 64))) + (set (match_operand:TI 2 "vsx_register_operand" "") + (rotate:TI (match_dup 0) + (const_int 64)))] + "!BYTES_BIG_ENDIAN && TARGET_VSX && TARGET_VSX_TIMODE && !TARGET_P9_VECTOR + && (rtx_equal_p (operands[0], operands[2]) + || peep2_reg_dead_p (2, operands[0]))" + [(set (match_dup 2) (match_dup 1))]) + ;; The post-reload split requires that we re-permute the source ;; register in case it is still live. (define_split [(set (match_operand:VSX_LE_128 0 "memory_operand" "") (match_operand:VSX_LE_128 1 "vsx_register_operand" ""))] - "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed" + "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed && !TARGET_P9_VECTOR" [(set (match_dup 1) (rotate:VSX_LE_128 (match_dup 1) (const_int 64))) @@ -1768,7 +1799,7 @@ (vec_select:VSX_LE (match_operand:VSX_LE 1 "memory_operand" "Z") (parallel [(const_int 1) (const_int 0)])))] - "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)" + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode) && !TARGET_P9_VECTOR" "lxvd2x %x0,%y1" [(set_attr "type" "vecload")]) @@ -1778,7 +1809,7 @@ (match_operand:VSX_W 1 "memory_operand" "Z") (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] - "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)" + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode) && !TARGET_P9_VECTOR" "lxvd2x %x0,%y1" [(set_attr "type" "vecload")]) @@ -1790,7 +1821,7 @@ (const_int 6) (const_int 7) (const_int 0) (const_int 1) (const_int 2) (const_int 3)])))] - "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode)" + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode) && !TARGET_P9_VECTOR" "lxvd2x %x0,%y1" [(set_attr "type" "vecload")]) @@ -1806,7 +1837,7 @@ (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)])))] - "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode)" + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode) && !TARGET_P9_VECTOR" "lxvd2x %x0,%y1" [(set_attr "type" "vecload")]) @@ -1817,7 +1848,7 @@ (vec_select:VSX_LE (match_operand:VSX_LE 1 "vsx_register_operand" "<VSa>") (parallel [(const_int 1) (const_int 0)])))] - "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)" + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode) && !TARGET_P9_VECTOR" "stxvd2x %x1,%y0" [(set_attr "type" "vecstore")]) @@ -1827,7 +1858,7 @@ (match_operand:VSX_W 1 "vsx_register_operand" "<VSa>") (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] - "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)" + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode) && !TARGET_P9_VECTOR" "stxvd2x %x1,%y0" [(set_attr "type" "vecstore")]) @@ -1839,7 +1870,7 @@ (const_int 6) (const_int 7) (const_int 0) (const_int 1) (const_int 2) (const_int 3)])))] - "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode)" + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode) && !TARGET_P9_VECTOR" "stxvd2x %x1,%y0" [(set_attr "type" "vecstore")]) @@ -1855,7 +1886,7 @@ (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)])))] - "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode)" + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode) && !TARGET_P9_VECTOR" "stxvd2x %x1,%y0" [(set_attr "type" "vecstore")]) @@ -2443,7 +2474,7 @@ (set (match_operand:VSX_M2 2 "vsx_register_operand" "") (mem:VSX_M2 (plus:P (match_dup 0) (match_operand:P 3 "int_reg_operand" ""))))] - "TARGET_VSX && TARGET_P8_FUSION" + "TARGET_VSX && TARGET_P8_FUSION && !TARGET_P9_VECTOR" "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M2:VSm>x %x2,%0,%3" [(set_attr "length" "8") (set_attr "type" "vecload")]) @@ -2454,7 +2485,7 @@ (set (match_operand:VSX_M2 2 "vsx_register_operand" "") (mem:VSX_M2 (plus:P (match_operand:P 3 "int_reg_operand" "") (match_dup 0))))] - "TARGET_VSX && TARGET_P8_FUSION" + "TARGET_VSX && TARGET_P8_FUSION && !TARGET_P9_VECTOR" "li %0,%1\t\t\t# vector load fusion\;lx<VSX_M2:VSm>x %x2,%0,%3" [(set_attr "length" "8") (set_attr "type" "vecload")]) diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h index 744017204ab..901a81c78d9 100644 --- a/gcc/config/rs6000/vxworks.h +++ b/gcc/config/rs6000/vxworks.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. Vxworks PowerPC version. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/rs6000/vxworksae.h b/gcc/config/rs6000/vxworksae.h index caee36c6efe..e607973252a 100644 --- a/gcc/config/rs6000/vxworksae.h +++ b/gcc/config/rs6000/vxworksae.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. PowerPC VxworksAE version. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/rs6000/vxworksmils.h b/gcc/config/rs6000/vxworksmils.h index 684c00b147c..a964581f7f5 100644 --- a/gcc/config/rs6000/vxworksmils.h +++ b/gcc/config/rs6000/vxworksmils.h @@ -1,7 +1,7 @@ /* PowerPC VxWorks MILS target definitions for GNU compiler. Overrides on top of the canonical VxWorks definitions. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/xcoff.h b/gcc/config/rs6000/xcoff.h index 301c7e1a56d..b7f6ca0685b 100644 --- a/gcc/config/rs6000/xcoff.h +++ b/gcc/config/rs6000/xcoff.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for some generic XCOFF file format - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rs6000/xfpu.h b/gcc/config/rs6000/xfpu.h index bd7038ee0a6..8d1bec47f09 100644 --- a/gcc/config/rs6000/xfpu.h +++ b/gcc/config/rs6000/xfpu.h @@ -1,6 +1,6 @@ /* Definitions for Xilinx PowerPC 405/440 APU. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. Contributed by Michael Eager (eager@eagercon.com) This file is part of GCC. diff --git a/gcc/config/rs6000/xfpu.md b/gcc/config/rs6000/xfpu.md index 9a603a2d515..14557eb81b7 100644 --- a/gcc/config/rs6000/xfpu.md +++ b/gcc/config/rs6000/xfpu.md @@ -1,5 +1,5 @@ ;; Scheduling description for the Xilinx PowerPC 405 APU Floating Point Unit. -;; Copyright (C) 2008-2015 Free Software Foundation, Inc. +;; Copyright (C) 2008-2016 Free Software Foundation, Inc. ;; Contributed by Michael Eager (eager@eagercon.com). ;; ;; This file is part of GCC. diff --git a/gcc/config/rs6000/xilinx.h b/gcc/config/rs6000/xilinx.h index 43a5ebac7dc..e3dec3f570e 100644 --- a/gcc/config/rs6000/xilinx.h +++ b/gcc/config/rs6000/xilinx.h @@ -1,5 +1,5 @@ /* Support for GCC on Xilinx embedded PowerPC systems - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. Contributed by Michael Eager, eager@eagercon.com This file is part of GCC. diff --git a/gcc/config/rs6000/xilinx.opt b/gcc/config/rs6000/xilinx.opt index c8d939ebb9a..4c70d57d5eb 100644 --- a/gcc/config/rs6000/xilinx.opt +++ b/gcc/config/rs6000/xilinx.opt @@ -1,6 +1,6 @@ ; Xilinx embedded PowerPC options. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/rtems.h b/gcc/config/rtems.h index af848403016..f13f72fd17c 100644 --- a/gcc/config/rtems.h +++ b/gcc/config/rtems.h @@ -1,5 +1,5 @@ /* Configuration common to all targets running RTEMS. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rtems.opt b/gcc/config/rtems.opt index 9c0ee837172..d56802b09d6 100644 --- a/gcc/config/rtems.opt +++ b/gcc/config/rtems.opt @@ -1,6 +1,6 @@ ; RTEMS options. -; Copyright (C) 2010-2015 Free Software Foundation, Inc. +; Copyright (C) 2010-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/rx/constraints.md b/gcc/config/rx/constraints.md index b41c232fff1..065e0ce6491 100644 --- a/gcc/config/rx/constraints.md +++ b/gcc/config/rx/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Renesas RX. -;; Copyright (C) 2008-2015 Free Software Foundation, Inc. +;; Copyright (C) 2008-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/rx/predicates.md b/gcc/config/rx/predicates.md index 26667cfda05..b00c1e31117 100644 --- a/gcc/config/rx/predicates.md +++ b/gcc/config/rx/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Renesas RX. -;; Copyright (C) 2008-2015 Free Software Foundation, Inc. +;; Copyright (C) 2008-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; ;; This file is part of GCC. diff --git a/gcc/config/rx/rx-modes.def b/gcc/config/rx/rx-modes.def index 60f872cf5e0..c71a3d69dc0 100644 --- a/gcc/config/rx/rx-modes.def +++ b/gcc/config/rx/rx-modes.def @@ -1,5 +1,5 @@ /* Definitions of target specific machine modes for the RX. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/rx/rx-opts.h b/gcc/config/rx/rx-opts.h index fa83e91b515..ec63b1322f7 100644 --- a/gcc/config/rx/rx-opts.h +++ b/gcc/config/rx/rx-opts.h @@ -1,5 +1,5 @@ /* GCC option-handling definitions for the Renesas RX processor. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/rx/rx-protos.h b/gcc/config/rx/rx-protos.h index 4986fe542bb..160b9cce4aa 100644 --- a/gcc/config/rx/rx-protos.h +++ b/gcc/config/rx/rx-protos.h @@ -1,5 +1,5 @@ /* Exported function prototypes from the Renesas RX backend. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c index 781b6b1b2b1..4cf840c26d1 100644 --- a/gcc/config/rx/rx.c +++ b/gcc/config/rx/rx.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on Renesas RX processors. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/rx/rx.h b/gcc/config/rx/rx.h index d2d6bce48c8..a6300cc0016 100644 --- a/gcc/config/rx/rx.h +++ b/gcc/config/rx/rx.h @@ -1,5 +1,5 @@ /* GCC backend definitions for the Renesas RX processor. - Copyright (C) 2008-2015 Free Software Foundation, Inc. + Copyright (C) 2008-2016 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of GCC. diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md index 6faf7719a9a..5b79e6a3571 100644 --- a/gcc/config/rx/rx.md +++ b/gcc/config/rx/rx.md @@ -1,5 +1,5 @@ ;; Machine Description for Renesas RX processors -;; Copyright (C) 2008-2015 Free Software Foundation, Inc. +;; Copyright (C) 2008-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat. ;; This file is part of GCC. diff --git a/gcc/config/rx/rx.opt b/gcc/config/rx/rx.opt index 56e8adf3f5c..3ca27216f26 100644 --- a/gcc/config/rx/rx.opt +++ b/gcc/config/rx/rx.opt @@ -1,5 +1,5 @@ ; Command line options for the Renesas RX port of GCC. -; Copyright (C) 2008-2015 Free Software Foundation, Inc. +; Copyright (C) 2008-2016 Free Software Foundation, Inc. ; Contributed by Red Hat. ; ; This file is part of GCC. diff --git a/gcc/config/rx/t-rx b/gcc/config/rx/t-rx index f29fd3dc0a5..4b4a2dc17ac 100644 --- a/gcc/config/rx/t-rx +++ b/gcc/config/rx/t-rx @@ -1,5 +1,5 @@ # Makefile fragment for building GCC for the Renesas RX target. -# Copyright (C) 2008-2015 Free Software Foundation, Inc. +# Copyright (C) 2008-2016 Free Software Foundation, Inc. # Contributed by Red Hat. # # This file is part of GCC. diff --git a/gcc/config/s390/2064.md b/gcc/config/s390/2064.md index 0c147e51217..d5dabc7679c 100644 --- a/gcc/config/s390/2064.md +++ b/gcc/config/s390/2064.md @@ -1,5 +1,5 @@ ;; Scheduling description for z900 (cpu 2064). -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and ;; Ulrich Weigand (uweigand@de.ibm.com). diff --git a/gcc/config/s390/2084.md b/gcc/config/s390/2084.md index f5597c8fea0..0cfc0fa3b59 100644 --- a/gcc/config/s390/2084.md +++ b/gcc/config/s390/2084.md @@ -1,5 +1,5 @@ ;; Scheduling description for z990 (cpu 2084). -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and ;; Ulrich Weigand (uweigand@de.ibm.com). diff --git a/gcc/config/s390/2097.md b/gcc/config/s390/2097.md index 4d7c0a91caa..1d312e73af5 100644 --- a/gcc/config/s390/2097.md +++ b/gcc/config/s390/2097.md @@ -1,5 +1,5 @@ ;; Scheduling description for z10 (cpu 2097). -;; Copyright (C) 2008-2015 Free Software Foundation, Inc. +;; Copyright (C) 2008-2016 Free Software Foundation, Inc. ;; Contributed by Wolfgang Gellerich (gellerich@de.ibm.com). diff --git a/gcc/config/s390/2817.md b/gcc/config/s390/2817.md index d00c5883251..2f4a8833b0d 100644 --- a/gcc/config/s390/2817.md +++ b/gcc/config/s390/2817.md @@ -1,5 +1,5 @@ ;; Scheduling description for z196 (cpu 2817). -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; Contributed by Christian Borntraeger (Christian.Borntraeger@de.ibm.com) ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) diff --git a/gcc/config/s390/2827.md b/gcc/config/s390/2827.md index f292046316d..7baf9900f03 100644 --- a/gcc/config/s390/2827.md +++ b/gcc/config/s390/2827.md @@ -1,5 +1,5 @@ ;; Scheduling description for zEC12 (cpu 2827). -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) ;; This file is part of GCC. diff --git a/gcc/config/s390/constraints.md b/gcc/config/s390/constraints.md index 1dab92ac66a..c1d2c8ec8f8 100644 --- a/gcc/config/s390/constraints.md +++ b/gcc/config/s390/constraints.md @@ -1,5 +1,5 @@ ;; Constraints definitions belonging to the gcc backend for IBM S/390. -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; Written by Wolfgang Gellerich, using code and information found in ;; files s390.md, s390.h, and s390.c. ;; diff --git a/gcc/config/s390/driver-native.c b/gcc/config/s390/driver-native.c index 5f7fe0aaea7..a59d177ba43 100644 --- a/gcc/config/s390/driver-native.c +++ b/gcc/config/s390/driver-native.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. This file is part of GCC. @@ -84,9 +84,8 @@ s390_host_detect_local_cpu (int argc, const char **argv) machine_id = strtol (p, NULL, 16); switch (machine_id) { + /* g5 and g6 default to z900 */ case 0x9672: - cpu = "g5"; - break; case 0x2064: case 0x2066: cpu = "z900"; diff --git a/gcc/config/s390/htmintrin.h b/gcc/config/s390/htmintrin.h index a5d0e9a38a1..b6abcff5a0d 100644 --- a/gcc/config/s390/htmintrin.h +++ b/gcc/config/s390/htmintrin.h @@ -1,5 +1,5 @@ /* GNU compiler hardware transactional execution intrinsics - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) This file is part of GCC. diff --git a/gcc/config/s390/htmxlintrin.h b/gcc/config/s390/htmxlintrin.h index 5e33fa7fd29..1318acd31c8 100644 --- a/gcc/config/s390/htmxlintrin.h +++ b/gcc/config/s390/htmxlintrin.h @@ -1,5 +1,5 @@ /* XL compiler hardware transactional execution intrinsics - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) This file is part of GCC. diff --git a/gcc/config/s390/linux.h b/gcc/config/s390/linux.h index 21f9825bf65..9b00af72b47 100644 --- a/gcc/config/s390/linux.h +++ b/gcc/config/s390/linux.h @@ -1,5 +1,5 @@ /* Definitions for Linux for S/390. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by Hartmut Penner (hpenner@de.ibm.com) and Ulrich Weigand (uweigand@de.ibm.com). diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md index 5c462c4fac5..cbc80921479 100644 --- a/gcc/config/s390/predicates.md +++ b/gcc/config/s390/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for S/390 and zSeries. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and ;; Ulrich Weigand (uweigand@de.ibm.com). ;; @@ -29,9 +29,10 @@ (and (match_code "const_int,const_wide_int,const_double,const_vector") (match_test "op == CONST0_RTX (mode)"))) -;; Return true if OP an all ones operand (int/float/vector). -(define_predicate "constm1_operand" - (and (match_code "const_int,const_wide_int,const_double,const_vector") +;; Return true if OP an all ones operand (int/vector). +(define_predicate "all_ones_operand" + (and (match_code "const_int, const_wide_int, const_vector") + (match_test "INTEGRAL_MODE_P (GET_MODE (op))") (match_test "op == CONSTM1_RTX (mode)"))) ;; Return true if OP is a 4 bit mask operand @@ -121,10 +122,7 @@ ;; Return true if OP a valid operand for the LARL instruction. (define_predicate "larl_operand" -; Note: Although CONST_INT and CONST_DOUBLE are not handled in this predicate, -; at least one of them needs to appear or otherwise safe_predicate_mode will -; assume that a VOIDmode LABEL_REF is not accepted either (see genrecog.c). - (match_code "label_ref, symbol_ref, const, const_int, const_double") + (match_code "label_ref, symbol_ref, const") { /* Allow labels and local symbols. */ if (GET_CODE (op) == LABEL_REF) diff --git a/gcc/config/s390/s390-builtin-types.def b/gcc/config/s390/s390-builtin-types.def index bd3d534cbb2..6179b040e27 100644 --- a/gcc/config/s390/s390-builtin-types.def +++ b/gcc/config/s390/s390-builtin-types.def @@ -1,5 +1,5 @@ /* Builtin type definitions for IBM S/390 and zSeries - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com). diff --git a/gcc/config/s390/s390-builtins.def b/gcc/config/s390/s390-builtins.def index b0a86e97999..408c51980c7 100644 --- a/gcc/config/s390/s390-builtins.def +++ b/gcc/config/s390/s390-builtins.def @@ -1,5 +1,5 @@ /* Builtin definitions for IBM S/390 and zSeries - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com). diff --git a/gcc/config/s390/s390-builtins.h b/gcc/config/s390/s390-builtins.h index f8f010ddad6..a56f3ad2514 100644 --- a/gcc/config/s390/s390-builtins.h +++ b/gcc/config/s390/s390-builtins.h @@ -1,5 +1,5 @@ /* Common data structures used for builtin handling on S/390. - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com). diff --git a/gcc/config/s390/s390-c.c b/gcc/config/s390/s390-c.c index d87cc90b0da..14d030d217c 100644 --- a/gcc/config/s390/s390-c.c +++ b/gcc/config/s390/s390-c.c @@ -1,6 +1,6 @@ /* Language specific subroutines used for code generation on IBM S/390 and zSeries - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com). diff --git a/gcc/config/s390/s390-modes.def b/gcc/config/s390/s390-modes.def index f4c53f82552..69235b61cab 100644 --- a/gcc/config/s390/s390-modes.def +++ b/gcc/config/s390/s390-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM S/390 - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Hartmut Penner (hpenner@de.ibm.com) and Ulrich Weigand (uweigand@de.ibm.com). diff --git a/gcc/config/s390/s390-opts.h b/gcc/config/s390/s390-opts.h index 39b8824040d..0ad87a26985 100644 --- a/gcc/config/s390/s390-opts.h +++ b/gcc/config/s390/s390-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for IBM S/390. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/s390/s390-protos.h b/gcc/config/s390/s390-protos.h index 962abb155c0..633bc1e072e 100644 --- a/gcc/config/s390/s390-protos.h +++ b/gcc/config/s390/s390-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM S/390. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Hartmut Penner (hpenner@de.ibm.com) diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index bc6f05b56cd..21a568767b7 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on IBM S/390 and zSeries - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by Hartmut Penner (hpenner@de.ibm.com) and Ulrich Weigand (uweigand@de.ibm.com) and Andreas Krebbel (Andreas.Krebbel@de.ibm.com). @@ -6139,29 +6139,70 @@ s390_expand_vcond (rtx target, rtx then, rtx els, machine_mode result_mode; rtx result_target; + machine_mode target_mode = GET_MODE (target); + machine_mode cmp_mode = GET_MODE (cmp_op1); + rtx op = (cond == LT) ? els : then; + + /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31 + and x < 0 ? 1 : 0 into (unsigned) x >> 31. Likewise + for short and byte (x >> 15 and x >> 7 respectively). */ + if ((cond == LT || cond == GE) + && target_mode == cmp_mode + && cmp_op2 == CONST0_RTX (cmp_mode) + && op == CONST0_RTX (target_mode) + && s390_vector_mode_supported_p (target_mode) + && GET_MODE_CLASS (target_mode) == MODE_VECTOR_INT) + { + rtx negop = (cond == LT) ? then : els; + + int shift = GET_MODE_BITSIZE (GET_MODE_INNER (target_mode)) - 1; + + /* if x < 0 ? 1 : 0 or if x >= 0 ? 0 : 1 */ + if (negop == CONST1_RTX (target_mode)) + { + rtx res = expand_simple_binop (cmp_mode, LSHIFTRT, cmp_op1, + GEN_INT (shift), target, + 1, OPTAB_DIRECT); + if (res != target) + emit_move_insn (target, res); + return; + } + + /* if x < 0 ? -1 : 0 or if x >= 0 ? 0 : -1 */ + else if (all_ones_operand (negop, target_mode)) + { + rtx res = expand_simple_binop (cmp_mode, ASHIFTRT, cmp_op1, + GEN_INT (shift), target, + 0, OPTAB_DIRECT); + if (res != target) + emit_move_insn (target, res); + return; + } + } + /* We always use an integral type vector to hold the comparison result. */ - result_mode = GET_MODE (cmp_op1) == V2DFmode ? V2DImode : GET_MODE (cmp_op1); + result_mode = cmp_mode == V2DFmode ? V2DImode : cmp_mode; result_target = gen_reg_rtx (result_mode); - /* Alternatively this could be done by reload by lowering the cmp* - predicates. But it appears to be better for scheduling etc. to - have that in early. */ + /* We allow vector immediates as comparison operands that + can be handled by the optimization above but not by the + following code. Hence, force them into registers here. */ if (!REG_P (cmp_op1)) - cmp_op1 = force_reg (GET_MODE (target), cmp_op1); + cmp_op1 = force_reg (target_mode, cmp_op1); if (!REG_P (cmp_op2)) - cmp_op2 = force_reg (GET_MODE (target), cmp_op2); + cmp_op2 = force_reg (target_mode, cmp_op2); s390_expand_vec_compare (result_target, cond, cmp_op1, cmp_op2); /* If the results are supposed to be either -1 or 0 we are done since this is what our compare instructions generate anyway. */ - if (constm1_operand (then, GET_MODE (then)) + if (all_ones_operand (then, GET_MODE (then)) && const0_operand (els, GET_MODE (els))) { - emit_move_insn (target, gen_rtx_SUBREG (GET_MODE (target), + emit_move_insn (target, gen_rtx_SUBREG (target_mode, result_target, 0)); return; } @@ -6170,10 +6211,10 @@ s390_expand_vcond (rtx target, rtx then, rtx els, /* This gets triggered e.g. with gcc.c-torture/compile/pr53410-1.c */ if (!REG_P (then)) - then = force_reg (GET_MODE (target), then); + then = force_reg (target_mode, then); if (!REG_P (els)) - els = force_reg (GET_MODE (target), els); + els = force_reg (target_mode, els); tmp = gen_rtx_fmt_ee (EQ, VOIDmode, result_target, @@ -6181,9 +6222,9 @@ s390_expand_vcond (rtx target, rtx then, rtx els, /* We compared the result against zero above so we have to swap then and els here. */ - tmp = gen_rtx_IF_THEN_ELSE (GET_MODE (target), tmp, els, then); + tmp = gen_rtx_IF_THEN_ELSE (target_mode, tmp, els, then); - gcc_assert (GET_MODE (target) == GET_MODE (then)); + gcc_assert (target_mode == GET_MODE (then)); emit_insn (gen_rtx_SET (target, tmp)); } @@ -9543,10 +9584,17 @@ s390_init_frame_layout (void) as base register to avoid save/restore overhead. */ if (!base_used) cfun->machine->base_reg = NULL_RTX; - else if (crtl->is_leaf && !df_regs_ever_live_p (5)) - cfun->machine->base_reg = gen_rtx_REG (Pmode, 5); else - cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM); + { + int br = 0; + + if (crtl->is_leaf) + /* Prefer r5 (most likely to be free). */ + for (br = 5; br >= 2 && df_regs_ever_live_p (br); br--) + ; + cfun->machine->base_reg = + gen_rtx_REG (Pmode, (br >= 2) ? br : BASE_REGNUM); + } s390_register_info (); s390_frame_info (); @@ -13569,9 +13617,27 @@ s390_function_specific_restore (struct gcc_options *opts, } static void -s390_option_override_internal (struct gcc_options *opts, +s390_option_override_internal (bool main_args_p, + struct gcc_options *opts, const struct gcc_options *opts_set) { + const char *prefix; + const char *suffix; + + /* Set up prefix/suffix so the error messages refer to either the command + line argument, or the attribute(target). */ + if (main_args_p) + { + prefix = "-m"; + suffix = ""; + } + else + { + prefix = "option(\""; + suffix = "\")"; + } + + /* Architecture mode defaults according to ABI. */ if (!(opts_set->x_target_flags & MASK_ZARCH)) { @@ -13583,13 +13649,26 @@ s390_option_override_internal (struct gcc_options *opts, /* Set the march default in case it hasn't been specified on cmdline. */ if (!opts_set->x_s390_arch) - opts->x_s390_arch = TARGET_ZARCH_P (opts->x_target_flags) - ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5; + opts->x_s390_arch = PROCESSOR_2064_Z900; + else if (opts->x_s390_arch == PROCESSOR_9672_G5 + || opts->x_s390_arch == PROCESSOR_9672_G6) + warning (OPT_Wdeprecated, "%sarch=%s%s is deprecated and will be removed " + "in future releases; use at least %sarch=z900%s", + prefix, opts->x_s390_arch == PROCESSOR_9672_G5 ? "g5" : "g6", + suffix, prefix, suffix); + opts->x_s390_arch_flags = processor_flags_table[(int) opts->x_s390_arch]; /* Determine processor to tune for. */ if (!opts_set->x_s390_tune) opts->x_s390_tune = opts->x_s390_arch; + else if (opts->x_s390_tune == PROCESSOR_9672_G5 + || opts->x_s390_tune == PROCESSOR_9672_G6) + warning (OPT_Wdeprecated, "%stune=%s%s is deprecated and will be removed " + "in future releases; use at least %stune=z900%s", + prefix, opts->x_s390_tune == PROCESSOR_9672_G5 ? "g5" : "g6", + suffix, prefix, suffix); + opts->x_s390_tune_flags = processor_flags_table[opts->x_s390_tune]; /* Sanity checks. */ @@ -13800,7 +13879,7 @@ s390_option_override (void) /* Set up function hooks. */ init_machine_status = s390_init_machine_status; - s390_option_override_internal (&global_options, &global_options_set); + s390_option_override_internal (true, &global_options, &global_options_set); /* Save the initial options in case the user does function specific options. */ @@ -14102,7 +14181,7 @@ s390_valid_target_attribute_tree (tree args, dest[i] |= src[i]; /* Do any overrides, such as arch=xxx, or tune=xxx support. */ - s390_option_override_internal (opts, &new_opts_set); + s390_option_override_internal (false, opts, &new_opts_set); /* Save the current options unless we are validating options for #pragma. */ t = build_target_option_node (opts); diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h index 52ed7a4a477..3a7be1af779 100644 --- a/gcc/config/s390/s390.h +++ b/gcc/config/s390/s390.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM S/390 - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by Hartmut Penner (hpenner@de.ibm.com) and Ulrich Weigand (uweigand@de.ibm.com). Andreas Krebbel (Andreas.Krebbel@de.ibm.com) @@ -214,7 +214,7 @@ extern const char *s390_host_detect_local_cpu (int argc, const char **argv); MARCH_MTUNE_NATIVE_SPECS, \ "%{!m31:%{!m64:-m" S390_TARGET_BITS_STRING "}}", \ "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ - "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" + "%{!march=*:-march=z900}" /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */ #define S390_TDC_POSITIVE_ZERO (1 << 11) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index a1fc96a0adc..3e340c35030 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -1,5 +1,5 @@ ;;- Machine description for GNU compiler -- S/390 / zSeries version. -;; Copyright (C) 1999-2015 Free Software Foundation, Inc. +;; Copyright (C) 1999-2016 Free Software Foundation, Inc. ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and ;; Ulrich Weigand (uweigand@de.ibm.com) and ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) @@ -10522,11 +10522,9 @@ (bswap:HI (match_operand:HI 1 "register_operand" "")))] "TARGET_CPU_ZARCH" [(set (match_dup 2) (bswap:SI (match_dup 3))) - (set (match_dup 2) (lshiftrt:SI (match_dup 2) - (const_int 16))) - (set (match_dup 0) (subreg:HI (match_dup 2) 2))] + (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] { - operands[2] = gen_reg_rtx (SImode); + operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); }) diff --git a/gcc/config/s390/s390.opt b/gcc/config/s390/s390.opt index a37c853d03d..1ae1396e9a5 100644 --- a/gcc/config/s390/s390.opt +++ b/gcc/config/s390/s390.opt @@ -1,6 +1,6 @@ ; Options for the S/390 / zSeries port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; @@ -171,12 +171,12 @@ Schedule code for given CPU. mmvcle Target Report Mask(MVCLE) Save -mvcle use. +Use the mvcle instruction for block moves. mzvector Target Report Mask(ZVECTOR) Save Enable the z vector language extension providing the context-sensitive -vector macro and enable the Altivec-style builtins in vecintrin.h +vector macro and enable the Altivec-style builtins in vecintrin.h. mwarn-dynamicstack Target Var(s390_warn_dynamicstack_p) Save diff --git a/gcc/config/s390/s390intrin.h b/gcc/config/s390/s390intrin.h index c25f69ef71a..43a875b464e 100644 --- a/gcc/config/s390/s390intrin.h +++ b/gcc/config/s390/s390intrin.h @@ -1,5 +1,5 @@ /* S/390 System z specific intrinsics - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) This file is part of GCC. diff --git a/gcc/config/s390/s390x.h b/gcc/config/s390/s390x.h index e84113148d1..ce56ae235fb 100644 --- a/gcc/config/s390/s390x.h +++ b/gcc/config/s390/s390x.h @@ -1,5 +1,5 @@ /* Definitions of target machine for IBM zSeries 64-bit - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Hartmut Penner (hpenner@de.ibm.com) and Ulrich Weigand (uweigand@de.ibm.com). diff --git a/gcc/config/s390/t-s390 b/gcc/config/s390/t-s390 index 800412c9dd2..fcffb17a4cc 100644 --- a/gcc/config/s390/t-s390 +++ b/gcc/config/s390/t-s390 @@ -1,4 +1,4 @@ -# Copyright (C) 2015 Free Software Foundation, Inc. +# Copyright (C) 2015-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/s390/tpf.h b/gcc/config/s390/tpf.h index b1ec9bdeab3..f794c6841d1 100644 --- a/gcc/config/s390/tpf.h +++ b/gcc/config/s390/tpf.h @@ -1,5 +1,5 @@ /* Definitions for target OS TPF for GNU compiler, for IBM S/390 hardware - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. Contributed by P.J. Darcy (darcypj@us.ibm.com), Hartmut Penner (hpenner@de.ibm.com), and Ulrich Weigand (uweigand@de.ibm.com). diff --git a/gcc/config/s390/tpf.md b/gcc/config/s390/tpf.md index 5634ebd3a23..b1254e30e63 100644 --- a/gcc/config/s390/tpf.md +++ b/gcc/config/s390/tpf.md @@ -1,5 +1,5 @@ ;; S390 TPF-OS specific machine patterns -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/s390/tpf.opt b/gcc/config/s390/tpf.opt index 145f2f8df54..e82444a5d9a 100644 --- a/gcc/config/s390/tpf.opt +++ b/gcc/config/s390/tpf.opt @@ -1,6 +1,6 @@ ; Options for the TPF-OS port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/s390/vecintrin.h b/gcc/config/s390/vecintrin.h index 621f96c9cc8..b9742ec1a17 100644 --- a/gcc/config/s390/vecintrin.h +++ b/gcc/config/s390/vecintrin.h @@ -1,5 +1,5 @@ /* GNU compiler hardware transactional execution intrinsics - Copyright (C) 2015 Free Software Foundation, Inc. + Copyright (C) 2015-2016 Free Software Foundation, Inc. Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) This file is part of GCC. diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index c9f589017dc..2302a8f4bd6 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -1,5 +1,5 @@ ;;- Instruction patterns for the System z vector facility -;; Copyright (C) 2015 Free Software Foundation, Inc. +;; Copyright (C) 2015-2016 Free Software Foundation, Inc. ;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) ;; This file is part of GCC. @@ -403,7 +403,7 @@ (if_then_else:V_HW (match_operator 3 "comparison_operator" [(match_operand:V_HW2 4 "register_operand" "") - (match_operand:V_HW2 5 "register_operand" "")]) + (match_operand:V_HW2 5 "nonmemory_operand" "")]) (match_operand:V_HW 1 "nonmemory_operand" "") (match_operand:V_HW 2 "nonmemory_operand" "")))] "TARGET_VX && GET_MODE_NUNITS (<V_HW:MODE>mode) == GET_MODE_NUNITS (<V_HW2:MODE>mode)" @@ -418,7 +418,7 @@ (if_then_else:V_HW (match_operator 3 "comparison_operator" [(match_operand:V_HW2 4 "register_operand" "") - (match_operand:V_HW2 5 "register_operand" "")]) + (match_operand:V_HW2 5 "nonmemory_operand" "")]) (match_operand:V_HW 1 "nonmemory_operand" "") (match_operand:V_HW 2 "nonmemory_operand" "")))] "TARGET_VX && GET_MODE_NUNITS (<V_HW:MODE>mode) == GET_MODE_NUNITS (<V_HW2:MODE>mode)" @@ -1107,7 +1107,7 @@ (eq (match_operand:<tointvec> 3 "register_operand" "") (match_operand:V 4 "const0_operand" "")) (match_operand:V 1 "const0_operand" "") - (match_operand:V 2 "constm1_operand" "")))] + (match_operand:V 2 "all_ones_operand" "")))] "TARGET_VX" [(set (match_dup 0) (match_dup 3))] { @@ -1120,7 +1120,7 @@ (if_then_else:V (eq (match_operand:<tointvec> 3 "register_operand" "") (match_operand:V 4 "const0_operand" "")) - (match_operand:V 1 "constm1_operand" "") + (match_operand:V 1 "all_ones_operand" "") (match_operand:V 2 "const0_operand" "")))] "TARGET_VX" [(set (match_dup 0) (not:V (match_dup 3)))] @@ -1134,7 +1134,7 @@ (if_then_else:V (ne (match_operand:<tointvec> 3 "register_operand" "") (match_operand:V 4 "const0_operand" "")) - (match_operand:V 1 "constm1_operand" "") + (match_operand:V 1 "all_ones_operand" "") (match_operand:V 2 "const0_operand" "")))] "TARGET_VX" [(set (match_dup 0) (match_dup 3))] @@ -1149,7 +1149,7 @@ (ne (match_operand:<tointvec> 3 "register_operand" "") (match_operand:V 4 "const0_operand" "")) (match_operand:V 1 "const0_operand" "") - (match_operand:V 2 "constm1_operand" "")))] + (match_operand:V 2 "all_ones_operand" "")))] "TARGET_VX" [(set (match_dup 0) (not:V (match_dup 3)))] { @@ -1185,7 +1185,7 @@ [(set (match_operand:V 0 "register_operand" "=v") (if_then_else:V (eq (match_operand:<tointvec> 3 "register_operand" "v") - (match_operand:<tointvec> 4 "constm1_operand" "")) + (match_operand:<tointvec> 4 "all_ones_operand" "")) (match_operand:V 1 "register_operand" "v") (match_operand:V 2 "register_operand" "v")))] "TARGET_VX" @@ -1197,7 +1197,7 @@ [(set (match_operand:V 0 "register_operand" "=v") (if_then_else:V (eq (not:<tointvec> (match_operand:<tointvec> 3 "register_operand" "v")) - (match_operand:<tointvec> 4 "constm1_operand" "")) + (match_operand:<tointvec> 4 "all_ones_operand" "")) (match_operand:V 1 "register_operand" "v") (match_operand:V 2 "register_operand" "v")))] "TARGET_VX" diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index b772439af54..81a2d072359 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -1,5 +1,5 @@ ;;- Instruction patterns for the System z vector facility builtins. -;; Copyright (C) 2015 Free Software Foundation, Inc. +;; Copyright (C) 2015-2016 Free Software Foundation, Inc. ;; Contributed by Andreas Krebbel (Andreas.Krebbel@de.ibm.com) ;; This file is part of GCC. diff --git a/gcc/config/sh/constraints.md b/gcc/config/sh/constraints.md index 41c88a2b568..b87ec2264bb 100644 --- a/gcc/config/sh/constraints.md +++ b/gcc/config/sh/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Renesas / SuperH SH. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sh/divcost-analysis b/gcc/config/sh/divcost-analysis index 7e103cdecc8..8a8dd426be1 100644 --- a/gcc/config/sh/divcost-analysis +++ b/gcc/config/sh/divcost-analysis @@ -81,7 +81,7 @@ jmp @r0 ; 2 cycles worse than SFUNC_STATIC -Copyright (C) 2006-2015 Free Software Foundation, Inc. +Copyright (C) 2006-2016 Free Software Foundation, Inc. Copying and distribution of this file, with or without modification, are permitted in any medium without royalty provided the copyright diff --git a/gcc/config/sh/divtab-sh4-300.c b/gcc/config/sh/divtab-sh4-300.c index 5b6d4fdc0f4..81db798466e 100644 --- a/gcc/config/sh/divtab-sh4-300.c +++ b/gcc/config/sh/divtab-sh4-300.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2004-2015 Free Software Foundation, Inc. +/* Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the diff --git a/gcc/config/sh/divtab-sh4.c b/gcc/config/sh/divtab-sh4.c index 1a41c98bec5..f0489b5b1da 100644 --- a/gcc/config/sh/divtab-sh4.c +++ b/gcc/config/sh/divtab-sh4.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2004-2015 Free Software Foundation, Inc. +/* Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the diff --git a/gcc/config/sh/divtab.c b/gcc/config/sh/divtab.c index b80b25cc8e0..401dd156a62 100644 --- a/gcc/config/sh/divtab.c +++ b/gcc/config/sh/divtab.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2003-2015 Free Software Foundation, Inc. +/* Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the diff --git a/gcc/config/sh/elf.h b/gcc/config/sh/elf.h index 3bcfbbe2208..f0f2f41529e 100644 --- a/gcc/config/sh/elf.h +++ b/gcc/config/sh/elf.h @@ -1,5 +1,5 @@ /* Definitions of target machine for gcc for Renesas / SuperH SH using ELF. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Ian Lance Taylor <ian@cygnus.com>. This file is part of GCC. diff --git a/gcc/config/sh/embed-elf.h b/gcc/config/sh/embed-elf.h index b43cd721f23..1333e4f89d2 100644 --- a/gcc/config/sh/embed-elf.h +++ b/gcc/config/sh/embed-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler for Renesas / SuperH SH non-Linux embedded targets. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by J"orn Rennecke <joern.rennecke@superh.com> This file is part of GCC. diff --git a/gcc/config/sh/iterators.md b/gcc/config/sh/iterators.md index d1578a45dcf..d5833c74008 100644 --- a/gcc/config/sh/iterators.md +++ b/gcc/config/sh/iterators.md @@ -1,5 +1,5 @@ ;; Iterator definitions for GCC SH machine description files. -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h index b032b04ee4f..2a036ac3f4b 100644 --- a/gcc/config/sh/linux.h +++ b/gcc/config/sh/linux.h @@ -1,5 +1,5 @@ /* Definitions for SH running Linux-based GNU systems using ELF - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by Kazumoto Kojima <kkojima@rr.iij4u.or.jp> This file is part of GCC. diff --git a/gcc/config/sh/little.h b/gcc/config/sh/little.h index 179338f3b45..6dea3ffdf88 100644 --- a/gcc/config/sh/little.h +++ b/gcc/config/sh/little.h @@ -1,6 +1,6 @@ /* Definition of little endian SH machine for GNU compiler. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sh/netbsd-elf.h b/gcc/config/sh/netbsd-elf.h index 39b6d6ce2ea..61db1ed9a97 100644 --- a/gcc/config/sh/netbsd-elf.h +++ b/gcc/config/sh/netbsd-elf.h @@ -1,5 +1,5 @@ /* Definitions for SH running NetBSD using ELF - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. This file is part of GCC. diff --git a/gcc/config/sh/newlib.h b/gcc/config/sh/newlib.h index 66ae6d694bf..1fe53be518e 100644 --- a/gcc/config/sh/newlib.h +++ b/gcc/config/sh/newlib.h @@ -1,5 +1,5 @@ /* Definitions of target machine for gcc for Super-H using sh-superh-elf. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. This file is part of GNU CC. diff --git a/gcc/config/sh/predicates.md b/gcc/config/sh/predicates.md index b847ae74a9d..e3eb59b90d7 100644 --- a/gcc/config/sh/predicates.md +++ b/gcc/config/sh/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Renesas / SuperH SH. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sh/rtems.h b/gcc/config/sh/rtems.h index b95c31aaea8..161d2551ee5 100644 --- a/gcc/config/sh/rtems.h +++ b/gcc/config/sh/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a SH using COFF. - Copyright (C) 1997-2015 Free Software Foundation, Inc. + Copyright (C) 1997-2016 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/sh/rtemself.h b/gcc/config/sh/rtemself.h index 0a0a6b6bc74..c4002f4b8a8 100644 --- a/gcc/config/sh/rtemself.h +++ b/gcc/config/sh/rtemself.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a SH using elf. - Copyright (C) 1997-2015 Free Software Foundation, Inc. + Copyright (C) 1997-2016 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/sh/sh-c.c b/gcc/config/sh/sh-c.c index 2dabf66bd47..4b2266d53af 100644 --- a/gcc/config/sh/sh-c.c +++ b/gcc/config/sh/sh-c.c @@ -1,5 +1,5 @@ /* Pragma handling for GCC for Renesas / SuperH SH. - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. Contributed by Joern Rennecke <joern.rennecke@st.com>. This file is part of GCC. diff --git a/gcc/config/sh/sh-mem.cc b/gcc/config/sh/sh-mem.cc index 5111fb111f6..6128adfde7e 100644 --- a/gcc/config/sh/sh-mem.cc +++ b/gcc/config/sh/sh-mem.cc @@ -1,5 +1,5 @@ /* Helper routines for memory move and comparison insns. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sh/sh-modes.def b/gcc/config/sh/sh-modes.def index 724a0443a5e..cab2011a300 100644 --- a/gcc/config/sh/sh-modes.def +++ b/gcc/config/sh/sh-modes.def @@ -1,5 +1,5 @@ /* SH extra machine modes. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h index c64a9488df9..b08120d3737 100644 --- a/gcc/config/sh/sh-protos.h +++ b/gcc/config/sh/sh-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for Renesas / SuperH SH. - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com). Improved by Jim Wilson (wilson@cygnus.com). diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 919ea1c99c7..0b18ce52719 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -1,5 +1,5 @@ /* Output routines for GCC for Renesas / SuperH SH. - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com). Improved by Jim Wilson (wilson@cygnus.com). diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index e6d63363fc6..7187c23dd0f 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for Renesas / SuperH SH. - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. Contributed by Steve Chamberlain (sac@cygnus.com). Improved by Jim Wilson (wilson@cygnus.com). diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index b6fe05c0edb..1b2523e3511 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -1,5 +1,5 @@ ;;- Machine description for Renesas / SuperH SH. -;; Copyright (C) 1993-2015 Free Software Foundation, Inc. +;; Copyright (C) 1993-2016 Free Software Foundation, Inc. ;; Contributed by Steve Chamberlain (sac@cygnus.com). ;; Improved by Jim Wilson (wilson@cygnus.com). diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt index 21898eff256..1026c7346c5 100644 --- a/gcc/config/sh/sh.opt +++ b/gcc/config/sh/sh.opt @@ -1,6 +1,6 @@ ; Options for the SH port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/sh/sh1.md b/gcc/config/sh/sh1.md index 64b6cf6e800..318efd29d05 100644 --- a/gcc/config/sh/sh1.md +++ b/gcc/config/sh/sh1.md @@ -1,5 +1,5 @@ ;; DFA scheduling description for Renesas / SuperH SH. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/sh/sh4-300.md b/gcc/config/sh/sh4-300.md index b41f1cc061a..028d764da07 100644 --- a/gcc/config/sh/sh4-300.md +++ b/gcc/config/sh/sh4-300.md @@ -1,5 +1,5 @@ ;; DFA scheduling description for ST40-300. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/sh/sh4.md b/gcc/config/sh/sh4.md index 6009d6d67f0..3dd85650452 100644 --- a/gcc/config/sh/sh4.md +++ b/gcc/config/sh/sh4.md @@ -1,5 +1,5 @@ ;; DFA scheduling description for SH4. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/sh/sh4a.md b/gcc/config/sh/sh4a.md index 1446148ace3..48b012625c0 100644 --- a/gcc/config/sh/sh4a.md +++ b/gcc/config/sh/sh4a.md @@ -1,5 +1,5 @@ ;; Scheduling description for Renesas SH4a -;; Copyright (C) 2003-2015 Free Software Foundation, Inc. +;; Copyright (C) 2003-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sh/sh64.h b/gcc/config/sh/sh64.h index 2897d8318db..45e5a5cb499 100644 --- a/gcc/config/sh/sh64.h +++ b/gcc/config/sh/sh64.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for SuperH SH 5. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Alexandre Oliva <aoliva@redhat.com> This file is part of GCC. diff --git a/gcc/config/sh/sh_optimize_sett_clrt.cc b/gcc/config/sh/sh_optimize_sett_clrt.cc index ca2a8f86464..11285dc112d 100644 --- a/gcc/config/sh/sh_optimize_sett_clrt.cc +++ b/gcc/config/sh/sh_optimize_sett_clrt.cc @@ -1,5 +1,5 @@ /* An SH specific RTL pass that tries to optimize clrt and sett insns. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sh/sh_treg_combine.cc b/gcc/config/sh/sh_treg_combine.cc index d5bf679ac80..bc1ee0e234e 100644 --- a/gcc/config/sh/sh_treg_combine.cc +++ b/gcc/config/sh/sh_treg_combine.cc @@ -1,6 +1,6 @@ /* An SH specific RTL pass that tries to combine comparisons and redundant condition code register stores across multiple basic blocks. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sh/shmedia.h b/gcc/config/sh/shmedia.h index 10ab894a520..6337441a8bd 100644 --- a/gcc/config/sh/shmedia.h +++ b/gcc/config/sh/shmedia.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2000-2015 Free Software Foundation, Inc. +/* Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sh/shmedia.md b/gcc/config/sh/shmedia.md index 21d00348394..f226113b59c 100644 --- a/gcc/config/sh/shmedia.md +++ b/gcc/config/sh/shmedia.md @@ -1,5 +1,5 @@ ;; DFA scheduling description for SH-5 SHmedia instructions. -;; Copyright (C) 2004-2015 Free Software Foundation, Inc. +;; Copyright (C) 2004-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/sh/sshmedia.h b/gcc/config/sh/sshmedia.h index 4403428dc0c..546ec3d211a 100644 --- a/gcc/config/sh/sshmedia.h +++ b/gcc/config/sh/sshmedia.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2000-2015 Free Software Foundation, Inc. +/* Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sh/superh.h b/gcc/config/sh/superh.h index fd39efd35a1..98f888e9e80 100644 --- a/gcc/config/sh/superh.h +++ b/gcc/config/sh/superh.h @@ -1,5 +1,5 @@ /* Definitions of target machine for gcc for Super-H using sh-superh-elf. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. This file is part of GNU CC. diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md index 6e054e6f39a..6f1337b33b4 100644 --- a/gcc/config/sh/sync.md +++ b/gcc/config/sh/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for SH synchronization instructions. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh index 9790746c9da..348cc0b63be 100644 --- a/gcc/config/sh/t-sh +++ b/gcc/config/sh/t-sh @@ -1,4 +1,4 @@ -# Copyright (C) 1993-2015 Free Software Foundation, Inc. +# Copyright (C) 1993-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sh/t-sh64 b/gcc/config/sh/t-sh64 index fb09f3fbbbf..3423b285cea 100644 --- a/gcc/config/sh/t-sh64 +++ b/gcc/config/sh/t-sh64 @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sh/ushmedia.h b/gcc/config/sh/ushmedia.h index 09755ba6fb1..4be53afc6f1 100644 --- a/gcc/config/sh/ushmedia.h +++ b/gcc/config/sh/ushmedia.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2000-2015 Free Software Foundation, Inc. +/* Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sh/vxworks.h b/gcc/config/sh/vxworks.h index d2f31b9b5bc..a7d828f66cf 100644 --- a/gcc/config/sh/vxworks.h +++ b/gcc/config/sh/vxworks.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for SuperH with targeting the VXWorks run time environment. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/sol2-c.c b/gcc/config/sol2-c.c index e20f1ab9467..8c163cc2aa1 100644 --- a/gcc/config/sol2-c.c +++ b/gcc/config/sol2-c.c @@ -1,5 +1,5 @@ /* Solaris support needed only by C/C++ frontends. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/sol2-cxx.c b/gcc/config/sol2-cxx.c index 9ddbdd9d2ba..b5443392a88 100644 --- a/gcc/config/sol2-cxx.c +++ b/gcc/config/sol2-cxx.c @@ -1,5 +1,5 @@ /* C++ specific Solaris system support. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sol2-protos.h b/gcc/config/sol2-protos.h index f6ac3222f04..4e6b0023102 100644 --- a/gcc/config/sol2-protos.h +++ b/gcc/config/sol2-protos.h @@ -1,6 +1,6 @@ /* Operating system specific prototypes to be used when targeting GCC for any Solaris 2 system. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sol2-stubs.c b/gcc/config/sol2-stubs.c index 87fa8de032c..45b25038103 100644 --- a/gcc/config/sol2-stubs.c +++ b/gcc/config/sol2-stubs.c @@ -1,5 +1,5 @@ /* Stubs for C++ specific Solaris system support. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sol2.c b/gcc/config/sol2.c index a3e23849745..560a07b6060 100644 --- a/gcc/config/sol2.c +++ b/gcc/config/sol2.c @@ -1,5 +1,5 @@ /* General Solaris system support. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/sol2.h b/gcc/config/sol2.h index 1758b9158db..5160e1fda18 100644 --- a/gcc/config/sol2.h +++ b/gcc/config/sol2.h @@ -1,6 +1,6 @@ /* Operating system specific defines to be used when targeting GCC for any Solaris 2 system. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sol2.opt b/gcc/config/sol2.opt index f2ae2cab5d4..84492fea827 100644 --- a/gcc/config/sol2.opt +++ b/gcc/config/sol2.opt @@ -1,6 +1,6 @@ ; Options for the Solaris 2 port of the compiler ; -; Copyright (C) 2010-2015 Free Software Foundation, Inc. +; Copyright (C) 2010-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/sparc/biarch64.h b/gcc/config/sparc/biarch64.h index f6821c63877..a6983e23ea5 100644 --- a/gcc/config/sparc/biarch64.h +++ b/gcc/config/sparc/biarch64.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC, for Sun SPARC. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by David E. O'Brien <obrien@FreeBSD.org>. This file is part of GCC. diff --git a/gcc/config/sparc/constraints.md b/gcc/config/sparc/constraints.md index e12efa12fdf..191c0bff223 100644 --- a/gcc/config/sparc/constraints.md +++ b/gcc/config/sparc/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for SPARC. -;; Copyright (C) 2008-2015 Free Software Foundation, Inc. +;; Copyright (C) 2008-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/cypress.md b/gcc/config/sparc/cypress.md index 5f942e1ba30..e528373d2b3 100644 --- a/gcc/config/sparc/cypress.md +++ b/gcc/config/sparc/cypress.md @@ -1,5 +1,5 @@ ;; Scheduling description for SPARC Cypress. -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/default-64.h b/gcc/config/sparc/default-64.h index b56d4991b83..be72d110692 100644 --- a/gcc/config/sparc/default-64.h +++ b/gcc/config/sparc/default-64.h @@ -1,7 +1,7 @@ /* Definitions of target machine for GCC, for bi-arch SPARC, defaulting to 64-bit code generation. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/driver-sparc.c b/gcc/config/sparc/driver-sparc.c index 5969735c411..7e9ee24ac24 100644 --- a/gcc/config/sparc/driver-sparc.c +++ b/gcc/config/sparc/driver-sparc.c @@ -1,5 +1,5 @@ /* Subroutines for the gcc driver. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/freebsd.h b/gcc/config/sparc/freebsd.h index f469bf1d89c..8841be22e72 100644 --- a/gcc/config/sparc/freebsd.h +++ b/gcc/config/sparc/freebsd.h @@ -1,5 +1,5 @@ /* Definitions for Sun SPARC64 running FreeBSD using the ELF format - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by David E. O'Brien <obrien@FreeBSD.org> and BSDi. This file is part of GCC. diff --git a/gcc/config/sparc/hypersparc.md b/gcc/config/sparc/hypersparc.md index 0317dd01e4a..4cd85c8134d 100644 --- a/gcc/config/sparc/hypersparc.md +++ b/gcc/config/sparc/hypersparc.md @@ -1,5 +1,5 @@ ;; Scheduling description for HyperSPARC. -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/leon.md b/gcc/config/sparc/leon.md index c579e394b58..cc3cb1e12d2 100644 --- a/gcc/config/sparc/leon.md +++ b/gcc/config/sparc/leon.md @@ -1,5 +1,5 @@ ;; Scheduling description for LEON. -;; Copyright (C) 2010-2015 Free Software Foundation, Inc. +;; Copyright (C) 2010-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/linux.h b/gcc/config/sparc/linux.h index 29763c4bae7..9b3257712f5 100644 --- a/gcc/config/sparc/linux.h +++ b/gcc/config/sparc/linux.h @@ -1,5 +1,5 @@ /* Definitions for SPARC running Linux-based GNU systems with ELF. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Eddie C. Dost (ecd@skynet.be) This file is part of GCC. diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h index efa33fbf77b..a1ef3259469 100644 --- a/gcc/config/sparc/linux64.h +++ b/gcc/config/sparc/linux64.h @@ -1,5 +1,5 @@ /* Definitions for 64-bit SPARC running Linux-based GNU systems with ELF. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by David S. Miller (davem@caip.rutgers.edu) This file is part of GCC. diff --git a/gcc/config/sparc/long-double-switch.opt b/gcc/config/sparc/long-double-switch.opt index ca7cb7a48ae..6f93cd7fcbe 100644 --- a/gcc/config/sparc/long-double-switch.opt +++ b/gcc/config/sparc/long-double-switch.opt @@ -1,6 +1,6 @@ ; Options for the SPARC port of the compiler ; -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/sparc/netbsd-elf.h b/gcc/config/sparc/netbsd-elf.h index 6f99ed4853c..26d9c093ab8 100644 --- a/gcc/config/sparc/netbsd-elf.h +++ b/gcc/config/sparc/netbsd-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for ELF on NetBSD/sparc and NetBSD/sparc64. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Matthew Green (mrg@eterna.com.au). This file is part of GCC. diff --git a/gcc/config/sparc/niagara.md b/gcc/config/sparc/niagara.md index ba80f5b28a9..c5cf69c85dc 100644 --- a/gcc/config/sparc/niagara.md +++ b/gcc/config/sparc/niagara.md @@ -1,5 +1,5 @@ ;; Scheduling description for Niagara. -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/niagara2.md b/gcc/config/sparc/niagara2.md index ebebb4b0005..7712005595e 100644 --- a/gcc/config/sparc/niagara2.md +++ b/gcc/config/sparc/niagara2.md @@ -1,5 +1,5 @@ ;; Scheduling description for Niagara-2 and Niagara-3. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/niagara4.md b/gcc/config/sparc/niagara4.md index e553a5d6097..a826fb458b4 100644 --- a/gcc/config/sparc/niagara4.md +++ b/gcc/config/sparc/niagara4.md @@ -1,5 +1,5 @@ ;; Scheduling description for Niagara-4 -;; Copyright (C) 2012-2015 Free Software Foundation, Inc. +;; Copyright (C) 2012-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/openbsd1-64.h b/gcc/config/sparc/openbsd1-64.h index 768b66942c7..a417390e315 100644 --- a/gcc/config/sparc/openbsd1-64.h +++ b/gcc/config/sparc/openbsd1-64.h @@ -1,5 +1,5 @@ /* Configuration file for sparc64 OpenBSD target. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/openbsd64.h b/gcc/config/sparc/openbsd64.h index b62f9c3e65c..c6ef0fb5f8f 100644 --- a/gcc/config/sparc/openbsd64.h +++ b/gcc/config/sparc/openbsd64.h @@ -1,5 +1,5 @@ /* Configuration file for sparc64 OpenBSD target. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md index 44d5922d587..787e0492284 100644 --- a/gcc/config/sparc/predicates.md +++ b/gcc/config/sparc/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for SPARC. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/rtemself.h b/gcc/config/sparc/rtemself.h index 6d1d4fdbc95..7bdb4d65dcf 100644 --- a/gcc/config/sparc/rtemself.h +++ b/gcc/config/sparc/rtemself.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a SPARC using ELF. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GCC. diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h index 9912e8c517d..07e6368caea 100644 --- a/gcc/config/sparc/sol2.h +++ b/gcc/config/sparc/sol2.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC, for SPARC running Solaris 2 - Copyright (C) 1992-2015 Free Software Foundation, Inc. + Copyright (C) 1992-2016 Free Software Foundation, Inc. Contributed by Ron Guilmette (rfg@netcom.com). Additional changes by David V. Henkel-Wallace (gumby@cygnus.com). diff --git a/gcc/config/sparc/sp-elf.h b/gcc/config/sparc/sp-elf.h index 932e443420b..0e81e9c3054 100644 --- a/gcc/config/sparc/sp-elf.h +++ b/gcc/config/sparc/sp-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GCC, for SPARC running in an embedded environment using the ELF file format. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/sp64-elf.h b/gcc/config/sparc/sp64-elf.h index 43adbb50839..67eb8fa2db5 100644 --- a/gcc/config/sparc/sp64-elf.h +++ b/gcc/config/sparc/sp64-elf.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC, for SPARC64, ELF. - Copyright (C) 1994-2015 Free Software Foundation, Inc. + Copyright (C) 1994-2016 Free Software Foundation, Inc. Contributed by Doug Evans, dje@cygnus.com. This file is part of GCC. diff --git a/gcc/config/sparc/sparc-c.c b/gcc/config/sparc/sparc-c.c index a72a9332b07..d3fd60e403d 100644 --- a/gcc/config/sparc/sparc-c.c +++ b/gcc/config/sparc/sparc-c.c @@ -1,5 +1,5 @@ /* Subroutines used for macro/preprocessor support on SPARC. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/sparc-modes.def b/gcc/config/sparc/sparc-modes.def index 8b12fe1d7cb..03241806f23 100644 --- a/gcc/config/sparc/sparc-modes.def +++ b/gcc/config/sparc/sparc-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC, for Sun SPARC. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com). 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, at Cygnus Support. diff --git a/gcc/config/sparc/sparc-opts.h b/gcc/config/sparc/sparc-opts.h index 7679d0d7c95..ce48f182c3c 100644 --- a/gcc/config/sparc/sparc-opts.h +++ b/gcc/config/sparc/sparc-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for SPARC. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h index 143143709d1..4a93cc27121 100644 --- a/gcc/config/sparc/sparc-protos.h +++ b/gcc/config/sparc/sparc-protos.h @@ -1,5 +1,5 @@ /* Prototypes of target machine for SPARC. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com). 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, at Cygnus Support. diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 02addbcb5a1..71609f27701 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for SPARC. - Copyright (C) 1987-2015 Free Software Foundation, Inc. + Copyright (C) 1987-2016 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com) 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, at Cygnus Support. @@ -6140,30 +6140,28 @@ sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) that is eligible for promotion in integer registers. - FP_REGS_P: the record contains at least one field or sub-field that is eligible for promotion in floating-point registers. - - PACKED_P: the record contains at least one field that is packed. - - Sub-fields are not taken into account for the PACKED_P predicate. */ + - PACKED_P: the record contains at least one field that is packed. */ static void scan_record_type (const_tree type, int *intregs_p, int *fpregs_p, int *packed_p) { - tree field; - - for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) + for (tree field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) { if (TREE_CODE (field) == FIELD_DECL) { - if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) - scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0); - else if ((FLOAT_TYPE_P (TREE_TYPE (field)) - || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE) + tree field_type = TREE_TYPE (field); + + if (TREE_CODE (field_type) == RECORD_TYPE) + scan_record_type (field_type, intregs_p, fpregs_p, packed_p); + else if ((FLOAT_TYPE_P (field_type) + || TREE_CODE (field_type) == VECTOR_TYPE) && TARGET_FPU) *fpregs_p = 1; else *intregs_p = 1; - if (packed_p && DECL_PACKED (field)) + if (DECL_PACKED (field)) *packed_p = 1; } } @@ -6647,9 +6645,10 @@ function_arg_record_value (const_tree type, machine_mode mode, parms.nregs += intslots; } - nregs = parms.nregs; /* Allocate the vector and handle some annoying special cases. */ + nregs = parms.nregs; + if (nregs == 0) { /* ??? Empty structure has no value? Duh? */ @@ -6661,16 +6660,15 @@ function_arg_record_value (const_tree type, machine_mode mode, load. */ return gen_rtx_REG (mode, regbase); } - else - { - /* ??? C++ has structures with no fields, and yet a size. Give up - for now and pass everything back in integer registers. */ - nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; - } + + /* ??? C++ has structures with no fields, and yet a size. Give up + for now and pass everything back in integer registers. */ + nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; if (nregs + slotno > SPARC_INT_ARG_MAX) nregs = SPARC_INT_ARG_MAX - slotno; } - gcc_assert (nregs != 0); + + gcc_assert (nregs > 0); parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs)); diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index ae8e962d111..ebfe87db046 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for Sun SPARC. - Copyright (C) 1987-2015 Free Software Foundation, Inc. + Copyright (C) 1987-2016 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com). 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, at Cygnus Support. @@ -1176,9 +1176,8 @@ extern char leaf_reg_remap[]; On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ #define FUNCTION_ARG_REGNO_P(N) \ -(TARGET_ARCH64 \ - ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \ - : ((N) >= 8 && (N) <= 13)) + (((N) >= 8 && (N) <= 13) \ + || (TARGET_ARCH64 && TARGET_FPU && (N) >= 32 && (N) <= 63)) /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index e1ffcc08434..56d4f63017d 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -1,5 +1,5 @@ ;; Machine description for SPARC chip for GCC -;; Copyright (C) 1987-2015 Free Software Foundation, Inc. +;; Copyright (C) 1987-2016 Free Software Foundation, Inc. ;; Contributed by Michael Tiemann (tiemann@cygnus.com) ;; 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, ;; at Cygnus Support. @@ -4740,24 +4740,7 @@ ;; Boolean instructions. -;; We define DImode `and' so with DImode `not' we can get -;; DImode `andn'. Other combinations are possible. - -(define_expand "anddi3" - [(set (match_operand:DI 0 "register_operand" "") - (and:DI (match_operand:DI 1 "arith_double_operand" "") - (match_operand:DI 2 "arith_double_operand" "")))] - "" - "") - -(define_insn "*anddi3_sp32" - [(set (match_operand:DI 0 "register_operand" "=r") - (and:DI (match_operand:DI 1 "arith_double_operand" "%r") - (match_operand:DI 2 "arith_double_operand" "rHI")))] - "! TARGET_ARCH64" - "#") - -(define_insn "*anddi3_sp64" +(define_insn "anddi3" [(set (match_operand:DI 0 "register_operand" "=r") (and:DI (match_operand:DI 1 "arith_operand" "%r") (match_operand:DI 2 "arith_operand" "rI")))] @@ -4783,28 +4766,6 @@ operands[4] = GEN_INT (~INTVAL (operands[2])); }) -(define_insn_and_split "*and_not_di_sp32" - [(set (match_operand:DI 0 "register_operand" "=&r") - (and:DI (not:DI (match_operand:DI 1 "register_operand" "%r")) - (match_operand:DI 2 "register_operand" "r")))] - "! TARGET_ARCH64" - "#" - "&& reload_completed - && ((GET_CODE (operands[0]) == REG - && SPARC_INT_REG_P (REGNO (operands[0]))) - || (GET_CODE (operands[0]) == SUBREG - && GET_CODE (SUBREG_REG (operands[0])) == REG - && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))" - [(set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5))) - (set (match_dup 6) (and:SI (not:SI (match_dup 7)) (match_dup 8)))] - "operands[3] = gen_highpart (SImode, operands[0]); - operands[4] = gen_highpart (SImode, operands[1]); - operands[5] = gen_highpart (SImode, operands[2]); - operands[6] = gen_lowpart (SImode, operands[0]); - operands[7] = gen_lowpart (SImode, operands[1]); - operands[8] = gen_lowpart (SImode, operands[2]);" - [(set_attr "length" "2")]) - (define_insn "*and_not_di_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (and:DI (not:DI (match_operand:DI 1 "register_operand" "%r")) @@ -4819,22 +4780,7 @@ "" "andn\t%2, %1, %0") -(define_expand "iordi3" - [(set (match_operand:DI 0 "register_operand" "") - (ior:DI (match_operand:DI 1 "arith_double_operand" "") - (match_operand:DI 2 "arith_double_operand" "")))] - "" - "") - -(define_insn "*iordi3_sp32" - [(set (match_operand:DI 0 "register_operand" "=r") - (ior:DI (match_operand:DI 1 "arith_double_operand" "%r") - (match_operand:DI 2 "arith_double_operand" "rHI")))] - "! TARGET_ARCH64" - "#" - [(set_attr "length" "2")]) - -(define_insn "*iordi3_sp64" +(define_insn "iordi3" [(set (match_operand:DI 0 "register_operand" "=r") (ior:DI (match_operand:DI 1 "arith_operand" "%r") (match_operand:DI 2 "arith_operand" "rI")))] @@ -4860,28 +4806,6 @@ operands[4] = gen_int_mode (~INTVAL (operands[2]), SImode); }) -(define_insn_and_split "*or_not_di_sp32" - [(set (match_operand:DI 0 "register_operand" "=&r") - (ior:DI (not:DI (match_operand:DI 1 "register_operand" "r")) - (match_operand:DI 2 "register_operand" "r")))] - "! TARGET_ARCH64" - "#" - "&& reload_completed - && ((GET_CODE (operands[0]) == REG - && SPARC_INT_REG_P (REGNO (operands[0]))) - || (GET_CODE (operands[0]) == SUBREG - && GET_CODE (SUBREG_REG (operands[0])) == REG - && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))" - [(set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5))) - (set (match_dup 6) (ior:SI (not:SI (match_dup 7)) (match_dup 8)))] - "operands[3] = gen_highpart (SImode, operands[0]); - operands[4] = gen_highpart (SImode, operands[1]); - operands[5] = gen_highpart (SImode, operands[2]); - operands[6] = gen_lowpart (SImode, operands[0]); - operands[7] = gen_lowpart (SImode, operands[1]); - operands[8] = gen_lowpart (SImode, operands[2]);" - [(set_attr "length" "2")]) - (define_insn "*or_not_di_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (ior:DI (not:DI (match_operand:DI 1 "register_operand" "r")) @@ -4896,22 +4820,7 @@ "" "orn\t%2, %1, %0") -(define_expand "xordi3" - [(set (match_operand:DI 0 "register_operand" "") - (xor:DI (match_operand:DI 1 "arith_double_operand" "") - (match_operand:DI 2 "arith_double_operand" "")))] - "" - "") - -(define_insn "*xordi3_sp32" - [(set (match_operand:DI 0 "register_operand" "=r") - (xor:DI (match_operand:DI 1 "arith_double_operand" "%r") - (match_operand:DI 2 "arith_double_operand" "rHI")))] - "! TARGET_ARCH64" - "#" - [(set_attr "length" "2")]) - -(define_insn "*xordi3_sp64" +(define_insn "xordi3" [(set (match_operand:DI 0 "register_operand" "=r") (xor:DI (match_operand:DI 1 "arith_operand" "%rJ") (match_operand:DI 2 "arith_operand" "rI")))] @@ -4949,54 +4858,6 @@ operands[4] = gen_int_mode (~INTVAL (operands[2]), SImode); }) -;; Split DImode logical operations requiring two instructions. -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (match_operator:DI 1 "cc_arith_operator" ; AND, IOR, XOR - [(match_operand:DI 2 "register_operand" "") - (match_operand:DI 3 "arith_double_operand" "")]))] - "! TARGET_ARCH64 - && reload_completed - && ((GET_CODE (operands[0]) == REG - && SPARC_INT_REG_P (REGNO (operands[0]))) - || (GET_CODE (operands[0]) == SUBREG - && GET_CODE (SUBREG_REG (operands[0])) == REG - && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))" - [(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)])) - (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))] -{ - operands[4] = gen_highpart (SImode, operands[0]); - operands[5] = gen_lowpart (SImode, operands[0]); - operands[6] = gen_highpart (SImode, operands[2]); - operands[7] = gen_lowpart (SImode, operands[2]); - operands[8] = gen_highpart_mode (SImode, DImode, operands[3]); - operands[9] = gen_lowpart (SImode, operands[3]); -}) - -;; xnor patterns. Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b). -;; Combine now canonicalizes to the rightmost expression. -(define_insn_and_split "*xor_not_di_sp32" - [(set (match_operand:DI 0 "register_operand" "=&r") - (not:DI (xor:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "register_operand" "r"))))] - "! TARGET_ARCH64" - "#" - "&& reload_completed - && ((GET_CODE (operands[0]) == REG - && SPARC_INT_REG_P (REGNO (operands[0]))) - || (GET_CODE (operands[0]) == SUBREG - && GET_CODE (SUBREG_REG (operands[0])) == REG - && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))" - [(set (match_dup 3) (not:SI (xor:SI (match_dup 4) (match_dup 5)))) - (set (match_dup 6) (not:SI (xor:SI (match_dup 7) (match_dup 8))))] - "operands[3] = gen_highpart (SImode, operands[0]); - operands[4] = gen_highpart (SImode, operands[1]); - operands[5] = gen_highpart (SImode, operands[2]); - operands[6] = gen_lowpart (SImode, operands[0]); - operands[7] = gen_lowpart (SImode, operands[1]); - operands[8] = gen_lowpart (SImode, operands[2]);" - [(set_attr "length" "2")]) - (define_insn "*xor_not_di_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (not:DI (xor:DI (match_operand:DI 1 "register_or_zero_operand" "rJ") @@ -5245,34 +5106,7 @@ "subcc\t%%g0, %1, %0" [(set_attr "type" "compare")]) -;; We cannot use the "not" pseudo insn because the Sun assembler -;; does not know how to make it work for constants. -(define_expand "one_cmpldi2" - [(set (match_operand:DI 0 "register_operand" "") - (not:DI (match_operand:DI 1 "register_operand" "")))] - "" - "") - -(define_insn_and_split "*one_cmpldi2_sp32" - [(set (match_operand:DI 0 "register_operand" "=&r") - (not:DI (match_operand:DI 1 "register_operand" "r")))] - "! TARGET_ARCH64" - "#" - "&& reload_completed - && ((GET_CODE (operands[0]) == REG - && SPARC_INT_REG_P (REGNO (operands[0]))) - || (GET_CODE (operands[0]) == SUBREG - && GET_CODE (SUBREG_REG (operands[0])) == REG - && SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))" - [(set (match_dup 2) (not:SI (xor:SI (match_dup 3) (const_int 0)))) - (set (match_dup 4) (not:SI (xor:SI (match_dup 5) (const_int 0))))] - "operands[2] = gen_highpart (SImode, operands[0]); - operands[3] = gen_highpart (SImode, operands[1]); - operands[4] = gen_lowpart (SImode, operands[0]); - operands[5] = gen_lowpart (SImode, operands[1]);" - [(set_attr "length" "2")]) - -(define_insn "*one_cmpldi2_sp64" +(define_insn "one_cmpldi2" [(set (match_operand:DI 0 "register_operand" "=r") (not:DI (match_operand:DI 1 "arith_operand" "rI")))] "TARGET_ARCH64" diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt index a50ba05ace4..25eaa1ae5f3 100644 --- a/gcc/config/sparc/sparc.opt +++ b/gcc/config/sparc/sparc.opt @@ -1,6 +1,6 @@ ; Options for the SPARC port of the compiler ; -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/sparc/sparclet.md b/gcc/config/sparc/sparclet.md index 8a2fe7c023b..77a82fcda45 100644 --- a/gcc/config/sparc/sparclet.md +++ b/gcc/config/sparc/sparclet.md @@ -1,5 +1,5 @@ ;; Scheduling description for SPARClet. -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/supersparc.md b/gcc/config/sparc/supersparc.md index 7cf7793217f..816f85090a5 100644 --- a/gcc/config/sparc/supersparc.md +++ b/gcc/config/sparc/supersparc.md @@ -1,5 +1,5 @@ ;; Scheduling description for SuperSPARC. -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md index 2fabff5f67f..6fac1f2da53 100644 --- a/gcc/config/sparc/sync.md +++ b/gcc/config/sparc/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for SPARC synchronization instructions. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/sysv4.h b/gcc/config/sparc/sysv4.h index 0b358bbe186..5ec0a1ef345 100644 --- a/gcc/config/sparc/sysv4.h +++ b/gcc/config/sparc/sysv4.h @@ -1,5 +1,5 @@ /* Target definitions for GNU compiler for SPARC running System V.4 - Copyright (C) 1991-2015 Free Software Foundation, Inc. + Copyright (C) 1991-2016 Free Software Foundation, Inc. Contributed by Ron Guilmette (rfg@monkeys.com). This file is part of GCC. diff --git a/gcc/config/sparc/t-elf b/gcc/config/sparc/t-elf index 4d7355f6857..97256f34ddd 100644 --- a/gcc/config/sparc/t-elf +++ b/gcc/config/sparc/t-elf @@ -1,4 +1,4 @@ -# Copyright (C) 1997-2015 Free Software Foundation, Inc. +# Copyright (C) 1997-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-leon b/gcc/config/sparc/t-leon index 1b203f6bc3c..a3f806a5c83 100644 --- a/gcc/config/sparc/t-leon +++ b/gcc/config/sparc/t-leon @@ -1,4 +1,4 @@ -# Copyright (C) 2010-2015 Free Software Foundation, Inc. +# Copyright (C) 2010-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-leon3 b/gcc/config/sparc/t-leon3 index a5edd4b3e2b..5cdb1fc7005 100644 --- a/gcc/config/sparc/t-leon3 +++ b/gcc/config/sparc/t-leon3 @@ -1,4 +1,4 @@ -# Copyright (C) 2010-2015 Free Software Foundation, Inc. +# Copyright (C) 2010-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-linux64 b/gcc/config/sparc/t-linux64 index 6467c31e1a0..cfb4150b4c7 100644 --- a/gcc/config/sparc/t-linux64 +++ b/gcc/config/sparc/t-linux64 @@ -1,4 +1,4 @@ -# Copyright (C) 1998-2015 Free Software Foundation, Inc. +# Copyright (C) 1998-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-rtems b/gcc/config/sparc/t-rtems index 6f7cc6fabca..5c03c40fd9a 100644 --- a/gcc/config/sparc/t-rtems +++ b/gcc/config/sparc/t-rtems @@ -1,4 +1,4 @@ -# Copyright (C) 2012-2015 Free Software Foundation, Inc. +# Copyright (C) 2012-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-rtems-64 b/gcc/config/sparc/t-rtems-64 index af5cbabd1ce..765703f3fa8 100644 --- a/gcc/config/sparc/t-rtems-64 +++ b/gcc/config/sparc/t-rtems-64 @@ -1,4 +1,4 @@ -# Copyright (C) 2012-2015 Free Software Foundation, Inc. +# Copyright (C) 2012-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/t-sparc b/gcc/config/sparc/t-sparc index 7968d921d36..1b691c43c79 100644 --- a/gcc/config/sparc/t-sparc +++ b/gcc/config/sparc/t-sparc @@ -1,6 +1,6 @@ # General rules that all sparc/ targets must have. # -# Copyright (C) 2011-2015 Free Software Foundation, Inc. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/sparc/tso.h b/gcc/config/sparc/tso.h index 5aaf97623c9..46b02ef959e 100644 --- a/gcc/config/sparc/tso.h +++ b/gcc/config/sparc/tso.h @@ -1,5 +1,5 @@ /* Include fragment for Sparc TSO operating systems. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/ultra1_2.md b/gcc/config/sparc/ultra1_2.md index 72f2281be35..53de5342982 100644 --- a/gcc/config/sparc/ultra1_2.md +++ b/gcc/config/sparc/ultra1_2.md @@ -1,5 +1,5 @@ ;; Scheduling description for UltraSPARC-I/II. -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/ultra3.md b/gcc/config/sparc/ultra3.md index c4426a30e9f..f0d547a3f33 100644 --- a/gcc/config/sparc/ultra3.md +++ b/gcc/config/sparc/ultra3.md @@ -1,5 +1,5 @@ ;; Scheduling description for UltraSPARC-III. -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/sparc/visintrin.h b/gcc/config/sparc/visintrin.h index e655e378d9a..51ef73906a8 100644 --- a/gcc/config/sparc/visintrin.h +++ b/gcc/config/sparc/visintrin.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2011-2015 Free Software Foundation, Inc. +/* Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/sparc/vxworks.h b/gcc/config/sparc/vxworks.h index e356b25d429..1bcbace2886 100644 --- a/gcc/config/sparc/vxworks.h +++ b/gcc/config/sparc/vxworks.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for SPARC targeting the VxWorks run time environment. - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/spu/constraints.md b/gcc/config/spu/constraints.md index 98114f6b684..a415f4e6990 100644 --- a/gcc/config/spu/constraints.md +++ b/gcc/config/spu/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for SPU -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; ;; This file is free software; you can redistribute it and/or modify it under ;; the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/predicates.md b/gcc/config/spu/predicates.md index ca2390ea504..b2e5506ecb9 100644 --- a/gcc/config/spu/predicates.md +++ b/gcc/config/spu/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for CELL SPU -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; ;; This file is free software; you can redistribute it and/or modify it under ;; the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/spu-builtins.def b/gcc/config/spu/spu-builtins.def index 26368a1397f..f90041c2191 100644 --- a/gcc/config/spu/spu-builtins.def +++ b/gcc/config/spu/spu-builtins.def @@ -1,5 +1,5 @@ /* Definitions of builtin functions for the Synergistic Processing Unit (SPU). */ -/* Copyright (C) 2006-2015 Free Software Foundation, Inc. +/* Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/spu-builtins.md b/gcc/config/spu/spu-builtins.md index f47f00080cc..d3667e6bd66 100644 --- a/gcc/config/spu/spu-builtins.md +++ b/gcc/config/spu/spu-builtins.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; This file is free software; you can redistribute it and/or modify it under ;; the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/spu-c.c b/gcc/config/spu/spu-c.c index ba5145493ef..684aba75dcc 100644 --- a/gcc/config/spu/spu-c.c +++ b/gcc/config/spu/spu-c.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2006-2015 Free Software Foundation, Inc. +/* Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/spu-elf.h b/gcc/config/spu/spu-elf.h index 46d35016af0..8b99471242a 100644 --- a/gcc/config/spu/spu-elf.h +++ b/gcc/config/spu/spu-elf.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2006-2015 Free Software Foundation, Inc. +/* Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/spu-modes.def b/gcc/config/spu/spu-modes.def index d905a0b858e..93b0b4261b3 100644 --- a/gcc/config/spu/spu-modes.def +++ b/gcc/config/spu/spu-modes.def @@ -1,4 +1,4 @@ -/* Copyright (C) 2006-2015 Free Software Foundation, Inc. +/* Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/spu-protos.h b/gcc/config/spu/spu-protos.h index 0b6ea4b53ea..0c7071259a8 100644 --- a/gcc/config/spu/spu-protos.h +++ b/gcc/config/spu/spu-protos.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2006-2015 Free Software Foundation, Inc. +/* Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c index 31502fb67b4..401c295b138 100644 --- a/gcc/config/spu/spu.c +++ b/gcc/config/spu/spu.c @@ -1,4 +1,4 @@ -/* Copyright (C) 2006-2015 Free Software Foundation, Inc. +/* Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/spu.h b/gcc/config/spu/spu.h index 25fa43563ee..c2c31e78900 100644 --- a/gcc/config/spu/spu.h +++ b/gcc/config/spu/spu.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2006-2015 Free Software Foundation, Inc. +/* Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md index 761dbc86c8c..6e0cf930831 100644 --- a/gcc/config/spu/spu.md +++ b/gcc/config/spu/spu.md @@ -1,4 +1,4 @@ -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; This file is free software; you can redistribute it and/or modify it under ;; the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/spu.opt b/gcc/config/spu/spu.opt index 8f0abb7d69b..2dcffcde6a7 100644 --- a/gcc/config/spu/spu.opt +++ b/gcc/config/spu/spu.opt @@ -1,5 +1,5 @@ ; Options for the SPU port of the compiler -; Copyright (C) 2006-2015 Free Software Foundation, Inc. +; Copyright (C) 2006-2016 Free Software Foundation, Inc. ; This file is free software; you can redistribute it and/or modify it under ; the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/spu_cache.h b/gcc/config/spu/spu_cache.h index 984b2312553..0c6825ca735 100644 --- a/gcc/config/spu/spu_cache.h +++ b/gcc/config/spu/spu_cache.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2008-2015 Free Software Foundation, Inc. +/* Copyright (C) 2008-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/spu_internals.h b/gcc/config/spu/spu_internals.h index ba997b3d04d..a7056d1e013 100644 --- a/gcc/config/spu/spu_internals.h +++ b/gcc/config/spu/spu_internals.h @@ -1,5 +1,5 @@ /* Definitions of Synergistic Processing Unit (SPU). */ -/* Copyright (C) 2006-2015 Free Software Foundation, Inc. +/* Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/spu_intrinsics.h b/gcc/config/spu/spu_intrinsics.h index 63d70920ac9..d859b6839ee 100644 --- a/gcc/config/spu/spu_intrinsics.h +++ b/gcc/config/spu/spu_intrinsics.h @@ -1,5 +1,5 @@ /* Definitions of Synergistic Processing Unit (SPU). */ -/* Copyright (C) 2006-2015 Free Software Foundation, Inc. +/* Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/spu_mfcio.h b/gcc/config/spu/spu_mfcio.h index a607b58107f..0d6726c56ab 100644 --- a/gcc/config/spu/spu_mfcio.h +++ b/gcc/config/spu/spu_mfcio.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2006-2015 Free Software Foundation, Inc. +/* Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/t-spu-elf b/gcc/config/spu/t-spu-elf index e7002576249..cfd6ee7b54c 100644 --- a/gcc/config/spu/t-spu-elf +++ b/gcc/config/spu/t-spu-elf @@ -1,4 +1,4 @@ -# Copyright (C) 2006-2015 Free Software Foundation, Inc. +# Copyright (C) 2006-2016 Free Software Foundation, Inc. # # This file is free software; you can redistribute it and/or modify it under # the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/vec_types.h b/gcc/config/spu/vec_types.h index 19099b1aa0b..d2de89c644e 100644 --- a/gcc/config/spu/vec_types.h +++ b/gcc/config/spu/vec_types.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2006-2015 Free Software Foundation, Inc. +/* Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/spu/vmx2spu.h b/gcc/config/spu/vmx2spu.h index d79db360df2..fb76bad04ab 100644 --- a/gcc/config/spu/vmx2spu.h +++ b/gcc/config/spu/vmx2spu.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2006-2015 Free Software Foundation, Inc. +/* Copyright (C) 2006-2016 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free diff --git a/gcc/config/stormy16/constraints.md b/gcc/config/stormy16/constraints.md index 232f07009e6..e591e4f93cc 100644 --- a/gcc/config/stormy16/constraints.md +++ b/gcc/config/stormy16/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for XSTORMY16. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/stormy16/predicates.md b/gcc/config/stormy16/predicates.md index dea620f5c63..8a87bc8f1b9 100644 --- a/gcc/config/stormy16/predicates.md +++ b/gcc/config/stormy16/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for XSTORMY16. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/stormy16/stormy-abi b/gcc/config/stormy16/stormy-abi index d795a9c7edb..c89d9be5cc0 100644 --- a/gcc/config/stormy16/stormy-abi +++ b/gcc/config/stormy16/stormy-abi @@ -167,7 +167,7 @@ means that overflow is reported for either signed or unsigned overflow. -Copyright (C) 2001-2015 Free Software Foundation, Inc. +Copyright (C) 2001-2016 Free Software Foundation, Inc. Copying and distribution of this file, with or without modification, are permitted in any medium without royalty provided the copyright diff --git a/gcc/config/stormy16/stormy16-protos.h b/gcc/config/stormy16/stormy16-protos.h index 93d09a9f85b..55d155c1d1d 100644 --- a/gcc/config/stormy16/stormy16-protos.h +++ b/gcc/config/stormy16/stormy16-protos.h @@ -1,5 +1,5 @@ /* Prototypes for exported functions defined in xstormy16.c - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/stormy16/stormy16.c b/gcc/config/stormy16/stormy16.c index f6268532254..50af15bd7cc 100644 --- a/gcc/config/stormy16/stormy16.c +++ b/gcc/config/stormy16/stormy16.c @@ -1,5 +1,5 @@ /* Xstormy16 target functions. - Copyright (C) 1997-2015 Free Software Foundation, Inc. + Copyright (C) 1997-2016 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/stormy16/stormy16.h b/gcc/config/stormy16/stormy16.h index ef787fdd3fe..547d38a62a9 100644 --- a/gcc/config/stormy16/stormy16.h +++ b/gcc/config/stormy16/stormy16.h @@ -1,5 +1,5 @@ /* Xstormy16 cpu description. - Copyright (C) 1997-2015 Free Software Foundation, Inc. + Copyright (C) 1997-2016 Free Software Foundation, Inc. Contributed by Red Hat, Inc. This file is part of GCC. diff --git a/gcc/config/stormy16/stormy16.md b/gcc/config/stormy16/stormy16.md index 4e13fbb4dcc..a23c7166a1e 100644 --- a/gcc/config/stormy16/stormy16.md +++ b/gcc/config/stormy16/stormy16.md @@ -1,5 +1,5 @@ ;; XSTORMY16 Machine description template -;; Copyright (C) 1997-2015 Free Software Foundation, Inc. +;; Copyright (C) 1997-2016 Free Software Foundation, Inc. ;; Contributed by Red Hat, Inc. ;; This file is part of GCC. diff --git a/gcc/config/stormy16/stormy16.opt b/gcc/config/stormy16/stormy16.opt index 5a457dc6c9e..6564477d7af 100644 --- a/gcc/config/stormy16/stormy16.opt +++ b/gcc/config/stormy16/stormy16.opt @@ -1,6 +1,6 @@ ; Options for the XSTORMY16 port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/t-darwin b/gcc/config/t-darwin index dd0c4154f53..e67bc9b9531 100644 --- a/gcc/config/t-darwin +++ b/gcc/config/t-darwin @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-glibc b/gcc/config/t-glibc index 4d9f86c4e4b..00276b33e8e 100644 --- a/gcc/config/t-glibc +++ b/gcc/config/t-glibc @@ -1,4 +1,4 @@ -# Copyright (C) 2012-2015 Free Software Foundation, Inc. +# Copyright (C) 2012-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-libunwind b/gcc/config/t-libunwind index 247a6e0c55a..877b44e7685 100644 --- a/gcc/config/t-libunwind +++ b/gcc/config/t-libunwind @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-linux b/gcc/config/t-linux index 75627874afe..e7da1891c24 100644 --- a/gcc/config/t-linux +++ b/gcc/config/t-linux @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-lynx b/gcc/config/t-lynx index 6bba2a0d83a..3fe4020e4d8 100644 --- a/gcc/config/t-lynx +++ b/gcc/config/t-lynx @@ -1,4 +1,4 @@ -# Copyright (C) 2004-2015 Free Software Foundation, Inc. +# Copyright (C) 2004-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-pnt16-warn b/gcc/config/t-pnt16-warn index 73df3e8af39..64ba678edef 100644 --- a/gcc/config/t-pnt16-warn +++ b/gcc/config/t-pnt16-warn @@ -1,5 +1,5 @@ # -Werror overrides for targets with 16 bit pointers -# Copyright (C) 2010-2015 Free Software Foundation, Inc. +# Copyright (C) 2010-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-sol2 b/gcc/config/t-sol2 index d499e8adf7a..0ab15aec5ab 100644 --- a/gcc/config/t-sol2 +++ b/gcc/config/t-sol2 @@ -1,4 +1,4 @@ -# Copyright (C) 2004-2015 Free Software Foundation, Inc. +# Copyright (C) 2004-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-vxworks b/gcc/config/t-vxworks index 9e7c9b413f0..39885e510bf 100644 --- a/gcc/config/t-vxworks +++ b/gcc/config/t-vxworks @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/t-winnt b/gcc/config/t-winnt index c00f390d58d..39361efce07 100644 --- a/gcc/config/t-winnt +++ b/gcc/config/t-winnt @@ -1,4 +1,4 @@ -# Copyright (C) 2013-2015 Free Software Foundation, Inc. +# Copyright (C) 2013-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/tilegx/constraints.md b/gcc/config/tilegx/constraints.md index f47d0f68296..51566868c74 100644 --- a/gcc/config/tilegx/constraints.md +++ b/gcc/config/tilegx/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Tilera TILE-Gx. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilegx/linux.h b/gcc/config/tilegx/linux.h index cbff114a912..f68b044da13 100644 --- a/gcc/config/tilegx/linux.h +++ b/gcc/config/tilegx/linux.h @@ -1,5 +1,5 @@ /* Definitions for TILE-Gx running Linux-based GNU systems with ELF. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/mul-tables.c b/gcc/config/tilegx/mul-tables.c index af881bd49c8..98081706d2b 100644 --- a/gcc/config/tilegx/mul-tables.c +++ b/gcc/config/tilegx/mul-tables.c @@ -1,5 +1,5 @@ /* Constant multiply table for TILE-Gx. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/predicates.md b/gcc/config/tilegx/predicates.md index ce04660f9ed..fabeef770e3 100644 --- a/gcc/config/tilegx/predicates.md +++ b/gcc/config/tilegx/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Tilera TILE-Gx. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilegx/sync.md b/gcc/config/tilegx/sync.md index 68157b77cf0..d3d1f844d34 100644 --- a/gcc/config/tilegx/sync.md +++ b/gcc/config/tilegx/sync.md @@ -1,6 +1,6 @@ ;; GCC machine description for Tilera TILE-Gx synchronization ;; instructions. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx-builtins.h b/gcc/config/tilegx/tilegx-builtins.h index fdd11445e2e..d681be29f03 100644 --- a/gcc/config/tilegx/tilegx-builtins.h +++ b/gcc/config/tilegx/tilegx-builtins.h @@ -1,5 +1,5 @@ /* Enum for builtin intrinsics for TILE-Gx. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx-c.c b/gcc/config/tilegx/tilegx-c.c index 11842aab186..8f756329fe6 100644 --- a/gcc/config/tilegx/tilegx-c.c +++ b/gcc/config/tilegx/tilegx-c.c @@ -1,5 +1,5 @@ /* Definitions of C specific functions for TILE-Gx. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx-generic.md b/gcc/config/tilegx/tilegx-generic.md index ee5e14aa26f..01d7cca3e79 100644 --- a/gcc/config/tilegx/tilegx-generic.md +++ b/gcc/config/tilegx/tilegx-generic.md @@ -1,5 +1,5 @@ ;; Scheduling description for Tilera TILE-Gx chip. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx-modes.def b/gcc/config/tilegx/tilegx-modes.def index cc04656b5f3..b6ab88b367f 100644 --- a/gcc/config/tilegx/tilegx-modes.def +++ b/gcc/config/tilegx/tilegx-modes.def @@ -1,5 +1,5 @@ /* TILE-Gx extra machine modes. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx-multiply.h b/gcc/config/tilegx/tilegx-multiply.h index 43f15200a72..6cd74ab34d8 100644 --- a/gcc/config/tilegx/tilegx-multiply.h +++ b/gcc/config/tilegx/tilegx-multiply.h @@ -1,5 +1,5 @@ /* Header for constant multiple table for TILE-Gx. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx-opts.h b/gcc/config/tilegx/tilegx-opts.h index 9608b608ae6..7de3cf9fbd7 100644 --- a/gcc/config/tilegx/tilegx-opts.h +++ b/gcc/config/tilegx/tilegx-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for TILE-Gx. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx-protos.h b/gcc/config/tilegx/tilegx-protos.h index 0b43fcf2c0a..758585de12a 100644 --- a/gcc/config/tilegx/tilegx-protos.h +++ b/gcc/config/tilegx/tilegx-protos.h @@ -1,5 +1,5 @@ /* Prototypes of target machine for TILE-Gx. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c index d2210622ae5..06c832c9f90 100644 --- a/gcc/config/tilegx/tilegx.c +++ b/gcc/config/tilegx/tilegx.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on the Tilera TILE-Gx. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx.h b/gcc/config/tilegx/tilegx.h index ac134b9d64c..ce9c9704022 100644 --- a/gcc/config/tilegx/tilegx.h +++ b/gcc/config/tilegx/tilegx.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for TILE-Gx. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md index 944953c34b2..361d51c6756 100644 --- a/gcc/config/tilegx/tilegx.md +++ b/gcc/config/tilegx/tilegx.md @@ -1,5 +1,5 @@ ;; Machine description for Tilera TILE-Gx chip for GCC. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. @@ -1799,13 +1799,16 @@ (define_expand "clzsi2" [(set (match_dup 2) - (ashift:DI (match_operand:SI 1 "reg_or_0_operand" "") + (zero_extend:DI (match_operand:SI 1 "reg_or_0_operand" ""))) + (set (match_dup 2) + (ashift:DI (match_dup 2) (const_int 32))) - (set (subreg:DI (match_operand:SI 0 "register_operand" "") 0) - (clz:DI (match_dup 2)))] + (set (match_dup 2) + (clz:DI (match_dup 2))) + (set (match_operand:SI 0 "register_operand" "") + (subreg:SI (match_dup 2) 0))] "" { - operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0); operands[2] = gen_reg_rtx (DImode); }) diff --git a/gcc/config/tilegx/tilegx.opt b/gcc/config/tilegx/tilegx.opt index 89f7bcfaeb4..017893d85d4 100644 --- a/gcc/config/tilegx/tilegx.opt +++ b/gcc/config/tilegx/tilegx.opt @@ -1,5 +1,5 @@ ; Options for the TILE-Gx port of the compiler. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; Contributed by Walter Lee (walt@tilera.com) ; ; This file is part of GCC. diff --git a/gcc/config/tilepro/constraints.md b/gcc/config/tilepro/constraints.md index 3ab9ab75650..901904a00a2 100644 --- a/gcc/config/tilepro/constraints.md +++ b/gcc/config/tilepro/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Tilera TILEPro chip. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilepro/gen-mul-tables.cc b/gcc/config/tilepro/gen-mul-tables.cc index 25c30ccb1fc..57e3cce0e13 100644 --- a/gcc/config/tilepro/gen-mul-tables.cc +++ b/gcc/config/tilepro/gen-mul-tables.cc @@ -1,5 +1,5 @@ /* Multiply table generator for tile. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. @@ -1230,7 +1230,7 @@ main () #else printf ("/* Constant multiply table for TILE-Gx.\n"); #endif - printf (" Copyright (C) 2011-2015 Free Software Foundation, Inc.\n"); + printf (" Copyright (C) 2011-2016 Free Software Foundation, Inc.\n"); printf (" Contributed by Walter Lee (walt@tilera.com)\n"); printf ("\n"); printf (" This file is part of GCC.\n"); diff --git a/gcc/config/tilepro/linux.h b/gcc/config/tilepro/linux.h index 5aee13fbc1d..c7791f92de0 100644 --- a/gcc/config/tilepro/linux.h +++ b/gcc/config/tilepro/linux.h @@ -1,5 +1,5 @@ /* Definitions for TILEPro running Linux-based GNU systems with ELF. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/mul-tables.c b/gcc/config/tilepro/mul-tables.c index 7cbbe802972..3edaa02cdba 100644 --- a/gcc/config/tilepro/mul-tables.c +++ b/gcc/config/tilepro/mul-tables.c @@ -1,5 +1,5 @@ /* Constant multiply table for TILEPro. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/predicates.md b/gcc/config/tilepro/predicates.md index ab62d20731a..50990728a49 100644 --- a/gcc/config/tilepro/predicates.md +++ b/gcc/config/tilepro/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Tilera TILEPro chip. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro-builtins.h b/gcc/config/tilepro/tilepro-builtins.h index d2cec16a1c5..5cee7f0b355 100644 --- a/gcc/config/tilepro/tilepro-builtins.h +++ b/gcc/config/tilepro/tilepro-builtins.h @@ -1,5 +1,5 @@ /* Enum for builtin intrinsics for TILEPro. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro-c.c b/gcc/config/tilepro/tilepro-c.c index 66eed119c14..ffd34a14e38 100644 --- a/gcc/config/tilepro/tilepro-c.c +++ b/gcc/config/tilepro/tilepro-c.c @@ -1,5 +1,5 @@ /* Definitions of C specific functions for TILEPro. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro-generic.md b/gcc/config/tilepro/tilepro-generic.md index a671aa3fa47..f5261400624 100644 --- a/gcc/config/tilepro/tilepro-generic.md +++ b/gcc/config/tilepro/tilepro-generic.md @@ -1,5 +1,5 @@ ;; Scheduling description for Tilera TILEPro chip. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro-modes.def b/gcc/config/tilepro/tilepro-modes.def index d1eeb3f027a..e8e47de607f 100644 --- a/gcc/config/tilepro/tilepro-modes.def +++ b/gcc/config/tilepro/tilepro-modes.def @@ -1,5 +1,5 @@ /* TILEPro extra machine modes. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro-multiply.h b/gcc/config/tilepro/tilepro-multiply.h index 5ba971cbfa5..554bcfcee89 100644 --- a/gcc/config/tilepro/tilepro-multiply.h +++ b/gcc/config/tilepro/tilepro-multiply.h @@ -1,5 +1,5 @@ /* Header for constant multiple table for TILEPro. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro-protos.h b/gcc/config/tilepro/tilepro-protos.h index 16b16af0b33..2c4418ae6d7 100644 --- a/gcc/config/tilepro/tilepro-protos.h +++ b/gcc/config/tilepro/tilepro-protos.h @@ -1,5 +1,5 @@ /* Prototypes of target machine for TILEPro. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c index 248b24e8385..628cd041384 100644 --- a/gcc/config/tilepro/tilepro.c +++ b/gcc/config/tilepro/tilepro.c @@ -1,5 +1,5 @@ /* Subroutines used for code generation on the Tilera TILEPro. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro.h b/gcc/config/tilepro/tilepro.h index a6d8c4eceb0..30f420a04c7 100644 --- a/gcc/config/tilepro/tilepro.h +++ b/gcc/config/tilepro/tilepro.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler for TILEPro. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Walter Lee (walt@tilera.com) This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro.md b/gcc/config/tilepro/tilepro.md index b1e6b81e71f..6493b06d736 100644 --- a/gcc/config/tilepro/tilepro.md +++ b/gcc/config/tilepro/tilepro.md @@ -1,5 +1,5 @@ ;; Machine description for Tilera TILEPro chip for GCC. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; Contributed by Walter Lee (walt@tilera.com) ;; ;; This file is part of GCC. diff --git a/gcc/config/tilepro/tilepro.opt b/gcc/config/tilepro/tilepro.opt index 07cef5e2b53..247c8cfafeb 100644 --- a/gcc/config/tilepro/tilepro.opt +++ b/gcc/config/tilepro/tilepro.opt @@ -1,5 +1,5 @@ ; Options for the TILEPro port of the compiler. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; Contributed by Walter Lee (walt@tilera.com) ; ; This file is part of GCC. diff --git a/gcc/config/usegas.h b/gcc/config/usegas.h index c44933bc643..e0103aad182 100644 --- a/gcc/config/usegas.h +++ b/gcc/config/usegas.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2001-2015 Free Software Foundation, Inc. +/* Copyright (C) 2001-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/v850/constraints.md b/gcc/config/v850/constraints.md index 15e25e7460e..88920a17765 100644 --- a/gcc/config/v850/constraints.md +++ b/gcc/config/v850/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for V850. -;; Copyright (C) 2011-2015 Free Software Foundation, Inc. +;; Copyright (C) 2011-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/v850/predicates.md b/gcc/config/v850/predicates.md index bd1ff6b39ca..9914993ee04 100644 --- a/gcc/config/v850/predicates.md +++ b/gcc/config/v850/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for NEC V850. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/v850/rtems.h b/gcc/config/v850/rtems.h index 0a02a897c8d..c36021436f9 100644 --- a/gcc/config/v850/rtems.h +++ b/gcc/config/v850/rtems.h @@ -1,5 +1,5 @@ /* Definitions for rtems targeting a v850 using ELF. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/v850/t-v850 b/gcc/config/v850/t-v850 index 0f6054eb962..f1acbfd1f58 100644 --- a/gcc/config/v850/t-v850 +++ b/gcc/config/v850/t-v850 @@ -1,4 +1,4 @@ -# Copyright (C) 1997-2015 Free Software Foundation, Inc. +# Copyright (C) 1997-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/v850/v850-c.c b/gcc/config/v850/v850-c.c index 752f3345627..0c16cc57c15 100644 --- a/gcc/config/v850/v850-c.c +++ b/gcc/config/v850/v850-c.c @@ -1,5 +1,5 @@ /* v850 specific, C compiler specific functions. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. Contributed by Jeff Law (law@cygnus.com). This file is part of GCC. diff --git a/gcc/config/v850/v850-modes.def b/gcc/config/v850/v850-modes.def index a93a335661e..cbefc8d6030 100644 --- a/gcc/config/v850/v850-modes.def +++ b/gcc/config/v850/v850-modes.def @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. NEC V850 series - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. Contributed by NEC EL This file is part of GCC. diff --git a/gcc/config/v850/v850-opts.h b/gcc/config/v850/v850-opts.h index 7ce02e3cf18..6e155bce4c0 100644 --- a/gcc/config/v850/v850-opts.h +++ b/gcc/config/v850/v850-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for NEC V850 series. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/v850/v850-protos.h b/gcc/config/v850/v850-protos.h index b4ca7f87e81..b023456b928 100644 --- a/gcc/config/v850/v850-protos.h +++ b/gcc/config/v850/v850-protos.h @@ -1,5 +1,5 @@ /* Prototypes for v850.c functions used in the md file & elsewhere. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c index d642eca207c..e0e4215e05f 100644 --- a/gcc/config/v850/v850.c +++ b/gcc/config/v850/v850.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for NEC V850 series - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Jeff Law (law@cygnus.com). This file is part of GCC. diff --git a/gcc/config/v850/v850.h b/gcc/config/v850/v850.h index 7b65187de79..c326df92e69 100644 --- a/gcc/config/v850/v850.h +++ b/gcc/config/v850/v850.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. NEC V850 series - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. Contributed by Jeff Law (law@cygnus.com). This file is part of GCC. diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md index 5d7bd5ff2af..06523658833 100644 --- a/gcc/config/v850/v850.md +++ b/gcc/config/v850/v850.md @@ -1,5 +1,5 @@ ;; GCC machine description for NEC V850 -;; Copyright (C) 1996-2015 Free Software Foundation, Inc. +;; Copyright (C) 1996-2016 Free Software Foundation, Inc. ;; Contributed by Jeff Law (law@cygnus.com). ;; This file is part of GCC. diff --git a/gcc/config/v850/v850.opt b/gcc/config/v850/v850.opt index d33b87b9d51..4b231928772 100644 --- a/gcc/config/v850/v850.opt +++ b/gcc/config/v850/v850.opt @@ -1,6 +1,6 @@ ; Options for the NEC V850 port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/vax/builtins.md b/gcc/config/vax/builtins.md index 436dd6c07a3..461f84e4ea5 100644 --- a/gcc/config/vax/builtins.md +++ b/gcc/config/vax/builtins.md @@ -1,5 +1,5 @@ ;; builtin definitions for DEC VAX. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/vax/constraints.md b/gcc/config/vax/constraints.md index 01ffdb5de29..302016605da 100644 --- a/gcc/config/vax/constraints.md +++ b/gcc/config/vax/constraints.md @@ -1,5 +1,5 @@ ;; Constraints for the DEC VAX port. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/vax/elf.h b/gcc/config/vax/elf.h index 53f1932ec5a..d92a86914c5 100644 --- a/gcc/config/vax/elf.h +++ b/gcc/config/vax/elf.h @@ -1,5 +1,5 @@ /* Target definitions for GNU compiler for VAX using ELF - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by Matt Thomas <matt@3am-software.com> This file is part of GCC. diff --git a/gcc/config/vax/elf.opt b/gcc/config/vax/elf.opt index cc4360a1f75..ae1984fc50a 100644 --- a/gcc/config/vax/elf.opt +++ b/gcc/config/vax/elf.opt @@ -1,6 +1,6 @@ ; VAX ELF options. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/vax/linux.h b/gcc/config/vax/linux.h index 0765ed99ecb..9f240a7e90f 100644 --- a/gcc/config/vax/linux.h +++ b/gcc/config/vax/linux.h @@ -1,5 +1,5 @@ /* Definitions for VAX running Linux-based GNU systems with ELF format. - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/netbsd-elf.h b/gcc/config/vax/netbsd-elf.h index 9d1ae48a3b8..17fb5e7491f 100644 --- a/gcc/config/vax/netbsd-elf.h +++ b/gcc/config/vax/netbsd-elf.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for NetBSD/vax ELF systems. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/openbsd.h b/gcc/config/vax/openbsd.h index e0fff0af361..89cad300f99 100644 --- a/gcc/config/vax/openbsd.h +++ b/gcc/config/vax/openbsd.h @@ -1,5 +1,5 @@ /* Configuration fragment for a VAX OpenBSD target. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/openbsd1.h b/gcc/config/vax/openbsd1.h index 0a8a7427d19..affbc34ecad 100644 --- a/gcc/config/vax/openbsd1.h +++ b/gcc/config/vax/openbsd1.h @@ -1,5 +1,5 @@ /* Configuration fragment for a VAX OpenBSD target. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/predicates.md b/gcc/config/vax/predicates.md index 1305a2df028..7344192db92 100644 --- a/gcc/config/vax/predicates.md +++ b/gcc/config/vax/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for DEC VAX. -;; Copyright (C) 2007-2015 Free Software Foundation, Inc. +;; Copyright (C) 2007-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/vax/vax-modes.def b/gcc/config/vax/vax-modes.def index 2b08dbb17be..fe3693c2fdf 100644 --- a/gcc/config/vax/vax-modes.def +++ b/gcc/config/vax/vax-modes.def @@ -1,5 +1,5 @@ /* VAX extra machine modes. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/vax-protos.h b/gcc/config/vax/vax-protos.h index b9d0e5d92c0..e99b7d44a93 100644 --- a/gcc/config/vax/vax-protos.h +++ b/gcc/config/vax/vax-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. VAX version. - Copyright (C) 2000-2015 Free Software Foundation, Inc. + Copyright (C) 2000-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/vax.c b/gcc/config/vax/vax.c index c059751915c..804f0c7a2e1 100644 --- a/gcc/config/vax/vax.c +++ b/gcc/config/vax/vax.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for VAX. - Copyright (C) 1987-2015 Free Software Foundation, Inc. + Copyright (C) 1987-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/vax.h b/gcc/config/vax/vax.h index 0b19014d57f..a381039d008 100644 --- a/gcc/config/vax/vax.h +++ b/gcc/config/vax/vax.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. VAX version. - Copyright (C) 1987-2015 Free Software Foundation, Inc. + Copyright (C) 1987-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vax/vax.md b/gcc/config/vax/vax.md index d5caa156370..c6d3ad7dc4f 100644 --- a/gcc/config/vax/vax.md +++ b/gcc/config/vax/vax.md @@ -1,5 +1,5 @@ ;; Machine description for GNU compiler, VAX Version -;; Copyright (C) 1987-2015 Free Software Foundation, Inc. +;; Copyright (C) 1987-2016 Free Software Foundation, Inc. ;; This file is part of GCC. diff --git a/gcc/config/vax/vax.opt b/gcc/config/vax/vax.opt index 4dfb28cc1b0..25926151bae 100644 --- a/gcc/config/vax/vax.opt +++ b/gcc/config/vax/vax.opt @@ -1,6 +1,6 @@ ; Options for the VAX port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/visium/constraints.md b/gcc/config/visium/constraints.md index 93900e89c33..589d80faf19 100644 --- a/gcc/config/visium/constraints.md +++ b/gcc/config/visium/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Visium. -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/visium/elf.h b/gcc/config/visium/elf.h index 713773daacc..d577541b20b 100644 --- a/gcc/config/visium/elf.h +++ b/gcc/config/visium/elf.h @@ -1,5 +1,5 @@ /* ELF-specific defines for Visium. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/visium/gr5.md b/gcc/config/visium/gr5.md index 9880b4d9beb..d75af616756 100644 --- a/gcc/config/visium/gr5.md +++ b/gcc/config/visium/gr5.md @@ -1,5 +1,5 @@ ;; Scheduling description for GR5. -;; Copyright (C) 2013-2015 Free Software Foundation, Inc. +;; Copyright (C) 2013-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/visium/gr6.md b/gcc/config/visium/gr6.md index 3129045af18..29cb7c253f4 100644 --- a/gcc/config/visium/gr6.md +++ b/gcc/config/visium/gr6.md @@ -1,5 +1,5 @@ ;; Scheduling description for GR6. -;; Copyright (C) 2013-2015 Free Software Foundation, Inc. +;; Copyright (C) 2013-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/visium/predicates.md b/gcc/config/visium/predicates.md index 66d282ea1ce..b08b06ef06a 100644 --- a/gcc/config/visium/predicates.md +++ b/gcc/config/visium/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Visium. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/visium/t-visium b/gcc/config/visium/t-visium index e10e22b3cb5..ad6e6b66a19 100644 --- a/gcc/config/visium/t-visium +++ b/gcc/config/visium/t-visium @@ -1,5 +1,5 @@ # Multilibs for Visium. -# Copyright (C) 2012-2015 Free Software Foundation, Inc. +# Copyright (C) 2012-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/visium/visium-modes.def b/gcc/config/visium/visium-modes.def index 8aa30d6201e..5af2db9737e 100644 --- a/gcc/config/visium/visium-modes.def +++ b/gcc/config/visium/visium-modes.def @@ -1,5 +1,5 @@ /* Machine description for Visium. - Copyright (C) 2014-2015 Free Software Foundation, Inc. + Copyright (C) 2014-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/visium/visium-opts.h b/gcc/config/visium/visium-opts.h index b438d520ab7..9049addc9f3 100644 --- a/gcc/config/visium/visium-opts.h +++ b/gcc/config/visium/visium-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for Visium. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/visium/visium-protos.h b/gcc/config/visium/visium-protos.h index 147af552a96..484d01e477d 100644 --- a/gcc/config/visium/visium-protos.h +++ b/gcc/config/visium/visium-protos.h @@ -1,5 +1,5 @@ /* Prototypes of target machine for Visium. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by C.Nettleton,J.P.Parkes and P.Garbett. This file is part of GCC. diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c index 0bf275c454a..7881b0ea458 100644 --- a/gcc/config/visium/visium.c +++ b/gcc/config/visium/visium.c @@ -1,5 +1,5 @@ /* Output routines for Visium. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by C.Nettleton, J.P.Parkes and P.Garbett. This file is part of GCC. diff --git a/gcc/config/visium/visium.h b/gcc/config/visium/visium.h index 9b92a74380b..0f195c07c66 100644 --- a/gcc/config/visium/visium.h +++ b/gcc/config/visium/visium.h @@ -1,5 +1,5 @@ /* Definitions of target machine for Visium. - Copyright (C) 2002-2015 Free Software Foundation, Inc. + Copyright (C) 2002-2016 Free Software Foundation, Inc. Contributed by C.Nettleton, J.P.Parkes and P.Garbett. This file is part of GCC. diff --git a/gcc/config/visium/visium.md b/gcc/config/visium/visium.md index dab265d1f31..09d136f5f0f 100644 --- a/gcc/config/visium/visium.md +++ b/gcc/config/visium/visium.md @@ -1,5 +1,5 @@ ;; Machine description for Visium. -;; Copyright (C) 2002-2015 Free Software Foundation, Inc. +;; Copyright (C) 2002-2016 Free Software Foundation, Inc. ;; Contributed by C.Nettleton, J.P.Parkes and P.Garbett. ;; This file is part of GCC. diff --git a/gcc/config/visium/visium.opt b/gcc/config/visium/visium.opt index cb42294c4a3..bab037643e2 100644 --- a/gcc/config/visium/visium.opt +++ b/gcc/config/visium/visium.opt @@ -1,5 +1,5 @@ ; Options for Visium. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/vms/make-crtlmap.awk b/gcc/config/vms/make-crtlmap.awk index a537572c86d..a34250a89da 100644 --- a/gcc/config/vms/make-crtlmap.awk +++ b/gcc/config/vms/make-crtlmap.awk @@ -1,5 +1,5 @@ # Generate the VMS crtl map -# Copyright (C) 2011-2015 Free Software Foundation, Inc. +# Copyright (C) 2011-2016 Free Software Foundation, Inc. BEGIN { is_first = 1; diff --git a/gcc/config/vms/t-vms b/gcc/config/vms/t-vms index 4973f9247e9..54f668904c2 100644 --- a/gcc/config/vms/t-vms +++ b/gcc/config/vms/t-vms @@ -1,4 +1,4 @@ -# Copyright (C) 2009-2015 Free Software Foundation, Inc. +# Copyright (C) 2009-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/vms/t-vmsnative b/gcc/config/vms/t-vmsnative index c8092d9e09a..57ba3ddfdb4 100644 --- a/gcc/config/vms/t-vmsnative +++ b/gcc/config/vms/t-vmsnative @@ -1,4 +1,4 @@ -# Copyright (C) 2010-2015 Free Software Foundation, Inc. +# Copyright (C) 2010-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/vms/vms-ar.c b/gcc/config/vms/vms-ar.c index 4339077333e..eb5fd550735 100644 --- a/gcc/config/vms/vms-ar.c +++ b/gcc/config/vms/vms-ar.c @@ -1,5 +1,5 @@ /* VMS archive wrapper. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by AdaCore. This file is part of GCC. diff --git a/gcc/config/vms/vms-c.c b/gcc/config/vms/vms-c.c index 4e0044f1df6..f2f519961b1 100644 --- a/gcc/config/vms/vms-c.c +++ b/gcc/config/vms/vms-c.c @@ -1,5 +1,5 @@ /* VMS specific, C compiler specific functions. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by Tristan Gingold (gingold@adacore.com). This file is part of GCC. diff --git a/gcc/config/vms/vms-f.c b/gcc/config/vms/vms-f.c index 4dc318deb60..2a8eed8b166 100644 --- a/gcc/config/vms/vms-f.c +++ b/gcc/config/vms/vms-f.c @@ -1,5 +1,5 @@ /* VMS support needed only by Fortran frontends. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vms/vms-ld.c b/gcc/config/vms/vms-ld.c index 8bc89780134..fb5a91602f3 100644 --- a/gcc/config/vms/vms-ld.c +++ b/gcc/config/vms/vms-ld.c @@ -1,5 +1,5 @@ /* VMS linker wrapper. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. Contributed by AdaCore This file is part of GCC. diff --git a/gcc/config/vms/vms-opts.h b/gcc/config/vms/vms-opts.h index dee3f7b3e48..1af3ec067d4 100644 --- a/gcc/config/vms/vms-opts.h +++ b/gcc/config/vms/vms-opts.h @@ -1,5 +1,5 @@ /* Definitions for option handling for OpenVMS. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vms/vms-protos.h b/gcc/config/vms/vms-protos.h index 9e5ade073ad..e30b441cbec 100644 --- a/gcc/config/vms/vms-protos.h +++ b/gcc/config/vms/vms-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GCC for VMS. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vms/vms-stdint.h b/gcc/config/vms/vms-stdint.h index 8320e5a59f4..095f4f1ad0a 100644 --- a/gcc/config/vms/vms-stdint.h +++ b/gcc/config/vms/vms-stdint.h @@ -1,5 +1,5 @@ /* Definitions for <stdint.h> types on VMS systems. - Copyright (C) 2012-2015 Free Software Foundation, Inc. + Copyright (C) 2012-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vms/vms.c b/gcc/config/vms/vms.c index b0445f4750c..9252aa4ce68 100644 --- a/gcc/config/vms/vms.c +++ b/gcc/config/vms/vms.c @@ -1,5 +1,5 @@ /* Definitions of target machine GNU compiler. 32bit VMS version. - Copyright (C) 2009-2015 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by Douglas B Rupp (rupp@gnat.com). This file is part of GCC. diff --git a/gcc/config/vms/vms.h b/gcc/config/vms/vms.h index dc6e42a28c1..b20d537e8d8 100644 --- a/gcc/config/vms/vms.h +++ b/gcc/config/vms/vms.h @@ -1,5 +1,5 @@ /* Definitions of target machine GNU compiler. VMS common version. - Copyright (C) 2003-2015 Free Software Foundation, Inc. + Copyright (C) 2003-2016 Free Software Foundation, Inc. Contributed by Douglas B Rupp (rupp@gnat.com). This file is part of GCC. diff --git a/gcc/config/vms/vms.opt b/gcc/config/vms/vms.opt index 4cbae2738c3..508fc81b81a 100644 --- a/gcc/config/vms/vms.opt +++ b/gcc/config/vms/vms.opt @@ -1,4 +1,4 @@ -; Copyright (C) 2009-2015 Free Software Foundation, Inc. +; Copyright (C) 2009-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/vms/x-vms b/gcc/config/vms/x-vms index 88d9a110e32..7bac94e50b1 100644 --- a/gcc/config/vms/x-vms +++ b/gcc/config/vms/x-vms @@ -1,4 +1,4 @@ -# Copyright (C) 2001-2015 Free Software Foundation, Inc. +# Copyright (C) 2001-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/vms/xm-vms.h b/gcc/config/vms/xm-vms.h index 5c3d4002c64..7e2f2389851 100644 --- a/gcc/config/vms/xm-vms.h +++ b/gcc/config/vms/xm-vms.h @@ -1,6 +1,6 @@ /* Configuration for GCC for hosting on VMS using a Unix style C library. - Copyright (C) 1996-2015 Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vx-common.h b/gcc/config/vx-common.h index ffc133ebc21..01884bfa439 100644 --- a/gcc/config/vx-common.h +++ b/gcc/config/vx-common.h @@ -1,5 +1,5 @@ /* Target-independent configuration for VxWorks and VxWorks AE. - Copyright (C) 2005-2015 Free Software Foundation, Inc. + Copyright (C) 2005-2016 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/vxworks-dummy.h b/gcc/config/vxworks-dummy.h index 2b5ddcccc7b..d6340d5bb81 100644 --- a/gcc/config/vxworks-dummy.h +++ b/gcc/config/vxworks-dummy.h @@ -1,5 +1,5 @@ /* Dummy definitions of VxWorks-related macros - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/vxworks.c b/gcc/config/vxworks.c index 5db4f42d267..ce2c1707e9a 100644 --- a/gcc/config/vxworks.c +++ b/gcc/config/vxworks.c @@ -1,5 +1,5 @@ /* Common VxWorks target definitions for GNU compiler. - Copyright (C) 2007-2015 Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. Contributed by CodeSourcery, Inc. This file is part of GCC. diff --git a/gcc/config/vxworks.h b/gcc/config/vxworks.h index 9ae2f6f529f..f3569267427 100644 --- a/gcc/config/vxworks.h +++ b/gcc/config/vxworks.h @@ -1,5 +1,5 @@ /* Common VxWorks target definitions for GNU compiler. - Copyright (C) 1999-2015 Free Software Foundation, Inc. + Copyright (C) 1999-2016 Free Software Foundation, Inc. Contributed by Wind River Systems. Rewritten by CodeSourcery, LLC. @@ -71,13 +71,13 @@ along with GCC; see the file COPYING3. If not see %{mrtp:%{!shared:%{!non-static:-static} \ %{non-static:--force-dynamic --export-dynamic}}}" -/* For VxWorks, the system provides libc_internal.a. This is a superset - of libgcc.a; we want to use it. Make sure not to dynamically export - any of its symbols, though. Always look for libgcc.a first so that - we get the latest versions of the GNU intrinsics during our builds. */ +/* For VxWorks static rtps, the system provides libc_internal.a, a superset + of libgcc.a that we want to use. Make sure not to dynamically export any + of its symbols, though, and always look for libgcc.a first so that we get + the latest versions of the GNU intrinsics during our builds. */ #undef VXWORKS_LIBGCC_SPEC #define VXWORKS_LIBGCC_SPEC \ - "-lgcc %{mrtp:--exclude-libs=libc_internal,libgcc -lc_internal}" + "-lgcc %{mrtp:%{!shared:--exclude-libs=libc_internal,libgcc -lc_internal}}" #undef VXWORKS_STARTFILE_SPEC #define VXWORKS_STARTFILE_SPEC "%{mrtp:%{!shared:-l:crt0.o}}" diff --git a/gcc/config/vxworks.opt b/gcc/config/vxworks.opt index 8ddefe0ad30..cf19401ea8e 100644 --- a/gcc/config/vxworks.opt +++ b/gcc/config/vxworks.opt @@ -1,6 +1,6 @@ ; Processor-independent options for VxWorks. ; -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; Contributed by CodeSourcery, LLC. ; ; This file is part of GCC. diff --git a/gcc/config/vxworksae.h b/gcc/config/vxworksae.h index 34a8a616fd1..fa461c47319 100644 --- a/gcc/config/vxworksae.h +++ b/gcc/config/vxworksae.h @@ -1,5 +1,5 @@ /* Common VxWorks AE target definitions for GNU compiler. - Copyright (C) 2004-2015 Free Software Foundation, Inc. + Copyright (C) 2004-2016 Free Software Foundation, Inc. Contributed by CodeSourcery, LLC. This file is part of GCC. diff --git a/gcc/config/winnt-c.c b/gcc/config/winnt-c.c index d3a45f1875b..76549aa8d5f 100644 --- a/gcc/config/winnt-c.c +++ b/gcc/config/winnt-c.c @@ -1,5 +1,5 @@ /* Default C-family target hooks initializer. - Copyright (C) 2013-2015 Free Software Foundation, Inc. + Copyright (C) 2013-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/xtensa/constraints.md b/gcc/config/xtensa/constraints.md index 773d4f9b3ad..5a794f28f0f 100644 --- a/gcc/config/xtensa/constraints.md +++ b/gcc/config/xtensa/constraints.md @@ -1,5 +1,5 @@ ;; Constraint definitions for Xtensa. -;; Copyright (C) 2006-2015 Free Software Foundation, Inc. +;; Copyright (C) 2006-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/xtensa/elf.h b/gcc/config/xtensa/elf.h index 12056f781ca..f479c03baa9 100644 --- a/gcc/config/xtensa/elf.h +++ b/gcc/config/xtensa/elf.h @@ -1,6 +1,6 @@ /* Xtensa/Elf configuration. Derived from the configuration for GCC for Intel i386 running Linux. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/xtensa/elf.opt b/gcc/config/xtensa/elf.opt index e15fc5c33d0..95567732403 100644 --- a/gcc/config/xtensa/elf.opt +++ b/gcc/config/xtensa/elf.opt @@ -1,6 +1,6 @@ ; Xtensa ELF (bare metal) options. -; Copyright (C) 2011-2015 Free Software Foundation, Inc. +; Copyright (C) 2011-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/xtensa/linux.h b/gcc/config/xtensa/linux.h index 5b0243aaff0..6ecb153e95f 100644 --- a/gcc/config/xtensa/linux.h +++ b/gcc/config/xtensa/linux.h @@ -1,6 +1,6 @@ /* Xtensa Linux configuration. Derived from the configuration for GCC for Intel i386 running Linux. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md index 00f23700d06..96e82d69c23 100644 --- a/gcc/config/xtensa/predicates.md +++ b/gcc/config/xtensa/predicates.md @@ -1,5 +1,5 @@ ;; Predicate definitions for Xtensa. -;; Copyright (C) 2005-2015 Free Software Foundation, Inc. +;; Copyright (C) 2005-2016 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; diff --git a/gcc/config/xtensa/t-xtensa b/gcc/config/xtensa/t-xtensa index 0c2ea8a4125..7f5944197d3 100644 --- a/gcc/config/xtensa/t-xtensa +++ b/gcc/config/xtensa/t-xtensa @@ -1,4 +1,4 @@ -# Copyright (C) 2002-2015 Free Software Foundation, Inc. +# Copyright (C) 2002-2016 Free Software Foundation, Inc. # # This file is part of GCC. # diff --git a/gcc/config/xtensa/uclinux.h b/gcc/config/xtensa/uclinux.h index 3c678569b6f..6279a9934ae 100644 --- a/gcc/config/xtensa/uclinux.h +++ b/gcc/config/xtensa/uclinux.h @@ -1,6 +1,6 @@ /* Xtensa uClinux configuration. Derived from the configuration for GCC for Intel i386 running Linux. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. This file is part of GCC. diff --git a/gcc/config/xtensa/uclinux.opt b/gcc/config/xtensa/uclinux.opt index 95ef777ab92..0283d5677a4 100644 --- a/gcc/config/xtensa/uclinux.opt +++ b/gcc/config/xtensa/uclinux.opt @@ -1,6 +1,6 @@ ; Xtensa uClinux options. -; Copyright (C) 2015 Free Software Foundation, Inc. +; Copyright (C) 2015-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; diff --git a/gcc/config/xtensa/xtensa-protos.h b/gcc/config/xtensa/xtensa-protos.h index 6a5362547d5..f2ca526aa17 100644 --- a/gcc/config/xtensa/xtensa-protos.h +++ b/gcc/config/xtensa/xtensa-protos.h @@ -1,5 +1,5 @@ /* Prototypes of target machine for GNU compiler for Xtensa. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. This file is part of GCC. diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c index 0f58655d34e..64d089bdfb0 100644 --- a/gcc/config/xtensa/xtensa.c +++ b/gcc/config/xtensa/xtensa.c @@ -1,5 +1,5 @@ /* Subroutines for insn-output.c for Tensilica's Xtensa architecture. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. This file is part of GCC. diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h index 01d93e98b6c..82e9900b42a 100644 --- a/gcc/config/xtensa/xtensa.h +++ b/gcc/config/xtensa/xtensa.h @@ -1,5 +1,5 @@ /* Definitions of Tensilica's Xtensa target machine for GNU compiler. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. This file is part of GCC. diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index a4228da2bb4..db54a12b7bc 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -1,5 +1,5 @@ ;; GCC machine description for Tensilica's Xtensa architecture. -;; Copyright (C) 2001-2015 Free Software Foundation, Inc. +;; Copyright (C) 2001-2016 Free Software Foundation, Inc. ;; Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. ;; This file is part of GCC. diff --git a/gcc/config/xtensa/xtensa.opt b/gcc/config/xtensa/xtensa.opt index df1d3380043..ea5c7d59671 100644 --- a/gcc/config/xtensa/xtensa.opt +++ b/gcc/config/xtensa/xtensa.opt @@ -1,6 +1,6 @@ ; Options for the Tensilica Xtensa port of the compiler. -; Copyright (C) 2005-2015 Free Software Foundation, Inc. +; Copyright (C) 2005-2016 Free Software Foundation, Inc. ; ; This file is part of GCC. ; |