Fix alpha-x-m32r-elf bugs.

	* cse.c (simplify_unary_operation): Sign-extend constants when
	they have the most significant bit set for the target.
	* real.c (endian): Sign-extend 32 bit output values on a 64 bit
	host.
	* m32r/m32r.c (m32r_expand_prologue): Store pretend_size in
	HOST_WIDE_INT temporary before negating it.
	* m32r/m32r.md (movsi_insn+1): Use ~0xffff instead of 0xffff0000.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@24254 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 13 insertions, 0 deletions

diff --git a/gcc/cse.c b/gcc/cse.c
index 7b81de47e4e..5e7763188e5 100644
--- a/gcc/cse.c
+++ b/gcc/cse.c
@@ -3242,6 +3242,19 @@ simplify_unary_operation (code, mode, op, op_mode)
 	      != ((HOST_WIDE_INT) (-1) << (width - 1))))
 	val &= ((HOST_WIDE_INT) 1 << width) - 1;
 
+      /* If this would be an entire word for the target, but is not for
+	 the host, then sign-extend on the host so that the number will look
+	 the same way on the host that it would on the target.
+
+	 For example, when building a 64 bit alpha hosted 32 bit sparc
+	 targeted compiler, then we want the 32 bit unsigned value -1 to be
+	 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
+	 The later confuses the sparc backend.  */
+
+      if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
+	  && (val & ((HOST_WIDE_INT) 1 << (width - 1))))
+	val |= ((HOST_WIDE_INT) (-1) << width);
+
       return GEN_INT (val);
     }