diff options
| author | hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-08-01 13:47:31 +0000 |
|---|---|---|
| committer | hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-08-01 13:47:31 +0000 |
| commit | a3398ee6671bc89db4de051393a4a42fe27c1335 (patch) | |
| tree | 35f575996429f663452714abea2458a0099073e1 /gcc/doc | |
| parent | c2220663092ccec1d5cfc5c7d249e111a28f9c5d (diff) | |
| download | gcc-a3398ee6671bc89db4de051393a4a42fe27c1335.tar.gz | |
Add -mlzcnt.
gcc/
2011-08-01 Kirill Yukhin <kirill.yukhin@intel.com>
PR target/49547
* config.gcc (i[34567]86-*-*): Replace abmintrin.h with
lzcntintrin.h.
(x86_64-*-*): Likewise.
* config/i386/i386.opt (mlzcnt): New.
* config/i386/abmintrin.h: File removed.
(__lzcnt_u16, __lzcnt, __lzcnt_u64): Moved to ...
* config/i386/lzcntintrin.h: ... here. New file.
(__lzcnt): Rename to ...
(__lzcnt32): ... this.
* config/i386/bmiintrin.h (head): Update copyright year.
(__lzcnt_u16): Removed.
(__lzcnt_u32): Likewise.
(__lzcnt_u64): Likewise.
* config/i386/x86intrin.h: Include lzcntintrin.h when __LZCNT__
is defined, remove abmintrin.h.
* config/i386/cpuid.h (bit_LZCNT): New.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect
LZCNT feature.
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__LZCNT__ if needed.
* config/i386/i386.c (ix86_target_string): New option -mlzcnt.
(ix86_option_override_internal): Handle LZCNT option.
(ix86_valid_target_attribute_inner_p): Likewise.
(struct builtin_description bdesc_args) <IX86_BUILTIN_CLZS>: Update.
* config/i386/i386.h (TARGET_LZCNT): New.
(CLZ_DEFINED_VALUE_AT_ZERO): Update.
* config/i386/i386.md (clz<mode>2): Update insn constraint.
(clz<mode>2_lzcnt): Likewise.
* doc/invoke.texi: Mention -mlzcnt option.
* doc/extend.texi: Likewise.
gcc/testsuite/
2011-08-01 Kirill Yukhin <kirill.yukhin@intel.com>
* gcc.target/i386/i386.exp (check_effective_target_lzcnt): New.
* gcc.target/i386/lzcnt-1.c: New test.
* gcc.target/i386/lzcnt-2.c: Likewise.
* gcc.target/i386/lzcnt-2a.c: Likewise.
* gcc.target/i386/lzcnt-3.c: Likewise.
* gcc.target/i386/lzcnt-4.c: Likewise.
* gcc.target/i386/lzcnt-4a.c: Likewise.
* gcc.target/i386/lzcnt-5.c: Likewise.
* gcc.target/i386/lzcnt-6.c: Likewise.
* gcc.target/i386/lzcnt-6a.c: Likewise.
* gcc.target/i386/lzcnt-check.h: Likewise.
* gcc.target/i386/sse-12.c (dg-compile): Add -mlzcnt.
* gcc.target/i386/sse-13.c: Likewise.
* gcc.target/i386/sse-14.c: Likewise.
* g++.dg/other/i386-2.C: Likewise.
* g++.dg/other/i386-3.C: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@177034 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/extend.texi | 5 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 8 |
2 files changed, 10 insertions, 3 deletions
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 0c95a795861..480a8b0288e 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -9676,6 +9676,11 @@ All of them generate the machine instruction that is part of the name. @smallexample unsigned int __builtin_ia32_bextr_u32(unsigned int, unsigned int); unsigned long long __builtin_ia32_bextr_u64 (unsigned long long, unsigned long long); +@end smallexample + +The following built-in functions are available when @option{-mlzcnt} is used. +All of them generate the machine instruction that is part of the name. +@smallexample unsigned short __builtin_ia32_lzcnt_16(unsigned short); unsigned int __builtin_ia32_lzcnt_u32(unsigned int); unsigned long long __builtin_ia32_lzcnt_u64 (unsigned long long); diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index db9a5da5051..264d1b0f350 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -606,8 +606,8 @@ Objective-C and Objective-C++ Dialects}. -mcld -mcx16 -msahf -mmovbe -mcrc32 -mrecip -mvzeroupper @gol -mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol -maes -mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol --msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlwp @gol --mthreads -mno-align-stringops -minline-all-stringops @gol +-msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlzcnt @gol +-mlwp -mthreads -mno-align-stringops -minline-all-stringops @gol -minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol -mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol -m96bit-long-double -mregparm=@var{num} -msseregparm @gol @@ -12692,6 +12692,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @itemx -mno-abm @itemx -mbmi @itemx -mno-bmi +@itemx -mlzcnt +@itemx -mno-lzcnt @itemx -mtbm @itemx -mno-tbm @opindex mmmx @@ -12702,7 +12704,7 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @opindex mno-3dnow These switches enable or disable the use of instructions in the MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, -SSE4A, FMA4, XOP, LWP, ABM, BMI, or 3DNow!@: extended instruction sets. +SSE4A, FMA4, XOP, LWP, ABM, BMI, LZCNT or 3DNow!@: extended instruction sets. These extensions are also available as built-in functions: see @ref{X86 Built-in Functions}, for details of the functions enabled and disabled by these switches. |