diff options
| author | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-11-21 09:36:11 +0000 |
|---|---|---|
| committer | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-11-21 09:36:11 +0000 |
| commit | 8726b204214570b8506b06e7f1af935e21cb25c9 (patch) | |
| tree | 197000f9c24e34c902c5357dd6d522f430ac0722 /gcc/doc | |
| parent | 0f3b427f9513aaff0bb89af90bb60fd21aa23ce8 (diff) | |
| download | gcc-8726b204214570b8506b06e7f1af935e21cb25c9.tar.gz | |
2011-11-21 Basile Starynkevitch <basile@starynkevitch.net>
MELT branch merged with trunk rev 181552 using svnmerge
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@181554 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/extend.texi | 1 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 9 |
2 files changed, 10 insertions, 0 deletions
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 15238c1b39e..de483a3d354 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -9384,6 +9384,7 @@ v2df __builtin_ia32_loadlpd (v2df, double const *) int __builtin_ia32_movmskpd (v2df) int __builtin_ia32_pmovmskb128 (v16qi) void __builtin_ia32_movnti (int *, int) +void __builtin_ia32_movnti64 (long long int *, long long int) void __builtin_ia32_movntpd (double *, v2df) void __builtin_ia32_movntdq (v2df *, v2df) v4si __builtin_ia32_pshufd (v4si, int) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 73f874f152c..7cc255c5c6e 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -12809,6 +12809,15 @@ Improved versions of k8, opteron and athlon64 with SSE3 instruction set support. AMD Family 10h core based CPUs with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit instruction set extensions.) +@item bdver1 +AMD Family 15h core based CPUs with x86-64 instruction set support. (This +supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, +SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit +instruction set extensions.) +@item btver1 +AMD Family 14h core based CPUs with x86-64 instruction set support. (This +supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit +instruction set extensions.) @item winchip-c6 IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction set support. |