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authorcongh <congh@138bc75d-0d04-0410-961f-82ee72b054a4>2014-06-25 02:58:43 +0000
committercongh <congh@138bc75d-0d04-0410-961f-82ee72b054a4>2014-06-25 02:58:43 +0000
commita2287001e780f4c18f16c47131b3d30b9d23e277 (patch)
tree84fbd0fced8d4e426b96dfd6edf4dfa423455a70 /gcc/expr.c
parent22104079cb48734e9adda11f0fbe8e43b4a9ee87 (diff)
downloadgcc-a2287001e780f4c18f16c47131b3d30b9d23e277.tar.gz
2014-06-24 Cong Hou <congh@google.com>
* tree-vect-patterns.c (vect_recog_sad_pattern): New function for SAD pattern recognition. (type_conversion_p): PROMOTION is true if it's a type promotion conversion, and false otherwise. Return true if the given expression is a type conversion one. * tree-vectorizer.h: Adjust the number of patterns. * tree.def: Add SAD_EXPR. * optabs.def: Add sad_optab. * cfgexpand.c (expand_debug_expr): Add SAD_EXPR case. * expr.c (expand_expr_real_2): Likewise. * gimple-pretty-print.c (dump_ternary_rhs): Likewise. * gimple.c (get_gimple_rhs_num_ops): Likewise. * optabs.c (optab_for_tree_code): Likewise. * tree-cfg.c (estimate_operator_cost): Likewise. * tree-ssa-operands.c (get_expr_operands): Likewise. * tree-vect-loop.c (get_initial_def_for_reduction): Likewise. * config/i386/sse.md: Add SSE2 and AVX2 expand for SAD. * doc/generic.texi: Add document for SAD_EXPR. * doc/md.texi: Add document for ssad and usad. 2014-06-24 Cong Hou <congh@google.com> * gcc.dg/vect/vect-reduc-sad.c: New. * lib/target-supports.exp (check_effective_target_vect_usad_char): New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211966 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/expr.c')
-rw-r--r--gcc/expr.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/gcc/expr.c b/gcc/expr.c
index 512c024e698..4d2163f721b 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -9110,6 +9110,20 @@ expand_expr_real_2 (sepops ops, rtx target, enum machine_mode tmode,
return target;
}
+ case SAD_EXPR:
+ {
+ tree oprnd0 = treeop0;
+ tree oprnd1 = treeop1;
+ tree oprnd2 = treeop2;
+ rtx op2;
+
+ expand_operands (oprnd0, oprnd1, NULL_RTX, &op0, &op1, EXPAND_NORMAL);
+ op2 = expand_normal (oprnd2);
+ target = expand_widen_pattern_expr (ops, op0, op1, op2,
+ target, unsignedp);
+ return target;
+ }
+
case REALIGN_LOAD_EXPR:
{
tree oprnd0 = treeop0;