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| author | aldyh <aldyh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-07-13 04:46:34 +0000 |
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| committer | aldyh <aldyh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-07-13 04:46:34 +0000 |
| commit | 47ae02b70c395550e01975e649e37f6ea829dac5 (patch) | |
| tree | b334918063791e89f97a111eb02e3d0c9f8a766e /gcc/regcprop.c | |
| parent | d7d884cefe202081bff234e3bd0a3dcaed79d5a1 (diff) | |
| download | gcc-47ae02b70c395550e01975e649e37f6ea829dac5.tar.gz | |
Fix double word typos.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@225726 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/regcprop.c')
| -rw-r--r-- | gcc/regcprop.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/regcprop.c b/gcc/regcprop.c index 46d0695898d..627c630d05e 100644 --- a/gcc/regcprop.c +++ b/gcc/regcprop.c @@ -352,7 +352,7 @@ copy_value (rtx dest, rtx src, struct value_data *vd) we must not do the same for the high part. Note we can still get low parts for the same mode combination through a two-step copy involving differently sized hard regs. - Assume hard regs fr* are 32 bits bits each, while r* are 64 bits each: + Assume hard regs fr* are 32 bits each, while r* are 64 bits each: (set (reg:DI r0) (reg:DI fr0)) (set (reg:SI fr2) (reg:SI r0)) loads the low part of (reg:DI fr0) - i.e. fr1 - into fr2, while: |