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authorwilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>1996-07-08 23:19:51 +0000
committerwilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>1996-07-08 23:19:51 +0000
commitdb42988f3dd3a69f8cb6a7668d1c303b08418ceb (patch)
tree700800f70053b67eb5b32a570b0d0869b8517897 /gcc/sched.c
parent7894dc88d4acdf3a46a675b4515ffb924d5961f8 (diff)
downloadgcc-db42988f3dd3a69f8cb6a7668d1c303b08418ceb.tar.gz
(true_dependence, anti_dependence, output_dependence):
Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@12416 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/sched.c')
-rw-r--r--gcc/sched.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/gcc/sched.c b/gcc/sched.c
index aea307f8eff..82acf33277f 100644
--- a/gcc/sched.c
+++ b/gcc/sched.c
@@ -807,11 +807,14 @@ memrefs_conflict_p (xsize, x, ysize, y, c)
changed. A volatile and non-volatile reference can be interchanged
though.
- A MEM_IN_STRUCT reference at a non-QImode varying address can never
+ A MEM_IN_STRUCT reference at a non-QImode non-AND varying address can never
conflict with a non-MEM_IN_STRUCT reference at a fixed address. We must
allow QImode aliasing because the ANSI C standard allows character
pointers to alias anything. We are assuming that characters are
- always QImode here. */
+ always QImode here. We also must allow AND addresses, because they may
+ generate accesses outside the object being referenced. This is used to
+ generate aligned addresses from unaligned addresses, for instance, the
+ alpha storeqi_unaligned pattern. */
/* Read dependence: X is read after read in MEM takes place. There can
only be a dependence here if both reads are volatile. */
@@ -848,9 +851,11 @@ true_dependence (mem, x)
SIZE_FOR_MODE (x), XEXP (x, 0), 0)
&& ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem)
&& GET_MODE (mem) != QImode
+ && GET_CODE (XEXP (mem, 0)) != AND
&& ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x))
&& ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x)
&& GET_MODE (x) != QImode
+ && GET_CODE (XEXP (x, 0)) != AND
&& ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem))));
}
@@ -874,9 +879,11 @@ anti_dependence (mem, x)
SIZE_FOR_MODE (x), XEXP (x, 0), 0)
&& ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem)
&& GET_MODE (mem) != QImode
+ && GET_CODE (XEXP (mem, 0)) != AND
&& ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x))
&& ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x)
&& GET_MODE (x) != QImode
+ && GET_CODE (XEXP (x, 0)) != AND
&& ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem))));
}
@@ -894,9 +901,11 @@ output_dependence (mem, x)
SIZE_FOR_MODE (x), XEXP (x, 0), 0)
&& ! (MEM_IN_STRUCT_P (mem) && rtx_addr_varies_p (mem)
&& GET_MODE (mem) != QImode
+ && GET_CODE (XEXP (mem, 0)) != AND
&& ! MEM_IN_STRUCT_P (x) && ! rtx_addr_varies_p (x))
&& ! (MEM_IN_STRUCT_P (x) && rtx_addr_varies_p (x)
&& GET_MODE (x) != QImode
+ && GET_CODE (XEXP (x, 0)) != AND
&& ! MEM_IN_STRUCT_P (mem) && ! rtx_addr_varies_p (mem))));
}