* arm.h (CLASS_LIKELY_SPILLED_P): Define.

testsuite
	* gcc.dg/spill-1.c: New test.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@80519 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 15 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.dg/spill-1.c b/gcc/testsuite/gcc.dg/spill-1.c
new file mode 100644
index 00000000000..b85942e87aa
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/spill-1.c
@@ -0,0 +1,15 @@
+/* This caused an ICE during register spilling when targeting thumb.
+   There are 8 registers available for arithmetic operations (r0-r7)
+   r7 is the frame pointer, and r0-r3 are used to pass arguments.
+   Combine was extending the lives of the arguments (in r0-r3) up until the
+   call to z. This leaves only 3 regs free which isn't enough to preform the
+   doubleword addition.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-omit-frame-pointer" } */
+void z(int);
+int foo(int a, int b, int c, int d, long long *q) 
+{ 
+  *q=*q+1; 
+  z (a+b+c+d); 
+}
+