PR target/18230

	* config/sparc/sparc.c (sparc_rtx_costs): Handle the NAND vector
	patterns.
	* config/sparc/sparc.md (V64I): New macro for 64-bit modes.
	(V32I): New macro for 32-bit modes.
	(anddi3, anddi_sp32, anddi_sp64, and_not_di_sp32, and_not_di_sp64,
	iordi3, iordi3_sp32, iordi_sp64, or_not_di_sp32, or_not_di_sp64,
	xordi3, xordi3_sp32, xordi3_sp64, {AND, IOR, XOR} DI splitter,
	xor_not_di_sp32, xordi_not_di_sp64, one_cmpldi2, one_cmpldi_sp32,
	one_cmpldi_sp64): Use V64I instead of DI.
	(andsi3, andsi_sp32, andsi_sp64, and_not_si, iorsi3, or_not_si,
	xorsi3, xor_not_si, one_cmplsi2): Use V32I instead of SI.
	(addv2si3, addv4hi3, addv2hi3): Remove % modifier.
	(nandv64i_vis, nandv32i_vis): New patterns.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@90578 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 48 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/sparc/fnand.c b/gcc/testsuite/gcc.target/sparc/fnand.c
new file mode 100644
index 00000000000..89fe8694df3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/fnand.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () & foo2_8 ());
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () & foo2_16 ());
+}
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~(foo1_32 () & foo2_32 ());
+}
+
+
+/* DeMorgan's Law's at work.  */
+vec8 fun8b(void)
+{
+  return ~foo1_8 () | ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return ~foo1_16 () | ~foo2_16 ();
+}
+
+vec32 fun32b(void)
+{
+  return ~foo1_32 () | ~foo2_32 ();
+}
+
+/* { dg-final { scan-assembler-times "fnand\t%" 6 } } */