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| author | davem <davem@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-10-02 02:21:20 +0000 |
|---|---|---|
| committer | davem <davem@138bc75d-0d04-0410-961f-82ee72b054a4> | 2011-10-02 02:21:20 +0000 |
| commit | 33e7b55c2549d655d88ec64c06c51912d0d07527 (patch) | |
| tree | 678e9f7f8529fb4e91e2480e8c8e5023253ce0e2 /gcc/testsuite/gcc.target/sparc/fucmp.c | |
| parent | b23b32a94937aa0d2edbec7767b52b5e7d232f6a (diff) | |
| download | gcc-33e7b55c2549d655d88ec64c06c51912d0d07527.tar.gz | |
Start adding support for VIS 3.0 instructions.
gcc/
* config/sparc/sparc.opt (VIS3): New option.
* doc/invoke.texi: Document it.
* config/sparc/sparc.h: Force TARGET_VIS3 to zero if assembler is
not capable of such instructions.
* config/sparc/sparc-c.c (sparc_target_macros): Define __VIS__
to 0x300 when TARGET_VIS3.
* config/sparc/sparc-modes.def: Create 16-byte vector modes.
* config/sparc/sparc.md (UNSPEC_CMASK8, UNSPEC_CMASK16, UNSPEC_CMASK32,
UNSPEC_FCHKSM16, UNSPEC_PDISTN, UNSPC_FUCMP): New unspecs.
(V64N8, VASS): New mode iterators.
(vis3_shift, vis3_addsub_ss): New code iterators.
(vbits, vconstr): New mode attributes.
(vis3_shift_insn, vis3_addsub_ss_insn): New code attributes.
(cmask8<P:mode>_vis, cmask16<P:mode>_vis, cmask32<P:mode>_vis,
fchksm16_vis, <vis3_shift_insn><vbits>_vis, pdistn<mode>_vis,
fmean16_vis, fpadd64_vis, fpsub64_vis, <vis3_addsub_ss_insn><vbits>_vis,
fucmp<code>8<P:mode>_vis): New VIS 3.0 instruction patterns.
* config/sparc/sparc.c (sparc_option_override): Set MASK_VIS3 by
default when targetting capable cpus. TARGET_VIS3 implies
TARGET_VIS2 and TARGET_VIS, and clear them when TARGET_FPU is
disabled.
(sparc_vis_init_builtins): Emit new VIS 3.0 builtins.
(sparc_fold_builtin): Do not eliminate cmask{8,16,32} when result
is ignored.
* config/sparc/visintrin.h (__vis_cmask8, __vis_cmask16,
__vis_cmask32, __vis_fchksm16, __vis_fsll16, __vis_fslas16,
__vis_fsrl16, __vis_fsra16, __vis_fsll32, __vis_fslas32,
__vis_fsrl32, __vis_fsra32, __vis_pdistn, __vis_fmean16,
__vis_fpadd64, __vis_fpsub64, __vis_fpadds16, __vis_fpadds16s,
__vis_fpsubs16, __vis_fpsubs16s, __vis_fpadds32, __vis_fpadds32s,
__vis_fpsubs32, __vis_fpsubs32s, __vis_fucmple8, __vis_fucmpne8,
__vis_fucmpgt8, __vis_fucmpeq8): New VIS 3.0 interfaces.
* doc/extend.texi: Document new VIS 3.0 builtins.
gcc/testsuite/
* gcc.target/sparc/cmask.c: New test.
* gcc.target/sparc/fpadds.c: New test.
* gcc.target/sparc/fshift.c: New test.
* gcc.target/sparc/fucmp.c: New test.
* gcc.target/sparc/vis3misc.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@179421 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/testsuite/gcc.target/sparc/fucmp.c')
| -rw-r--r-- | gcc/testsuite/gcc.target/sparc/fucmp.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/sparc/fucmp.c b/gcc/testsuite/gcc.target/sparc/fucmp.c new file mode 100644 index 00000000000..7f291c3e7ed --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/fucmp.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=niagara3 -mvis" } */ +typedef unsigned char vec8 __attribute__((vector_size(8))); + +long test_fucmple8 (vec8 a, vec8 b) +{ + return __builtin_vis_fucmple8 (a, b); +} + +long test_fucmpne8 (vec8 a, vec8 b) +{ + return __builtin_vis_fucmpne8 (a, b); +} + +long test_fucmpgt8 (vec8 a, vec8 b) +{ + return __builtin_vis_fucmpgt8 (a, b); +} + +long test_fucmpeq8 (vec8 a, vec8 b) +{ + return __builtin_vis_fucmpeq8 (a, b); +} + +/* { dg-final { scan-assembler "fucmple8\t%" } } */ +/* { dg-final { scan-assembler "fucmpne8\t%" } } */ +/* { dg-final { scan-assembler "fucmpgt8\t%" } } */ +/* { dg-final { scan-assembler "fucmpeq8\t%" } } */ |