diff options
| author | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-02-10 17:20:51 +0000 |
|---|---|---|
| committer | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-02-10 17:20:51 +0000 |
| commit | 2d9d01985a7a7866916fafa19c5c296702e69714 (patch) | |
| tree | 259c095c65fc0c6279b7a17755b3f851f51babb3 /gcc/testsuite/gcc.target | |
| parent | c8ebeb0e3c6b093e649592be7d51d1c0032a1dc7 (diff) | |
| download | gcc-2d9d01985a7a7866916fafa19c5c296702e69714.tar.gz | |
2016-02-10 Basile Starynkevitch <basile@starynkevitch.net>
{{merging with even more of GCC 6, using subversion 1.9
svn merge -r227001:227400 ^/trunk ;
there is some gengtype issue before svn r228000... }}
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@233281 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/testsuite/gcc.target')
63 files changed, 770 insertions, 50 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/ashltidisi.c b/gcc/testsuite/gcc.target/aarch64/ashltidisi.c new file mode 100644 index 00000000000..293a0f2563b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ashltidisi.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -save-temps" } */ + +extern void abort (void); + +#define GEN_TEST_CASE(x, y, z)\ +__uint128_t __attribute__ ((noinline))\ +ushift_##x##_##z (unsigned y data)\ +{\ + return (__uint128_t) data << x;\ +}\ +__int128_t __attribute__ ((noinline)) \ +shift_##x##_##z (y data) \ +{\ + return (__int128_t) data << x;\ +} + +GEN_TEST_CASE (53, int, i) +GEN_TEST_CASE (3, long long, ll) +GEN_TEST_CASE (13, long long, ll) +GEN_TEST_CASE (53, long long, ll) + +int +main (int argc, char **argv) +{ + +#define SHIFT_CHECK(x, y, z, p) \ + if (ushift_##y##_##p (x)\ + != ((__uint128_t) (unsigned z) x << y)) \ + abort ();\ + if (shift_##y##_##p (x)\ + != ((__uint128_t) (signed z) x << y)) \ + abort (); + + SHIFT_CHECK (0x12345678, 53, int, i) + SHIFT_CHECK (0xcafecafe, 53, int, i) + + SHIFT_CHECK (0x1234567890abcdefLL, 3, long long, ll) + SHIFT_CHECK (0x1234567890abcdefLL, 13, long long, ll) + SHIFT_CHECK (0x1234567890abcdefLL, 53, long long, ll) + SHIFT_CHECK (0xcafecafedeaddeadLL, 3, long long, ll) + SHIFT_CHECK (0xcafecafedeaddeadLL, 13, long long, ll) + SHIFT_CHECK (0xcafecafedeaddeadLL, 53, long long, ll) + + return 0; +} + +/* { dg-final { scan-assembler-times "asr" 4 } } */ +/* { dg-final { scan-assembler-not "extr\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/combine_bfi_1.c b/gcc/testsuite/gcc.target/aarch64/combine_bfi_1.c new file mode 100644 index 00000000000..accf1441093 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/combine_bfi_1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-rtl-combine" } */ + +int +f1 (int x, int y) +{ + return (x & ~0x0ffff00) | ((y << 8) & 0x0ffff00); +} + +int +f2 (int x, int y) +{ + return (x & ~0x0ff000) | ((y & 0x0ff) << 12); +} + +int +f3 (int x, int y) +{ + return (x & ~0xffff) | (y & 0xffff); +} + +int +f4 (int x, int y) +{ + return (x & ~0xff) | (y & 0xff); +} + +long +f5 (long x, long y) +{ + return (x & ~0xffffffffull) | (y & 0xffffffff); +} + +/* { dg-final { scan-rtl-dump-times "\\*aarch64_bfi" 5 "combine" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/long_branch_1.c b/gcc/testsuite/gcc.target/aarch64/long_branch_1.c new file mode 100644 index 00000000000..46f500d36a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/long_branch_1.c @@ -0,0 +1,91 @@ +/* { dg-do assemble } */ +/* { dg-timeout-factor 2.0 } */ +/* { dg-options "-O1 -fno-reorder-blocks -fno-tree-cselim --save-temps" } */ + + +__attribute__((noinline, noclone)) int +restore (int a, int b) +{ + return a * b; +} + +__attribute__((noinline, noclone)) void +do_nothing (int *input) +{ + *input = restore (*input, 1); + return; +} +#define ENTRY_SUM(n, x) \ + sum = sum / ((n) + (x)); \ + sum = restore (sum, (n) + (x)); + +#define ENTRY_SUM2(n, x) ENTRY_SUM ((n), (x)) ENTRY_SUM ((n), (x)+1) +#define ENTRY_SUM4(n, x) ENTRY_SUM2 ((n), (x)) ENTRY_SUM2 ((n), (x)+2) +#define ENTRY_SUM8(n, x) ENTRY_SUM4 ((n), (x)) ENTRY_SUM4 ((n), (x)+4) +#define ENTRY_SUM16(n, x) ENTRY_SUM8 ((n), (x)) ENTRY_SUM8 ((n), (x)+8) +#define ENTRY_SUM32(n, x) ENTRY_SUM16 ((n), (x)) ENTRY_SUM16 ((n), (x)+16) +#define ENTRY_SUM64(n, x) ENTRY_SUM32 ((n), (x)) ENTRY_SUM32 ((n), (x)+32) +#define ENTRY_SUM128(n, x) ENTRY_SUM64 ((n), (x)) ENTRY_SUM64 ((n), (x)+64) + +#define CASE_ENTRY(n) \ + case n: \ + sum = sum / (n + 1); \ + sum = restore (sum, n + 1); \ + if (sum == (n + addend)) \ + break;\ + ENTRY_SUM128 ((n), 2) \ + ENTRY_SUM16 ((n), 130) \ + break; + +#define CASE_ENTRY2(n) CASE_ENTRY ((n)) CASE_ENTRY ((n)+1) +#define CASE_ENTRY4(n) CASE_ENTRY2 ((n)) CASE_ENTRY2 ((n)+2) +#define CASE_ENTRY8(n) CASE_ENTRY4 ((n)) CASE_ENTRY4 ((n)+4) +#define CASE_ENTRY16(n) CASE_ENTRY8 ((n)) CASE_ENTRY8 ((n)+8) +#define CASE_ENTRY32(n) CASE_ENTRY16 ((n)) CASE_ENTRY16 ((n)+16) +#define CASE_ENTRY64(n) CASE_ENTRY32 ((n)) CASE_ENTRY32 ((n)+32) +#define CASE_ENTRY128(n) CASE_ENTRY64 ((n)) CASE_ENTRY64 ((n)+64) + +__attribute__((noinline, noclone)) long long +test_and_branch (int selector, int addend, int cond) +{ + long long sum = selector + 1; + + if (selector > 200) + { +start0: + return sum - 1; +start1: + return sum + 1; +start2: + return sum; +start3: + return sum - 2; + } + else + { + switch (selector) + { + CASE_ENTRY128 (1) + CASE_ENTRY64 (129) + CASE_ENTRY16 (193) + } + + do_nothing ((int *)&sum); + + if (cond == 0) + goto start0; + else if (cond < 0) + goto start1; + else if ((cond & 0x010) != 0) + goto start2; + else if (cond >= 14) + goto start3; + + } + + return -1; +} + +/* { dg-final { scan-assembler "Lbcond" } } */ +/* { dg-final { scan-assembler "Lcb" } } */ +/* { dg-final { scan-assembler "Ltb" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c new file mode 100644 index 00000000000..d6e7b681832 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=thunderx+nofp" } */ + +/* Make sure that we don't ICE when dealing with vector parameters + in a simd-tagged function within a non-simd translation unit. */ + +#pragma GCC push_options +#pragma GCC target ("+nothing+simd") +typedef unsigned int __uint32_t; +typedef __uint32_t uint32_t ; +typedef __Uint32x4_t uint32x4_t; +#pragma GCC pop_options + + +__attribute__ ((target ("cpu=cortex-a57"))) +uint32x4_t +foo (uint32x4_t a, uint32_t b, uint32x4_t c) +{ + return c; +} diff --git a/gcc/testsuite/gcc.target/aarch64/tls_1.x b/gcc/testsuite/gcc.target/aarch64/tls_1.x new file mode 100644 index 00000000000..d92281b6de2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tls_1.x @@ -0,0 +1,14 @@ +void abort (void); + +__thread int t0 = 0x10; +__thread int t1 = 0x10; + +int +main (int argc, char **argv) +{ + if (t0 != t1) + abort (); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/aarch64/tlsie_tiny_1.c b/gcc/testsuite/gcc.target/aarch64/tlsie_tiny_1.c new file mode 100644 index 00000000000..7477fa60661 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tlsie_tiny_1.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target tls_native } */ +/* { dg-options "-O2 -fpic -ftls-model=initial-exec -mcmodel=tiny" } */ + +#include "tls_1.x" + +/* { dg-final { scan-assembler-times ":gottprel:" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/tlsle12_1.c b/gcc/testsuite/gcc.target/aarch64/tlsle12_1.c new file mode 100644 index 00000000000..c0bf488b3b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tlsle12_1.c @@ -0,0 +1,8 @@ +/* { dg-do run } */ +/* { dg-require-effective-target tls_native } */ +/* { dg-options "-O2 -fpic -ftls-model=local-exec -mtls-size=12 --save-temps" } */ + +#include "tls_1.x" + +/* { dg-final { scan-assembler-times "#:tprel_lo12" 2 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/tlsle24_1.c b/gcc/testsuite/gcc.target/aarch64/tlsle24_1.c new file mode 100644 index 00000000000..9acc4c85a76 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tlsle24_1.c @@ -0,0 +1,9 @@ +/* { dg-do run } */ +/* { dg-require-effective-target tls_native } */ +/* { dg-options "-O2 -fpic -ftls-model=local-exec -mtls-size=24 --save-temps" } */ + +#include "tls_1.x" + +/* { dg-final { scan-assembler-times "#:tprel_lo12_nc" 2 } } */ +/* { dg-final { scan-assembler-times "#:tprel_hi12" 2 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/tlsle32_1.c b/gcc/testsuite/gcc.target/aarch64/tlsle32_1.c new file mode 100644 index 00000000000..0610d2ac15c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/tlsle32_1.c @@ -0,0 +1,10 @@ +/* { dg-do run } */ +/* { dg-require-effective-target tls_native } */ +/* { dg-require-effective-target aarch64_tlsle32 } */ +/* { dg-options "-O2 -fpic -ftls-model=local-exec -mtls-size=32 --save-temps" } */ + +#include "tls_1.x" + +/* { dg-final { scan-assembler-times "#:tprel_g1" 2 } } */ +/* { dg-final { scan-assembler-times "#:tprel_g0_nc" 2 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c b/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c index 9fff611b6c0..b0ba6e253df 100644 --- a/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c +++ b/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-madx -O2" } */ -/* { dg-final { scan-assembler-times "adcx" 2 } } */ +/* { dg-final { scan-assembler-times "adc\[xl\]" 2 } } */ /* { dg-final { scan-assembler-times "sbbl" 1 } } */ #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c b/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c index 3608dea79b9..cbe19856c6f 100644 --- a/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c +++ b/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-madx -O2" } */ -/* { dg-final { scan-assembler-times "adcx" 2 } } */ +/* { dg-final { scan-assembler-times "adc\[xq\]" 2 } } */ /* { dg-final { scan-assembler-times "sbbq" 1 } } */ #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/pr66821.c b/gcc/testsuite/gcc.target/i386/pr66821.c new file mode 100644 index 00000000000..d32f03d5a96 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr66821.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-O2 -fdump-tree-optimized -mtune=iamcu" } */ + +void bar (void); + +void +foo (int x) +{ + if (x != 2 && x != 3 && x != 10 && x != 11 && x != 17 && x != 18 && x != 23) + bar (); +} + +/* Check if the tests have been folded into a bit test. */ +/* { dg-final { scan-tree-dump "(8784908|0x0*860c0c)" "optimized" } } */ +/* { dg-final { scan-tree-dump "(<<|>>)" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr67317-1.c b/gcc/testsuite/gcc.target/i386/pr67317-1.c new file mode 100644 index 00000000000..7db4e5f31a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67317-1.c @@ -0,0 +1,18 @@ +/* PR target/67317 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef unsigned int u32; + +u32 testcarry_u32 (u32 a, u32 b, u32 c, u32 d) +{ + u32 result0, result1; + + __builtin_ia32_addcarryx_u32 + (__builtin_ia32_addcarryx_u32 (0, a, c, &result0), b, d, &result1); + + return result0 ^ result1; +} + +/* { dg-final { scan-assembler-not "addb" } } */ +/* { dg-final { scan-assembler-not "setn?c" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr67317-2.c b/gcc/testsuite/gcc.target/i386/pr67317-2.c new file mode 100644 index 00000000000..97b2eff88dc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67317-2.c @@ -0,0 +1,18 @@ +/* PR target/67317 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +typedef unsigned long long u64; + +u64 testcarry_u64 (u64 a, u64 b, u64 c, u64 d) +{ + u64 result0, result1; + + __builtin_ia32_addcarryx_u64 + (__builtin_ia32_addcarryx_u64 (0, a, c, &result0), b, d, &result1); + + return result0 ^ result1; +} + +/* { dg-final { scan-assembler-not "addb" } } */ +/* { dg-final { scan-assembler-not "setn?c" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr67317-3.c b/gcc/testsuite/gcc.target/i386/pr67317-3.c new file mode 100644 index 00000000000..c141d098108 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67317-3.c @@ -0,0 +1,18 @@ +/* PR target/67317 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef unsigned int u32; + +u32 testcarry_u32 (u32 a, u32 b, u32 c, u32 d) +{ + u32 result0, result1; + + __builtin_ia32_sbb_u32 + (__builtin_ia32_sbb_u32 (0, a, c, &result0), b, d, &result1); + + return result0 ^ result1; +} + +/* { dg-final { scan-assembler-not "addb" } } */ +/* { dg-final { scan-assembler-not "setn?c" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr67317-4.c b/gcc/testsuite/gcc.target/i386/pr67317-4.c new file mode 100644 index 00000000000..2f95dbc16f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67317-4.c @@ -0,0 +1,18 @@ +/* PR target/67317 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +typedef unsigned long long u64; + +u64 testcarry_u64 (u64 a, u64 b, u64 c, u64 d) +{ + u64 result0, result1; + + __builtin_ia32_sbb_u64 + (__builtin_ia32_sbb_u64 (0, a, c, &result0), b, d, &result1); + + return result0 ^ result1; +} + +/* { dg-final { scan-assembler-not "addb" } } */ +/* { dg-final { scan-assembler-not "setn?c" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr67329.c b/gcc/testsuite/gcc.target/i386/pr67329.c new file mode 100644 index 00000000000..a29dd5b4f8d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr67329.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target ia32 } } */ +/* { dg-options "-O3 -fno-tree-fre -fno-tree-pre -fdump-tree-optimized -mtune=iamcu" } */ + +int +foo () +{ + const int a[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; + int i, sum; + + sum = 0; + for (i = 0; i < sizeof (a) / sizeof (*a); i++) + sum += a[i]; + + return sum; +} + +/* After late unrolling the above loop completely DOM should be + able to optimize this to return 28. */ + +/* { dg-final { scan-tree-dump "return 28;" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/i386/ssp-default.c b/gcc/testsuite/gcc.target/i386/ssp-default.c new file mode 100644 index 00000000000..3f65ed8a80d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/ssp-default.c @@ -0,0 +1,22 @@ +/* { dg-do run { target native } } */ +/* { dg-require-effective-target fstack_protector_enabled } */ + +#include <stdlib.h> + +void +__stack_chk_fail (void) +{ + exit (0); /* pass */ +} + +int main () +{ + int i; + char foo[255]; + + /* smash stack */ + for (i = 0; i <= 400; i++) + foo[i] = 42; + + return 1; /* fail */ +} diff --git a/gcc/testsuite/gcc.target/mips/branch-10.c b/gcc/testsuite/gcc.target/mips/branch-10.c index eb21c165462..9428254f0df 100644 --- a/gcc/testsuite/gcc.target/mips/branch-10.c +++ b/gcc/testsuite/gcc.target/mips/branch-10.c @@ -1,6 +1,6 @@ /* { dg-options "-mshared -mabi=n32" } */ /* { dg-final { scan-assembler-not "(\\\$28|%gp_rel|%got)" } } */ -/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler-not "\tjrc?\t\\\$1\n" } } */ #include "branch-helper.h" diff --git a/gcc/testsuite/gcc.target/mips/branch-11.c b/gcc/testsuite/gcc.target/mips/branch-11.c index bd8e83418c0..9238d9ca1eb 100644 --- a/gcc/testsuite/gcc.target/mips/branch-11.c +++ b/gcc/testsuite/gcc.target/mips/branch-11.c @@ -4,7 +4,7 @@ /* { dg-final { scan-assembler "\taddiu\t\\\$28,\\\$28,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */ /* { dg-final { scan-assembler "\tlw\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$28\\)\n" } } */ /* { dg-final { scan-assembler "\taddiu\t\\\$1,\\\$1,%got_ofst\\(\[^)\]*\\)\n" } } */ -/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler "\tjrc?\t\\\$1\n" } } */ #include "branch-helper.h" diff --git a/gcc/testsuite/gcc.target/mips/branch-12.c b/gcc/testsuite/gcc.target/mips/branch-12.c index 49446341ad2..97261acea60 100644 --- a/gcc/testsuite/gcc.target/mips/branch-12.c +++ b/gcc/testsuite/gcc.target/mips/branch-12.c @@ -1,6 +1,6 @@ /* { dg-options "-mshared -mabi=64" } */ /* { dg-final { scan-assembler-not "(\\\$28|%gp_rel|%got)" } } */ -/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler-not "\tjrc?\t\\\$1\n" } } */ #include "branch-helper.h" diff --git a/gcc/testsuite/gcc.target/mips/branch-13.c b/gcc/testsuite/gcc.target/mips/branch-13.c index f5269b9b33b..5ea5f1b64fe 100644 --- a/gcc/testsuite/gcc.target/mips/branch-13.c +++ b/gcc/testsuite/gcc.target/mips/branch-13.c @@ -4,7 +4,7 @@ /* { dg-final { scan-assembler "\tdaddiu\t\\\$28,\\\$28,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */ /* { dg-final { scan-assembler "\tld\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$28\\)\n" } } */ /* { dg-final { scan-assembler "\tdaddiu\t\\\$1,\\\$1,%got_ofst\\(\[^)\]*\\)\n" } } */ -/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler "\tjrc?\t\\\$1\n" } } */ #include "branch-helper.h" diff --git a/gcc/testsuite/gcc.target/mips/branch-3.c b/gcc/testsuite/gcc.target/mips/branch-3.c index 69300f6417c..310812aa4da 100644 --- a/gcc/testsuite/gcc.target/mips/branch-3.c +++ b/gcc/testsuite/gcc.target/mips/branch-3.c @@ -1,6 +1,6 @@ /* { dg-options "-mshared -mabi=32" } */ /* { dg-final { scan-assembler "\t\\.cpload\t\\\$25\n" } } */ -/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler "\tjrc?\t\\\$1\n" } } */ /* { dg-final { scan-assembler-not "\\.cprestore" } } */ #include "branch-helper.h" diff --git a/gcc/testsuite/gcc.target/mips/branch-4.c b/gcc/testsuite/gcc.target/mips/branch-4.c index 29f5c9f2be3..9dec90469f5 100644 --- a/gcc/testsuite/gcc.target/mips/branch-4.c +++ b/gcc/testsuite/gcc.target/mips/branch-4.c @@ -1,6 +1,6 @@ /* { dg-options "-mshared -mabi=n32" } */ /* { dg-final { scan-assembler-not "(\\\$25|\\\$28|%gp_rel|%got)" } } */ -/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler-not "\tjrc?\t\\\$1\n" } } */ #include "branch-helper.h" diff --git a/gcc/testsuite/gcc.target/mips/branch-5.c b/gcc/testsuite/gcc.target/mips/branch-5.c index 0538646210a..60daf27d06b 100644 --- a/gcc/testsuite/gcc.target/mips/branch-5.c +++ b/gcc/testsuite/gcc.target/mips/branch-5.c @@ -1,7 +1,7 @@ /* { dg-options "-mshared -mabi=n32" } */ /* { dg-final { scan-assembler "\taddiu\t\\\$3,\\\$3,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */ /* { dg-final { scan-assembler "\tlw\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$3\\)\\n" } } */ -/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler "\tjrc?\t\\\$1\n" } } */ /* { dg-final { scan-assembler-not "\\\$28" } } */ #include "branch-helper.h" diff --git a/gcc/testsuite/gcc.target/mips/branch-6.c b/gcc/testsuite/gcc.target/mips/branch-6.c index 19baee1db9f..4262ba7e849 100644 --- a/gcc/testsuite/gcc.target/mips/branch-6.c +++ b/gcc/testsuite/gcc.target/mips/branch-6.c @@ -1,6 +1,6 @@ /* { dg-options "-mshared -mabi=64" } */ /* { dg-final { scan-assembler-not "(\\\$25|\\\$28|%gp_rel|%got)" } } */ -/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler-not "\tjrc?\t\\\$1\n" } } */ #include "branch-helper.h" diff --git a/gcc/testsuite/gcc.target/mips/branch-7.c b/gcc/testsuite/gcc.target/mips/branch-7.c index 16c6d8e1ac6..a0c28a2bb65 100644 --- a/gcc/testsuite/gcc.target/mips/branch-7.c +++ b/gcc/testsuite/gcc.target/mips/branch-7.c @@ -1,7 +1,7 @@ /* { dg-options "-mshared -mabi=64" } */ /* { dg-final { scan-assembler "\tdaddiu\t\\\$3,\\\$3,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */ /* { dg-final { scan-assembler "\tld\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$3\\)\\n" } } */ -/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler "\tjrc?\t\\\$1\n" } } */ /* { dg-final { scan-assembler-not "\\\$28" } } */ #include "branch-helper.h" diff --git a/gcc/testsuite/gcc.target/mips/branch-8.c b/gcc/testsuite/gcc.target/mips/branch-8.c index 2e468448fe9..5a5494e0bd1 100644 --- a/gcc/testsuite/gcc.target/mips/branch-8.c +++ b/gcc/testsuite/gcc.target/mips/branch-8.c @@ -1,6 +1,6 @@ /* { dg-options "-mshared -mabi=32" } */ /* { dg-final { scan-assembler-not "(\\\$28|cpload|cprestore)" } } */ -/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler-not "\tjrc?\t\\\$1\n" } } */ #include "branch-helper.h" diff --git a/gcc/testsuite/gcc.target/mips/branch-9.c b/gcc/testsuite/gcc.target/mips/branch-9.c index b87f2ba675b..88a6d9a063f 100644 --- a/gcc/testsuite/gcc.target/mips/branch-9.c +++ b/gcc/testsuite/gcc.target/mips/branch-9.c @@ -4,7 +4,7 @@ /* { dg-final { scan-assembler "\tlw\t\\\$1,16\\(\\\$(fp|sp)\\)\n" } } */ /* { dg-final { scan-assembler "\tlw\t\\\$1,%got\\(\[^)\]*\\)\\(\\\$1\\)\n" } } */ /* { dg-final { scan-assembler "\taddiu\t\\\$1,\\\$1,%lo\\(\[^)\]*\\)\n" } } */ -/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */ +/* { dg-final { scan-assembler "\tjrc?\t\\\$1\n" } } */ /* { dg-final { scan-assembler-not "\\\$28" } } */ #include "branch-helper.h" diff --git a/gcc/testsuite/gcc.target/mips/branch-cost-1.c b/gcc/testsuite/gcc.target/mips/branch-cost-1.c index f72f2acfb3a..61c3029dd77 100644 --- a/gcc/testsuite/gcc.target/mips/branch-cost-1.c +++ b/gcc/testsuite/gcc.target/mips/branch-cost-1.c @@ -6,4 +6,4 @@ foo (int x, int y, int z, int k) return x == k ? x + y : z - x; } /* { dg-final { scan-assembler-not "\t(movz|movn)\t" } } */ -/* { dg-final { scan-assembler "\t(bne|beq)\t" } } */ +/* { dg-final { scan-assembler "\t(bnec?|beqc?)\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/call-1.c b/gcc/testsuite/gcc.target/mips/call-1.c index a00126eb693..46a2536754b 100644 --- a/gcc/testsuite/gcc.target/mips/call-1.c +++ b/gcc/testsuite/gcc.target/mips/call-1.c @@ -1,12 +1,12 @@ /* { dg-options "-mrelax-pic-calls -mshared -foptimize-sibling-calls -mabi=32" } */ /* { dg-skip-if "requires -foptimize-sibling-calls" { *-*-* } { "-O0" } { "" } } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal\n1:\tjalrs?\t" } } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal2\n1:\tjalrs?\t" } } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,staticfunc\n1:\tjalrs?\t" } } */ -/* { dg-final { scan-assembler "(\\.reloc\t1f,R_MIPS_JALR,tail\n1:)?\tjrc?\t" } } */ -/* { dg-final { scan-assembler "(\\.reloc\t1f,R_MIPS_JALR,tail2\n1:)?\tjrc?\t" } } */ -/* { dg-final { scan-assembler "(\\.reloc\t1f,R_MIPS_JALR,tail3\n1:)?\tjrc?\t" } } */ -/* { dg-final { scan-assembler "(\\.reloc\t1f,R_MIPS_JALR,tail4\n1:)?\tjrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal\n1:\tjalrc?s?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal2\n1:\tjalrc?s?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,staticfunc\n1:\tjalrc?s?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail\n1:\tjrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail2\n1:\tjrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail3\n1:\tjrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail4\n1:\tjrc?\t" } } */ __attribute__ ((noinline)) static void staticfunc () { asm (""); } int normal (); diff --git a/gcc/testsuite/gcc.target/mips/call-2.c b/gcc/testsuite/gcc.target/mips/call-2.c index 58cc2c6b03c..175933cbe77 100644 --- a/gcc/testsuite/gcc.target/mips/call-2.c +++ b/gcc/testsuite/gcc.target/mips/call-2.c @@ -1,6 +1,6 @@ /* See through some simple data-flow. */ /* { dg-options "-mrelax-pic-calls" } */ -/* { dg-final { scan-assembler-times "\\.reloc\t1f,R_MIPS_JALR,g\n1:\tjalrs?\t" 2 } } */ +/* { dg-final { scan-assembler-times "\\.reloc\t1f,R_MIPS_JALR,g\n1:\tjalrc?s?\t" 2 } } */ extern void g (void); diff --git a/gcc/testsuite/gcc.target/mips/call-3.c b/gcc/testsuite/gcc.target/mips/call-3.c index 4a662e300ec..08cf336a424 100644 --- a/gcc/testsuite/gcc.target/mips/call-3.c +++ b/gcc/testsuite/gcc.target/mips/call-3.c @@ -1,5 +1,5 @@ /* { dg-options "-mrelax-pic-calls -mno-shared" } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,g\n1:\tjalrs?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,g\n1:\tjalrc?s?\t" } } */ /* { dg-require-visibility "" } */ __attribute__ ((visibility ("hidden"))) void g (); diff --git a/gcc/testsuite/gcc.target/mips/call-4.c b/gcc/testsuite/gcc.target/mips/call-4.c index a343c429a6a..bf357c7a5b0 100644 --- a/gcc/testsuite/gcc.target/mips/call-4.c +++ b/gcc/testsuite/gcc.target/mips/call-4.c @@ -1,6 +1,6 @@ /* See through some simple data-flow. */ /* { dg-options "-mrelax-pic-calls" } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,g\n1:\tjalr\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,g\n1:\tjalrc?\t" } } */ extern void g (void); diff --git a/gcc/testsuite/gcc.target/mips/call-5.c b/gcc/testsuite/gcc.target/mips/call-5.c index d8d84d3782e..f6ebae9db79 100644 --- a/gcc/testsuite/gcc.target/mips/call-5.c +++ b/gcc/testsuite/gcc.target/mips/call-5.c @@ -2,13 +2,13 @@ in this case (PR target/57260). */ /* { dg-options "-mrelax-pic-calls -mshared -foptimize-sibling-calls -mabi=n32" } */ /* { dg-skip-if "requires -foptimize-sibling-calls" { *-*-* } { "-O0" } { "" } } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal\n1:\tjalr\t" } } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal2\n1:\tjalr\t" } } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,staticfunc\n1:\tjalr\t" } } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail\n1:\tjalr\t" } } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail2\n1:\tjalr\t" } } */ -/* { dg-final { scan-assembler "(\\.reloc\t1f,R_MIPS_JALR,tail3\n1:)?\tjrc?\t" } } */ -/* { dg-final { scan-assembler "(\\.reloc\t1f,R_MIPS_JALR,tail4\n1:)?\tjrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal\n1:\tjalrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal2\n1:\tjalrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,staticfunc\n1:\tjalrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail\n1:\tjalrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail2\n1:\tjalrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail3\n1:\tjrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail4\n1:\tjrc?\t" } } */ __attribute__ ((noinline)) static void staticfunc () { asm (""); } int normal (); diff --git a/gcc/testsuite/gcc.target/mips/call-6.c b/gcc/testsuite/gcc.target/mips/call-6.c index e6c90d7b5a3..00f4a1ef353 100644 --- a/gcc/testsuite/gcc.target/mips/call-6.c +++ b/gcc/testsuite/gcc.target/mips/call-6.c @@ -1,13 +1,13 @@ /* Like call-5.c, but for n64. */ /* { dg-options "-mrelax-pic-calls -mshared -foptimize-sibling-calls -mabi=64" } */ /* { dg-skip-if "requires -foptimize-sibling-calls" { *-*-* } { "-O0" } { "" } } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal\n1:\tjalr\t" } } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal2\n1:\tjalr\t" } } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,staticfunc\n1:\tjalr\t" } } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail\n1:\tjalr\t" } } */ -/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail2\n1:\tjalr\t" } } */ -/* { dg-final { scan-assembler "(\\.reloc\t1f,R_MIPS_JALR,tail3\n1:)?\tjrc?\t" } } */ -/* { dg-final { scan-assembler "(\\.reloc\t1f,R_MIPS_JALR,tail4\n1:)?\tjrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal\n1:\tjalrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal2\n1:\tjalrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,staticfunc\n1:\tjalrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail\n1:\tjalrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail2\n1:\tjalrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail3\n1:\tjrc?\t" } } */ +/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail4\n1:\tjrc?\t" } } */ __attribute__ ((noinline)) static void staticfunc () { asm (""); } int normal (); diff --git a/gcc/testsuite/gcc.target/mips/compact-branches-1.c b/gcc/testsuite/gcc.target/mips/compact-branches-1.c new file mode 100644 index 00000000000..9c7365e2659 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/compact-branches-1.c @@ -0,0 +1,12 @@ +/* { dg-options "-mcompact-branches=always -mno-micromips" } */ +int glob; + +void +foo (int a, int b) +{ + if (a < b) + glob = 1; +} + +/* { dg-final { scan-assembler "\tbgec\t\\\$\[0-9\]*,\\\$\[0-9\]*" } } */ +/* { dg-final { scan-assembler "\tjrc\t\\\$31" } } */ diff --git a/gcc/testsuite/gcc.target/mips/compact-branches-2.c b/gcc/testsuite/gcc.target/mips/compact-branches-2.c new file mode 100644 index 00000000000..0f8064f5d88 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/compact-branches-2.c @@ -0,0 +1,12 @@ +/* { dg-options "-mcompact-branches=never" } */ +int glob; + +void +foo (int a, int b) +{ + if (a < b) + glob = 1; +} + +/* { dg-final { scan-assembler-not "\tb\[^ \t\]*c" } } */ +/* { dg-final { scan-assembler-not "\tj\[^ \t\]*c" } } */ diff --git a/gcc/testsuite/gcc.target/mips/compact-branches-3.c b/gcc/testsuite/gcc.target/mips/compact-branches-3.c new file mode 100644 index 00000000000..d6becb10eee --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/compact-branches-3.c @@ -0,0 +1,13 @@ +/* { dg-options "-mcompact-branches=never isa_rev>=6" } */ +int glob; + +void +foo (int a, int b, volatile int * bar) +{ + if (a < b) + glob = *bar; +} + +/* { dg-final { scan-assembler "\tnop" } } */ +/* { dg-final { scan-assembler-not "\tb\[^ \t\]*c" } } */ +/* { dg-final { scan-assembler-not "\tj\[^ \t\]*c" } } */ diff --git a/gcc/testsuite/gcc.target/mips/compact-branches-4.c b/gcc/testsuite/gcc.target/mips/compact-branches-4.c new file mode 100644 index 00000000000..fd99ad64f6d --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/compact-branches-4.c @@ -0,0 +1,11 @@ +/* { dg-options "-mcompact-branches=optimal isa_rev>=6" } */ +int glob; + +void +foo (int a, int b, volatile int * bar) +{ + if (a < b) + glob = *bar; +} + +/* { dg-final { scan-assembler "\tb\[^ \t\]*c" } } */ diff --git a/gcc/testsuite/gcc.target/mips/compact-branches-5.c b/gcc/testsuite/gcc.target/mips/compact-branches-5.c new file mode 100644 index 00000000000..90d312c614d --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/compact-branches-5.c @@ -0,0 +1,10 @@ +/* { dg-options "-mno-abicalls -mcompact-branches=never isa_rev>=6" } */ +void bar (int); + +void +foo () +{ + bar (1); +} + +/* { dg-final { scan-assembler "\t(j|jal)\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/compact-branches-6.c b/gcc/testsuite/gcc.target/mips/compact-branches-6.c new file mode 100644 index 00000000000..dd35a5581bd --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/compact-branches-6.c @@ -0,0 +1,10 @@ +/* { dg-options "-mno-abicalls -mcompact-branches=optimal isa_rev>=6" } */ +void bar (int); + +void +foo () +{ + bar (1); +} + +/* { dg-final { scan-assembler "\t(bc|balc)\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/compact-branches-7.c b/gcc/testsuite/gcc.target/mips/compact-branches-7.c new file mode 100644 index 00000000000..36700c9a2ce --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/compact-branches-7.c @@ -0,0 +1,12 @@ +/* { dg-options "-mhard-float -mcompact-branches=always isa_rev>=6 -mno-micromips" } */ +int bar; + +void +foo (float a, volatile int * b) +{ + if (a < 0.1) + bar = *b; +} + +/* { dg-final { scan-assembler "\t(bc1eqz|bc1nez)\t" } } */ +/* { dg-final { scan-assembler "\tnop" } } */ diff --git a/gcc/testsuite/gcc.target/mips/inline-memcpy-1.c b/gcc/testsuite/gcc.target/mips/inline-memcpy-1.c new file mode 100644 index 00000000000..5a254b1eaa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inline-memcpy-1.c @@ -0,0 +1,16 @@ +/* { dg-options "-fno-common isa_rev>=6" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-Os" } { "" } } */ +/* { dg-final { scan-assembler-not "\tmemcpy" } } */ + +/* Test that memcpy is inline for target hardware + without swl, swr. */ + +#include <string.h> + +char c[40] __attribute__ ((aligned(8))); + +void +f1 () +{ + memcpy (c, "1234567890QWERTYUIOPASDFGHJKLZXCVBNM", 32); +} diff --git a/gcc/testsuite/gcc.target/mips/inline-memcpy-2.c b/gcc/testsuite/gcc.target/mips/inline-memcpy-2.c new file mode 100644 index 00000000000..e144e61a800 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inline-memcpy-2.c @@ -0,0 +1,17 @@ +/* { dg-options "-fno-common isa_rev>=6" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-Os"} { "" } } */ +/* { dg-final { scan-assembler-not "\tmemcpy" } } */ +/* { dg-final { scan-assembler-times "\tsh\t" 16 } } */ + +/* Test that inline memcpy is expanded for target hardware without + swl, swr when alignment is halfword and sufficent shs are produced. */ + +#include <string.h> + +char c[40] __attribute__ ((aligned(2))); + +void +f1 () +{ + memcpy (c, "1234567890QWERTYUIOPASDFGHJKLZXCVBNM", 32); +} diff --git a/gcc/testsuite/gcc.target/mips/inline-memcpy-3.c b/gcc/testsuite/gcc.target/mips/inline-memcpy-3.c new file mode 100644 index 00000000000..96a0387fce5 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inline-memcpy-3.c @@ -0,0 +1,18 @@ +/* { dg-options "-fno-common isa_rev<=5" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-Os"} { "" } } */ +/* { dg-final { scan-assembler-not "\tmemcpy" } } */ +/* { dg-final { scan-assembler-times "swl" 8 } } */ +/* { dg-final { scan-assembler-times "swr" 8 } } */ + +/* Test that inline memcpy for hardware with swl, swr handles subword + alignment and produces enough swl/swrs for mips32. */ + +#include <string.h> + +char c[40] __attribute__ ((aligned(2))); + +void +f1 () +{ + memcpy (c, "1234567890QWERTYUIOPASDFGHJKLZXCVBNM", 32); +} diff --git a/gcc/testsuite/gcc.target/mips/inline-memcpy-4.c b/gcc/testsuite/gcc.target/mips/inline-memcpy-4.c new file mode 100644 index 00000000000..0e7a22e8a33 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inline-memcpy-4.c @@ -0,0 +1,18 @@ +/* { dg-options "-fno-common isa_rev<=5 -mabi=64" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-Os"} { "" } } */ +/* { dg-final { scan-assembler-not "\tmemcpy" } } */ +/* { dg-final { scan-assembler-times "sdl" 4 } } */ +/* { dg-final { scan-assembler-times "sdr" 4 } } */ + +/* Test that inline memcpy for hardware with sdl, sdr handles subword + alignment and produces enough sdl/sdrs on n64. */ + +#include <string.h> + +char c[40] __attribute__ ((aligned(2))); + +void +f1 () +{ + memcpy (c, "1234567890QWERTYUIOPASDFGHJKLZXCVBNM", 32); +} diff --git a/gcc/testsuite/gcc.target/mips/inline-memcpy-5.c b/gcc/testsuite/gcc.target/mips/inline-memcpy-5.c new file mode 100644 index 00000000000..1b9fa16b2a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/inline-memcpy-5.c @@ -0,0 +1,18 @@ +/* { dg-options "-fno-common isa_rev<=5 -mabi=n32" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-Os"} { "" } } */ +/* { dg-final { scan-assembler-not "\tmemcpy" } } */ +/* { dg-final { scan-assembler-times "sdl" 4 } } */ +/* { dg-final { scan-assembler-times "sdr" 4 } } */ + +/* Test that inline memcpy for hardware with sdl, sdr handles subword + alignment and produces enough sdr/sdls on n32. */ + +#include <string.h> + +char c[40] __attribute__ ((aligned(2))); + +void +f1 () +{ + memcpy (c, "1234567890QWERTYUIOPASDFGHJKLZXCVBNM", 32); +} diff --git a/gcc/testsuite/gcc.target/mips/lazy-binding-1.c b/gcc/testsuite/gcc.target/mips/lazy-binding-1.c index a30594840dd..a112781a99e 100644 --- a/gcc/testsuite/gcc.target/mips/lazy-binding-1.c +++ b/gcc/testsuite/gcc.target/mips/lazy-binding-1.c @@ -19,6 +19,6 @@ foo (int n) /* There should be exactly five uses of $25: one to set up $gp, two to load the address of bar (), and two to call it. */ /* { dg-final { scan-assembler-times "\tl.\t\\\$25,%call16\\\(bar\\\)" 2 } } */ -/* { dg-final { scan-assembler-times "\tjalrs?\t\\\$25" 2 } } */ +/* { dg-final { scan-assembler-times "\tjalrc?s?\t\\\$25" 2 } } */ /* { dg-final { scan-assembler "(\\\$28,|\t.cpload\t)\\\$25" } } */ /* { dg-final { scan-assembler-times "\\\$25" 5 } } */ diff --git a/gcc/testsuite/gcc.target/mips/madd-8.c b/gcc/testsuite/gcc.target/mips/madd-8.c index 794a6ff1727..56c194788a1 100644 --- a/gcc/testsuite/gcc.target/mips/madd-8.c +++ b/gcc/testsuite/gcc.target/mips/madd-8.c @@ -11,6 +11,6 @@ f2 (int x, int y, int z) asm volatile ("" ::: "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25", - "$31"); + "$31", "lo"); return x * y + z; } diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index 55e4223d7fd..42e7fff0de5 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -243,6 +243,7 @@ set mips_option_groups { mips16 "-mips16|-mno-mips16|-mflip-mips16" mips3d "-mips3d|-mno-mips3d" pic "-f(no-|)(pic|PIC)" + cb "-mcompact-branches=.*" profiling "-pg" small-data "-G[0-9]+" warnings "-w" @@ -1068,8 +1069,10 @@ proc mips-dg-options { args } { # We need a revision 6 or better ISA for: # # - When the LSA instruction is required + # - When only using compact branches if { $isa_rev < 6 - && ([mips_have_test_option_p options "HAS_LSA"]) } { + && ([mips_have_test_option_p options "HAS_LSA"] + || [mips_have_test_option_p options "-mcompact-branches=always"]) } { if { $gp_size == 32 } { mips_make_test_option options "-mips32r6" } else { @@ -1164,6 +1167,9 @@ proc mips-dg-options { args } { mips_make_test_option options "-mips64r5" } mips_make_test_option options "-mnan=2008" + if { [mips_have_option_p options "-mcompact-branches=always"] } { + mips_make_test_option options "-mcompact-branches=optimal" + } # Check whether we need to switch from a 32-bit processor to the # "nearest" 64-bit processor. } elseif { $gp_size == 64 && [mips_32bit_arch_p $arch] } { @@ -1308,6 +1314,11 @@ proc mips-dg-options { args } { mips_make_test_option options "-mno-micromips" mips_make_test_option options "-mnan=legacy" } + if { $isa_rev < 6 } { + if { [mips_have_option_p options "-mcompact-branches=always"] } { + mips_make_test_option options "-mcompact-branches=optimal" + } + } if { $isa_rev > 5 } { mips_make_test_option options "-mno-dsp" mips_make_test_option options "-mno-mips16" diff --git a/gcc/testsuite/gcc.target/mips/msub-8.c b/gcc/testsuite/gcc.target/mips/msub-8.c index a66307f1041..b0f1523cf31 100644 --- a/gcc/testsuite/gcc.target/mips/msub-8.c +++ b/gcc/testsuite/gcc.target/mips/msub-8.c @@ -11,6 +11,6 @@ f2 (int x, int y, int z) asm volatile ("" ::: "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25", - "$31"); + "$31", "lo"); return x - y * z; } diff --git a/gcc/testsuite/gcc.target/mips/near-far-1.c b/gcc/testsuite/gcc.target/mips/near-far-1.c index 8806e930fc3..b746cf6030c 100644 --- a/gcc/testsuite/gcc.target/mips/near-far-1.c +++ b/gcc/testsuite/gcc.target/mips/near-far-1.c @@ -16,5 +16,5 @@ int test () /* { dg-final { scan-assembler-not "\tjal\tlong_call_func\n" } } */ /* { dg-final { scan-assembler-not "\tjal\tfar_func\n" } } */ -/* { dg-final { scan-assembler "\tjal(|s)\tnear_func\n" } } */ +/* { dg-final { scan-assembler "\t(jal(|s)|balc)\tnear_func\n" } } */ /* { dg-final { scan-assembler-not "\tjal\tnormal_func\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/near-far-2.c b/gcc/testsuite/gcc.target/mips/near-far-2.c index b4062a744cf..2c140e2ceb2 100644 --- a/gcc/testsuite/gcc.target/mips/near-far-2.c +++ b/gcc/testsuite/gcc.target/mips/near-far-2.c @@ -16,5 +16,5 @@ int test () /* { dg-final { scan-assembler-not "\tjal(|s)\tlong_call_func\n" } } */ /* { dg-final { scan-assembler-not "\tjal(|s)\tfar_func\n" } } */ -/* { dg-final { scan-assembler "\tjal(|s)\tnear_func\n" } } */ -/* { dg-final { scan-assembler "\tjal(|s)\tnormal_func\n" } } */ +/* { dg-final { scan-assembler "\t(jal(|s)|balc)\tnear_func\n" } } */ +/* { dg-final { scan-assembler "\t(jal(|s)|balc)\tnormal_func\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/near-far-3.c b/gcc/testsuite/gcc.target/mips/near-far-3.c index e6af939e081..7bf3e14bc80 100644 --- a/gcc/testsuite/gcc.target/mips/near-far-3.c +++ b/gcc/testsuite/gcc.target/mips/near-far-3.c @@ -13,5 +13,5 @@ NOMIPS16 int test4 () { return normal_func (); } /* { dg-final { scan-assembler-not "\tj\tlong_call_func\n" } } */ /* { dg-final { scan-assembler-not "\tj\tfar_func\n" } } */ -/* { dg-final { scan-assembler "\tj(|al|als)\tnear_func\n" } } */ +/* { dg-final { scan-assembler "\t(j(|al|als)|b(|al)c)\tnear_func\n" } } */ /* { dg-final { scan-assembler-not "\tj\tnormal_func\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/near-far-4.c b/gcc/testsuite/gcc.target/mips/near-far-4.c index 969f68f3811..cd12a1dbcbb 100644 --- a/gcc/testsuite/gcc.target/mips/near-far-4.c +++ b/gcc/testsuite/gcc.target/mips/near-far-4.c @@ -13,5 +13,5 @@ NOMIPS16 int test4 () { return normal_func (); } /* { dg-final { scan-assembler-not "\tj\tlong_call_func\n" } } */ /* { dg-final { scan-assembler-not "\tj\tfar_func\n" } } */ -/* { dg-final { scan-assembler "\tj(|al|als)\tnear_func\n" } } */ -/* { dg-final { scan-assembler "\tj(|al|als)\tnormal_func\n" } } */ +/* { dg-final { scan-assembler "\t(j(|al|als)|b(|al)c)\tnear_func\n" } } */ +/* { dg-final { scan-assembler "\t(j(|al|als)|b(|al)c)\tnormal_func\n" } } */ diff --git a/gcc/testsuite/gcc.target/mips/umips-branch-3.c b/gcc/testsuite/gcc.target/mips/umips-branch-3.c index 8717362e044..74465c9f808 100644 --- a/gcc/testsuite/gcc.target/mips/umips-branch-3.c +++ b/gcc/testsuite/gcc.target/mips/umips-branch-3.c @@ -1,4 +1,4 @@ -/* { dg-options "(-mmicromips)" } */ +/* { dg-options "(-mmicromips) -mcompact-branches=optimal" } */ /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ void MICROMIPS diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-35.c b/gcc/testsuite/gcc.target/powerpc/altivec-35.c index 6217c9f966b..46e8eed7fea 100644 --- a/gcc/testsuite/gcc.target/powerpc/altivec-35.c +++ b/gcc/testsuite/gcc.target/powerpc/altivec-35.c @@ -7,10 +7,19 @@ /* Test Altivec built-ins added for version 1.1 of ELFv2 ABI. */ vector signed int vsia, vsib; +vector signed short vssa, vssb, vssc; +vector unsigned short vusa, vusb, vusc; -void foo (vector signed int *vsir) +void foo (vector signed int *vsir, + vector signed short *vssr, + vector unsigned short *vusr) { *vsir++ = vec_addc (vsia, vsib); + *vssr++ = vec_madd (vssa, vssb, vssc); + *vssr++ = vec_madd (vssa, vusb, vusc); + *vssr++ = vec_madd (vusa, vssb, vssc); + *vusr++ = vec_madd (vusa, vusb, vusc); } /* { dg-final { scan-assembler-times "vaddcuw" 1 } } */ +/* { dg-final { scan-assembler-times "vmladduhm" 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c index 4554099b6a7..bb5e182832e 100644 --- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c +++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c @@ -8,7 +8,9 @@ vector unsigned char vuca, vucb, vucc; vector bool char vbca, vbcb; +vector unsigned short vusa, vusb; vector bool short vbsa, vbsb; +vector unsigned int vuia, vuib; vector bool int vbia, vbib; vector signed long long vsla, vslb; vector unsigned long long vula, vulb, vulc; @@ -19,7 +21,9 @@ vector double vda, vdb; void foo (vector unsigned char *vucr, vector bool char *vbcr, + vector unsigned short *vusr, vector bool short *vbsr, + vector unsigned int *vuir, vector bool int *vbir, vector unsigned long long *vulr, vector bool long long *vblr, @@ -48,6 +52,12 @@ void foo (vector unsigned char *vucr, *vblr++ = vec_orc (vbla, vblb); *vbsr++ = vec_orc (vbsa, vbsb); *vblr++ = vec_perm (vbla, vblb, vucc); + *vusr++ = vec_pmsum_be (vuca, vucb); + *vuir++ = vec_pmsum_be (vusa, vusb); + *vulr++ = vec_pmsum_be (vuia, vuib); + *vuxr++ = vec_pmsum_be (vula, vulb); + *vuir++ = vec_shasigma_be (vuia, 0, 1); + *vulr++ = vec_shasigma_be (vula, 0, 1); } /* { dg-final { scan-assembler-times "vaddcuq" 2 } } */ @@ -59,4 +69,10 @@ void foo (vector unsigned char *vucr, /* { dg-final { scan-assembler-times "xxlnand" 4 } } */ /* { dg-final { scan-assembler-times "xxlorc" 4 } } */ /* { dg-final { scan-assembler-times "vperm" 1 } } */ +/* { dg-final { scan-assembler-times "vpmsumb" 1 } } */ +/* { dg-final { scan-assembler-times "vpmsumh" 1 } } */ +/* { dg-final { scan-assembler-times "vpmsumw" 1 } } */ +/* { dg-final { scan-assembler-times "vpmsumd" 1 } } */ +/* { dg-final { scan-assembler-times "vshasigmaw" 1 } } */ +/* { dg-final { scan-assembler-times "vshasigmad" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-19.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-19.c new file mode 100644 index 00000000000..6dffbb9b892 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-19.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-O2 -ftree-vectorize -mcpu=power8 -ffast-math -fvect-cost-model=unlimited" } */ + +/* This tests special handling for various uses of xxpermdi, other than + to perform doubleword swaps. */ + +void foo (_Complex double *self, _Complex double *a, _Complex double *b, + int a1, int a2) +{ + int i, j; + for (i = 0; i < a1; ++i) + for (j = 0; j < a2; ++j) + self[i] = self[i] + a[i,j] * b[j]; +} + +/* { dg-final { scan-assembler-times "xxpermdi .*,.*,.*,0" 1 } } */ +/* { dg-final { scan-assembler-times "xxpermdi .*,.*,.*,1" 1 } } */ +/* { dg-final { scan-assembler-times "xxpermdi .*,.*,.*,2" 1 } } */ +/* { dg-final { scan-assembler-times "xxpermdi .*,.*,.*,3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-shr.c b/gcc/testsuite/gcc.target/powerpc/vec-shr.c new file mode 100644 index 00000000000..31a27c8832d --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-shr.c @@ -0,0 +1,34 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -fno-inline" } */ + +#include <stdlib.h> + +typedef struct { double r, i; } complex; +#define LEN 30 +complex c[LEN]; +double d[LEN]; + +void +foo (complex *c, double *d, int len1) +{ + int i; + for (i = 0; i < len1; i++) + { + c[i].r = d[i]; + c[i].i = 0.0; + } +} + +int +main (void) +{ + int i; + for (i = 0; i < LEN; i++) + d[i] = (double) i; + foo (c, d, LEN); + for (i=0;i<LEN;i++) + if ((c[i].r != (double) i) || (c[i].i != 0.0)) + abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/s390/20150826-1.c b/gcc/testsuite/gcc.target/s390/20150826-1.c new file mode 100644 index 00000000000..1567ced42e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/20150826-1.c @@ -0,0 +1,12 @@ +/* Check that emitting a dynamic stack check for sizes below the + current frame size work. */ + +/* { dg-do compile } */ +/* { dg-options "-O3 -mstack-size=32" } */ + +extern int bar(char *); +int foo(void) +{ + char b[100]; + return bar(b); +} /* { dg-warning "An unconditional trap is added" } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-load_bndry-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec-load_bndry-1.c new file mode 100644 index 00000000000..9ebf6c7064f --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/vec-load_bndry-1.c @@ -0,0 +1,80 @@ +/* { dg-do compile { target { s390*-*-* } } } */ +/* { dg-options "-O0 -mzarch -march=z13 -mzvector" } */ + +#include <vecintrin.h> + +signed char +foo64 (signed char *p) +{ + return vec_load_bndry (p, 64)[0]; + /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),0" 1 } } */ +} + +signed char +foo128 (signed char *p) +{ + return + vec_load_bndry (p, 128)[0] + + vec_load_bndry (p + 16, 128)[0]; + /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),1" 2 } } */ +} + +signed char +foo256 (signed char *p) +{ + return + vec_load_bndry (p, 256)[0] + + vec_load_bndry (p + 16, 256)[0] + + vec_load_bndry (p + 32, 256)[0]; + /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),2" 3 } } */ +} + +signed char +foo512 (signed char *p) +{ + return + vec_load_bndry (p, 512)[0] + + vec_load_bndry (p + 16, 512)[0] + + vec_load_bndry (p + 32, 512)[0] + + vec_load_bndry (p + 48, 512)[0]; + /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),3" 4 } } */ +} + +signed char +foo1024 (signed char *p) +{ + return + vec_load_bndry (p, 1024)[0] + + vec_load_bndry (p + 16, 1024)[0] + + vec_load_bndry (p + 32, 1024)[0] + + vec_load_bndry (p + 48, 1024)[0] + + vec_load_bndry (p + 64, 1024)[0]; + /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),4" 5 } } */ +} + +signed char +foo2048 (signed char *p) +{ + return + vec_load_bndry (p, 2048)[0] + + vec_load_bndry (p + 16, 2048)[0] + + vec_load_bndry (p + 32, 2048)[0] + + vec_load_bndry (p + 48, 2048)[0] + + vec_load_bndry (p + 64, 2048)[0] + + vec_load_bndry (p + 80, 2048)[0]; + /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),5" 6 } } */ +} + +signed char +foo4096 (signed char *p) +{ + return + vec_load_bndry (p, 4096)[0] + + vec_load_bndry (p + 16, 4096)[0] + + vec_load_bndry (p + 32, 4096)[0] + + vec_load_bndry (p + 48, 4096)[0] + + vec_load_bndry (p + 64, 4096)[0] + + vec_load_bndry (p + 80, 4096)[0] + + vec_load_bndry (p + 96, 4096)[0]; + /* { dg-final { scan-assembler-times "\tvlbb\t%v..?,0\\(%r..?\\),6" 7 } } */ +} |