2014-03-25 Basile Starynkevitch <basile@starynkevitch.net>

	{{merge using svnmerge.py with trunk GCC 4.9 svn
	rev.208803. Updated gcc/melt-runtime.cc...}}


[gcc/]
2014-03-25  Basile Starynkevitch  <basile@starynkevitch.net>

	{{merged with trunk, and....}}
	* melt-runtime.cc (melt_load_module_index): Accept very short versionmelt strings.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@208808 138bc75d-0d04-0410-961f-82ee72b054a4

3 files changed, 91 insertions, 4 deletions

diff --git a/gcc/testsuite/gcc.target/aarch64/ushr64_1.c b/gcc/testsuite/gcc.target/aarch64/ushr64_1.c
new file mode 100644
index 00000000000..b1c741dac31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ushr64_1.c
@@ -0,0 +1,84 @@
+/* Test logical SIMD shift works correctly.  */
+/* { dg-do run } */
+/* { dg-options "--save-temps" } */
+
+#include "arm_neon.h"
+
+extern void abort (void);
+
+int __attribute__ ((noinline))
+test_vshr_n_u64_64 (uint64x1_t passed, uint64_t expected)
+{
+  return vget_lane_u64 (vshr_n_u64 (passed, 64), 0) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshr_n_u64_4 (uint64x1_t passed, uint64_t expected)
+{
+  return vget_lane_u64 (vshr_n_u64 (passed, 4), 0) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshr_n_u64_0 (uint64x1_t passed, uint64_t expected)
+{
+  return vget_lane_u64 (vshr_n_u64 (passed, 0), 0) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshrd_n_u64_64 (uint64_t passed, uint64_t expected)
+{
+  return vshrd_n_u64 (passed, 64) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshrd_n_u64_4 (uint64_t passed, uint64_t expected)
+{
+  return vshrd_n_u64 (passed, 4) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshrd_n_u64_0 (uint64_t passed, uint64_t expected)
+{
+  return vshrd_n_u64 (passed, 0) != expected;
+}
+
+/* { dg-final { scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 64" 2 } } */
+/* { dg-final { (scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 4" 2)  || \
+   (scan-assembler-times "lsr\\tx\[0-9\]+, x\[0-9\]+, 4" 2) } } */
+/* { dg-final { scan-assembler-not "ushr\\td\[0-9\]+, d\[0-9\]+, 0" } } */
+
+int
+main (int argc, char *argv[])
+{
+  /* Testing vshr_n_u64.  */
+  if (test_vshr_n_u64_64 (vcreate_u64 (0x0000000080000000), 0))
+    abort ();
+  if (test_vshr_n_u64_64 (vcreate_u64 (0xffffffff80000000), 0))
+    abort ();
+
+  if (test_vshr_n_u64_4 (vcreate_u64 (0x0000000080000000), 0x0000000008000000))
+    abort ();
+  if (test_vshr_n_u64_4 (vcreate_u64 (0xffffffff80000000), 0x0ffffffff8000000))
+    abort ();
+
+  if (test_vshr_n_u64_0 (vcreate_u64 (0x0000000080000000), 0x0000000080000000))
+    abort ();
+
+  /* Testing vshrd_n_u64.  */
+  if (test_vshrd_n_u64_64 (0x0000000080000000, 0))
+    abort ();
+  if (test_vshrd_n_u64_64 (0xffffffff80000000, 0))
+    abort ();
+
+  if (test_vshrd_n_u64_4 (0x0000000080000000, 0x0000000008000000))
+    abort ();
+  if (test_vshrd_n_u64_4 (0xffffffff80000000, 0x0ffffffff8000000))
+    abort ();
+
+  if (test_vshrd_n_u64_0 (0x0000000080000000, 0x0000000080000000))
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/vect-abs.c b/gcc/testsuite/gcc.target/aarch64/vect-abs.c
index 954b10615a3..9e0ed99ca6a 100644
--- a/gcc/testsuite/gcc.target/aarch64/vect-abs.c
+++ b/gcc/testsuite/gcc.target/aarch64/vect-abs.c
@@ -1,6 +1,6 @@
 
 /* { dg-do run } */
-/* { dg-options "-O3" } */
+/* { dg-options "-O3 -std=c99" } */
 
 #include "limits.h"
 
@@ -37,8 +37,9 @@ extern void abort (void);
 SET_RVEC (8, SCHAR)
 SET_RVEC (16, SHRT)
 SET_RVEC (32, INT)
-SET_RVEC (64, LONG_LONG)
+SET_RVEC (64, LLONG)
 
+void
 set_rvector_long (pRLONG a)
 {
   int i;
@@ -49,8 +50,9 @@ set_rvector_long (pRLONG a)
 SET_VEC (8, SCHAR)
 SET_VEC (16, SHRT)
 SET_VEC (32, INT)
-SET_VEC (64, LONG_LONG)
+SET_VEC (64, LLONG)
 
+void
 set_vector_long (long *__restrict__ a)
 {
   long i;
@@ -63,6 +65,7 @@ CHECK_VEC (16)
 CHECK_VEC (32)
 CHECK_VEC (64)
 
+void
 check_vector_long (long *__restrict__ a, long *__restrict__ b)
 {
   long i;
diff --git a/gcc/testsuite/gcc.target/arm/neon-modes-3.c b/gcc/testsuite/gcc.target/arm/neon-modes-3.c
index fe8187570b5..f3e4f335ee3 100644
--- a/gcc/testsuite/gcc.target/arm/neon-modes-3.c
+++ b/gcc/testsuite/gcc.target/arm/neon-modes-3.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-O" } */
+/* { dg-options "-O -g" } */
 /* { dg-add-options arm_neon } */
 
 #include <arm_neon.h>