2009-02-23 Basile Starynkevitch <basile@starynkevitch.net>

	MELT branch merged with trunk r144379



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@144380 138bc75d-0d04-0410-961f-82ee72b054a4

9 files changed, 98 insertions, 32 deletions

diff --git a/gcc/testsuite/gcc.target/arm/va_list.c b/gcc/testsuite/gcc.target/arm/va_list.c
new file mode 100644
index 00000000000..b988a0d3365
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/va_list.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_eabi } */
+
+#include <stdarg.h>
+#include <stddef.h>
+
+/* AAPCS \S 7.1.4 requires that va_list match the structure shown
+   here */
+typedef struct my_va_list 
+{
+  void *ap;
+} my_va_list;
+
+int 
+main () {
+  if (sizeof (va_list) != sizeof (my_va_list))
+    return 1;
+  /* This check confirms both that "va_list" has a member named "__ap"
+     and that it is located at the correct position.  */
+  if (offsetof (va_list, __ap) 
+      != offsetof (my_va_list, ap))
+    return 2;
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/i386/abi-1.c b/gcc/testsuite/gcc.target/i386/abi-1.c
index 032274c46fd..62b80ef4062 100644
--- a/gcc/testsuite/gcc.target/i386/abi-1.c
+++ b/gcc/testsuite/gcc.target/i386/abi-1.c
@@ -5,4 +5,4 @@
 typedef double v2df __attribute__((vector_size (16)));
 v2df foo (void) { return (v2df){ 1.0, 2.0 }; }
 
-/* { dg-final { scan-assembler "xmm0" } } */
+/* { dg-final { scan-assembler-times "xmm0" 1 } } */
diff --git a/gcc/testsuite/gcc.target/i386/abi-2.c b/gcc/testsuite/gcc.target/i386/abi-2.c
new file mode 100644
index 00000000000..5ed6b4a56dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/abi-2.c
@@ -0,0 +1,8 @@
+/* Make certain that we pass __m256i in the correct register for AVX.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -mavx" } */
+
+typedef long long __m256i __attribute__ ((__vector_size__ (32)));
+__m256i foo (void) { return (__m256i){ 1, 2, 3, 4 }; }
+
+/* { dg-final { scan-assembler-times "ymm0" 1 } } */
diff --git a/gcc/testsuite/gcc.target/i386/amd64-abi-3.c b/gcc/testsuite/gcc.target/i386/amd64-abi-3.c
index 3841e6dabee..8db7f13b1ea 100644
--- a/gcc/testsuite/gcc.target/i386/amd64-abi-3.c
+++ b/gcc/testsuite/gcc.target/i386/amd64-abi-3.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -mno-sse" } */
+/* { dg-options "-O2 -fomit-frame-pointer -mno-sse" } */
 /* { dg-final { scan-assembler "subq\[\\t \]*\\\$88,\[\\t \]*%rsp" } } */
 /* { dg-final { scan-assembler-not "subq\[\\t \]*\\\$216,\[\\t \]*%rsp" } } */
 
diff --git a/gcc/testsuite/gcc.target/i386/i386.exp b/gcc/testsuite/gcc.target/i386/i386.exp
index fa470e11a66..f70c81f33fb 100644
--- a/gcc/testsuite/gcc.target/i386/i386.exp
+++ b/gcc/testsuite/gcc.target/i386/i386.exp
@@ -1,4 +1,4 @@
-# Copyright (C) 1997, 2004, 2007 Free Software Foundation, Inc.
+# Copyright (C) 1997, 2004, 2007, 2008, 2009 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
diff --git a/gcc/testsuite/gcc.target/mips/branch-1.c b/gcc/testsuite/gcc.target/mips/branch-1.c
index fb715362e08..b70b2640f8c 100644
--- a/gcc/testsuite/gcc.target/mips/branch-1.c
+++ b/gcc/testsuite/gcc.target/mips/branch-1.c
@@ -1,6 +1,8 @@
-/* We should implement these "if" statements using an "andi" instruction
-   followed by a branch on zero.  */
-/* { dg-options "-O2" } */
+/* Octeon targets should use "bbit" instructions for these "if" statements,
+   but we test for "bbit" elsewhere.  On other targets, we should implement
+   the "if" statements using an "andi" instruction followed by a branch
+   on zero.  */
+/* { dg-options "-O2 isa=!octeon" } */
 
 void bar (void);
 NOMIPS16 void f1 (int x) { if (x & 4) bar (); }
diff --git a/gcc/testsuite/gcc.target/mips/dmult-1.c b/gcc/testsuite/gcc.target/mips/dmult-1.c
index 61e66c20ffc..6d4120435b7 100644
--- a/gcc/testsuite/gcc.target/mips/dmult-1.c
+++ b/gcc/testsuite/gcc.target/mips/dmult-1.c
@@ -1,4 +1,4 @@
-/* { dg-options "-mips64 -mgp64" } */
+/* { dg-options "isa=64!octeon -mgp64" } */
 /* { dg-final { scan-assembler "\tdmult\t" } } */
 /* { dg-final { scan-assembler "\tmflo\t" } } */
 /* { dg-final { scan-assembler-not "\tdmul\t" } } */
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp
index c5d6089a964..7befff5a1fa 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -1,4 +1,4 @@
-#   Copyright (C) 1997, 2007, 2008 Free Software Foundation, Inc.
+# Copyright (C) 1997, 2007, 2008, 2009 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -135,10 +135,18 @@
 #	the value of the __mips_isa_rev macro, or 0 if it isn't defined.
 #
 # For example, "isa_rev>=1" selects a MIPS32 or MIPS64 processor,
-# "isa=4" selects a MIPS IV processor, and so on.  There are also
-# the following special pseudo-options:
+# "isa=4" selects a MIPS IV processor, and so on.
 #
-#   isa=loongson:
+# If certain processor-specific extensions are not applicable to the
+# test you can list them as !CPU in the isa or isa_rev options.  For
+# example, isa=64!octeon enforces MIPS64 while avoiding octeon.  You
+# can also use ! without an ISA value.  For example
+# isa=!octeon!loongson2e disables octeon and loongson2e if otherwise
+# you would compile for one of them.
+#
+# There are also the following special pseudo-options:
+#
+#   isa=loongson
 #	select a Loongson processor
 #
 #   addressing=absolute
@@ -173,6 +181,9 @@
 #	options.  For example, if the feature is present on revision 2
 #	processors and above, try to use "isa_rev>=2" instead of
 #	"-mips32r2" or "-mips64r2".
+#
+#   (6) If you need to disable processor-specific extensions use
+#	isa=!CPU instead of forcing a generic ISA.
 
 # Exit immediately if this isn't a MIPS target.
 if ![istarget mips*-*-*] {
@@ -825,29 +836,49 @@ proc mips-dg-options { args } {
 		set arch "-march=loongson2f"
 	    }
 	} else {
-	    if { ![regexp {^(isa(?:|_rev))(=|<=|>=)([0-9]+)$} $spec \
-		       dummy prop relation value] } {
-		error "Unrecognized isa specification: $isa_spec"
+	    # With ! and = the ISA value is optional.
+	    if { ![regexp {^(isa(?:|_rev))(=|<=|>=)([0-9]*)((?:![^!]+)*)$} \
+		       $spec dummy prop relation value nocpus]
+		 || ($value eq ""
+		     && ($relation ne "="
+			 || $nocpus eq ""))} {
+		error "Unrecognized isa specification: $spec"
 	    }
-	    set current [mips_arch_info $arch $prop]
-	    if { ($current < $value && ![string equal $relation "<="])
-		 || ($current > $value && ![string equal $relation ">="])
-		 || ([mips_have_test_option_p options "-mgp64"]
-		     && [mips_32bit_arch_p $arch]) } {
-		# The current setting is out of range; it cannot
-		# possibly be used.  Find a replacement that can.
-		if { [string equal $prop "isa"] } {
-		    set arch "-mips$value"
-		} elseif { $value == 0 } {
-		    set arch "-mips4"
-		} else {
-		    if { [mips_have_option_p options "-mgp32"] } {
-			set arch "-mips32"
+	    if { $value ne "" } {
+		set current [mips_arch_info $arch $prop]
+		if { ($current < $value && ![string equal $relation "<="])
+		     || ($current > $value && ![string equal $relation ">="])
+		     || ([mips_have_test_option_p options "-mgp64"]
+			 && [mips_32bit_arch_p $arch]) } {
+		    # The current setting is out of range; it cannot
+		    # possibly be used.  Find a replacement that can.
+		    if { [string equal $prop "isa"] } {
+			set arch "-mips$value"
+		    } elseif { $value == 0 } {
+			set arch "-mips4"
 		    } else {
-			set arch "-mips64"
+			if { [mips_have_option_p options "-mgp32"] } {
+			    set arch "-mips32"
+			} else {
+			    set arch "-mips64"
+			}
+			if { $value > 1 } {
+			    append arch "r$value"
+			}
 		    }
-		    if { $value > 1 } {
-			append arch "r$value"
+		}
+	    }
+	    # If we haven't switched to a generic ISA based on the
+	    # isa* value, do it here if the processor-specific
+	    # extension is not allowed.
+	    if { $nocpus ne ""
+		 && $arch eq [mips_option mips_base_options arch] } {
+		set cpu [regsub -- {-march=} $arch ""]
+		if { [regexp "!$cpu!" "$nocpus!"] } {
+		    set isa_rev [mips_arch_info $arch isa_rev]
+		    set arch "-mips[mips_arch_info $arch isa]"		
+		    if { $isa_rev > 1 } {
+			append arch "r$isa_rev"
 		    }
 		}
 	    }
diff --git a/gcc/testsuite/gcc.target/x86_64/abi/abi-x86_64.exp b/gcc/testsuite/gcc.target/x86_64/abi/abi-x86_64.exp
index 57ffc525879..521bd53ee92 100644
--- a/gcc/testsuite/gcc.target/x86_64/abi/abi-x86_64.exp
+++ b/gcc/testsuite/gcc.target/x86_64/abi/abi-x86_64.exp
@@ -1,4 +1,4 @@
-# Copyright (C) 2005, 2007 Free Software Foundation, Inc.
+# Copyright (C) 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by