diff options
| author | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-02-10 17:45:52 +0000 |
|---|---|---|
| committer | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-02-10 17:45:52 +0000 |
| commit | eb76579392e0d61b9f33c90fdd8b620e563d0a12 (patch) | |
| tree | 4307edacc6d226e528b690b44a329d430fe03a61 /gcc/testsuite/gcc.target | |
| parent | 2d9d01985a7a7866916fafa19c5c296702e69714 (diff) | |
| download | gcc-eb76579392e0d61b9f33c90fdd8b620e563d0a12.tar.gz | |
2016-02-10 Basile Starynkevitch <basile@starynkevitch.net>
{{merging with even more of GCC 6, using subversion 1.9
svn merge -r227401:227700 ^/trunk
}}
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@233282 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/testsuite/gcc.target')
63 files changed, 1493 insertions, 78 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp index ceada839d98..462696315e0 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/advsimd-intrinsics.exp @@ -52,8 +52,12 @@ if {[istarget arm*-*-*]} then { torture-init set-torture-options $C_TORTURE_OPTIONS {{}} $LTO_TORTURE_OPTIONS -# Make sure Neon flags are provided, if necessary. -set additional_flags [add_options_for_arm_neon ""] +# Make sure Neon flags are provided, if necessary. Use fp16 if we can. +if {[check_effective_target_arm_neon_fp16_ok]} then { + set additional_flags [add_options_for_arm_neon_fp16 ""] +} else { + set additional_flags [add_options_for_arm_neon ""] +} # Main loop. gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.c]] \ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h index 4e728d5572c..49fbd843e50 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h @@ -7,6 +7,7 @@ #include <inttypes.h> /* helper type, to help write floating point results in integer form. */ +typedef uint16_t hfloat16_t; typedef uint32_t hfloat32_t; typedef uint64_t hfloat64_t; @@ -132,6 +133,9 @@ static ARRAY(result, uint, 32, 2); static ARRAY(result, uint, 64, 1); static ARRAY(result, poly, 8, 8); static ARRAY(result, poly, 16, 4); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +static ARRAY(result, float, 16, 4); +#endif static ARRAY(result, float, 32, 2); static ARRAY(result, int, 8, 16); static ARRAY(result, int, 16, 8); @@ -143,6 +147,9 @@ static ARRAY(result, uint, 32, 4); static ARRAY(result, uint, 64, 2); static ARRAY(result, poly, 8, 16); static ARRAY(result, poly, 16, 8); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +static ARRAY(result, float, 16, 8); +#endif static ARRAY(result, float, 32, 4); #ifdef __aarch64__ static ARRAY(result, float, 64, 2); @@ -160,6 +167,7 @@ extern ARRAY(expected, uint, 32, 2); extern ARRAY(expected, uint, 64, 1); extern ARRAY(expected, poly, 8, 8); extern ARRAY(expected, poly, 16, 4); +extern ARRAY(expected, hfloat, 16, 4); extern ARRAY(expected, hfloat, 32, 2); extern ARRAY(expected, int, 8, 16); extern ARRAY(expected, int, 16, 8); @@ -171,38 +179,11 @@ extern ARRAY(expected, uint, 32, 4); extern ARRAY(expected, uint, 64, 2); extern ARRAY(expected, poly, 8, 16); extern ARRAY(expected, poly, 16, 8); +extern ARRAY(expected, hfloat, 16, 8); extern ARRAY(expected, hfloat, 32, 4); extern ARRAY(expected, hfloat, 64, 2); -/* Check results. Operates on all possible vector types. */ -#define CHECK_RESULTS(test_name,comment) \ - { \ - CHECK(test_name, int, 8, 8, PRIx8, expected, comment); \ - CHECK(test_name, int, 16, 4, PRIx16, expected, comment); \ - CHECK(test_name, int, 32, 2, PRIx32, expected, comment); \ - CHECK(test_name, int, 64, 1, PRIx64, expected, comment); \ - CHECK(test_name, uint, 8, 8, PRIx8, expected, comment); \ - CHECK(test_name, uint, 16, 4, PRIx16, expected, comment); \ - CHECK(test_name, uint, 32, 2, PRIx32, expected, comment); \ - CHECK(test_name, uint, 64, 1, PRIx64, expected, comment); \ - CHECK(test_name, poly, 8, 8, PRIx8, expected, comment); \ - CHECK(test_name, poly, 16, 4, PRIx16, expected, comment); \ - CHECK_FP(test_name, float, 32, 2, PRIx32, expected, comment); \ - \ - CHECK(test_name, int, 8, 16, PRIx8, expected, comment); \ - CHECK(test_name, int, 16, 8, PRIx16, expected, comment); \ - CHECK(test_name, int, 32, 4, PRIx32, expected, comment); \ - CHECK(test_name, int, 64, 2, PRIx64, expected, comment); \ - CHECK(test_name, uint, 8, 16, PRIx8, expected, comment); \ - CHECK(test_name, uint, 16, 8, PRIx16, expected, comment); \ - CHECK(test_name, uint, 32, 4, PRIx32, expected, comment); \ - CHECK(test_name, uint, 64, 2, PRIx64, expected, comment); \ - CHECK(test_name, poly, 8, 16, PRIx8, expected, comment); \ - CHECK(test_name, poly, 16, 8, PRIx16, expected, comment); \ - CHECK_FP(test_name, float, 32, 4, PRIx32, expected, comment); \ - } \ - -#define CHECK_RESULTS_NAMED(test_name,EXPECTED,comment) \ +#define CHECK_RESULTS_NAMED_NO_FP16(test_name,EXPECTED,comment) \ { \ CHECK(test_name, int, 8, 8, PRIx8, EXPECTED, comment); \ CHECK(test_name, int, 16, 4, PRIx16, EXPECTED, comment); \ @@ -229,6 +210,24 @@ extern ARRAY(expected, hfloat, 64, 2); CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment); \ } \ +/* Check results against EXPECTED. Operates on all possible vector types. */ +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +#define CHECK_RESULTS_NAMED(test_name,EXPECTED,comment) \ + { \ + CHECK_RESULTS_NAMED_NO_FP16(test_name, EXPECTED, comment) \ + CHECK_FP(test_name, float, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK_FP(test_name, float, 16, 8, PRIx16, EXPECTED, comment); \ + } +#else +#define CHECK_RESULTS_NAMED(test_name,EXPECTED,comment) \ + CHECK_RESULTS_NAMED_NO_FP16(test_name, EXPECTED, comment) +#endif + +#define CHECK_RESULTS_NO_FP16(test_name,comment) \ + CHECK_RESULTS_NAMED_NO_FP16(test_name, expected, comment) + +#define CHECK_RESULTS(test_name,comment) \ + CHECK_RESULTS_NAMED(test_name, expected, comment) #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ @@ -380,6 +379,9 @@ static void clean_results (void) CLEAN(result, uint, 64, 1); CLEAN(result, poly, 8, 8); CLEAN(result, poly, 16, 4); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + CLEAN(result, float, 16, 4); +#endif CLEAN(result, float, 32, 2); CLEAN(result, int, 8, 16); @@ -392,6 +394,9 @@ static void clean_results (void) CLEAN(result, uint, 64, 2); CLEAN(result, poly, 8, 16); CLEAN(result, poly, 16, 8); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + CLEAN(result, float, 16, 8); +#endif CLEAN(result, float, 32, 4); #if defined(__aarch64__) @@ -443,21 +448,40 @@ static void clean_results (void) DECL_VARIABLE(VAR, uint, 64, 2) /* Declare all 64 bits variants. */ +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +#define DECL_VARIABLE_64BITS_VARIANTS(VAR) \ + DECL_VARIABLE_64BITS_SIGNED_VARIANTS(VAR); \ + DECL_VARIABLE_64BITS_UNSIGNED_VARIANTS(VAR); \ + DECL_VARIABLE(VAR, poly, 8, 8); \ + DECL_VARIABLE(VAR, poly, 16, 4); \ + DECL_VARIABLE(VAR, float, 16, 4); \ + DECL_VARIABLE(VAR, float, 32, 2) +#else #define DECL_VARIABLE_64BITS_VARIANTS(VAR) \ DECL_VARIABLE_64BITS_SIGNED_VARIANTS(VAR); \ DECL_VARIABLE_64BITS_UNSIGNED_VARIANTS(VAR); \ DECL_VARIABLE(VAR, poly, 8, 8); \ DECL_VARIABLE(VAR, poly, 16, 4); \ DECL_VARIABLE(VAR, float, 32, 2) +#endif /* Declare all 128 bits variants. */ +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) #define DECL_VARIABLE_128BITS_VARIANTS(VAR) \ DECL_VARIABLE_128BITS_SIGNED_VARIANTS(VAR); \ DECL_VARIABLE_128BITS_UNSIGNED_VARIANTS(VAR); \ DECL_VARIABLE(VAR, poly, 8, 16); \ DECL_VARIABLE(VAR, poly, 16, 8); \ + DECL_VARIABLE(VAR, float, 16, 8); \ DECL_VARIABLE(VAR, float, 32, 4) - +#else +#define DECL_VARIABLE_128BITS_VARIANTS(VAR) \ + DECL_VARIABLE_128BITS_SIGNED_VARIANTS(VAR); \ + DECL_VARIABLE_128BITS_UNSIGNED_VARIANTS(VAR); \ + DECL_VARIABLE(VAR, poly, 8, 16); \ + DECL_VARIABLE(VAR, poly, 16, 8); \ + DECL_VARIABLE(VAR, float, 32, 4) +#endif /* Declare all variants. */ #define DECL_VARIABLE_ALL_VARIANTS(VAR) \ DECL_VARIABLE_64BITS_VARIANTS(VAR); \ @@ -476,6 +500,15 @@ static void clean_results (void) /* Helpers to initialize vectors. */ #define VDUP(VAR, Q, T1, T2, W, N, V) \ VECT_VAR(VAR, T1, W, N) = vdup##Q##_n_##T2##W(V) +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +/* Work around that there is no vdup_n_f16 intrinsic. */ +#define vdup_n_f16(VAL) \ + __extension__ \ + ({ \ + float16_t f = VAL; \ + vld1_dup_f16(&f); \ + }) +#endif #define VSET_LANE(VAR, Q, T1, T2, W, N, L, V) \ VECT_VAR(VAR, T1, W, N) = vset##Q##_lane_##T2##W(V, \ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h index 26203cc0a69..c8d43367bef 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h @@ -118,6 +118,10 @@ VECT_VAR_DECL_INIT(buffer, uint, 32, 2); PAD(buffer_pad, uint, 32, 2); VECT_VAR_DECL_INIT(buffer, uint, 64, 1); PAD(buffer_pad, uint, 64, 1); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +VECT_VAR_DECL_INIT(buffer, float, 16, 4); +PAD(buffer_pad, float, 16, 4); +#endif VECT_VAR_DECL_INIT(buffer, float, 32, 2); PAD(buffer_pad, float, 32, 2); VECT_VAR_DECL_INIT(buffer, int, 8, 16); @@ -140,6 +144,10 @@ VECT_VAR_DECL_INIT(buffer, poly, 8, 16); PAD(buffer_pad, poly, 8, 16); VECT_VAR_DECL_INIT(buffer, poly, 16, 8); PAD(buffer_pad, poly, 16, 8); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +VECT_VAR_DECL_INIT(buffer, float, 16, 8); +PAD(buffer_pad, float, 16, 8); +#endif VECT_VAR_DECL_INIT(buffer, float, 32, 4); PAD(buffer_pad, float, 32, 4); #ifdef __aarch64__ @@ -170,6 +178,10 @@ VECT_VAR_DECL_INIT(buffer_dup, poly, 8, 8); VECT_VAR_DECL(buffer_dup_pad, poly, 8, 8); VECT_VAR_DECL_INIT(buffer_dup, poly, 16, 4); VECT_VAR_DECL(buffer_dup_pad, poly, 16, 4); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +VECT_VAR_DECL_INIT4(buffer_dup, float, 16, 4); +VECT_VAR_DECL(buffer_dup_pad, float, 16, 4); +#endif VECT_VAR_DECL_INIT4(buffer_dup, float, 32, 2); VECT_VAR_DECL(buffer_dup_pad, float, 32, 2); @@ -193,5 +205,9 @@ VECT_VAR_DECL_INIT(buffer_dup, poly, 8, 16); VECT_VAR_DECL(buffer_dup_pad, poly, 8, 16); VECT_VAR_DECL_INIT(buffer_dup, poly, 16, 8); VECT_VAR_DECL(buffer_dup_pad, poly, 16, 8); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +VECT_VAR_DECL_INIT(buffer_dup, float, 16, 8); +VECT_VAR_DECL(buffer_dup_pad, float, 16, 8); +#endif VECT_VAR_DECL_INIT(buffer_dup, float, 32, 4); VECT_VAR_DECL(buffer_dup_pad, float, 32, 4); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbsl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbsl.c index bb17f0a9649..c4fdbb45102 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbsl.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vbsl.c @@ -114,7 +114,7 @@ void exec_vbsl (void) TEST_VBSL(uint, , float, f, 32, 2); TEST_VBSL(uint, q, float, f, 32, 4); - CHECK_RESULTS (TEST_MSG, ""); + CHECK_RESULTS_NO_FP16 (TEST_MSG, ""); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcombine.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcombine.c index 295768a0348..5100375e5fe 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcombine.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcombine.c @@ -27,6 +27,8 @@ VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0x66, 0x66, 0x66, 0x66 }; VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000, 0x40533333, 0x40533333 }; +VECT_VAR_DECL(expected,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80, + 0x4080, 0x4080, 0x4080, 0x4080 }; #define TEST_MSG "VCOMBINE" void exec_vcombine (void) @@ -44,6 +46,9 @@ void exec_vcombine (void) /* Initialize input "vector64_a" from "buffer". */ TEST_MACRO_64BITS_VARIANTS_2_5(VLOAD, vector64_a, buffer); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VLOAD(vector64_a, buffer, , float, f, 16, 4); +#endif VLOAD(vector64_a, buffer, , float, f, 32, 2); /* Choose init value arbitrarily. */ @@ -57,6 +62,9 @@ void exec_vcombine (void) VDUP(vector64_b, , uint, u, 64, 1, 0x88); VDUP(vector64_b, , poly, p, 8, 8, 0x55); VDUP(vector64_b, , poly, p, 16, 4, 0x66); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VDUP(vector64_b, , float, f, 16, 4, 2.25); +#endif VDUP(vector64_b, , float, f, 32, 2, 3.3f); clean_results (); @@ -72,6 +80,9 @@ void exec_vcombine (void) TEST_VCOMBINE(uint, u, 64, 1, 2); TEST_VCOMBINE(poly, p, 8, 8, 16); TEST_VCOMBINE(poly, p, 16, 4, 8); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VCOMBINE(float, f, 16, 4, 8); +#endif TEST_VCOMBINE(float, f, 32, 2, 4); CHECK(TEST_MSG, int, 8, 16, PRIx8, expected, ""); @@ -84,6 +95,9 @@ void exec_vcombine (void) CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, ""); CHECK(TEST_MSG, poly, 8, 16, PRIx8, expected, ""); CHECK(TEST_MSG, poly, 16, 8, PRIx16, expected, ""); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected, ""); +#endif CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, ""); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcreate.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcreate.c index b2289d3a628..b8b338ef3c0 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcreate.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcreate.c @@ -16,6 +16,7 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0x123456789abcdef0 }; VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xde, 0xbc, 0x9a, 0x78, 0x56, 0x34, 0x12 }; VECT_VAR_DECL(expected,poly,16,4) [] = { 0xdef0, 0x9abc, 0x5678, 0x1234 }; +VECT_VAR_DECL(expected,hfloat,16,4) [] = { 0xdef0, 0x9abc, 0x5678, 0x1234 }; VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x9abcdef0, 0x12345678 }; #define INSN_NAME vcreate @@ -38,6 +39,9 @@ FNNAME (INSN_NAME) DECL_VAL(val, int, 16, 4); DECL_VAL(val, int, 32, 2); DECL_VAL(val, int, 64, 1); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + DECL_VAL(val, float, 16, 4); +#endif DECL_VAL(val, float, 32, 2); DECL_VAL(val, uint, 8, 8); DECL_VAL(val, uint, 16, 4); @@ -50,6 +54,9 @@ FNNAME (INSN_NAME) DECL_VARIABLE(vector_res, int, 16, 4); DECL_VARIABLE(vector_res, int, 32, 2); DECL_VARIABLE(vector_res, int, 64, 1); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + DECL_VARIABLE(vector_res, float, 16, 4); +#endif DECL_VARIABLE(vector_res, float, 32, 2); DECL_VARIABLE(vector_res, uint, 8, 8); DECL_VARIABLE(vector_res, uint, 16, 4); @@ -65,6 +72,9 @@ FNNAME (INSN_NAME) VECT_VAR(val, int, 16, 4) = 0x123456789abcdef0LL; VECT_VAR(val, int, 32, 2) = 0x123456789abcdef0LL; VECT_VAR(val, int, 64, 1) = 0x123456789abcdef0LL; +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VECT_VAR(val, float, 16, 4) = 0x123456789abcdef0LL; +#endif VECT_VAR(val, float, 32, 2) = 0x123456789abcdef0LL; VECT_VAR(val, uint, 8, 8) = 0x123456789abcdef0ULL; VECT_VAR(val, uint, 16, 4) = 0x123456789abcdef0ULL; @@ -76,6 +86,9 @@ FNNAME (INSN_NAME) TEST_VCREATE(int, s, 8, 8); TEST_VCREATE(int, s, 16, 4); TEST_VCREATE(int, s, 32, 2); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VCREATE(float, f, 16, 4); +#endif TEST_VCREATE(float, f, 32, 2); TEST_VCREATE(int, s, 64, 1); TEST_VCREATE(uint, u, 8, 8); @@ -95,6 +108,9 @@ FNNAME (INSN_NAME) CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, ""); CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, ""); CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, ""); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, ""); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c new file mode 100644 index 00000000000..48e50e18263 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c @@ -0,0 +1,98 @@ +/* { dg-require-effective-target arm_neon_fp16_hw { target { arm*-*-* } } } */ +#include <arm_neon.h> +#include "arm-neon-ref.h" +#include "compute-ref-data.h" +#include <math.h> + +/* Expected results for vcvt. */ +VECT_VAR_DECL (expected,hfloat,32,4) [] = { 0x41800000, 0x41700000, + 0x41600000, 0x41500000 }; +VECT_VAR_DECL (expected,hfloat,16,4) [] = { 0x3e00, 0x4100, 0x4300, 0x4480 }; + +/* Expected results for vcvt_high_f32_f16. */ +VECT_VAR_DECL (expected_high,hfloat,32,4) [] = { 0xc1400000, 0xc1300000, + 0xc1200000, 0xc1100000 }; +/* Expected results for vcvt_high_f16_f32. */ +VECT_VAR_DECL (expected_high,hfloat,16,8) [] = { 0x4000, 0x4000, 0x4000, 0x4000, + 0xcc00, 0xcb80, 0xcb00, 0xca80 }; + +void +exec_vcvt (void) +{ + clean_results (); + +#define TEST_MSG vcvt_f32_f16 + { + VECT_VAR_DECL (buffer_src, float, 16, 4) [] = { 16.0, 15.0, 14.0, 13.0 }; + + DECL_VARIABLE (vector_src, float, 16, 4); + + VLOAD (vector_src, buffer_src, , float, f, 16, 4); + DECL_VARIABLE (vector_res, float, 32, 4) = + vcvt_f32_f16 (VECT_VAR (vector_src, float, 16, 4)); + vst1q_f32 (VECT_VAR (result, float, 32, 4), + VECT_VAR (vector_res, float, 32, 4)); + + CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, ""); + } +#undef TEST_MSG + + clean_results (); + +#define TEST_MSG vcvt_f16_f32 + { + VECT_VAR_DECL (buffer_src, float, 32, 4) [] = { 1.5, 2.5, 3.5, 4.5 }; + DECL_VARIABLE (vector_src, float, 32, 4); + + VLOAD (vector_src, buffer_src, q, float, f, 32, 4); + DECL_VARIABLE (vector_res, float, 16, 4) = + vcvt_f16_f32 (VECT_VAR (vector_src, float, 32, 4)); + vst1_f16 (VECT_VAR (result, float, 16, 4), + VECT_VAR (vector_res, float, 16 ,4)); + + CHECK_FP (TEST_MSG, float, 16, 4, PRIx16, expected, ""); + } +#undef TEST_MSG + +#if defined (__aarch64__) + clean_results (); + +#define TEST_MSG "vcvt_high_f32_f16" + { + DECL_VARIABLE (vector_src, float, 16, 8); + VLOAD (vector_src, buffer, q, float, f, 16, 8); + DECL_VARIABLE (vector_res, float, 32, 4); + VECT_VAR (vector_res, float, 32, 4) = + vcvt_high_f32_f16 (VECT_VAR (vector_src, float, 16, 8)); + vst1q_f32 (VECT_VAR (result, float, 32, 4), + VECT_VAR (vector_res, float, 32, 4)); + CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected_high, ""); + } +#undef TEST_MSG + clean_results (); + +#define TEST_MSG "vcvt_high_f16_f32" + { + DECL_VARIABLE (vector_low, float, 16, 4); + VDUP (vector_low, , float, f, 16, 4, 2.0); + + DECL_VARIABLE (vector_src, float, 32, 4); + VLOAD (vector_src, buffer, q, float, f, 32, 4); + + DECL_VARIABLE (vector_res, float, 16, 8) = + vcvt_high_f16_f32 (VECT_VAR (vector_low, float, 16, 4), + VECT_VAR (vector_src, float, 32, 4)); + vst1q_f16 (VECT_VAR (result, float, 16, 8), + VECT_VAR (vector_res, float, 16, 8)); + + CHECK_FP (TEST_MSG, float, 16, 8, PRIx16, expected_high, ""); + } +#endif +} + +int +main (void) +{ + exec_vcvt (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c index b5132f41ac4..22d45d56c8e 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c @@ -187,13 +187,13 @@ void exec_vdup_vmov (void) switch (i) { case 0: - CHECK_RESULTS_NAMED (TEST_MSG, expected0, ""); + CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected0, ""); break; case 1: - CHECK_RESULTS_NAMED (TEST_MSG, expected1, ""); + CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected1, ""); break; case 2: - CHECK_RESULTS_NAMED (TEST_MSG, expected2, ""); + CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected2, ""); break; default: abort(); @@ -232,13 +232,13 @@ void exec_vdup_vmov (void) switch (i) { case 0: - CHECK_RESULTS_NAMED (TEST_MSG, expected0, ""); + CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected0, ""); break; case 1: - CHECK_RESULTS_NAMED (TEST_MSG, expected1, ""); + CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected1, ""); break; case 2: - CHECK_RESULTS_NAMED (TEST_MSG, expected2, ""); + CHECK_RESULTS_NAMED_NO_FP16 (TEST_MSG, expected2, ""); break; default: abort(); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c index c1ff6dd3007..ef708dcba17 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c @@ -90,7 +90,7 @@ void exec_vdup_lane (void) TEST_VDUP_LANE(q, poly, p, 16, 8, 4, 1); TEST_VDUP_LANE(q, float, f, 32, 4, 2, 1); - CHECK_RESULTS (TEST_MSG, ""); + CHECK_RESULTS_NO_FP16 (TEST_MSG, ""); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vext.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vext.c index 0b014ebda87..98f88a69898 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vext.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vext.c @@ -113,7 +113,7 @@ void exec_vext (void) TEST_VEXT(q, poly, p, 16, 8, 6); TEST_VEXT(q, float, f, 32, 4, 3); - CHECK_RESULTS (TEST_MSG, ""); + CHECK_RESULTS_NO_FP16 (TEST_MSG, ""); } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_high.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_high.c index d7581125edd..9f0a1687f18 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_high.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_high.c @@ -16,6 +16,7 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff1 }; VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff }; VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; +VECT_VAR_DECL(expected,hfloat,16,4) [] = { 0xca00, 0xc980, 0xc900, 0xc880 }; VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 }; #define TEST_MSG "VGET_HIGH" @@ -31,6 +32,9 @@ void exec_vget_high (void) DECL_VARIABLE_128BITS_VARIANTS(vector128); TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vector128, buffer); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VLOAD(vector128, buffer, q, float, f, 16, 8); +#endif VLOAD(vector128, buffer, q, float, f, 32, 4); clean_results (); @@ -46,6 +50,9 @@ void exec_vget_high (void) TEST_VGET_HIGH(uint, u, 64, 1, 2); TEST_VGET_HIGH(poly, p, 8, 8, 16); TEST_VGET_HIGH(poly, p, 16, 4, 8); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VGET_HIGH(float, f, 16, 4, 8); +#endif TEST_VGET_HIGH(float, f, 32, 2, 4); CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_low.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_low.c index 12ecfc21ba0..2b875b9b7b8 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_low.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_low.c @@ -16,6 +16,7 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 }; VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }; VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; +VECT_VAR_DECL(expected,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 }; VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; #define TEST_MSG "VGET_LOW" @@ -31,6 +32,9 @@ void exec_vget_low (void) DECL_VARIABLE_128BITS_VARIANTS(vector128); TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vector128, buffer); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VLOAD(vector128, buffer, q, float, f, 16, 8); +#endif VLOAD(vector128, buffer, q, float, f, 32, 4); clean_results (); @@ -46,6 +50,9 @@ void exec_vget_low (void) TEST_VGET_LOW(uint, u, 64, 1, 2); TEST_VGET_LOW(poly, p, 8, 8, 16); TEST_VGET_LOW(poly, p, 16, 4, 8); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VGET_LOW(float, f, 16, 4, 8); +#endif TEST_VGET_LOW(float, f, 32, 2, 4); CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); @@ -58,6 +65,9 @@ void exec_vget_low (void) CHECK(TEST_MSG, uint, 64, 1, PRIx64, expected, ""); CHECK(TEST_MSG, poly, 8, 8, PRIx8, expected, ""); CHECK(TEST_MSG, poly, 16, 4, PRIx16, expected, ""); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected, ""); +#endif CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, ""); } diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1.c index ced9d736d6d..4ed0e464f9c 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1.c @@ -16,6 +16,7 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 }; VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }; VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; +VECT_VAR_DECL(expected,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 }; VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, @@ -44,6 +45,8 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xfc, 0xfd, 0xfe, 0xff }; VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; +VECT_VAR_DECL(expected,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80, + 0xca00, 0xc980, 0xc900, 0xc880 }; VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000, 0xc1600000, 0xc1500000 }; @@ -62,6 +65,10 @@ void exec_vld1 (void) TEST_MACRO_ALL_VARIANTS_2_5(TEST_VLD1, vector, buffer); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VLD1(vector, buffer, , float, f, 16, 4); + TEST_VLD1(vector, buffer, q, float, f, 16, 8); +#endif TEST_VLD1(vector, buffer, , float, f, 32, 2); TEST_VLD1(vector, buffer, q, float, f, 32, 4); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_dup.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_dup.c index 0e052743926..34be214e912 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_dup.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_dup.c @@ -17,6 +17,7 @@ VECT_VAR_DECL(expected0,uint,64,1) [] = { 0xfffffffffffffff0 }; VECT_VAR_DECL(expected0,poly,8,8) [] = { 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0 }; VECT_VAR_DECL(expected0,poly,16,4) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0 }; +VECT_VAR_DECL(expected0,hfloat,16,4) [] = { 0xcc00, 0xcc00, 0xcc00, 0xcc00 }; VECT_VAR_DECL(expected0,hfloat,32,2) [] = { 0xc1800000, 0xc1800000 }; VECT_VAR_DECL(expected0,int,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, @@ -44,6 +45,8 @@ VECT_VAR_DECL(expected0,poly,8,16) [] = { 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0, 0xf0 }; VECT_VAR_DECL(expected0,poly,16,8) [] = { 0xfff0, 0xfff0, 0xfff0, 0xfff0, 0xfff0, 0xfff0, 0xfff0, 0xfff0 }; +VECT_VAR_DECL(expected0,hfloat,16,8) [] = { 0xcc00, 0xcc00, 0xcc00, 0xcc00, + 0xcc00, 0xcc00, 0xcc00, 0xcc00 }; VECT_VAR_DECL(expected0,hfloat,32,4) [] = { 0xc1800000, 0xc1800000, 0xc1800000, 0xc1800000 }; @@ -61,6 +64,7 @@ VECT_VAR_DECL(expected1,uint,64,1) [] = { 0xfffffffffffffff1 }; VECT_VAR_DECL(expected1,poly,8,8) [] = { 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1 }; VECT_VAR_DECL(expected1,poly,16,4) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1 }; +VECT_VAR_DECL(expected1,hfloat,16,4) [] = { 0xcb80, 0xcb80, 0xcb80, 0xcb80 }; VECT_VAR_DECL(expected1,hfloat,32,2) [] = { 0xc1700000, 0xc1700000 }; VECT_VAR_DECL(expected1,int,8,16) [] = { 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, @@ -88,6 +92,8 @@ VECT_VAR_DECL(expected1,poly,8,16) [] = { 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1, 0xf1 }; VECT_VAR_DECL(expected1,poly,16,8) [] = { 0xfff1, 0xfff1, 0xfff1, 0xfff1, 0xfff1, 0xfff1, 0xfff1, 0xfff1 }; +VECT_VAR_DECL(expected1,hfloat,16,8) [] = { 0xcb80, 0xcb80, 0xcb80, 0xcb80, + 0xcb80, 0xcb80, 0xcb80, 0xcb80 }; VECT_VAR_DECL(expected1,hfloat,32,4) [] = { 0xc1700000, 0xc1700000, 0xc1700000, 0xc1700000 }; @@ -105,6 +111,7 @@ VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff2 }; VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2 }; VECT_VAR_DECL(expected2,poly,16,4) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff2 }; +VECT_VAR_DECL(expected2,hfloat,16,4) [] = { 0xcb00, 0xcb00, 0xcb00, 0xcb00 }; VECT_VAR_DECL(expected2,hfloat,32,2) [] = { 0xc1600000, 0xc1600000 }; VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, @@ -132,6 +139,8 @@ VECT_VAR_DECL(expected2,poly,8,16) [] = { 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2 }; VECT_VAR_DECL(expected2,poly,16,8) [] = { 0xfff2, 0xfff2, 0xfff2, 0xfff2, 0xfff2, 0xfff2, 0xfff2, 0xfff2 }; +VECT_VAR_DECL(expected2,hfloat,16,8) [] = { 0xcb00, 0xcb00, 0xcb00, 0xcb00, + 0xcb00, 0xcb00, 0xcb00, 0xcb00 }; VECT_VAR_DECL(expected2,hfloat,32,4) [] = { 0xc1600000, 0xc1600000, 0xc1600000, 0xc1600000 }; @@ -154,6 +163,10 @@ void exec_vld1_dup (void) TEST_MACRO_ALL_VARIANTS_2_5(TEST_VLD1_DUP, vector, buffer_dup); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VLD1_DUP(vector, buffer_dup, , float, f, 16, 4); + TEST_VLD1_DUP(vector, buffer_dup, q, float, f, 16, 8); +#endif TEST_VLD1_DUP(vector, buffer_dup, , float, f, 32, 2); TEST_VLD1_DUP(vector, buffer_dup, q, float, f, 32, 4); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c index d5c5d22a8ce..1f39006498d 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c @@ -16,6 +16,7 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 }; VECT_VAR_DECL(expected,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xf0 }; VECT_VAR_DECL(expected,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 }; +VECT_VAR_DECL(expected,hfloat,16,4) [] = { 0xaaaa, 0xaaaa, 0xcc00, 0xaaaa }; VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xaaaaaaaa, 0xc1800000 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, @@ -43,6 +44,8 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0, 0xaaaa }; +VECT_VAR_DECL(expected,hfloat,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, + 0xaaaa, 0xcc00, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xc1800000, 0xaaaaaaaa }; @@ -72,6 +75,9 @@ void exec_vld1_lane (void) ARRAY(buffer_src, uint, 64, 1); ARRAY(buffer_src, poly, 8, 8); ARRAY(buffer_src, poly, 16, 4); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + ARRAY(buffer_src, float, 16, 4); +#endif ARRAY(buffer_src, float, 32, 2); ARRAY(buffer_src, int, 8, 16); @@ -84,6 +90,9 @@ void exec_vld1_lane (void) ARRAY(buffer_src, uint, 64, 2); ARRAY(buffer_src, poly, 8, 16); ARRAY(buffer_src, poly, 16, 8); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + ARRAY(buffer_src, float, 16, 8); +#endif ARRAY(buffer_src, float, 32, 4); clean_results (); @@ -99,6 +108,9 @@ void exec_vld1_lane (void) TEST_VLD1_LANE(, uint, u, 64, 1, 0); TEST_VLD1_LANE(, poly, p, 8, 8, 7); TEST_VLD1_LANE(, poly, p, 16, 4, 3); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VLD1_LANE(, float, f, 16, 4, 2); +#endif TEST_VLD1_LANE(, float, f, 32, 2, 1); TEST_VLD1_LANE(q, int, s, 8, 16, 15); @@ -111,6 +123,9 @@ void exec_vld1_lane (void) TEST_VLD1_LANE(q, uint, u, 64, 2, 0); TEST_VLD1_LANE(q, poly, p, 8, 16, 12); TEST_VLD1_LANE(q, poly, p, 16, 8, 6); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VLD1_LANE(q, float, f, 16, 8, 5); +#endif TEST_VLD1_LANE(q, float, f, 32, 4, 2); CHECK_RESULTS (TEST_MSG, ""); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c new file mode 100644 index 00000000000..2174d6eaa8f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float16x4x2_t +f_vld2_lane_f16 (float16_t * p, float16x4x2_t v) +{ + float16x4x2_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_f16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld2_lane_f16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c new file mode 100644 index 00000000000..83ae82c8242 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float16x8x2_t +f_vld2q_lane_f16 (float16_t * p, float16x8x2_t v) +{ + float16x8x2_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_f16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld2q_lane_f16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c new file mode 100644 index 00000000000..21b7861ba75 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float16x4x3_t +f_vld3_lane_f16 (float16_t * p, float16x4x3_t v) +{ + float16x4x3_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_f16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld3_lane_f16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c new file mode 100644 index 00000000000..95ec3913eef --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float16x8x3_t +f_vld3q_lane_f16 (float16_t * p, float16x8x3_t v) +{ + float16x8x3_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_f16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld3q_lane_f16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c new file mode 100644 index 00000000000..bd7ecf06690 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float16x4x4_t +f_vld4_lane_f16 (float16_t * p, float16x4x4_t v) +{ + float16x4x4_t res; + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_f16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + res = vld4_lane_f16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c new file mode 100644 index 00000000000..c27559f4ee8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c @@ -0,0 +1,16 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +float16x8x4_t +f_vld4q_lane_f16 (float16_t * p, float16x8x4_t v) +{ + float16x8x4_t res; + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_f16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + res = vld4q_lane_f16 (p, v, -1); + return res; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX.c index f20aa03f51b..1e02dc3fa10 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX.c @@ -18,6 +18,7 @@ VECT_VAR_DECL(expected_vld2_0,uint,64,1) [] = { 0xfffffffffffffff0 }; VECT_VAR_DECL(expected_vld2_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }; VECT_VAR_DECL(expected_vld2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; +VECT_VAR_DECL(expected_vld2_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 }; VECT_VAR_DECL(expected_vld2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; VECT_VAR_DECL(expected_vld2_0,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, @@ -41,6 +42,8 @@ VECT_VAR_DECL(expected_vld2_0,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xfc, 0xfd, 0xfe, 0xff }; VECT_VAR_DECL(expected_vld2_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; +VECT_VAR_DECL(expected_vld2_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80, + 0xca00, 0xc980, 0xc900, 0xc880 }; VECT_VAR_DECL(expected_vld2_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000, 0xc1600000, 0xc1500000 }; @@ -58,6 +61,7 @@ VECT_VAR_DECL(expected_vld2_1,uint,64,1) [] = { 0xfffffffffffffff1 }; VECT_VAR_DECL(expected_vld2_1,poly,8,8) [] = { 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff }; VECT_VAR_DECL(expected_vld2_1,poly,16,4) [] = { 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; +VECT_VAR_DECL(expected_vld2_1,hfloat,16,4) [] = { 0xca00, 0xc980, 0xc900, 0xc880 }; VECT_VAR_DECL(expected_vld2_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 }; VECT_VAR_DECL(expected_vld2_1,int,8,16) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, @@ -81,6 +85,8 @@ VECT_VAR_DECL(expected_vld2_1,poly,8,16) [] = { 0x0, 0x1, 0x2, 0x3, 0xc, 0xd, 0xe, 0xf }; VECT_VAR_DECL(expected_vld2_1,poly,16,8) [] = { 0xfff8, 0xfff9, 0xfffa, 0xfffb, 0xfffc, 0xfffd, 0xfffe, 0xffff }; +VECT_VAR_DECL(expected_vld2_1,hfloat,16,8) [] = { 0xc800, 0xc700, 0xc600, 0xc500, + 0xc400, 0xc200, 0xc000, 0xbc00 }; VECT_VAR_DECL(expected_vld2_1,hfloat,32,4) [] = { 0xc1400000, 0xc1300000, 0xc1200000, 0xc1100000 }; @@ -98,6 +104,7 @@ VECT_VAR_DECL(expected_vld3_0,uint,64,1) [] = { 0xfffffffffffffff0 }; VECT_VAR_DECL(expected_vld3_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }; VECT_VAR_DECL(expected_vld3_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; +VECT_VAR_DECL(expected_vld3_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 }; VECT_VAR_DECL(expected_vld3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; VECT_VAR_DECL(expected_vld3_0,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, @@ -121,6 +128,8 @@ VECT_VAR_DECL(expected_vld3_0,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xfc, 0xfd, 0xfe, 0xff }; VECT_VAR_DECL(expected_vld3_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; +VECT_VAR_DECL(expected_vld3_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80, + 0xca00, 0xc980, 0xc900, 0xc880 }; VECT_VAR_DECL(expected_vld3_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000, 0xc1600000, 0xc1500000 }; @@ -138,6 +147,7 @@ VECT_VAR_DECL(expected_vld3_1,uint,64,1) [] = { 0xfffffffffffffff1 }; VECT_VAR_DECL(expected_vld3_1,poly,8,8) [] = { 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff }; VECT_VAR_DECL(expected_vld3_1,poly,16,4) [] = { 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; +VECT_VAR_DECL(expected_vld3_1,hfloat,16,4) [] = { 0xca00, 0xc980, 0xc900, 0xc880 }; VECT_VAR_DECL(expected_vld3_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 }; VECT_VAR_DECL(expected_vld3_1,int,8,16) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, @@ -161,6 +171,8 @@ VECT_VAR_DECL(expected_vld3_1,poly,8,16) [] = { 0x0, 0x1, 0x2, 0x3, 0xc, 0xd, 0xe, 0xf }; VECT_VAR_DECL(expected_vld3_1,poly,16,8) [] = { 0xfff8, 0xfff9, 0xfffa, 0xfffb, 0xfffc, 0xfffd, 0xfffe, 0xffff }; +VECT_VAR_DECL(expected_vld3_1,hfloat,16,8) [] = { 0xc800, 0xc700, 0xc600, 0xc500, + 0xc400, 0xc200, 0xc000, 0xbc00 }; VECT_VAR_DECL(expected_vld3_1,hfloat,32,4) [] = { 0xc1400000, 0xc1300000, 0xc1200000, 0xc1100000 }; @@ -181,6 +193,7 @@ VECT_VAR_DECL(expected_vld3_2,poly,8,8) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 }; VECT_VAR_DECL(expected_vld3_2,poly,16,4) [] = { 0xfff8, 0xfff9, 0xfffa, 0xfffb }; +VECT_VAR_DECL(expected_vld3_2,hfloat,16,4) [] = { 0xc800, 0xc700, 0xc600, 0xc500 }; VECT_VAR_DECL(expected_vld3_2,hfloat,32,2) [] = { 0xc1400000, 0xc1300000 }; VECT_VAR_DECL(expected_vld3_2,int,8,16) [] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, @@ -204,6 +217,8 @@ VECT_VAR_DECL(expected_vld3_2,poly,8,16) [] = { 0x10, 0x11, 0x12, 0x13, 0x1c, 0x1d, 0x1e, 0x1f }; VECT_VAR_DECL(expected_vld3_2,poly,16,8) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 }; +VECT_VAR_DECL(expected_vld3_2,hfloat,16,8) [] = { 0x0000, 0x3c00, 0x4000, 0x4200, + 0x4400, 0x4500, 0x4600, 0x4700 }; VECT_VAR_DECL(expected_vld3_2,hfloat,32,4) [] = { 0xc1000000, 0xc0e00000, 0xc0c00000, 0xc0a00000 }; @@ -223,6 +238,7 @@ VECT_VAR_DECL(expected_vld4_0,uint,64,1) [] = { 0xfffffffffffffff0 }; VECT_VAR_DECL(expected_vld4_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 }; VECT_VAR_DECL(expected_vld4_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; +VECT_VAR_DECL(expected_vld4_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 }; VECT_VAR_DECL(expected_vld4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; VECT_VAR_DECL(expected_vld4_0,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, @@ -246,6 +262,8 @@ VECT_VAR_DECL(expected_vld4_0,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xfc, 0xfd, 0xfe, 0xff }; VECT_VAR_DECL(expected_vld4_0,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; +VECT_VAR_DECL(expected_vld4_0,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80, + 0xca00, 0xc980, 0xc900, 0xc880 }; VECT_VAR_DECL(expected_vld4_0,hfloat,32,4) [] = { 0xc1800000, 0xc1700000, 0xc1600000, 0xc1500000 }; @@ -263,6 +281,7 @@ VECT_VAR_DECL(expected_vld4_1,uint,64,1) [] = { 0xfffffffffffffff1 }; VECT_VAR_DECL(expected_vld4_1,poly,8,8) [] = { 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff }; VECT_VAR_DECL(expected_vld4_1,poly,16,4) [] = { 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; +VECT_VAR_DECL(expected_vld4_1,hfloat,16,4) [] = { 0xca00, 0xc980, 0xc900, 0xc880 }; VECT_VAR_DECL(expected_vld4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 }; VECT_VAR_DECL(expected_vld4_1,int,8,16) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, @@ -286,6 +305,8 @@ VECT_VAR_DECL(expected_vld4_1,poly,8,16) [] = { 0x0, 0x1, 0x2, 0x3, 0xc, 0xd, 0xe, 0xf }; VECT_VAR_DECL(expected_vld4_1,poly,16,8) [] = { 0xfff8, 0xfff9, 0xfffa, 0xfffb, 0xfffc, 0xfffd, 0xfffe, 0xffff }; +VECT_VAR_DECL(expected_vld4_1,hfloat,16,8) [] = { 0xc800, 0xc700, 0xc600, 0xc500, + 0xc400, 0xc200, 0xc000, 0xbc00 }; VECT_VAR_DECL(expected_vld4_1,hfloat,32,4) [] = { 0xc1400000, 0xc1300000, 0xc1200000, 0xc1100000 }; @@ -303,6 +324,7 @@ VECT_VAR_DECL(expected_vld4_2,uint,64,1) [] = { 0xfffffffffffffff2 }; VECT_VAR_DECL(expected_vld4_2,poly,8,8) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 }; VECT_VAR_DECL(expected_vld4_2,poly,16,4) [] = { 0xfff8, 0xfff9, 0xfffa, 0xfffb }; +VECT_VAR_DECL(expected_vld4_2,hfloat,16,4) [] = { 0xc800, 0xc700, 0xc600, 0xc500 }; VECT_VAR_DECL(expected_vld4_2,hfloat,32,2) [] = { 0xc1400000, 0xc1300000 }; VECT_VAR_DECL(expected_vld4_2,int,8,16) [] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, @@ -326,6 +348,8 @@ VECT_VAR_DECL(expected_vld4_2,poly,8,16) [] = { 0x10, 0x11, 0x12, 0x13, 0x1c, 0x1d, 0x1e, 0x1f }; VECT_VAR_DECL(expected_vld4_2,poly,16,8) [] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 }; +VECT_VAR_DECL(expected_vld4_2,hfloat,16,8) [] = { 0x0000, 0x3c00, 0x4000, 0x4200, + 0x4400, 0x4500, 0x4600, 0x4700 }; VECT_VAR_DECL(expected_vld4_2,hfloat,32,4) [] = { 0xc1000000, 0xc0e00000, 0xc0c00000, 0xc0a00000 }; @@ -343,6 +367,7 @@ VECT_VAR_DECL(expected_vld4_3,uint,64,1) [] = { 0xfffffffffffffff3 }; VECT_VAR_DECL(expected_vld4_3,poly,8,8) [] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf }; VECT_VAR_DECL(expected_vld4_3,poly,16,4) [] = { 0xfffc, 0xfffd, 0xfffe, 0xffff }; +VECT_VAR_DECL(expected_vld4_3,hfloat,16,4) [] = { 0xc400, 0xc200, 0xc000, 0xbc00 }; VECT_VAR_DECL(expected_vld4_3,hfloat,32,2) [] = { 0xc1200000, 0xc1100000 }; VECT_VAR_DECL(expected_vld4_3,int,8,16) [] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, @@ -366,6 +391,8 @@ VECT_VAR_DECL(expected_vld4_3,poly,8,16) [] = { 0x20, 0x21, 0x22, 0x23, 0x2c, 0x2d, 0x2e, 0x2f }; VECT_VAR_DECL(expected_vld4_3,poly,16,8) [] = { 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf }; +VECT_VAR_DECL(expected_vld4_3,hfloat,16,8) [] = { 0x4800, 0x4880, 0x4900, 0x4980, + 0x4a00, 0x4a80, 0x4b00, 0x4b80 }; VECT_VAR_DECL(expected_vld4_3,hfloat,32,4) [] = { 0xc0800000, 0xc0400000, 0xc0000000, 0xbf800000 }; @@ -398,7 +425,7 @@ void exec_vldX (void) sizeof(VECT_VAR(result, T1, W, N))); /* We need all variants in 64 bits, but there is no 64x2 variant. */ -#define DECL_ALL_VLDX(X) \ +#define DECL_ALL_VLDX_NO_FP16(X) \ DECL_VLDX(int, 8, 8, X); \ DECL_VLDX(int, 16, 4, X); \ DECL_VLDX(int, 32, 2, X); \ @@ -420,7 +447,16 @@ void exec_vldX (void) DECL_VLDX(poly, 16, 8, X); \ DECL_VLDX(float, 32, 4, X) -#define TEST_ALL_VLDX(X) \ +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +#define DECL_ALL_VLDX(X) \ + DECL_ALL_VLDX_NO_FP16(X); \ + DECL_VLDX(float, 16, 4, X); \ + DECL_VLDX(float, 16, 8, X) +#else +#define DECL_ALL_VLDX(X) DECL_ALL_VLDX_NO_FP16(X) +#endif + +#define TEST_ALL_VLDX_NO_FP16(X) \ TEST_VLDX(, int, s, 8, 8, X); \ TEST_VLDX(, int, s, 16, 4, X); \ TEST_VLDX(, int, s, 32, 2, X); \ @@ -442,7 +478,16 @@ void exec_vldX (void) TEST_VLDX(q, poly, p, 16, 8, X); \ TEST_VLDX(q, float, f, 32, 4, X) -#define TEST_ALL_EXTRA_CHUNKS(X, Y) \ +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +#define TEST_ALL_VLDX(X) \ + TEST_ALL_VLDX_NO_FP16(X); \ + TEST_VLDX(, float, f, 16, 4, X); \ + TEST_VLDX(q, float, f, 16, 8, X) +#else +#define TEST_ALL_VLDX(X) TEST_ALL_VLDX_NO_FP16(X) +#endif + +#define TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y) \ TEST_EXTRA_CHUNK(int, 8, 8, X, Y); \ TEST_EXTRA_CHUNK(int, 16, 4, X, Y); \ TEST_EXTRA_CHUNK(int, 32, 2, X, Y); \ @@ -464,9 +509,17 @@ void exec_vldX (void) TEST_EXTRA_CHUNK(poly, 16, 8, X, Y); \ TEST_EXTRA_CHUNK(float, 32, 4, X, Y) +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +#define TEST_ALL_EXTRA_CHUNKS(X, Y) \ + TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y) \ + TEST_EXTRA_CHUNK(float, 16, 4, X, Y); \ + TEST_EXTRA_CHUNK(float, 16, 8, X, Y); +#else +#define TEST_ALL_EXTRA_CHUNKS(X, Y) TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y) +#endif + /* vldX supports all vector types except [u]int64x2. */ -#define CHECK_RESULTS_VLDX(test_name,EXPECTED,comment) \ - { \ +#define CHECK_RESULTS_VLDX_NO_FP16(test_name,EXPECTED,comment) \ CHECK(test_name, int, 8, 8, PRIx8, EXPECTED, comment); \ CHECK(test_name, int, 16, 4, PRIx16, EXPECTED, comment); \ CHECK(test_name, int, 32, 2, PRIx32, EXPECTED, comment); \ @@ -487,8 +540,19 @@ void exec_vldX (void) CHECK(test_name, uint, 32, 4, PRIx32, EXPECTED, comment); \ CHECK(test_name, poly, 8, 16, PRIx8, EXPECTED, comment); \ CHECK(test_name, poly, 16, 8, PRIx16, EXPECTED, comment); \ - CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment); \ - } \ + CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment) + +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +#define CHECK_RESULTS_VLDX(test_name,EXPECTED,comment) \ + { \ + CHECK_RESULTS_VLDX_NO_FP16(test_name, EXPECTED, comment); \ + CHECK_FP(test_name, float, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK_FP(test_name, float, 16, 8, PRIx16, EXPECTED, comment); \ + } +#else +#define CHECK_RESULTS_VLDX(test_name, EXPECTED, comment) \ + { CHECK_RESULTS_VLDX_NO_FP16(test_name, EXPECTED, comment); } +#endif DECL_ALL_VLDX(2); DECL_ALL_VLDX(3); @@ -516,6 +580,10 @@ void exec_vldX (void) PAD(buffer_vld2_pad, poly, 8, 8); VECT_ARRAY_INIT2(buffer_vld2, poly, 16, 4); PAD(buffer_vld2_pad, poly, 16, 4); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VECT_ARRAY_INIT2(buffer_vld2, float, 16, 4); + PAD(buffer_vld2_pad, float, 16, 4); +#endif VECT_ARRAY_INIT2(buffer_vld2, float, 32, 2); PAD(buffer_vld2_pad, float, 32, 2); @@ -539,6 +607,10 @@ void exec_vldX (void) PAD(buffer_vld2_pad, poly, 8, 16); VECT_ARRAY_INIT2(buffer_vld2, poly, 16, 8); PAD(buffer_vld2_pad, poly, 16, 8); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VECT_ARRAY_INIT2(buffer_vld2, float, 16, 8); + PAD(buffer_vld2_pad, float, 16, 8); +#endif VECT_ARRAY_INIT2(buffer_vld2, float, 32, 4); PAD(buffer_vld2_pad, float, 32, 4); @@ -563,6 +635,10 @@ void exec_vldX (void) PAD(buffer_vld3_pad, poly, 8, 8); VECT_ARRAY_INIT3(buffer_vld3, poly, 16, 4); PAD(buffer_vld3_pad, poly, 16, 4); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VECT_ARRAY_INIT3(buffer_vld3, float, 16, 4); + PAD(buffer_vld3_pad, float, 16, 4); +#endif VECT_ARRAY_INIT3(buffer_vld3, float, 32, 2); PAD(buffer_vld3_pad, float, 32, 2); @@ -586,6 +662,10 @@ void exec_vldX (void) PAD(buffer_vld3_pad, poly, 8, 16); VECT_ARRAY_INIT3(buffer_vld3, poly, 16, 8); PAD(buffer_vld3_pad, poly, 16, 8); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VECT_ARRAY_INIT3(buffer_vld3, float, 16, 8); + PAD(buffer_vld3_pad, float, 16, 8); +#endif VECT_ARRAY_INIT3(buffer_vld3, float, 32, 4); PAD(buffer_vld3_pad, float, 32, 4); @@ -610,6 +690,10 @@ void exec_vldX (void) PAD(buffer_vld4_pad, poly, 8, 8); VECT_ARRAY_INIT4(buffer_vld4, poly, 16, 4); PAD(buffer_vld4_pad, poly, 16, 4); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VECT_ARRAY_INIT4(buffer_vld4, float, 16, 4); + PAD(buffer_vld4_pad, float, 16, 4); +#endif VECT_ARRAY_INIT4(buffer_vld4, float, 32, 2); PAD(buffer_vld4_pad, float, 32, 2); @@ -633,6 +717,10 @@ void exec_vldX (void) PAD(buffer_vld4_pad, poly, 8, 16); VECT_ARRAY_INIT4(buffer_vld4, poly, 16, 8); PAD(buffer_vld4_pad, poly, 16, 8); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VECT_ARRAY_INIT4(buffer_vld4, float, 16, 8); + PAD(buffer_vld4_pad, float, 16, 8); +#endif VECT_ARRAY_INIT4(buffer_vld4, float, 32, 4); PAD(buffer_vld4_pad, float, 32, 4); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c index c66dade8e45..e4cde46725f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c @@ -18,6 +18,7 @@ VECT_VAR_DECL(expected_vld2_0,uint,64,1) [] = { 0xfffffffffffffff0 }; VECT_VAR_DECL(expected_vld2_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1, 0xf0, 0xf1, 0xf0, 0xf1 }; VECT_VAR_DECL(expected_vld2_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 }; +VECT_VAR_DECL(expected_vld2_0,hfloat,16,4) [] = {0xcc00, 0xcb80, 0xcc00, 0xcb80 }; VECT_VAR_DECL(expected_vld2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; /* vld2_dup/chunk 1. */ @@ -35,6 +36,7 @@ VECT_VAR_DECL(expected_vld2_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf0, 0xf1, 0xf0, 0xf1, 0xf0, 0xf1 }; VECT_VAR_DECL(expected_vld2_1,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff0, 0xfff1 }; +VECT_VAR_DECL(expected_vld2_1,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcc00, 0xcb80 }; VECT_VAR_DECL(expected_vld2_1,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; /* vld3_dup/chunk 0. */ @@ -54,6 +56,7 @@ VECT_VAR_DECL(expected_vld3_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf0, 0xf1, 0xf2, 0xf0, 0xf1 }; VECT_VAR_DECL(expected_vld3_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff0 }; +VECT_VAR_DECL(expected_vld3_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xcc00 }; VECT_VAR_DECL(expected_vld3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; /* vld3_dup/chunk 1. */ @@ -73,6 +76,7 @@ VECT_VAR_DECL(expected_vld3_1,poly,8,8) [] = { 0xf2, 0xf0, 0xf1, 0xf2, 0xf0, 0xf1, 0xf2, 0xf0 }; VECT_VAR_DECL(expected_vld3_1,poly,16,4) [] = { 0xfff1, 0xfff2, 0xfff0, 0xfff1 }; +VECT_VAR_DECL(expected_vld3_1,hfloat,16,4) [] = { 0xcb80, 0xcb00, 0xcc00, 0xcb80 }; VECT_VAR_DECL(expected_vld3_1,hfloat,32,2) [] = { 0xc1600000, 0xc1800000 }; /* vld3_dup/chunk 2. */ @@ -92,6 +96,7 @@ VECT_VAR_DECL(expected_vld3_2,poly,8,8) [] = { 0xf1, 0xf2, 0xf0, 0xf1, 0xf2, 0xf0, 0xf1, 0xf2 }; VECT_VAR_DECL(expected_vld3_2,poly,16,4) [] = { 0xfff2, 0xfff0, 0xfff1, 0xfff2 }; +VECT_VAR_DECL(expected_vld3_2,hfloat,16,4) [] = { 0xcb00, 0xcc00, 0xcb80, 0xcb00 }; VECT_VAR_DECL(expected_vld3_2,hfloat,32,2) [] = { 0xc1700000, 0xc1600000 }; /* vld4_dup/chunk 0. */ @@ -109,6 +114,7 @@ VECT_VAR_DECL(expected_vld4_0,uint,64,1) [] = { 0xfffffffffffffff0 }; VECT_VAR_DECL(expected_vld4_0,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf0, 0xf1, 0xf2, 0xf3 }; VECT_VAR_DECL(expected_vld4_0,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; +VECT_VAR_DECL(expected_vld4_0,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 }; VECT_VAR_DECL(expected_vld4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; /* vld4_dup/chunk 1. */ @@ -125,6 +131,7 @@ VECT_VAR_DECL(expected_vld4_1,uint,64,1) [] = { 0xfffffffffffffff1 }; VECT_VAR_DECL(expected_vld4_1,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf0, 0xf1, 0xf2, 0xf3 }; VECT_VAR_DECL(expected_vld4_1,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; +VECT_VAR_DECL(expected_vld4_1,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 }; VECT_VAR_DECL(expected_vld4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 }; /* vld4_dup/chunk 2. */ @@ -141,6 +148,7 @@ VECT_VAR_DECL(expected_vld4_2,uint,64,1) [] = { 0xfffffffffffffff2 }; VECT_VAR_DECL(expected_vld4_2,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf0, 0xf1, 0xf2, 0xf3 }; VECT_VAR_DECL(expected_vld4_2,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; +VECT_VAR_DECL(expected_vld4_2,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 }; VECT_VAR_DECL(expected_vld4_2,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; /* vld4_dup/chunk3. */ @@ -157,6 +165,7 @@ VECT_VAR_DECL(expected_vld4_3,uint,64,1) [] = { 0xfffffffffffffff3 }; VECT_VAR_DECL(expected_vld4_3,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf0, 0xf1, 0xf2, 0xf3 }; VECT_VAR_DECL(expected_vld4_3,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; +VECT_VAR_DECL(expected_vld4_3,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 }; VECT_VAR_DECL(expected_vld4_3,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 }; void exec_vldX_dup (void) @@ -188,7 +197,7 @@ void exec_vldX_dup (void) &(VECT_VAR(result_bis_##X, T1, W, N)[Y*N]), \ sizeof(VECT_VAR(result, T1, W, N))); -#define DECL_ALL_VLDX_DUP(X) \ +#define DECL_ALL_VLDX_DUP_NO_FP16(X) \ DECL_VLDX_DUP(int, 8, 8, X); \ DECL_VLDX_DUP(int, 16, 4, X); \ DECL_VLDX_DUP(int, 32, 2, X); \ @@ -201,7 +210,15 @@ void exec_vldX_dup (void) DECL_VLDX_DUP(poly, 16, 4, X); \ DECL_VLDX_DUP(float, 32, 2, X) -#define TEST_ALL_VLDX_DUP(X) \ +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +#define DECL_ALL_VLDX_DUP(X) \ + DECL_ALL_VLDX_DUP_NO_FP16(X); \ + DECL_VLDX_DUP(float, 16, 4, X) +#else +#define DECL_ALL_VLDX_DUP(X) DECL_ALL_VLDX_DUP_NO_FP16(X) +#endif + +#define TEST_ALL_VLDX_DUP_NO_FP16(X) \ TEST_VLDX_DUP(, int, s, 8, 8, X); \ TEST_VLDX_DUP(, int, s, 16, 4, X); \ TEST_VLDX_DUP(, int, s, 32, 2, X); \ @@ -214,7 +231,15 @@ void exec_vldX_dup (void) TEST_VLDX_DUP(, poly, p, 16, 4, X); \ TEST_VLDX_DUP(, float, f, 32, 2, X) -#define TEST_ALL_EXTRA_CHUNKS(X, Y) \ +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +#define TEST_ALL_VLDX_DUP(X) \ + TEST_ALL_VLDX_DUP_NO_FP16(X); \ + TEST_VLDX_DUP(, float, f, 16, 4, X) +#else +#define TEST_ALL_VLDX_DUP(X) TEST_ALL_VLDX_DUP_NO_FP16(X) +#endif + +#define TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y) \ TEST_EXTRA_CHUNK(int, 8, 8, X, Y); \ TEST_EXTRA_CHUNK(int, 16, 4, X, Y); \ TEST_EXTRA_CHUNK(int, 32, 2, X, Y); \ @@ -227,9 +252,16 @@ void exec_vldX_dup (void) TEST_EXTRA_CHUNK(poly, 16, 4, X, Y); \ TEST_EXTRA_CHUNK(float, 32, 2, X, Y) +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +#define TEST_ALL_EXTRA_CHUNKS(X, Y) \ + TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y); \ + TEST_EXTRA_CHUNK(float, 16, 4, X, Y) +#else +#define TEST_ALL_EXTRA_CHUNKS(X, Y) TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y) +#endif + /* vldX_dup supports only 64-bit inputs. */ -#define CHECK_RESULTS_VLDX_DUP(test_name,EXPECTED,comment) \ - { \ +#define CHECK_RESULTS_VLDX_DUP_NO_FP16(test_name,EXPECTED,comment) \ CHECK(test_name, int, 8, 8, PRIx8, EXPECTED, comment); \ CHECK(test_name, int, 16, 4, PRIx16, EXPECTED, comment); \ CHECK(test_name, int, 32, 2, PRIx32, EXPECTED, comment); \ @@ -240,8 +272,20 @@ void exec_vldX_dup (void) CHECK(test_name, uint, 64, 1, PRIx64, EXPECTED, comment); \ CHECK(test_name, poly, 8, 8, PRIx8, EXPECTED, comment); \ CHECK(test_name, poly, 16, 4, PRIx16, EXPECTED, comment); \ - CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment); \ - } \ + CHECK_FP(test_name, float, 32, 2, PRIx32, EXPECTED, comment) + +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +#define CHECK_RESULTS_VLDX_DUP(test_name,EXPECTED,comment) \ + { \ + CHECK_RESULTS_VLDX_DUP_NO_FP16(test_name,EXPECTED,comment); \ + CHECK_FP(test_name, float, 16, 4, PRIx16, EXPECTED, comment); \ + } +#else +#define CHECK_RESULTS_VLDX_DUP(test_name,EXPECTED,comment) \ + { \ + CHECK_RESULTS_VLDX_DUP_NO_FP16(test_name,EXPECTED,comment); \ + } +#endif DECL_ALL_VLDX_DUP(2); DECL_ALL_VLDX_DUP(3); @@ -269,6 +313,10 @@ void exec_vldX_dup (void) PAD(buffer_vld2_pad, poly, 8, 8); VECT_ARRAY_INIT2(buffer_vld2, poly, 16, 4); PAD(buffer_vld2_pad, poly, 16, 4); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VECT_ARRAY_INIT2(buffer_vld2, float, 16, 4); + PAD(buffer_vld2_pad, float, 16, 4); +#endif VECT_ARRAY_INIT2(buffer_vld2, float, 32, 2); PAD(buffer_vld2_pad, float, 32, 2); @@ -292,6 +340,10 @@ void exec_vldX_dup (void) PAD(buffer_vld2_pad, poly, 8, 16); VECT_ARRAY_INIT2(buffer_vld2, poly, 16, 8); PAD(buffer_vld2_pad, poly, 16, 8); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VECT_ARRAY_INIT2(buffer_vld2, float, 16, 8); + PAD(buffer_vld2_pad, float, 16, 8); +#endif VECT_ARRAY_INIT2(buffer_vld2, float, 32, 4); PAD(buffer_vld2_pad, float, 32, 4); @@ -316,6 +368,10 @@ void exec_vldX_dup (void) PAD(buffer_vld3_pad, poly, 8, 8); VECT_ARRAY_INIT3(buffer_vld3, poly, 16, 4); PAD(buffer_vld3_pad, poly, 16, 4); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VECT_ARRAY_INIT3(buffer_vld3, float, 16, 4); + PAD(buffer_vld3_pad, float, 16, 4); +#endif VECT_ARRAY_INIT3(buffer_vld3, float, 32, 2); PAD(buffer_vld3_pad, float, 32, 2); @@ -339,6 +395,10 @@ void exec_vldX_dup (void) PAD(buffer_vld3_pad, poly, 8, 16); VECT_ARRAY_INIT3(buffer_vld3, poly, 16, 8); PAD(buffer_vld3_pad, poly, 16, 8); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VECT_ARRAY_INIT3(buffer_vld3, float, 16, 8); + PAD(buffer_vld3_pad, float, 16, 8); +#endif VECT_ARRAY_INIT3(buffer_vld3, float, 32, 4); PAD(buffer_vld3_pad, float, 32, 4); @@ -363,6 +423,10 @@ void exec_vldX_dup (void) PAD(buffer_vld4_pad, poly, 8, 8); VECT_ARRAY_INIT4(buffer_vld4, poly, 16, 4); PAD(buffer_vld4_pad, poly, 16, 4); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VECT_ARRAY_INIT4(buffer_vld4, float, 16, 4); + PAD(buffer_vld4_pad, float, 16, 4); +#endif VECT_ARRAY_INIT4(buffer_vld4, float, 32, 2); PAD(buffer_vld4_pad, float, 32, 2); @@ -386,6 +450,10 @@ void exec_vldX_dup (void) PAD(buffer_vld4_pad, poly, 8, 16); VECT_ARRAY_INIT4(buffer_vld4, poly, 16, 8); PAD(buffer_vld4_pad, poly, 16, 8); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VECT_ARRAY_INIT4(buffer_vld4, float, 16, 8); + PAD(buffer_vld4_pad, float, 16, 8); +#endif VECT_ARRAY_INIT4(buffer_vld4, float, 32, 4); PAD(buffer_vld4_pad, float, 32, 4); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c index 2f2e62f0e3e..33b0eafbadb 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c @@ -18,6 +18,7 @@ VECT_VAR_DECL(expected_vld2_0,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld2_0,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; +VECT_VAR_DECL(expected_vld2_0,hfloat,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld2_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; VECT_VAR_DECL(expected_vld2_0,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; @@ -29,6 +30,8 @@ VECT_VAR_DECL(expected_vld2_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xaaaaaaaa, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld2_0,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; +VECT_VAR_DECL(expected_vld2_0,hfloat,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, + 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa } ; VECT_VAR_DECL(expected_vld2_0,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; @@ -44,6 +47,7 @@ VECT_VAR_DECL(expected_vld2_1,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; VECT_VAR_DECL(expected_vld2_1,poly,8,8) [] = { 0xf0, 0xf1, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld2_1,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xfff0, 0xfff1 }; +VECT_VAR_DECL(expected_vld2_1,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld2_1,hfloat,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld2_1,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0, 0xfff1, 0xaaaa, 0xaaaa }; @@ -55,6 +59,8 @@ VECT_VAR_DECL(expected_vld2_1,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld2_1,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xfff0, 0xfff1, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; +VECT_VAR_DECL(expected_vld2_1,hfloat,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, + 0xcc00, 0xcb80, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld2_1,hfloat,32,4) [] = { 0xc1800000, 0xc1700000, 0xaaaaaaaa, 0xaaaaaaaa }; @@ -70,6 +76,7 @@ VECT_VAR_DECL(expected_vld3_0,uint,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld3_0,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld3_0,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; +VECT_VAR_DECL(expected_vld3_0,hfloat,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; VECT_VAR_DECL(expected_vld3_0,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; @@ -81,6 +88,8 @@ VECT_VAR_DECL(expected_vld3_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld3_0,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; +VECT_VAR_DECL(expected_vld3_0,hfloat,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, + 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_0,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; @@ -96,6 +105,7 @@ VECT_VAR_DECL(expected_vld3_1,uint,32,2) [] = { 0xaaaaaaaa, 0xfffffff0 }; VECT_VAR_DECL(expected_vld3_1,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xf0, 0xf1, 0xf2, 0xaa }; VECT_VAR_DECL(expected_vld3_1,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; +VECT_VAR_DECL(expected_vld3_1,hfloat,16,4) [] = { 0xaaaa, 0xaaaa, 0xcc00, 0xcb80 }; VECT_VAR_DECL(expected_vld3_1,hfloat,32,2) [] = { 0xc1600000, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld3_1,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; @@ -107,6 +117,8 @@ VECT_VAR_DECL(expected_vld3_1,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld3_1,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0 }; +VECT_VAR_DECL(expected_vld3_1,hfloat,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, + 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_1,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xc1800000, 0xc1700000 }; @@ -122,6 +134,7 @@ VECT_VAR_DECL(expected_vld3_2,uint,32,2) [] = { 0xfffffff1, 0xfffffff2 }; VECT_VAR_DECL(expected_vld3_2,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld3_2,poly,16,4) [] = { 0xaaaa, 0xfff0, 0xfff1, 0xfff2 }; +VECT_VAR_DECL(expected_vld3_2,hfloat,16,4) [] = { 0xcb00, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_2,hfloat,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld3_2,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xfff0, 0xfff1, 0xfff2, 0xaaaa, 0xaaaa, 0xaaaa }; @@ -133,6 +146,8 @@ VECT_VAR_DECL(expected_vld3_2,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld3_2,poly,16,8) [] = { 0xfff1, 0xfff2, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; +VECT_VAR_DECL(expected_vld3_2,hfloat,16,8) [] = { 0xaaaa, 0xaaaa, 0xcc00, 0xcb80, + 0xcb00, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld3_2,hfloat,32,4) [] = { 0xc1600000, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; @@ -148,6 +163,7 @@ VECT_VAR_DECL(expected_vld4_0,uint,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld4_0,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_0,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; +VECT_VAR_DECL(expected_vld4_0,hfloat,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_0,hfloat,32,2) [] = { 0xc1800000, 0xc1700000 }; VECT_VAR_DECL(expected_vld4_0,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; @@ -159,6 +175,8 @@ VECT_VAR_DECL(expected_vld4_0,uint,32,4) [] = { 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xfffffff3 }; VECT_VAR_DECL(expected_vld4_0,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; +VECT_VAR_DECL(expected_vld4_0,hfloat,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, + 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_0,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; @@ -174,6 +192,7 @@ VECT_VAR_DECL(expected_vld4_1,uint,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld4_1,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_1,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; +VECT_VAR_DECL(expected_vld4_1,hfloat,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_1,hfloat,32,2) [] = { 0xc1600000, 0xc1500000 }; VECT_VAR_DECL(expected_vld4_1,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; @@ -185,6 +204,8 @@ VECT_VAR_DECL(expected_vld4_1,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld4_1,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; +VECT_VAR_DECL(expected_vld4_1,hfloat,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, + 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_1,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; @@ -200,6 +221,7 @@ VECT_VAR_DECL(expected_vld4_2,uint,32,2) [] = { 0xfffffff0, 0xfffffff1 }; VECT_VAR_DECL(expected_vld4_2,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_2,poly,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; +VECT_VAR_DECL(expected_vld4_2,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80 }; VECT_VAR_DECL(expected_vld4_2,hfloat,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld4_2,int,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; @@ -211,6 +233,8 @@ VECT_VAR_DECL(expected_vld4_2,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld4_2,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; +VECT_VAR_DECL(expected_vld4_2,hfloat,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, + 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_2,hfloat,32,4) [] = { 0xc1800000, 0xc1700000, 0xc1600000, 0xc1500000 }; @@ -226,6 +250,7 @@ VECT_VAR_DECL(expected_vld4_3,uint,32,2) [] = { 0xfffffff2, 0xfffffff3 }; VECT_VAR_DECL(expected_vld4_3,poly,8,8) [] = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; VECT_VAR_DECL(expected_vld4_3,poly,16,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; +VECT_VAR_DECL(expected_vld4_3,hfloat,16,4) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_3,hfloat,32,2) [] = { 0xaaaaaaaa, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld4_3,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; @@ -237,6 +262,8 @@ VECT_VAR_DECL(expected_vld4_3,uint,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; VECT_VAR_DECL(expected_vld4_3,poly,16,8) [] = { 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; +VECT_VAR_DECL(expected_vld4_3,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80, + 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa }; VECT_VAR_DECL(expected_vld4_3,hfloat,32,4) [] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa }; @@ -252,6 +279,9 @@ VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 32, 2); VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 64, 2); VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 8, 2); VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 16, 2); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +VECT_VAR_DECL_INIT(buffer_vld2_lane, float, 16, 2); +#endif VECT_VAR_DECL_INIT(buffer_vld2_lane, float, 32, 2); /* Input buffers for vld3_lane */ @@ -265,6 +295,9 @@ VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 32, 3); VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 64, 3); VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 8, 3); VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 16, 3); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +VECT_VAR_DECL_INIT(buffer_vld3_lane, float, 16, 3); +#endif VECT_VAR_DECL_INIT(buffer_vld3_lane, float, 32, 3); /* Input buffers for vld4_lane */ @@ -278,6 +311,9 @@ VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 32, 4); VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 64, 4); VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 8, 4); VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 16, 4); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +VECT_VAR_DECL_INIT(buffer_vld4_lane, float, 16, 4); +#endif VECT_VAR_DECL_INIT(buffer_vld4_lane, float, 32, 4); void exec_vldX_lane (void) @@ -321,7 +357,7 @@ void exec_vldX_lane (void) sizeof(VECT_VAR(result, T1, W, N))); /* We need all variants in 64 bits, but there is no 64x2 variant. */ -#define DECL_ALL_VLDX_LANE(X) \ +#define DECL_ALL_VLDX_LANE_NO_FP16(X) \ DECL_VLDX_LANE(int, 8, 8, X); \ DECL_VLDX_LANE(int, 16, 4, X); \ DECL_VLDX_LANE(int, 32, 2, X); \ @@ -338,6 +374,15 @@ void exec_vldX_lane (void) DECL_VLDX_LANE(float, 32, 2, X); \ DECL_VLDX_LANE(float, 32, 4, X) +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +#define DECL_ALL_VLDX_LANE(X) \ + DECL_ALL_VLDX_LANE_NO_FP16(X); \ + DECL_VLDX_LANE(float, 16, 4, X); \ + DECL_VLDX_LANE(float, 16, 8, X) +#else +#define DECL_ALL_VLDX_LANE(X) DECL_ALL_VLDX_LANE_NO_FP16(X) +#endif + /* Add some padding to try to catch out of bound accesses. */ #define ARRAY1(V, T, W, N) VECT_VAR_DECL(V,T,W,N)[1]={42} #define DUMMY_ARRAY(V, T, W, N, L) \ @@ -346,7 +391,7 @@ void exec_vldX_lane (void) /* Use the same lanes regardless of the size of the array (X), for simplicity. */ -#define TEST_ALL_VLDX_LANE(X) \ +#define TEST_ALL_VLDX_LANE_NO_FP16(X) \ TEST_VLDX_LANE(, int, s, 8, 8, X, 7); \ TEST_VLDX_LANE(, int, s, 16, 4, X, 2); \ TEST_VLDX_LANE(, int, s, 32, 2, X, 0); \ @@ -363,7 +408,16 @@ void exec_vldX_lane (void) TEST_VLDX_LANE(, float, f, 32, 2, X, 0); \ TEST_VLDX_LANE(q, float, f, 32, 4, X, 2) -#define TEST_ALL_EXTRA_CHUNKS(X, Y) \ +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +#define TEST_ALL_VLDX_LANE(X) \ + TEST_ALL_VLDX_LANE_NO_FP16(X); \ + TEST_VLDX_LANE(, float, f, 16, 4, X, 2); \ + TEST_VLDX_LANE(q, float, f, 16, 8, X, 6) +#else +#define TEST_ALL_VLDX_LANE(X) TEST_ALL_VLDX_LANE_NO_FP16(X) +#endif + +#define TEST_ALL_EXTRA_CHUNKS_NO_FP16(X,Y) \ TEST_EXTRA_CHUNK(int, 8, 8, X, Y); \ TEST_EXTRA_CHUNK(int, 16, 4, X, Y); \ TEST_EXTRA_CHUNK(int, 32, 2, X, Y); \ @@ -380,9 +434,17 @@ void exec_vldX_lane (void) TEST_EXTRA_CHUNK(float, 32, 2, X, Y); \ TEST_EXTRA_CHUNK(float, 32, 4, X, Y) +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +#define TEST_ALL_EXTRA_CHUNKS(X,Y) \ + TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y); \ + TEST_EXTRA_CHUNK(float, 16, 4, X, Y); \ + TEST_EXTRA_CHUNK(float, 16, 8, X, Y) +#else +#define TEST_ALL_EXTRA_CHUNKS(X,Y) TEST_ALL_EXTRA_CHUNKS_NO_FP16(X, Y) +#endif + /* vldX_lane supports only a subset of all variants. */ -#define CHECK_RESULTS_VLDX_LANE(test_name,EXPECTED,comment) \ - { \ +#define CHECK_RESULTS_VLDX_LANE_NO_FP16(test_name,EXPECTED,comment) \ CHECK(test_name, int, 8, 8, PRIx8, EXPECTED, comment); \ CHECK(test_name, int, 16, 4, PRIx16, EXPECTED, comment); \ CHECK(test_name, int, 32, 2, PRIx32, EXPECTED, comment); \ @@ -397,8 +459,21 @@ void exec_vldX_lane (void) CHECK(test_name, uint, 16, 8, PRIx16, EXPECTED, comment); \ CHECK(test_name, uint, 32, 4, PRIx32, EXPECTED, comment); \ CHECK(test_name, poly, 16, 8, PRIx16, EXPECTED, comment); \ - CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment); \ - } \ + CHECK_FP(test_name, float, 32, 4, PRIx32, EXPECTED, comment) + +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +#define CHECK_RESULTS_VLDX_LANE(test_name,EXPECTED,comment) \ + { \ + CHECK_RESULTS_VLDX_LANE_NO_FP16(test_name,EXPECTED,comment); \ + CHECK_FP(test_name, float, 16, 4, PRIx16, EXPECTED, comment); \ + CHECK_FP(test_name, float, 16, 8, PRIx16, EXPECTED, comment); \ + } +#else +#define CHECK_RESULTS_VLDX_LANE(test_name,EXPECTED,comment) \ + { \ + CHECK_RESULTS_VLDX_LANE_NO_FP16(test_name,EXPECTED,comment); \ + } +#endif /* Declare the temporary buffers / variables. */ DECL_ALL_VLDX_LANE(2); @@ -419,6 +494,10 @@ void exec_vldX_lane (void) DUMMY_ARRAY(buffer_src, uint, 16, 8, 4); DUMMY_ARRAY(buffer_src, uint, 32, 4, 4); DUMMY_ARRAY(buffer_src, poly, 16, 8, 4); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + DUMMY_ARRAY(buffer_src, float, 16, 4, 4); + DUMMY_ARRAY(buffer_src, float, 16, 8, 4); +#endif DUMMY_ARRAY(buffer_src, float, 32, 2, 4); DUMMY_ARRAY(buffer_src, float, 32, 4, 4); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c index 51594068364..e0499df5170 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vset_lane.c @@ -16,6 +16,7 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0x88 }; VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0x55, 0xf7 }; VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff0, 0xfff1, 0x66, 0xfff3 }; +VECT_VAR_DECL(expected,hfloat,16,4) [] = { 0xcc00, 0xcb80, 0x4840, 0xca80 }; VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1800000, 0x4204cccd }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, @@ -41,6 +42,8 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xf0, 0xf1, 0xf2, 0xf3, 0xfc, 0xfd, 0xdd, 0xff }; VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, 0xfff4, 0xfff5, 0xee, 0xfff7 }; +VECT_VAR_DECL(expected,hfloat,16,8) [] = { 0xcc00, 0xcb80, 0xcb00, 0xca80, + 0xca00, 0x4480, 0xc900, 0xc880 }; VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1800000, 0xc1700000, 0xc1600000, 0x41333333 }; @@ -61,6 +64,10 @@ void exec_vset_lane (void) /* Initialize input "vector" from "buffer". */ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + VLOAD(vector, buffer, , float, f, 16, 4); + VLOAD(vector, buffer, q, float, f, 16, 8); +#endif VLOAD(vector, buffer, , float, f, 32, 2); VLOAD(vector, buffer, q, float, f, 32, 4); @@ -75,6 +82,9 @@ void exec_vset_lane (void) TEST_VSET_LANE(, uint, u, 64, 1, 0x88, 0); TEST_VSET_LANE(, poly, p, 8, 8, 0x55, 6); TEST_VSET_LANE(, poly, p, 16, 4, 0x66, 2); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VSET_LANE(, float, f, 16, 4, 8.5f, 2); +#endif TEST_VSET_LANE(, float, f, 32, 2, 33.2f, 1); TEST_VSET_LANE(q, int, s, 8, 16, 0x99, 15); @@ -87,6 +97,9 @@ void exec_vset_lane (void) TEST_VSET_LANE(q, uint, u, 64, 2, 0x11, 1); TEST_VSET_LANE(q, poly, p, 8, 16, 0xDD, 14); TEST_VSET_LANE(q, poly, p, 16, 8, 0xEE, 6); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VSET_LANE(q, float, f, 16, 8, 4.5f, 5); +#endif TEST_VSET_LANE(q, float, f, 32, 4, 11.2f, 3); CHECK_RESULTS(TEST_MSG, ""); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c index 08583b88cf3..825d07dbf77 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c @@ -16,6 +16,7 @@ VECT_VAR_DECL(expected,uint,64,1) [] = { 0xfffffffffffffff0 }; VECT_VAR_DECL(expected,poly,8,8) [] = { 0xf6, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected,poly,16,4) [] = { 0xfff2, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,16,4) [] = { 0xcb80, 0x3333, 0x3333, 0x3333 }; VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc1700000, 0x33333333 }; VECT_VAR_DECL(expected,int,8,16) [] = { 0xff, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, @@ -42,6 +43,8 @@ VECT_VAR_DECL(expected,poly,8,16) [] = { 0xfa, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x33 }; VECT_VAR_DECL(expected,poly,16,8) [] = { 0xfff4, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333 }; +VECT_VAR_DECL(expected,hfloat,16,8) [] = { 0xc900, 0x3333, 0x3333, 0x3333, + 0x3333, 0x3333, 0x3333, 0x3333 }; VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc1700000, 0x33333333, 0x33333333, 0x33333333 }; @@ -69,6 +72,9 @@ void exec_vst1_lane (void) TEST_VST1_LANE(, uint, u, 64, 1, 0); TEST_VST1_LANE(, poly, p, 8, 8, 6); TEST_VST1_LANE(, poly, p, 16, 4, 2); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VST1_LANE(, float, f, 16, 4, 1); +#endif TEST_VST1_LANE(, float, f, 32, 2, 1); TEST_VST1_LANE(q, int, s, 8, 16, 15); @@ -81,6 +87,9 @@ void exec_vst1_lane (void) TEST_VST1_LANE(q, uint, u, 64, 2, 0); TEST_VST1_LANE(q, poly, p, 8, 16, 10); TEST_VST1_LANE(q, poly, p, 16, 8, 4); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) + TEST_VST1_LANE(q, float, f, 16, 8, 6); +#endif TEST_VST1_LANE(q, float, f, 32, 4, 1); CHECK_RESULTS(TEST_MSG, ""); diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c new file mode 100644 index 00000000000..dbf5241b591 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2_lane_f16 (float16_t * p, float16x4x2_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst2_lane_f16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst2_lane_f16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c new file mode 100644 index 00000000000..e3c0296534b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst2q_lane_f16 (float16_t * p, float16x8x2_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_f16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst2q_lane_f16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c new file mode 100644 index 00000000000..406dfd410a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3_lane_f16 (float16_t * p, float16x4x3_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst3_lane_f16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst3_lane_f16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c new file mode 100644 index 00000000000..4e8b24cff8a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst3q_lane_f16 (float16_t * p, float16x8x3_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_f16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst3q_lane_f16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c new file mode 100644 index 00000000000..0fe65116712 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4_lane_f16 (float16_t * p, float16x4x4_t v) +{ + /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst4_lane_f16 (p, v, 4); + /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */ + vst4_lane_f16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c new file mode 100644 index 00000000000..9a5f09aa5fa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c @@ -0,0 +1,15 @@ +#include <arm_neon.h> + +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-excess-errors "" { xfail arm*-*-* } } */ + +void +f_vst4q_lane_f16 (float16_t * p, float16x8x4_t v) +{ + /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_f16 (p, v, 8); + /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */ + vst4q_lane_f16 (p, v, -1); + return; +} diff --git a/gcc/testsuite/gcc.target/aarch64/arm_align_max_pwr.c b/gcc/testsuite/gcc.target/aarch64/arm_align_max_pwr.c index bbb4c6f9d04..ffa4d229922 100644 --- a/gcc/testsuite/gcc.target/aarch64/arm_align_max_pwr.c +++ b/gcc/testsuite/gcc.target/aarch64/arm_align_max_pwr.c @@ -1,15 +1,23 @@ -/* { dg-do run } */ - -#include <stdio.h> -#include <assert.h> +/* { dg-do compile } */ +/* { dg-options "-O1" } */ #define align (1ul << __ARM_ALIGN_MAX_PWR) static int x __attribute__ ((aligned (align))); +static int y __attribute__ ((aligned (align))); + +extern void foo (int *x, int *y); +extern int bar (int x, int y); int -main () +dummy () { - assert ((((unsigned long)&x) & (align - 1)) == 0); + int result; - return 0; + foo (&x, &y); + result = bar (x, y); + + return result; } + +/* { dg-final { scan-assembler-times "zero\t4" 2 } } */ +/* { dg-final { scan-assembler "zero\t268435452" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/arm_align_max_stack_pwr.c b/gcc/testsuite/gcc.target/aarch64/arm_align_max_stack_pwr.c index 7a6355b054e..7f356fe300a 100644 --- a/gcc/testsuite/gcc.target/aarch64/arm_align_max_stack_pwr.c +++ b/gcc/testsuite/gcc.target/aarch64/arm_align_max_stack_pwr.c @@ -1,15 +1,20 @@ -/* { dg-do run } */ - -#include <stdio.h> -#include <assert.h> +/* { dg-do compile } */ +/* { dg-options "-O1" } */ #define align (1ul << __ARM_ALIGN_MAX_STACK_PWR) +extern void foo (int *x); +extern int bar (int x); int -main () +dummy () { int x __attribute__ ((aligned (align))); + int result; + + foo (&x); + result = bar (x); - assert ((((unsigned long)&x) & (align - 1)) == 0); - return 0; + return result; } + +/* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -65536" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/mod_2.c b/gcc/testsuite/gcc.target/aarch64/mod_2.c new file mode 100644 index 00000000000..2645c18e741 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/mod_2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=cortex-a57 -save-temps" } */ + +#include "mod_2.x" + +/* { dg-final { scan-assembler "csneg\t\[wx\]\[0-9\]*" } } */ +/* { dg-final { scan-assembler-times "and\t\[wx\]\[0-9\]*" 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/mod_2.x b/gcc/testsuite/gcc.target/aarch64/mod_2.x new file mode 100644 index 00000000000..2b079a4b883 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/mod_2.x @@ -0,0 +1,5 @@ +int +f (int x) +{ + return x % 2; +} diff --git a/gcc/testsuite/gcc.target/aarch64/mod_256.c b/gcc/testsuite/gcc.target/aarch64/mod_256.c new file mode 100644 index 00000000000..567332c04e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/mod_256.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=cortex-a57 -save-temps" } */ + +#include "mod_256.x" + +/* { dg-final { scan-assembler "csneg\t\[wx\]\[0-9\]*" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/mod_256.x b/gcc/testsuite/gcc.target/aarch64/mod_256.x new file mode 100644 index 00000000000..c1de42ce389 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/mod_256.x @@ -0,0 +1,5 @@ +int +f (int x) +{ + return x % 256; +} diff --git a/gcc/testsuite/gcc.target/aarch64/pic-small.c b/gcc/testsuite/gcc.target/aarch64/pic-small.c index 282e4d073c0..2ea056af27d 100644 --- a/gcc/testsuite/gcc.target/aarch64/pic-small.c +++ b/gcc/testsuite/gcc.target/aarch64/pic-small.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-effective-target aarch64_small_fpic } */ /* { dg-options "-O2 -fpic -fno-inline --save-temps" } */ +/* { dg-skip-if "-fpic for AArch64 small code model" { aarch64*-*-* } { "-mcmodel=tiny" "-mcmodel=large" } { "" } } */ void abort (); int global_a; diff --git a/gcc/testsuite/gcc.target/aarch64/vget_high_1.c b/gcc/testsuite/gcc.target/aarch64/vget_high_1.c index 4cb872da2cd..b6b57e0c546 100644 --- a/gcc/testsuite/gcc.target/aarch64/vget_high_1.c +++ b/gcc/testsuite/gcc.target/aarch64/vget_high_1.c @@ -14,6 +14,7 @@ VARIANT (int8_t, 8, int8x8_t, int8x16_t, s8) \ VARIANT (int16_t, 4, int16x4_t, int16x8_t, s16) \ VARIANT (int32_t, 2, int32x2_t, int32x4_t, s32) \ VARIANT (int64_t, 1, int64x1_t, int64x2_t, s64) \ +VARIANT (float16_t, 4, float16x4_t, float16x8_t, f16) \ VARIANT (float32_t, 2, float32x2_t, float32x4_t, f32) \ VARIANT (float64_t, 1, float64x1_t, float64x2_t, f64) @@ -51,6 +52,8 @@ main (int argc, char **argv) int16_t int16_t_data[8] = { -17, 19, 3, -999, 44048, 505, 9999, 1000}; int32_t int32_t_data[4] = { 123456789, -987654321, -135792468, 975318642 }; int64_t int64_t_data[2] = {0xfedcba9876543210LL, 0xdeadbabecafebeefLL }; + float16_t float16_t_data[8] = { 1.25, 4.5, 7.875, 2.3125, 5.675, 8.875, + 3.6875, 6.75}; float32_t float32_t_data[4] = { 3.14159, 2.718, 1.414, 100.0 }; float64_t float64_t_data[2] = { 1.01001000100001, 12345.6789 }; diff --git a/gcc/testsuite/gcc.target/aarch64/vget_low_1.c b/gcc/testsuite/gcc.target/aarch64/vget_low_1.c index f8016ef7312..2223676521c 100644 --- a/gcc/testsuite/gcc.target/aarch64/vget_low_1.c +++ b/gcc/testsuite/gcc.target/aarch64/vget_low_1.c @@ -14,6 +14,7 @@ VARIANT (int8_t, 8, int8x8_t, int8x16_t, s8) \ VARIANT (int16_t, 4, int16x4_t, int16x8_t, s16) \ VARIANT (int32_t, 2, int32x2_t, int32x4_t, s32) \ VARIANT (int64_t, 1, int64x1_t, int64x2_t, s64) \ +VARIANT (float16_t, 4, float16x4_t, float16x8_t, f16) \ VARIANT (float32_t, 2, float32x2_t, float32x4_t, f32) \ VARIANT (float64_t, 1, float64x1_t, float64x2_t, f64) @@ -51,6 +52,8 @@ main (int argc, char **argv) int16_t int16_t_data[8] = { -17, 19, 3, -999, 44048, 505, 9999, 1000}; int32_t int32_t_data[4] = { 123456789, -987654321, -135792468, 975318642 }; int64_t int64_t_data[2] = {0xfedcba9876543210LL, 0xdeadbabecafebeefLL }; + float16_t float16_t_data[8] = { 1.25, 4.5, 7.875, 2.3125, 5.675, 8.875, + 3.6875, 6.75}; float32_t float32_t_data[4] = { 3.14159, 2.718, 1.414, 100.0 }; float64_t float64_t_data[2] = { 1.01001000100001, 12345.6789 }; diff --git a/gcc/testsuite/gcc.target/aarch64/vld1-vst1_1.c b/gcc/testsuite/gcc.target/aarch64/vld1-vst1_1.c index f8c6edb3bcf..fa9ef0f4e43 100644 --- a/gcc/testsuite/gcc.target/aarch64/vld1-vst1_1.c +++ b/gcc/testsuite/gcc.target/aarch64/vld1-vst1_1.c @@ -31,6 +31,7 @@ THING (int8x8_t, 8, int8_t, _s8) \ THING (uint8x8_t, 8, uint8_t, _u8) \ THING (int16x4_t, 4, int16_t, _s16) \ THING (uint16x4_t, 4, uint16_t, _u16) \ +THING (float16x4_t, 4, float16_t, _f16) \ THING (int32x2_t, 2, int32_t, _s32) \ THING (uint32x2_t, 2, uint32_t, _u32) \ THING (float32x2_t, 2, float32_t, _f32) \ @@ -38,6 +39,7 @@ THING (int8x16_t, 16, int8_t, q_s8) \ THING (uint8x16_t, 16, uint8_t, q_u8) \ THING (int16x8_t, 8, int16_t, q_s16) \ THING (uint16x8_t, 8, uint16_t, q_u16) \ +THING (float16x8_t, 8, float16_t, q_f16)\ THING (int32x4_t, 4, int32_t, q_s32) \ THING (uint32x4_t, 4, uint32_t, q_u32) \ THING (float32x4_t, 4, float32_t, q_f32)\ diff --git a/gcc/testsuite/gcc.target/aarch64/vld1_lane.c b/gcc/testsuite/gcc.target/aarch64/vld1_lane.c index 463c88c0a5f..c70df7135c1 100644 --- a/gcc/testsuite/gcc.target/aarch64/vld1_lane.c +++ b/gcc/testsuite/gcc.target/aarch64/vld1_lane.c @@ -16,6 +16,7 @@ VARIANT (int32, , 2, _s32, 0) \ VARIANT (int64, , 1, _s64, 0) \ VARIANT (poly8, , 8, _p8, 7) \ VARIANT (poly16, , 4, _p16, 2) \ +VARIANT (float16, , 4, _f16, 3) \ VARIANT (float32, , 2, _f32, 1) \ VARIANT (float64, , 1, _f64, 0) \ VARIANT (uint8, q, 16, _u8, 13) \ @@ -28,6 +29,7 @@ VARIANT (int32, q, 4, _s32, 1) \ VARIANT (int64, q, 2, _s64, 1) \ VARIANT (poly8, q, 16, _p8, 7) \ VARIANT (poly16, q, 8, _p16, 4) \ +VARIANT (float16, q, 8, _f16, 3)\ VARIANT (float32, q, 4, _f32, 2)\ VARIANT (float64, q, 2, _f64, 1) @@ -76,6 +78,7 @@ main (int argc, char **argv) int64_t int64_data = 0x1234567890abcdefLL; poly8_t poly8_data = 13; poly16_t poly16_data = 11111; + float16_t float16_data = 8.75; float32_t float32_data = 3.14159; float64_t float64_data = 1.010010001; diff --git a/gcc/testsuite/gcc.target/aarch64/vldN_1.c b/gcc/testsuite/gcc.target/aarch64/vldN_1.c index b64de16a165..caac94f86ce 100644 --- a/gcc/testsuite/gcc.target/aarch64/vldN_1.c +++ b/gcc/testsuite/gcc.target/aarch64/vldN_1.c @@ -39,6 +39,7 @@ VARIANT (int32, 2, STRUCT, _s32) \ VARIANT (int64, 1, STRUCT, _s64) \ VARIANT (poly8, 8, STRUCT, _p8) \ VARIANT (poly16, 4, STRUCT, _p16) \ +VARIANT (float16, 4, STRUCT, _f16) \ VARIANT (float32, 2, STRUCT, _f32) \ VARIANT (float64, 1, STRUCT, _f64) \ VARIANT (uint8, 16, STRUCT, q_u8) \ @@ -51,6 +52,7 @@ VARIANT (int32, 4, STRUCT, q_s32) \ VARIANT (int64, 2, STRUCT, q_s64) \ VARIANT (poly8, 16, STRUCT, q_p8) \ VARIANT (poly16, 8, STRUCT, q_p16) \ +VARIANT (float16, 8, STRUCT, q_f16) \ VARIANT (float32, 4, STRUCT, q_f32) \ VARIANT (float64, 2, STRUCT, q_f64) diff --git a/gcc/testsuite/gcc.target/aarch64/vldN_dup_1.c b/gcc/testsuite/gcc.target/aarch64/vldN_dup_1.c index 9af0565d617..68c3fc34f5a 100644 --- a/gcc/testsuite/gcc.target/aarch64/vldN_dup_1.c +++ b/gcc/testsuite/gcc.target/aarch64/vldN_dup_1.c @@ -16,6 +16,7 @@ VARIANT (int32, , 2, _s32, STRUCT) \ VARIANT (int64, , 1, _s64, STRUCT) \ VARIANT (poly8, , 8, _p8, STRUCT) \ VARIANT (poly16, , 4, _p16, STRUCT) \ +VARIANT (float16, , 4, _f16, STRUCT) \ VARIANT (float32, , 2, _f32, STRUCT) \ VARIANT (float64, , 1, _f64, STRUCT) \ VARIANT (uint8, q, 16, _u8, STRUCT) \ @@ -28,6 +29,7 @@ VARIANT (int32, q, 4, _s32, STRUCT) \ VARIANT (int64, q, 2, _s64, STRUCT) \ VARIANT (poly8, q, 16, _p8, STRUCT) \ VARIANT (poly16, q, 8, _p16, STRUCT) \ +VARIANT (float16, q, 8, _f16, STRUCT) \ VARIANT (float32, q, 4, _f32, STRUCT) \ VARIANT (float64, q, 2, _f64, STRUCT) @@ -74,6 +76,7 @@ main (int argc, char **argv) int64_t *int64_data = (int64_t *)uint64_data; poly8_t poly8_data[4] = { 0, 7, 13, 18, }; poly16_t poly16_data[4] = { 11111, 2222, 333, 44 }; + float16_t float16_data[4] = { 1.0625, 3.125, 0.03125, 7.75 }; float32_t float32_data[4] = { 3.14159, 2.718, 1.414, 100.0 }; float64_t float64_data[4] = { 1.010010001, 12345.6789, -9876.54321, 1.618 }; diff --git a/gcc/testsuite/gcc.target/aarch64/vldN_lane_1.c b/gcc/testsuite/gcc.target/aarch64/vldN_lane_1.c index 13ab45459f4..6837a116117 100644 --- a/gcc/testsuite/gcc.target/aarch64/vldN_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/vldN_lane_1.c @@ -16,6 +16,7 @@ VARIANT (int32, , 2, _s32, 0, STRUCT) \ VARIANT (int64, , 1, _s64, 0, STRUCT) \ VARIANT (poly8, , 8, _p8, 7, STRUCT) \ VARIANT (poly16, , 4, _p16, 1, STRUCT) \ +VARIANT (float16, , 4, _f16, 3, STRUCT) \ VARIANT (float32, , 2, _f32, 1, STRUCT) \ VARIANT (float64, , 1, _f64, 0, STRUCT) \ VARIANT (uint8, q, 16, _u8, 14, STRUCT) \ @@ -28,6 +29,7 @@ VARIANT (int32, q, 4, _s32, 2, STRUCT) \ VARIANT (int64, q, 2, _s64, 1, STRUCT) \ VARIANT (poly8, q, 16, _p8, 12, STRUCT) \ VARIANT (poly16, q, 8, _p16, 5, STRUCT) \ +VARIANT (float16, q, 8, _f16, 7, STRUCT)\ VARIANT (float32, q, 4, _f32, 1, STRUCT)\ VARIANT (float64, q, 2, _f64, 0, STRUCT) @@ -71,7 +73,7 @@ main (int argc, char **argv) { /* Original data for all vector formats. */ uint64_t orig_data[8] = {0x1234567890abcdefULL, 0x13579bdf02468aceULL, - 0x012389ab4567cdefULL, 0xfeeddadacafe0431ULL, + 0x012389ab4567cdefULL, 0xdeeddadacafe0431ULL, 0x1032547698badcfeULL, 0xbadbadbadbad0badULL, 0x0102030405060708ULL, 0x0f0e0d0c0b0a0908ULL}; @@ -87,6 +89,7 @@ main (int argc, char **argv) int64_t *int64_data = (int64_t *)uint64_data; poly8_t poly8_data[4] = { 0, 7, 13, 18, }; poly16_t poly16_data[4] = { 11111, 2222, 333, 44 }; + float16_t float16_data[4] = { 0.8125, 7.5, 19, 0.046875 }; float32_t float32_data[4] = { 3.14159, 2.718, 1.414, 100.0 }; float64_t float64_data[4] = { 1.010010001, 12345.6789, -9876.54321, 1.618 }; diff --git a/gcc/testsuite/gcc.target/aarch64/vset_lane_1.c b/gcc/testsuite/gcc.target/aarch64/vset_lane_1.c index 5fb11399f20..bc0132c20a7 100644 --- a/gcc/testsuite/gcc.target/aarch64/vset_lane_1.c +++ b/gcc/testsuite/gcc.target/aarch64/vset_lane_1.c @@ -16,6 +16,7 @@ VARIANT (int32_t, , 2, int32x2_t, _s32, 0) \ VARIANT (int64_t, , 1, int64x1_t, _s64, 0) \ VARIANT (poly8_t, , 8, poly8x8_t, _p8, 6) \ VARIANT (poly16_t, , 4, poly16x4_t, _p16, 2) \ +VARIANT (float16_t, , 4, float16x4_t, _f16, 3) \ VARIANT (float32_t, , 2, float32x2_t, _f32, 1) \ VARIANT (float64_t, , 1, float64x1_t, _f64, 0) \ VARIANT (uint8_t, q, 16, uint8x16_t, _u8, 11) \ @@ -28,6 +29,7 @@ VARIANT (int32_t, q, 4, int32x4_t, _s32, 3) \ VARIANT (int64_t, q, 2, int64x2_t, _s64, 0) \ VARIANT (poly8_t, q, 16, poly8x16_t, _p8, 14) \ VARIANT (poly16_t, q, 8, poly16x8_t, _p16, 6) \ +VARIANT (float16_t, q, 8, float16x8_t, _f16, 6) \ VARIANT (float32_t, q, 4, float32x4_t, _f32, 2) \ VARIANT (float64_t, q, 2, float64x2_t, _f64, 1) @@ -76,6 +78,9 @@ main (int argc, char **argv) poly8_t poly8_t_data[16] = { 0, 7, 13, 18, 22, 25, 27, 28, 29, 31, 34, 38, 43, 49, 56, 64 }; poly16_t poly16_t_data[8] = { 11111, 2222, 333, 44, 5, 65432, 54321, 43210 }; + float16_t float16_t_data[8] = { 1.25, 4.5, 7.875, 2.3125, 5.675, 8.875, + 3.6875, 6.75}; + float32_t float32_t_data[4] = { 3.14159, 2.718, 1.414, 100.0 }; float64_t float64_t_data[2] = { 1.01001000100001, 12345.6789 }; diff --git a/gcc/testsuite/gcc.target/arm/mod_2.c b/gcc/testsuite/gcc.target/arm/mod_2.c new file mode 100644 index 00000000000..93017a10683 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mod_2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O2 -mcpu=cortex-a57 -save-temps" } */ + +#include "../aarch64/mod_2.x" + +/* { dg-final { scan-assembler "rsblt\tr\[0-9\]*" } } */ +/* { dg-final { scan-assembler-times "and\tr\[0-9\].*1" 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mod_256.c b/gcc/testsuite/gcc.target/arm/mod_256.c new file mode 100644 index 00000000000..ccb7f3cf68d --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mod_256.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm32 } */ +/* { dg-options "-O2 -mcpu=cortex-a57 -save-temps" } */ + +#include "../aarch64/mod_256.x" + +/* { dg-final { scan-assembler "rsbpl\tr\[0-9\]*" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/pr63210.c b/gcc/testsuite/gcc.target/arm/pr63210.c index c3ae92801f5..9b63a67d3f0 100644 --- a/gcc/testsuite/gcc.target/arm/pr63210.c +++ b/gcc/testsuite/gcc.target/arm/pr63210.c @@ -1,6 +1,8 @@ /* { dg-do assemble } */ /* { dg-options "-mthumb -Os " } */ /* { dg-require-effective-target arm_thumb1_ok } */ +/* { dg-skip-if "do not test on armv4t" { *-*-* } { "-march=armv4t" } } */ +/* { dg-additional-options "-march=armv5t" {target arm_arch_v5t_ok} } */ int foo1 (int c); int foo2 (int c); diff --git a/gcc/testsuite/gcc.target/arm/pr67439_1.c b/gcc/testsuite/gcc.target/arm/pr67439_1.c new file mode 100644 index 00000000000..f7a6128758a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr67439_1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_thumb2_ok } */ +/* { dg-options "-O1 -mfp16-format=ieee -march=armv7-a -mfpu=neon -mthumb -mrestrict-it" } */ + +__fp16 h0 = -1.0; + +void +f (__fp16 *p) +{ + h0 = 1.0; +} diff --git a/gcc/testsuite/gcc.target/avr/pr65210.c b/gcc/testsuite/gcc.target/avr/pr65210.c new file mode 100644 index 00000000000..1aed4417c1f --- /dev/null +++ b/gcc/testsuite/gcc.target/avr/pr65210.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ + +/* This testcase exposes PR65210. Usage of the io_low attribute + causes assertion failure because code only looks for the io + attribute if SYMBOL_FLAG_IO is set. */ + +volatile char q __attribute__((io_low,address(0x81))); diff --git a/gcc/testsuite/gcc.target/i386/avx512f-scatter-1.c b/gcc/testsuite/gcc.target/i386/avx512f-scatter-1.c new file mode 100644 index 00000000000..575f3bfa70c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-scatter-1.c @@ -0,0 +1,218 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-options "-O3 -mavx512f" } */ + +#define AVX512F + +#include "avx512f-check.h" + +#define N 1024 +float vf1[N], vf2[2*N+16]; +double vd1[N], vd2[2*N+16]; +int vi1[N], vi2[2*N+16], k[N]; +long vl1[N], vl2[2*N+16], l[N]; + +__attribute__((noinline, noclone)) void +f1 (void) +{ + int i; + for (i = 0; i < N; i++) + vf2[k[i]] = vf1[i]; +} + +__attribute__((noinline, noclone)) void +f2 (void) +{ + int i; + for (i = 0; i < N; i++) + vi2[k[i]] = vi1[i]; +} + +__attribute__((noinline, noclone)) void +f3 (int x) +{ + int i; + for (i = 0; i < N; i++) + vf2[k[i] + x] = vf1[i]; +} + +__attribute__((noinline, noclone)) void +f4 (int x) +{ + int i; + for (i = 0; i < N; i++) + vi2[k[i] + x] = vi1[i]; +} + +__attribute__((noinline, noclone)) void +f5 (void) +{ + int i; + for (i = 0; i < N; i++) + vd2[k[i]] = vd1[i]; +} + +__attribute__((noinline, noclone)) void +f6 (void) +{ + int i; + for (i = 0; i < N; i++) + vl2[k[i]] = vl1[i]; +} + +__attribute__((noinline, noclone)) void +f7 (int x) +{ + int i; + for (i = 0; i < N; i++) + vd2[k[i] + x] = vd1[i]; +} + +__attribute__((noinline, noclone)) void +f8 (int x) +{ + int i; + for (i = 0; i < N; i++) + vl2[k[i] + x] = vl1[i]; +} + +__attribute__((noinline, noclone)) void +f9 (void) +{ + int i; + for (i = 0; i < N; i++) + vf2[l[i]] = vf1[i]; +} + +__attribute__((noinline, noclone)) void +f10 (void) +{ + int i; + for (i = 0; i < N; i++) + vi2[l[i]] = vi1[i]; +} + +__attribute__((noinline, noclone)) void +f11 (long x) +{ + int i; + for (i = 0; i < N; i++) + vf2[l[i] + x] = vf1[i]; +} + +__attribute__((noinline, noclone)) void +f12 (long x) +{ + int i; + for (i = 0; i < N; i++) + vi2[l[i] + x] = vi1[i]; +} + +__attribute__((noinline, noclone)) void +f13 (void) +{ + int i; + for (i = 0; i < N; i++) + vd2[l[i]] = vd1[i]; +} + +__attribute__((noinline, noclone)) void +f14 (void) +{ + int i; + for (i = 0; i < N; i++) + vl2[l[i]] = vl1[i]; +} + +__attribute__((noinline, noclone)) void +f15 (long x) +{ + int i; + for (i = 0; i < N; i++) + vd2[l[i] + x] = vd1[i]; +} + +__attribute__((noinline, noclone)) void +f16 (long x) +{ + int i; + for (i = 0; i < N; i++) + vl2[l[i] + x] = vl1[i]; +} + +static void +avx512f_test (void) +{ + int i; + + for (i = 0; i < N; i++) + { + asm (""); + vf1[i] = 17.0f + i; + vd1[i] = 19.0 + i; + vi1[i] = 21 + i; + vl1[i] = 23L + i; + } + for (i = 0; i < N; i++) + { + asm (""); + k[i] = (i % 2) ? (N / 2 + i) : (N / 2 - i / 2); + l[i] = 2 * i + i % 2; + } + + f1 (); + f2 (); + for (i = 0; i < N; i++) + if (vf2[(i % 2) ? (N / 2 + i) : (N / 2 - i / 2)] != i + 17 + || vi2[(i % 2) ? (N / 2 + i) : (N / 2 - i / 2)] != i + 21) + abort (); + + f3 (12); + f4 (14); + for (i = 0; i < N; i++) + if (vf2[((i % 2) ? (N / 2 + i) : (N / 2 - i / 2)) + 12] != i + 17 + || vi2[((i % 2) ? (N / 2 + i) : (N / 2 - i / 2)) + 14] != i + 21) + abort (); + + f5 (); + f6 (); + for (i = 0; i < N; i++) + if (vd2[(i % 2) ? (N / 2 + i) : (N / 2 - i / 2)] != i + 19 + || vl2[(i % 2) ? (N / 2 + i) : (N / 2 - i / 2)] != i + 23) + abort (); + + f7 (7); + f8 (9); + for (i = 0; i < N; i++) + if (vd2[((i % 2) ? (N / 2 + i) : (N / 2 - i / 2)) + 7] != i + 19 + || vl2[((i % 2) ? (N / 2 + i) : (N / 2 - i / 2)) + 9] != i + 23) + abort (); + + f9 (); + f10 (); + for (i = 0; i < N; i++) + if (vf2[2 * i + i % 2] != i + 17 + || vi2[2 * i + i % 2] != i + 21) + abort (); + + f11 (2); + f12 (4); + for (i = 0; i < N; i++) + if (vf2[2 * i + i % 2 + 2] != i + 17 + || vi2[2 * i + i % 2 + 4] != i + 21) + abort (); + + f13 (); + f14 (); + for (i = 0; i < N; i++) + if (vd2[2 * i + i % 2] != i + 19 + || vl2[2 * i + i % 2] != i + 23) + abort (); + + f15 (13); + f16 (15); + for (i = 0; i < N; i++) + if (vd2[2 * i + i % 2 + 13] != i + 19 + || vl2[2 * i + i % 2 + 15] != i + 23) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-scatter-2.c b/gcc/testsuite/gcc.target/i386/avx512f-scatter-2.c new file mode 100644 index 00000000000..c59ce234f17 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-scatter-2.c @@ -0,0 +1,217 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-options "-O3 -mavx512f" } */ + +#define AVX512F + +#include "avx512f-check.h" + +#define N 1024 +float vf1[N], vf2[2*N+16]; +double vd1[N], vd2[2*N+16]; +int k[N]; +long l[N]; +short n[2*N+16]; + +__attribute__((noinline, noclone)) void +f1 (void) +{ + int i; + for (i = 0; i < N; i++) + vf2[k[i]] = vf1[i]; +} + +__attribute__((noinline, noclone)) void +f2 (void) +{ + int i; + for (i = 0; i < N; i++) + n[k[i]] = (int) vf1[i]; +} + +__attribute__((noinline, noclone)) void +f3 (int x) +{ + int i; + for (i = 0; i < N; i++) + vf2[k[i] + x] = vf1[i]; +} + +__attribute__((noinline, noclone)) void +f4 (int x) +{ + int i; + for (i = 0; i < N; i++) + n[k[i] + x] = (int) vf1[i]; +} + +__attribute__((noinline, noclone)) void +f5 (void) +{ + int i; + for (i = 0; i < N; i++) + vd2[k[i]] = vd1[i]; +} + +__attribute__((noinline, noclone)) void +f6 (void) +{ + int i; + for (i = 0; i < N; i++) + n[k[i]] = (int) vd1[i]; +} + +__attribute__((noinline, noclone)) void +f7 (int x) +{ + int i; + for (i = 0; i < N; i++) + vd2[k[i] + x] = vd1[i]; +} + +__attribute__((noinline, noclone)) void +f8 (int x) +{ + int i; + for (i = 0; i < N; i++) + n[k[i] + x] = vd1[i]; +} + +__attribute__((noinline, noclone)) void +f9 (void) +{ + int i; + for (i = 0; i < N; i++) + vf2[l[i]] = vf1[i]; +} + +__attribute__((noinline, noclone)) void +f10 (void) +{ + int i; + for (i = 0; i < N; i++) + n[l[i]] = (int) vf1[i]; +} + +__attribute__((noinline, noclone)) void +f11 (long x) +{ + int i; + for (i = 0; i < N; i++) + vf2[l[i] + x] = vf1[i]; +} + +__attribute__((noinline, noclone)) void +f12 (long x) +{ + int i; + for (i = 0; i < N; i++) + n[l[i] + x] = (int) vf1[i]; +} + +__attribute__((noinline, noclone)) void +f13 (void) +{ + int i; + for (i = 0; i < N; i++) + vd2[l[i]] = vd1[i]; +} + +__attribute__((noinline, noclone)) void +f14 (void) +{ + int i; + for (i = 0; i < N; i++) + n[l[i]] = (int) vd1[i]; +} + +__attribute__((noinline, noclone)) void +f15 (long x) +{ + int i; + for (i = 0; i < N; i++) + vd2[l[i] + x] = vd1[i]; +} + +__attribute__((noinline, noclone)) void +f16 (long x) +{ + int i; + for (i = 0; i < N; i++) + n[l[i] + x] = (int) vd1[i]; +} + +static void +avx512f_test (void) +{ + int i; + + for (i = 0; i < N; i++) + { + asm (""); + vf1[i] = 17.0f + i; + vd1[i] = 19.0 + i; + } + for (i = 0; i < N; i++) + { + asm (""); + k[i] = (i % 2) ? (N / 2 + i) : (N / 2 - i / 2); + l[i] = 2 * i + i % 2; + } + + f1 (); + f2 (); + for (i = 0; i < N; i++) + if (vf2[(i % 2) ? (N / 2 + i) : (N / 2 - i / 2)] != i + 17 + || n[(i % 2) ? (N / 2 + i) : (N / 2 - i / 2)] != i + 17) + abort (); + + f3 (12); + f4 (14); + for (i = 0; i < N; i++) + if (vf2[((i % 2) ? (N / 2 + i) : (N / 2 - i / 2)) + 12] != i + 17 + || n[((i % 2) ? (N / 2 + i) : (N / 2 - i / 2)) + 14] != i + 17) + abort (); + + f5 (); + f6 (); + for (i = 0; i < N; i++) + if (vd2[(i % 2) ? (N / 2 + i) : (N / 2 - i / 2)] != i + 19 + || n[(i % 2) ? (N / 2 + i) : (N / 2 - i / 2)] != i + 19) + abort (); + + f7 (7); + f8 (9); + for (i = 0; i < N; i++) + if (vd2[((i % 2) ? (N / 2 + i) : (N / 2 - i / 2)) + 7] != i + 19 + || n[((i % 2) ? (N / 2 + i) : (N / 2 - i / 2)) + 9] != i + 19) + abort (); + + f9 (); + f10 (); + for (i = 0; i < N; i++) + if (vf2[2 * i + i % 2] != i + 17 + || n[2 * i + i % 2] != i + 17) + abort (); + + f11 (2); + f12 (4); + for (i = 0; i < N; i++) + if (vf2[2 * i + i % 2 + 2] != i + 17 + || n[2 * i + i % 2 + 4] != i + 17) + abort (); + + f13 (); + f14 (); + for (i = 0; i < N; i++) + if (vd2[2 * i + i % 2] != i + 19 + || n[2 * i + i % 2] != i + 19) + abort (); + + f15 (13); + f16 (15); + for (i = 0; i < N; i++) + if (vd2[2 * i + i % 2 + 13] != i + 19 + || n[2 * i + i % 2 + 15] != i + 19) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512f-scatter-3.c b/gcc/testsuite/gcc.target/i386/avx512f-scatter-3.c new file mode 100644 index 00000000000..37137fd268a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-scatter-3.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-options "-O3 -mavx512f" } */ + +#define AVX512F + +#include "avx512f-check.h" + +#define N 1024 +int a[N], b[N]; + +__attribute__((noinline, noclone)) void +foo (float *__restrict p, float *__restrict q, + int s1, int s2, int s3) +{ + int i; + for (i = 0; i < (N / 8); i++) + p[a[i] * s1 + b[i] * s2 + s3] = q[i]; +} + +static void +avx512f_test (void) +{ + int i; + float c[N], d[N]; + for (i = 0; i < N; i++) + { + a[i] = (i * 7) & (N / 8 - 1); + b[i] = (i * 13) & (N / 8 - 1); + c[i] = 179.13 + i; + } + foo (d, c, 3, 2, 4); + for (i = 0; i < (N / 8); i++) + if (d[a[i] * 3 + b[i] * 2 + 4] != (float) (179.13 + i)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c new file mode 100644 index 00000000000..7463781281e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-20.c @@ -0,0 +1,29 @@ +/* { dg-do run { target { powerpc64le-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -mcpu=power8 -maltivec" } */ + +/* The expansion for vector character multiply introduces a vperm operation. + This tests that the swap optimization to remove swaps by changing the + vperm mask results in correct code. */ + +#include <altivec.h> + +void abort (); + +vector unsigned char r; +vector unsigned char v = + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; +vector unsigned char i = + { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 }; +vector unsigned char e = + {0, 2, 6, 12, 20, 30, 42, 56, 72, 90, 110, 132, 156, 182, 210, 240}; + +int main () +{ + int j; + r = v * i; + if (!vec_all_eq (r, e)) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/swaps-p8-21.c b/gcc/testsuite/gcc.target/powerpc/swaps-p8-21.c new file mode 100644 index 00000000000..b981fcf2f36 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/swaps-p8-21.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } +/* { dg-options "-O2 -mcpu=power8 -maltivec" } */ + +/* The expansion for vector character multiply introduces a vperm operation. + This tests that changing the vperm mask allows us to remove all swaps + from the generated code. */ + +#include <altivec.h> + +void abort (); + +vector unsigned char r; +vector unsigned char v = + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; +vector unsigned char i = + { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 }; + +int main () +{ + int j; + r = v * i; + return 0; +} + +/* { dg-final { scan-assembler-times "vperm" 1 } } */ +/* { dg-final { scan-assembler-not "xxpermdi" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mult-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-mult-char-1.c new file mode 100644 index 00000000000..4c9dbdc8188 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-mult-char-1.c @@ -0,0 +1,53 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include <altivec.h> + +extern void abort (void); + +vector unsigned char vmului(vector unsigned char v, + vector unsigned char i) +{ + return v * i; +} + +vector signed char vmulsi(vector signed char v, + vector signed char i) +{ + return v * i; +} + +int main () +{ + vector unsigned char a = {2, 4, 6, 8, 10, 12, 14, 16, + 18, 20, 22, 24, 26, 28, 30, 32}; + vector unsigned char b = {3, 6, 9, 12, 15, 18, 21, 24, + 27, 30, 33, 36, 39, 42, 45, 48}; + vector unsigned char c = vmului (a, b); + vector unsigned char expect_c = {6, 24, 54, 96, 150, 216, 38, 128, + 230, 88, 214, 96, 246, 152, 70, 0}; + + vector signed char d = {2, -4, 6, -8, 10, -12, 14, -16, + 18, -20, 22, -24, 26, -28, 30, -32}; + vector signed char e = {3, 6, -9, -12, 15, 18, -21, -24, + 27, 30, -33, -36, 39, 42, -45, -48}; + vector signed char f = vmulsi (d, e); + vector signed char expect_f = {6, -24, -54, 96, -106, 40, -38, -128, + -26, -88, 42, 96, -10, 104, -70, 0}; + + vector signed char g = {127, -128, 126, -126, 125, -125, 124, -124, + 123, -123, 122, -122, 121, -121, 120, -120}; + vector signed char h = { 2, 2, -2, -2, 127, 127, -128, -128, + 10, 10, -10, -10, 64, 65, -64, -65}; + vector signed char i = vmulsi (g, h); + vector signed char expect_i = {-2, 0, 4, -4, 3, -3, 0, 0, + -50, 50, 60, -60, 64, 71, 0, 120}; + + if (!vec_all_eq (c, expect_c)) + abort (); + if (!vec_all_eq (f, expect_f)) + abort (); + if (!vec_all_eq (i, expect_i)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vec-mult-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-mult-char-2.c new file mode 100644 index 00000000000..04c67109bef --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-mult-char-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include <altivec.h> + +vector unsigned char vmului(vector unsigned char v, + vector unsigned char i) +{ + return v * i; +} + +vector signed char vmulsi(vector signed char v, + vector signed char i) +{ + return v * i; +} + +/* { dg-final { scan-assembler-times "vmulesb" 2 } } */ +/* { dg-final { scan-assembler-times "vmulosb" 2 } } */ +/* { dg-final { scan-assembler-times "vperm" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-shift.c b/gcc/testsuite/gcc.target/powerpc/vec-shift.c new file mode 100644 index 00000000000..80b59a2d3e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec-shift.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ +/* { dg-options "-mcpu=power7 -O2" } */ + +/* This used to ICE. During gimplification, "i" is widened to an unsigned + int. We used to fail at expand time as we tried to cram an SImode item + into a QImode memory slot. This has been fixed to properly truncate the + shift amount when splatting it into a vector. */ + +typedef unsigned char v16ui __attribute__((vector_size(16))); + +v16ui vslb(v16ui v, unsigned char i) +{ + return v << i; +} + +/* { dg-final { scan-assembler "vspltb" } } */ +/* { dg-final { scan-assembler "vslb" } } */ diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-genbytemask-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-genbytemask-1.c index b8cf3140bd7..26c189af15d 100644 --- a/gcc/testsuite/gcc.target/s390/vector/vec-genbytemask-1.c +++ b/gcc/testsuite/gcc.target/s390/vector/vec-genbytemask-1.c @@ -1,11 +1,13 @@ /* { dg-do run } */ /* { dg-options "-O3 -mzarch -march=z13 --save-temps" } */ /* { dg-require-effective-target vector } */ +/* { dg-require-effective-target int128 } */ typedef unsigned char uv16qi __attribute__((vector_size(16))); typedef unsigned short uv8hi __attribute__((vector_size(16))); typedef unsigned int uv4si __attribute__((vector_size(16))); typedef unsigned long long uv2di __attribute__((vector_size(16))); +typedef unsigned __int128 uv1ti __attribute__((vector_size(16))); uv2di __attribute__((noinline)) foo1 () @@ -45,6 +47,13 @@ foo4 () 0xff, 0, 0xff, 0, 0, 0xff, 0, 0xff }; } + +uv1ti __attribute__((noinline)) +foo5 () +{ + return (uv1ti){ 0xff00ff00ff00ff00ULL }; +} + /* { dg-final { scan-assembler-times "vgbm\t%v24,61605" 1 } } */ int @@ -64,6 +73,10 @@ main () if (foo4()[1] != 0xff) __builtin_abort (); + + if (foo5()[0] != 0xff00ff00ff00ff00ULL) + __builtin_abort (); + return 0; } diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-genmask-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-genmask-1.c index b0747f713bb..6093422fd0d 100644 --- a/gcc/testsuite/gcc.target/s390/vector/vec-genmask-1.c +++ b/gcc/testsuite/gcc.target/s390/vector/vec-genmask-1.c @@ -66,4 +66,3 @@ main () __builtin_abort (); return 0; } - diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-genmask-2.c b/gcc/testsuite/gcc.target/s390/vector/vec-genmask-2.c index e3ae34154ca..46256e92531 100644 --- a/gcc/testsuite/gcc.target/s390/vector/vec-genmask-2.c +++ b/gcc/testsuite/gcc.target/s390/vector/vec-genmask-2.c @@ -1,10 +1,12 @@ /* { dg-do compile } */ /* { dg-options "-O3 -mzarch -march=z13" } */ +/* { dg-require-effective-target int128 } */ typedef unsigned char uv16qi __attribute__((vector_size(16))); typedef unsigned short uv8hi __attribute__((vector_size(16))); typedef unsigned int uv4si __attribute__((vector_size(16))); typedef unsigned long long uv2di __attribute__((vector_size(16))); +typedef unsigned __int128 uv1ti __attribute__((vector_size(16))); /* The elements differ. */ uv2di __attribute__((noinline)) @@ -43,4 +45,11 @@ foo4 () 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82, 0x82 }; } + +/* We do not have vgmq. */ +uv1ti +foo5() +{ + return (uv1ti){ ((unsigned __int128)1 << 53) - 1 }; +} /* { dg-final { scan-assembler-not "vgm" } } */ |