gcc/

	* doc/md.texi: Document that the % constraint character must
	be at the beginning of the string.
	* genoutput.c (validate_insn_alternatives): Check that '=',
	'+' and '%' only appear at the beginning of a constraint.
	* ira.c (commutative_constraint_p): Delete.
	(ira_get_dup_out_num): Expect the '%' commutativity marker to be
	at the start of the string.
	* config/alpha/alpha.md (*movmemdi_1, *clrmemdi_1): Remove
	duplicate '='s.
	* config/arm/neon.md (bicdi3_neon): Likewise.
	* config/iq2000/iq2000.md (addsi3_internal, subsi3_internal, sgt_si)
	(slt_si, sltu_si): Likewise.
	* config/vax/vax.md (sbcdi3): Likewise.
	* config/h8300/h8300.md (*cmpstz): Remove duplicate '+'.
	* config/arc/arc.md (mulsi_600, mulsidi_600, umulsidi_600)
	(mul64): Move '%' to beginning of constraint.
	* config/arm/arm.md (*xordi3_insn): Likewise.
	* config/nds32/nds32.md (add<mode>3, mulsi3, andsi3, iorsi3)
	(xorsi3): Likewise.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211031 138bc75d-0d04-0410-961f-82ee72b054a4

12 files changed, 61 insertions, 60 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 11c3103c323..034d9b051c0 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,27 @@
 2014-05-28  Richard Sandiford  <rdsandiford@googlemail.com>
 
+	* doc/md.texi: Document that the % constraint character must
+	be at the beginning of the string.
+	* genoutput.c (validate_insn_alternatives): Check that '=',
+	'+' and '%' only appear at the beginning of a constraint.
+	* ira.c (commutative_constraint_p): Delete.
+	(ira_get_dup_out_num): Expect the '%' commutativity marker to be
+	at the start of the string.
+	* config/alpha/alpha.md (*movmemdi_1, *clrmemdi_1): Remove
+	duplicate '='s.
+	* config/arm/neon.md (bicdi3_neon): Likewise.
+	* config/iq2000/iq2000.md (addsi3_internal, subsi3_internal, sgt_si)
+	(slt_si, sltu_si): Likewise.
+	* config/vax/vax.md (sbcdi3): Likewise.
+	* config/h8300/h8300.md (*cmpstz): Remove duplicate '+'.
+	* config/arc/arc.md (mulsi_600, mulsidi_600, umulsidi_600)
+	(mul64): Move '%' to beginning of constraint.
+	* config/arm/arm.md (*xordi3_insn): Likewise.
+	* config/nds32/nds32.md (add<mode>3, mulsi3, andsi3, iorsi3)
+	(xorsi3): Likewise.
+
+2014-05-28  Richard Sandiford  <rdsandiford@googlemail.com>
+
 	* doc/md.texi: Document the restrictions on the "enabled" attribute.
 
 2014-05-28  Jason Merrill  <jason@redhat.com>
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 795b4df3fbf..34ff1f0062f 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -4764,7 +4764,7 @@
   "operands[4] = gen_rtx_SYMBOL_REF (Pmode, \"OTS$MOVE\");")
 
 (define_insn "*movmemdi_1"
-  [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
+  [(set (match_operand:BLK 0 "memory_operand" "=m,m")
 	(match_operand:BLK 1 "memory_operand" "m,m"))
    (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
    (use (match_operand:DI 3 "immediate_operand"))
@@ -4831,7 +4831,7 @@
 })
 
 (define_insn "*clrmemdi_1"
-  [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
+  [(set (match_operand:BLK 0 "memory_operand" "=m,m")
 		   (const_int 0))
    (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
    (use (match_operand:DI 2 "immediate_operand"))
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 72ba470e6ea..2f93d7cd2be 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -1698,7 +1698,7 @@
 
 (define_insn "mulsi_600"
   [(set (match_operand:SI 2 "mlo_operand" "")
-	(mult:SI (match_operand:SI 0 "register_operand"  "Rcq#q,c,c,%c")
+	(mult:SI (match_operand:SI 0 "register_operand"  "%Rcq#q,c,c,c")
 		 (match_operand:SI 1 "nonmemory_operand" "Rcq#q,cL,I,Cal")))
    (clobber (match_operand:SI 3 "mhi_operand" ""))]
   "TARGET_MUL64_SET"
@@ -1750,7 +1750,7 @@
 (define_insn "mulsidi_600"
   [(set (reg:DI MUL64_OUT_REG)
 	(mult:DI (sign_extend:DI
-		   (match_operand:SI 0 "register_operand"  "Rcq#q,c,c,%c"))
+		   (match_operand:SI 0 "register_operand"  "%Rcq#q,c,c,c"))
 		 (sign_extend:DI
 ; assembler issue for "I", see mulsi_600
 ;		   (match_operand:SI 1 "register_operand" "Rcq#q,cL,I,Cal"))))]
@@ -1766,7 +1766,7 @@
 (define_insn "umulsidi_600"
   [(set (reg:DI MUL64_OUT_REG)
 	(mult:DI (zero_extend:DI
-		   (match_operand:SI 0 "register_operand"  "c,c,%c"))
+		   (match_operand:SI 0 "register_operand"  "%c,c,c"))
 		 (sign_extend:DI
 ; assembler issue for "I", see mulsi_600
 ;		   (match_operand:SI 1 "register_operand" "cL,I,Cal"))))]
@@ -4134,7 +4134,7 @@
 
 ;; FIXME: an intrinsic for multiply is daft.  Can we remove this?
 (define_insn "mul64"
-  [(unspec [(match_operand:SI 0 "general_operand" "q,r,r,%r")
+  [(unspec [(match_operand:SI 0 "general_operand" "%q,r,r,r")
 		     (match_operand:SI 1 "general_operand" "q,rL,I,Cal")]
 		   UNSPEC_MUL64)]
   "TARGET_MUL64_SET"
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 348a89c7b0a..74403fdc7c0 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -3169,7 +3169,7 @@
 
 (define_insn_and_split "*xordi3_insn"
   [(set (match_operand:DI         0 "s_register_operand" "=w,&r,&r,&r,&r,?w")
-	(xor:DI (match_operand:DI 1 "s_register_operand" "w ,%0,r ,0 ,r ,w")
+	(xor:DI (match_operand:DI 1 "s_register_operand" "%w ,0,r ,0 ,r ,w")
 		(match_operand:DI 2 "arm_xordi_operand"  "w ,r ,r ,Dg,Dg,w")))]
   "TARGET_32BIT && !TARGET_IWMMXT"
 {
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 83970618a69..1fc4dcd8275 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -728,7 +728,7 @@
 
 ;; Compare to *anddi_notdi_di.
 (define_insn "bicdi3_neon"
-  [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r")
+  [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r")
         (and:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,r,0"))
 		(match_operand:DI 1 "s_register_operand" "w,0,r")))]
   "TARGET_NEON"
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index e20ed35fea4..bc592dcfaf3 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -3589,7 +3589,7 @@
   [(set_attr "cc" "clobber")])
 
 (define_insn_and_split "*cmpstz"
-  [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU,+WU")
+  [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU,WU")
 			 (const_int 1)
 			 (match_operand:QI 1 "immediate_operand" "n,n"))
 	(match_operator:QI 2 "eqne_operator"
diff --git a/gcc/config/iq2000/iq2000.md b/gcc/config/iq2000/iq2000.md
index f7c7b34e13d..96ba555f8d2 100644
--- a/gcc/config/iq2000/iq2000.md
+++ b/gcc/config/iq2000/iq2000.md
@@ -260,7 +260,7 @@
   "")
 
 (define_insn "addsi3_internal"
-  [(set (match_operand:SI 0 "register_operand" "=d,=d")
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
 	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
 		 (match_operand:SI 2 "arith_operand" "d,I")))]
   ""
@@ -286,7 +286,7 @@
   "")
 
 (define_insn "subsi3_internal"
-  [(set (match_operand:SI 0 "register_operand" "=d,=d")
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
 	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
 		  (match_operand:SI 2 "arith_operand" "d,I")))]
   ""
@@ -1229,7 +1229,7 @@
    (set_attr "mode"	"SI")])
 
 (define_insn "sgt_si"
-  [(set (match_operand:SI 0 "register_operand" "=d,=d")
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
 	(gt:SI (match_operand:SI 1 "register_operand" "d,d")
 	       (match_operand:SI 2 "reg_or_0_operand" "d,J")))]
   ""
@@ -1240,7 +1240,7 @@
    (set_attr "mode"	"SI,SI")])
 
 (define_insn "slt_si"
-  [(set (match_operand:SI 0 "register_operand" "=d,=d")
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
 	(lt:SI (match_operand:SI 1 "register_operand" "d,d")
 	       (match_operand:SI 2 "arith_operand" "d,I")))]
   ""
@@ -1273,7 +1273,7 @@
    (set_attr "mode"	"SI")])
 
 (define_insn "sltu_si"
-  [(set (match_operand:SI 0 "register_operand" "=d,=d")
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
 	(ltu:SI (match_operand:SI 1 "register_operand" "d,d")
 		(match_operand:SI 2 "arith_operand" "d,I")))]
   ""
diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md
index 0402cadd6b2..da3a97a538f 100644
--- a/gcc/config/nds32/nds32.md
+++ b/gcc/config/nds32/nds32.md
@@ -261,7 +261,7 @@
 
 (define_insn "add<mode>3"
   [(set (match_operand:QIHISI 0 "register_operand"                   "=   d,    l,    d,    l,  d, l,    k,    l,    r, r")
-	(plus:QIHISI (match_operand:QIHISI 1 "register_operand"      "    0,    l,    0,    l, %0, l,    0,    k,    r, r")
+	(plus:QIHISI (match_operand:QIHISI 1 "register_operand"      "%   0,    l,    0,    l,  0, l,    0,    k,    r, r")
 		     (match_operand:QIHISI 2 "nds32_rimm15s_operand" " In05, In03, Iu05, Iu03,  r, l, Is10, Iu06, Is15, r")))]
   ""
 {
@@ -382,9 +382,9 @@
 ;; Multiplication instructions.
 
 (define_insn "mulsi3"
-  [(set (match_operand:SI 0 "register_operand"          "= w, r")
-	(mult:SI (match_operand:SI 1 "register_operand" " %0, r")
-		 (match_operand:SI 2 "register_operand" "  w, r")))]
+  [(set (match_operand:SI 0 "register_operand"          "=w, r")
+	(mult:SI (match_operand:SI 1 "register_operand" "%0, r")
+		 (match_operand:SI 2 "register_operand" " w, r")))]
   ""
   "@
   mul33\t%0, %2
@@ -489,9 +489,9 @@
 )
 
 (define_insn "andsi3"
-  [(set (match_operand:SI 0 "register_operand"         "= w, r,    l,    l,    l,    l,    l,    l,    r,   r,     r,    r,    r")
-	(and:SI (match_operand:SI 1 "register_operand" " %0, r,    l,    l,    l,    l,    0,    0,    r,   r,     r,    r,    r")
-		(match_operand:SI 2 "general_operand"  "  w, r, Izeb, Izeh, Ixls, Ix11, Ibms, Ifex, Izeb, Izeh, Iu15, Ii15, Ic15")))]
+  [(set (match_operand:SI 0 "register_operand"         "=w, r,    l,    l,    l,    l,    l,    l,    r,   r,     r,    r,    r")
+	(and:SI (match_operand:SI 1 "register_operand" "%0, r,    l,    l,    l,    l,    0,    0,    r,   r,     r,    r,    r")
+		(match_operand:SI 2 "general_operand"  " w, r, Izeb, Izeh, Ixls, Ix11, Ibms, Ifex, Izeb, Izeh, Iu15, Ii15, Ic15")))]
   ""
 {
   HOST_WIDE_INT mask = INTVAL (operands[2]);
@@ -585,9 +585,9 @@
 ;; For V3/V3M ISA, we have 'or33' instruction.
 ;; So we can identify 'or Rt3,Rt3,Ra3' case and set its length to be 2.
 (define_insn "iorsi3"
-  [(set (match_operand:SI 0 "register_operand"         "= w, r,    r,    r")
-	(ior:SI (match_operand:SI 1 "register_operand" " %0, r,    r,    r")
-		(match_operand:SI 2 "general_operand"  "  w, r, Iu15, Ie15")))]
+  [(set (match_operand:SI 0 "register_operand"         "=w, r,    r,    r")
+	(ior:SI (match_operand:SI 1 "register_operand" "%0, r,    r,    r")
+		(match_operand:SI 2 "general_operand"  " w, r, Iu15, Ie15")))]
   ""
 {
   int one_position;
@@ -645,9 +645,9 @@
 ;; For V3/V3M ISA, we have 'xor33' instruction.
 ;; So we can identify 'xor Rt3,Rt3,Ra3' case and set its length to be 2.
 (define_insn "xorsi3"
-  [(set (match_operand:SI 0 "register_operand"         "= w, r,    r,    r")
-	(xor:SI (match_operand:SI 1 "register_operand" " %0, r,    r,    r")
-		(match_operand:SI 2 "general_operand"  "  w, r, Iu15, It15")))]
+  [(set (match_operand:SI 0 "register_operand"         "=w, r,    r,    r")
+	(xor:SI (match_operand:SI 1 "register_operand" "%0, r,    r,    r")
+		(match_operand:SI 2 "general_operand"  " w, r, Iu15, It15")))]
   ""
 {
   int one_position;
diff --git a/gcc/config/vax/vax.md b/gcc/config/vax/vax.md
index d3929731b64..fc73367dfea 100644
--- a/gcc/config/vax/vax.md
+++ b/gcc/config/vax/vax.md
@@ -423,7 +423,7 @@
   "vax_expand_addsub_di_operands (operands, MINUS); DONE;")
 
 (define_insn "sbcdi3"
-  [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,=Rr")
+  [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,Rr")
 	(minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I")
 		  (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))]
   "TARGET_QMATH"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 3bd1c564d92..7c3d7142aa1 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -1589,7 +1589,10 @@ See, for example, the @samp{mulsi3} insn of the ARM@.
 Declares the instruction to be commutative for this operand and the
 following operand.  This means that the compiler may interchange the
 two operands if that is the cheapest way to make all operands fit the
-constraints.
+constraints.  @samp{%} applies to all alternatives and must appear as
+the first character in the constraint.  Only input operands can use
+@samp{%}.
+
 @ifset INTERNALS
 This is often used in patterns for addition instructions
 that really have only two operands: the result must go in one of the
diff --git a/gcc/genoutput.c b/gcc/genoutput.c
index 26fb1acfde7..b3ce120f33a 100644
--- a/gcc/genoutput.c
+++ b/gcc/genoutput.c
@@ -781,6 +781,11 @@ validate_insn_alternatives (struct data *d)
 
 	for (p = d->operand[start].constraint; (c = *p); p += len)
 	  {
+	    if ((c == '%' || c == '=' || c == '+')
+		&& p != d->operand[start].constraint)
+	      error_with_line (d->lineno,
+			       "character '%c' can only be used at the"
+			       " beginning of a constraint string", c);
 #ifdef USE_MD_CONSTRAINTS
 	    if (ISSPACE (c) || strchr (indep_constraints, c))
 	      len = 1;
diff --git a/gcc/ira.c b/gcc/ira.c
index 076c53231f3..26d017e0820 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -1770,34 +1770,6 @@ setup_prohibited_mode_move_regs (void)
 
 
 
-/* Return TRUE if the operand constraint STR is commutative.  */
-static bool
-commutative_constraint_p (const char *str)
-{
-  int c;
-
-  alternative_mask enabled = recog_data.enabled_alternatives;
-  for (;;)
-    {
-      c = *str;
-      if (c == '\0')
-	break;
-      str += CONSTRAINT_LEN (c, str);
-      if (c == '#')
-	enabled &= ~ALTERNATIVE_BIT (0);
-      else if (c == ',')
-	enabled >>= 1;
-      else if (enabled & 1)
-	{
-	  /* Usually `%' is the first constraint character but the
-	     documentation does not require this.  */
-	  if (c == '%')
-	    return true;
-	}
-    }
-  return false;
-}
-
 /* Setup possible alternatives in ALTS for INSN.  */
 void
 ira_setup_alts (rtx insn, HARD_REG_SET &alts)
@@ -2099,10 +2071,9 @@ ira_get_dup_out_num (int op_num, HARD_REG_SET &alts)
       if (use_commut_op_p)
 	break;
       use_commut_op_p = true;
-      if (commutative_constraint_p (recog_data.constraints[op_num]))
+      if (recog_data.constraints[op_num][0] == '%')
 	str = recog_data.constraints[op_num + 1];
-      else if (op_num > 0 && commutative_constraint_p (recog_data.constraints
-						       [op_num - 1]))
+      else if (op_num > 0 && recog_data.constraints[op_num - 1][0] == '%')
 	str = recog_data.constraints[op_num - 1];
       else
 	break;