diff options
| author | wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4> | 1998-06-08 18:13:34 +0000 |
|---|---|---|
| committer | wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4> | 1998-06-08 18:13:34 +0000 |
| commit | cadc074f3ceba9152798c4f861447b013753faa7 (patch) | |
| tree | 2067b762f6bb055f65e85796bd0f7c38d3d71f8b /gcc | |
| parent | 213134bc90ca98e9f134e517c03ceb5c69005c1a (diff) | |
| download | gcc-cadc074f3ceba9152798c4f861447b013753faa7.tar.gz | |
Fix mips64vr4100-elf build failure.
* mips.c (mips_secondary_reload_class): Use gp_reg_p instead of
GP_REG_P. Use gr_regs instead of GR_REGS.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@20350 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mips/mips.c | 12 |
2 files changed, 11 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a5ebd22d346..d9452835dac 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Mon Jun 8 18:12:06 1998 Jim Wilson <wilson@cygnus.com> + + * mips.c (mips_secondary_reload_class): Use gp_reg_p instead of + GP_REG_P. Use gr_regs instead of GR_REGS. + Mon Jun 8 16:54:12 1998 Ken Raeburn <raeburn@cygnus.com> Jeff Law <law@cygnus.com> diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index e10c0484922..56f52103633 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -7086,14 +7086,14 @@ mips_secondary_reload_class (class, mode, x, in_p) to a general register, or when copying from register 0. */ if (class == HILO_REG && regno != GP_REG_FIRST + 0) return ((! in_p - && GP_REG_P (regno) + && gp_reg_p && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode)) - ? NO_REGS : GR_REGS); + ? NO_REGS : gr_regs); else if (regno == HILO_REGNUM) return ((in_p - && class == GR_REGS + && class == gr_regs && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode)) - ? NO_REGS : GR_REGS); + ? NO_REGS : gr_regs); /* Copying from HI or LO to anywhere other than a general register requires a general register. */ @@ -7104,7 +7104,7 @@ mips_secondary_reload_class (class, mode, x, in_p) /* We can't really copy to HI or LO at all in mips16 mode. */ return M16_REGS; } - return gp_reg_p ? NO_REGS : GR_REGS; + return gp_reg_p ? NO_REGS : gr_regs; } if (MD_REG_P (regno)) { @@ -7113,7 +7113,7 @@ mips_secondary_reload_class (class, mode, x, in_p) /* We can't really copy to HI or LO at all in mips16 mode. */ return M16_REGS; } - return class == gr_regs ? NO_REGS : GR_REGS; + return class == gr_regs ? NO_REGS : gr_regs; } /* We can only copy a value to a condition code register from a |