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| author | rearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-06-19 06:18:28 +0000 |
|---|---|---|
| committer | rearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4> | 1999-06-19 06:18:28 +0000 |
| commit | cbd60e743688c561ea73ae93812a7202db2af66f (patch) | |
| tree | b95e2e6b39bbf72d7ad40c6a85c90f1c1f2e4e6a /gcc | |
| parent | 735ef99e8fb0a9dc31f33b922dc75e52b440ed60 (diff) | |
| download | gcc-cbd60e743688c561ea73ae93812a7202db2af66f.tar.gz | |
* arm.md (*adddf_esfdf_df): Renamed from *adddf_df_esfdf.
(*strsi_predec): Renamed from *strqi_predec.
(*loadsi_shiftpreinc): Renamed from *loadqi_shiftpreinc.
(*loadsi_shiftpredec): Renamed from *loadqi_shiftpredec.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@27609 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 8 |
2 files changed, 9 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 94a60d9f5f9..62151b0eabf 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -13,6 +13,11 @@ Sat Jun 19 05:25:05 1999 Richard Earnshaw (rearnsha@arm.com) (output_func_{prologue,epilogue}): Likewise. (output_expand_prologue): Likewise. + * arm.md (*adddf_esfdf_df): Renamed from *adddf_df_esfdf. + (*strsi_predec): Renamed from *strqi_predec. + (*loadsi_shiftpreinc): Renamed from *loadqi_shiftpreinc. + (*loadsi_shiftpredec): Renamed from *loadqi_shiftpredec. + Fri Jun 18 23:47:06 1999 David Edelsohn <edelsohn@gnu.org> * rs6000.c (find_addr_reg): New function. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index acc5d34eb49..f632d773a3a 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -559,7 +559,7 @@ suf%?d\\t%0, %1, #%N2" [(set_attr "type" "farith")]) -(define_insn "*adddf_df_esfdf" +(define_insn "*adddf_esfdf_df" [(set (match_operand:DF 0 "s_register_operand" "=f,f") (plus:DF (float_extend:DF (match_operand:SF 1 "s_register_operand" "f,f")) @@ -5571,7 +5571,7 @@ "str%?\\t%3, [%0, %2]!" [(set_attr "type" "store1")]) -(define_insn "*strqi_predec" +(define_insn "*strsi_predec" [(set (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0") (match_operand:SI 2 "s_register_operand" "r"))) (match_operand:SI 3 "s_register_operand" "r")) @@ -5730,7 +5730,7 @@ "str%?\\t%5, [%0, -%3%S2]!" [(set_attr "type" "store1")]) -(define_insn "*loadqi_shiftpreinc" +(define_insn "*loadsi_shiftpreinc" [(set (match_operand:SI 5 "s_register_operand" "=r") (mem:SI (plus:SI (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r") @@ -5745,7 +5745,7 @@ "ldr%?\\t%5, [%0, %3%S2]!" [(set_attr "type" "load")]) -(define_insn "*loadqi_shiftpredec" +(define_insn "*loadsi_shiftpredec" [(set (match_operand:SI 5 "s_register_operand" "=r") (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0") (match_operator:SI 2 "shift_operator" |