diff options
| author | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-11-21 14:26:12 +0000 |
|---|---|---|
| committer | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-11-21 14:26:12 +0000 |
| commit | 3794d2f9c42acb8b9dcf036785e1e4a68b447b1d (patch) | |
| tree | c008138542a2f30e26b4205a1f6f63e9e94368f0 /gcc | |
| parent | 677f8c6b8258c0b4c121f515063e8fab4ffa9c4a (diff) | |
| parent | 7f8a3f4983825df08d845b7093beb81ecd7bb320 (diff) | |
| download | gcc-3794d2f9c42acb8b9dcf036785e1e4a68b447b1d.tar.gz | |
Merge with trunk.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/wide-int@205218 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
71 files changed, 4975 insertions, 858 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d962593581c..f9c4cc564fe 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,237 @@ +2013-11-21 Richard Biener <rguenther@suse.de> + + * tree-ssa-forwprop.c (simplify_vce): New function. + (ssa_forward_propagate_and_combine): Call it. + +2013-11-21 Richard Biener <rguenther@suse.de> + + * tree-vect-loop-manip.c (vect_build_loop_niters, + vect_generate_tmps_on_preheader): Move ... + * tree-vect-loop.c (vect_build_loop_niters, + vect_generate_tmps_on_preheader): ... here and simplify. + (vect_transform_loop): Call them here and pass down results + to consumers. + * tree-vect-loop-manip.c (vect_do_peeling_for_loop_bound): + Get niter variables from caller. + (vect_do_peeling_for_alignment): Likewise. + * tree-vectorizer.h (vect_generate_tmps_on_preheader): Remove. + (vect_do_peeling_for_loop_bound, vect_do_peeling_for_alignment): + Adjust prototypes. + +2013-11-21 Richard Biener <rguenther@suse.de> + + * tree-ssa-loop-ch.c (copy_loop_headers): Decrement + nb_iterations_upper_bound by one. + +2013-11-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/59058 + * tree-loop-distribution.c (struct partition_s): Add plus_one + member. + (build_size_arg_loc): Apply niter adjustment here. + (generate_memset_builtin): Adjust. + (generate_memcpy_builtin): Likewise. + (classify_partition): Do not use number_of_exit_cond_executions + but record whether niter needs to be adjusted. + +2013-11-21 Eric Botcazou <ebotcazou@adacore.com> + + * tree-ssa-tail-merge.c (stmt_local_def): Return false if the statement + could throw. + +2013-11-21 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/53976 + * config/sh/sh_optimize_sett_clrt.cc: New SH specific RTL pass. + * config/sh/sh.c (register_sh_passes): Add sh_optimize_sett_clrt pass. + * config/sh/sh/t-sh (sh_optimize_sett_clrt pass.o): New entry. + * config.gcc (sh[123456789lbe]*-*-* | sh-*-*): Add + sh_optimize_sett_clrt pass.o to extra_objs. + +2013-11-20 David Malcolm <dmalcolm@redhat.com> + + * cfg.c (dump_edge_info): Remove redundant comment. + * cfgcleanup.c (outgoing_edges_match): Reword reference to + EXIT_BLOCK_PTR in comment. + (try_optimize_cfg): Likewise. + * cfgrtl.c (last_bb_in_partition): Likewise. + * cgraph.c (cgraph_node_cannot_return): Likewise. + * function.c (thread_prologue_and_epilogue_insns): Likewise. + * graphite-scop-detection.c (scopdet_basic_block_info): Likewise. + * ipa-split.c (consider_split): Likewise. + * profile.c (find_spanning_tree): Likewise. + * sched-int.h (common_sched_info_def.add_block): Likewise. + * dominance.c (calc_dfs_tree_nonrec): Reword references in + comments to now removed ENTRY_BLOCK_PTR and EXIT_BLOCK_PTR macros. + * tree-cfgcleanup.c (cleanup_control_flow_bb): Reword references + in comments to now removed ENTRY_BLOCK_PTR macro. + (tree_forwarder_block_p): Reword reference in comment to + EXIT_BLOCK_PTR. + * tree-inline.c (copy_cfg_body): Reword references in comments to + now removed ENTRY_BLOCK_PTR macro. + * tree-ssa-propagate.c (ssa_prop_init): Likewise. + * tree-scalar-evolution.h ( block_before_loop): Likewise. Add + a comma to the comment to clarify the meaning. + +2013-11-20 Andrew MacLeod <amacleod@redhat.com> + + * gimplify.h (gimplify_hasher : typed_free_remove, struct gimplify_ctx): + Move to gimplify.c. + (free_gimplify_stack): Add prototype. + * gimplify.c (gimplify_hasher:typed_free_remove): Relocate here. + (struct gimplify_ctx): Relocate here. + (gimplify_ctxp): Make static. + (ctx_pool, ctx_alloc, ctx_free, free_gimplify_stack): New. Manage a + list of struct gimplify_ctx. + (push_gimplify_context): Add default parameters and allocate a struct + from the pool. + (pop_gimplify_context): Free a struct back to the pool. + (gimplify_scan_omp_clauses, gimplify_omp_parallel, gimplify_omp_task, + gimplify_omp_workshare, gimplify_transaction, gimplify_body): Don't + use a local 'struct gimplify_ctx'. + * cgraphunit.c (expand_all_functions): call free_gimplify_stack. + * gimplify-me.c (force_gimple_operand_1, gimple_regimplify_operands): + Likewise. + * omp-low.c (lower_omp_sections, lower_omp_single, lower_omp_master, + lower_omp_ordered, lower_omp_critical, lower_omp_for, + create_task_copyfn, lower_omp_taskreg, lower_omp_target, + lower_omp_teams, execute_lower_omp): Likewise. + * gimple-fold.c (gimplify_and_update_call_from_tree): Likewise. + * tree-inline.c (optimize_inline_calls): Likewise. + +2013-11-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/vsx.md (vsx_set_<mode>): Adjust for little endian. + (vsx_extract_<mode>): Likewise. + (*vsx_extract_<mode>_one_le): New LE variant on + *vsx_extract_<mode>_zero. + (vsx_extract_v4sf): Adjust for little endian. + +2013-11-20 Vladimir Makarov <vmakarov@redhat.com> + + PR rtl-optimization/59133 + * lra.c (expand_reg_data): Add new argument. Set up ALL_REGS for + new pseudos. + (lra_create_new_reg_with_unique_value): Pass new argument value. + (lra_emit_add, lra_emit_move): Ditto. + * lra-constraints.c (in_class_p): Add check for move for a new + insn. + (change_class): Rename to lra_change_class. Move to lra-int.h. + (get_reload_reg, narrow_reload_pseudo_class): Adjust calls of + change_class. + (process_addr_reg, process_addr): Ditto. + (curr_insn_transform): Ditto. Add check on old pseudo for + optional reload. + * lra-int.h (lra_get_regno_hard_regno): Move below. + (lra_change_class): Renamed change_class from lra.c. + +2013-11-20 David Malcolm <dmalcolm@redhat.com> + + * gdbhooks.py (VecPrinter.children): Don't attempt to iterate + the children of a NULL pointer. + +2013-11-20 Robert Suchanek <Robert.Suchanek@imgtec.com> + + * lra.c (lra): Set lra_in_progress before check_rtl call. + * recog.c (insn_invalid_p): Add !lra_in_progress to prevent + adding clobber regs when LRA is running. + +2013-11-20 Maciej W. Rozycki <macro@codesourcery.com> + + * config/mips/mips.h (ISA_HAS_FP4): Remove TARGET_FLOAT64 + restriction for ISA_MIPS32R2. + (ISA_HAS_LXC1_SXC1): New macro. + (ISA_HAS_FP_MADD4_MSUB4): Remove ISA_MIPS32R2 special-casing. + (ISA_HAS_NMADD4_NMSUB4): Likewise. + (ISA_HAS_FP_RECIP_RSQRT): Likewise. + (ISA_HAS_PREFETCHX): Redefine in terms of ISA_HAS_FP4. + * config/mips/mips.md (*<ANYF:loadx>_<P:mode>): Use + ISA_HAS_LXC1_SXC1 rather than ISA_HAS_FP4. + (*<ANYF:storex>_<P:mode>): Likewise. + +2013-11-20 Maciej W. Rozycki <macro@codesourcery.com> + + * config/mips/mips.h (ISA_HAS_FP_RECIP_RSQRT): New macro. + * config/mips/mips.c (mips_rtx_costs) <DIV>: Check for + ISA_HAS_FP_RECIP_RSQRT rather than ISA_HAS_FP4. + * config/mips/mips.md (recip_condition): Remove mode attribute. + (div<mode>3): Use ISA_HAS_FP_RECIP_RSQRT rather than + <recip_condition>. + (*recip<mode>3, *rsqrt<mode>a, *rsqrt<mode>b): Likewise. + +2013-11-20 Eric Botcazou <ebotcazou@adacore.com> + + PR target/59207 + * config/sparc/sparc.c (sparc_fold_builtin) <case CODE_FOR_pdist_vis>: + Make sure neg2_ovf is set before being used. + +2013-11-20 Basile Starynkevitch <basile@starynkevitch.net> + + * plugin.def: Add comment about register_callback and + invoke_plugin_callbacks_full. + + * plugin.c (register_callback, invoke_plugin_callbacks_full): + Handle PLUGIN_INCLUDE_FILE event. + +2013-11-20 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> + + * config/rs6000/rs6000.c (rs6000_cannot_change_mode_class): Do not + allow subregs of TDmode in FPRs of smaller size in little-endian. + (rs6000_split_multireg_move): When splitting an access to TDmode + in FPRs, do not use simplify_gen_subreg. + +2013-11-20 Joseph Myers <joseph@codesourcery.com> + + PR middle-end/21718 + * real.c: Remove comment about decimal string conversion and + rounding errors. + (real_from_string): Use MPFR to convert nonzero decimal constant + to REAL_VALUE_TYPE. + +2013-11-20 Eric Botcazou <ebotcazou@adacore.com> + + * config/arm/arm.c (arm_dwarf_register_span): Take into account the + endianness of the D registers for the legacy encodings. + +2013-11-20 Richard Earnshaw <rearnsha@arm.com> + + PR rtl-optimization/54300 + * regcprop.c (copyprop_hardreg_forward_1): Ensure any unused + outputs in a single-set are killed from the value chains. + +2013-11-20 Ilya Enkovich <ilya.enkovich@intel.com> + + * cgraph.h (varpool_node): Add need_bounds_init field. + * lto-cgraph.c (lto_output_varpool_node): Output + need_bounds_init value. + (input_varpool_node): Read need_bounds_init value. + * varpool.c (dump_varpool_node): Dump need_bounds_init field. + +2013-11-20 Jan Hubicka <jh@suse.cz> + + * opts.c (finish_options): Imply -ffat-lto-objects with -fno-use-linker-plugin. + * common.opt (fuse-linker-plugin): Add var. + +2013-11-20 Ilya Enkovich <ilya.enkovich@intel.com> + + * dbxout.c (dbxout_type): Ignore POINTER_BOUNDS_TYPE. + * dwarf2out.c (gen_subprogram_die): Ignore bound args. + (gen_type_die_with_usage): Skip pointer bounds. + (dwarf2out_global_decl): Likewise. + +2013-11-20 James Greenhalgh <james.greenhalgh@arm.com> + + * config/aarch64/aarch64.md: Remove "mode" and "mode2" attributes + from all insns. + +2013-11-20 Yuri Rumyantsev <ysrumyan@gmail.com> + + PR target/57756 + * config/i386/i386.c (ix86_option_override_internal): Add missed + argument prefix for 'ix86_fpmath'. + * config/i386/ssemath.h: Add missed definition of + TARGET_FPMATH_DEFAULT_P macros. + 2013-11-20 Kenneth Zadeck <zadeck@naturalbridge.com> Mike Stump <mikestump@comcast.net> Richard Sandiford <rdsandiford@googlemail.com> @@ -1572,7 +1806,7 @@ * tree.c (int_fits_type_p): Change GET_MODE_BITSIZE to GET_MODE_PRECISION. * fold-const.c (fold_single_bit_test_into_sign_test) - (fold_binary_loc): Change GET_MODE_BITSIZE to GET_MODE_PRECISION. + (fold_binary_loc): Change GET_MODE_BITSIZE to GET_MODE_PRECISION. 2013-11-18 Teresa Johnson <tejohnson@google.com> @@ -9117,7 +9351,8 @@ PR target/51244 * config/sh/sh_treg_combine.cc: New SH specific RTL pass. - * config.gcc (SH extra_objs): Add sh_ifcvt.o. + * config.gcc (sh[123456789lbe]*-*-* | sh-*-*): Add sh_treg_combine.o to + extra_objs. * config/sh/t-sh (sh_treg_combine.o): New entry. * config/sh/sh.c (sh_fixed_condition_code_regs): New function that implements the target hook TARGET_FIXED_CONDITION_CODE_REGS. diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 91b73955538..dbbbc09457b 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20131120 +20131121 diff --git a/gcc/c/Make-lang.in b/gcc/c/Make-lang.in index d79fc4f410c..e68000a8246 100644 --- a/gcc/c/Make-lang.in +++ b/gcc/c/Make-lang.in @@ -137,4 +137,3 @@ c.stageprofile: stageprofile-start -mv c/*$(objext) stageprofile/c c.stagefeedback: stagefeedback-start -mv c/*$(objext) stagefeedback/c - diff --git a/gcc/cfg.c b/gcc/cfg.c index e35eee9a9bc..6bceca5ed26 100644 --- a/gcc/cfg.c +++ b/gcc/cfg.c @@ -473,8 +473,6 @@ dump_edge_info (FILE *file, edge e, int flags, int do_succ) && (flags & TDF_SLIM) == 0) do_details = true; - /* ENTRY_BLOCK_PTR/EXIT_BLOCK_PTR depend on cfun. - Compare against ENTRY_BLOCK/EXIT_BLOCK to avoid that dependency. */ if (side->index == ENTRY_BLOCK) fputs (" ENTRY", file); else if (side->index == EXIT_BLOCK) diff --git a/gcc/cfgcleanup.c b/gcc/cfgcleanup.c index 9c126102a54..dbaee9667ab 100644 --- a/gcc/cfgcleanup.c +++ b/gcc/cfgcleanup.c @@ -1535,7 +1535,7 @@ outgoing_edges_match (int mode, basic_block bb1, basic_block bb2) edge e1, e2; edge_iterator ei; - /* If we performed shrink-wrapping, edges to the EXIT_BLOCK_PTR can + /* If we performed shrink-wrapping, edges to the exit block can only be distinguished for JUMP_INSNs. The two paths may differ in whether they went through the prologue. Sibcalls are fine, we know that we either didn't need or inserted an epilogue before them. */ @@ -2684,7 +2684,7 @@ try_optimize_cfg (int mode) } delete_basic_block (b); changed = true; - /* Avoid trying to remove ENTRY_BLOCK_PTR. */ + /* Avoid trying to remove the exit block. */ b = (c == ENTRY_BLOCK_PTR_FOR_FN (cfun) ? c->next_bb : c); continue; } diff --git a/gcc/cfgrtl.c b/gcc/cfgrtl.c index 7ad38721606..63f44afbbae 100644 --- a/gcc/cfgrtl.c +++ b/gcc/cfgrtl.c @@ -1795,7 +1795,7 @@ last_bb_in_partition (basic_block start_bb) if (BB_PARTITION (start_bb) != BB_PARTITION (bb->next_bb)) return bb; } - /* Return bb before EXIT_BLOCK_PTR. */ + /* Return bb before the exit block. */ return bb->prev_bb; } diff --git a/gcc/cgraph.c b/gcc/cgraph.c index 936b405294c..cfbd79edc76 100644 --- a/gcc/cgraph.c +++ b/gcc/cgraph.c @@ -2333,7 +2333,7 @@ cgraph_node_cannot_return (struct cgraph_node *node) and thus it is safe to ignore its side effects for IPA analysis when computing side effects of the caller. FIXME: We could actually mark all edges that have no reaching - patch to EXIT_BLOCK_PTR or throw to get better results. */ + patch to the exit block or throw to get better results. */ bool cgraph_edge_cannot_lead_to_return (struct cgraph_edge *e) { diff --git a/gcc/cgraph.h b/gcc/cgraph.h index 4acf2d0c286..15719fb6872 100644 --- a/gcc/cgraph.h +++ b/gcc/cgraph.h @@ -528,6 +528,10 @@ class GTY((tag ("SYMTAB_VARIABLE"))) varpool_node : public symtab_node { public: /* Set when variable is scheduled to be assembled. */ unsigned output : 1; + + /* Set when variable has statically initialized pointer + or is a static bounds variable and needs initalization. */ + unsigned need_bounds_init : 1; }; /* Every top level asm statement is put into a asm_node. */ diff --git a/gcc/cgraphunit.c b/gcc/cgraphunit.c index fb23abed8da..f56f7c7abbb 100644 --- a/gcc/cgraphunit.c +++ b/gcc/cgraphunit.c @@ -205,6 +205,7 @@ along with GCC; see the file COPYING3. If not see #include "context.h" #include "pass_manager.h" #include "tree-nested.h" +#include "gimplify.h" /* Queue of cgraph nodes scheduled to be added into cgraph. This is a secondary queue used during optimization to accommodate passes that @@ -1866,6 +1867,7 @@ expand_all_functions (void) } } cgraph_process_new_functions (); + free_gimplify_stack (); free (order); diff --git a/gcc/common.opt b/gcc/common.opt index 43d49ace352..2216d6e0392 100644 --- a/gcc/common.opt +++ b/gcc/common.opt @@ -2247,7 +2247,7 @@ Common Negative(fuse-ld=bfd) Use the gold linker instead of the default linker fuse-linker-plugin -Common Undocumented +Common Undocumented Var(flag_use_linker_plugin) ; Positive if we should track variables, negative if we should run ; the var-tracking pass only to discard debug annotations, zero if diff --git a/gcc/config.gcc b/gcc/config.gcc index 2907018987d..1f20f18aa2c 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -469,7 +469,7 @@ sh[123456789lbe]*-*-* | sh-*-*) cpu_type=sh need_64bit_hwint=yes extra_options="${extra_options} fused-madd.opt" - extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o" + extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" ;; v850*-*-*) cpu_type=v850 diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 22051ec27e6..8b3dbd7550e 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -117,14 +117,6 @@ ;; Instruction types and attributes ;; ------------------------------------------------------------------- -;; Main data types used by the insntructions - -(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF" - (const_string "unknown")) - -(define_attr "mode2" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF" - (const_string "unknown")) - ; The "type" attribute is is included here from AArch32 backend to be able ; to share pipeline descriptions. (include "../arm/types.md") @@ -378,7 +370,6 @@ return \"<tbz>\\t%<w>0, %1, %l2\"; " [(set_attr "type" "branch") - (set_attr "mode" "<MODE>") (set (attr "length") (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -32768)) (lt (minus (match_dup 2) (pc)) (const_int 32764))) @@ -399,7 +390,6 @@ return \"<tbz>\\t%<w>0, <sizem1>, %l1\"; " [(set_attr "type" "branch") - (set_attr "mode" "<MODE>") (set (attr "length") (if_then_else (and (ge (minus (match_dup 1) (pc)) (const_int -32768)) (lt (minus (match_dup 1) (pc)) (const_int 32764))) @@ -630,8 +620,7 @@ } [(set_attr "type" "mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\ neon_from_gp<q>,neon_from_gp<q>, neon_dup") - (set_attr "simd" "*,*,yes,*,*,*,*,yes,yes,yes") - (set_attr "mode" "<MODE>")] + (set_attr "simd" "*,*,yes,*,*,*,*,yes,yes,yes")] ) (define_expand "mov<mode>" @@ -671,7 +660,6 @@ fmov\\t%s0, %s1" [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\ adr,adr,fmov,fmov,fmov") - (set_attr "mode" "SI") (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")] ) @@ -697,7 +685,6 @@ movi\\t%d0, %1" [(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\ adr,adr,fmov,fmov,fmov,fmov") - (set_attr "mode" "DI") (set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*") (set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")] ) @@ -710,8 +697,7 @@ "UINTVAL (operands[1]) < GET_MODE_BITSIZE (<MODE>mode) && UINTVAL (operands[1]) % 16 == 0" "movk\\t%<w>0, %X2, lsl %1" - [(set_attr "type" "mov_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "mov_imm")] ) (define_expand "movti" @@ -743,7 +729,6 @@ str\\t%q1, %0" [(set_attr "type" "multiple,f_mcr,f_mrc,neon_logic_q, \ load2,store2,store2,f_loadd,f_stored") - (set_attr "mode" "DI,DI,DI,TI,DI,DI,DI,TI,TI") (set_attr "length" "8,8,8,4,4,4,4,4,4") (set_attr "simd" "*,*,*,yes,*,*,*,*,*") (set_attr "fp" "*,*,*,*,*,*,*,yes,yes")] @@ -794,8 +779,7 @@ str\\t%w1, %0 mov\\t%w0, %w1" [(set_attr "type" "f_mcr,f_mrc,fmov,fconsts,\ - f_loads,f_stores,f_loads,f_stores,fmov") - (set_attr "mode" "SF")] + f_loads,f_stores,f_loads,f_stores,fmov")] ) (define_insn "*movdf_aarch64" @@ -814,8 +798,7 @@ str\\t%x1, %0 mov\\t%x0, %x1" [(set_attr "type" "f_mcr,f_mrc,fmov,fconstd,\ - f_loadd,f_stored,f_loadd,f_stored,mov_reg") - (set_attr "mode" "DF")] + f_loadd,f_stored,f_loadd,f_stored,mov_reg")] ) (define_expand "movtf" @@ -854,7 +837,6 @@ stp\\t%1, %H1, %0" [(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,fconstd,fconstd,\ f_loadd,f_stored,neon_load1_2reg,neon_store1_2reg") - (set_attr "mode" "DF,DF,DF,DF,DF,DF,TF,TF,DF,DF") (set_attr "length" "4,8,8,8,4,4,4,4,4,4") (set_attr "fp" "*,*,yes,yes,*,yes,yes,yes,*,*") (set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*")] @@ -883,8 +865,7 @@ XEXP (operands[1], 0), GET_MODE_SIZE (<MODE>mode)))" "ldp\\t%<w>0, %<w>2, %1" - [(set_attr "type" "load2") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "load2")] ) ;; Operands 0 and 2 are tied together by the final condition; so we allow @@ -899,8 +880,7 @@ XEXP (operands[0], 0), GET_MODE_SIZE (<MODE>mode)))" "stp\\t%<w>1, %<w>3, %0" - [(set_attr "type" "store2") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "store2")] ) ;; Operands 1 and 3 are tied together by the final condition; so we allow @@ -915,8 +895,7 @@ XEXP (operands[1], 0), GET_MODE_SIZE (<MODE>mode)))" "ldp\\t%<w>0, %<w>2, %1" - [(set_attr "type" "neon_load1_2reg<q>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "neon_load1_2reg<q>")] ) ;; Operands 0 and 2 are tied together by the final condition; so we allow @@ -931,8 +910,7 @@ XEXP (operands[0], 0), GET_MODE_SIZE (<MODE>mode)))" "stp\\t%<w>1, %<w>3, %0" - [(set_attr "type" "neon_store1_2reg<q>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "neon_store1_2reg<q>")] ) ;; Load pair with writeback. This is primarily used in function epilogues @@ -950,8 +928,7 @@ (match_operand:P 5 "const_int_operand" "n"))))])] "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPI:MODE>mode)" "ldp\\t%<w>2, %<w>3, [%1], %4" - [(set_attr "type" "load2") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "load2")] ) ;; Store pair with writeback. This is primarily used in function prologues @@ -969,8 +946,7 @@ (match_operand:GPI 3 "register_operand" "r"))])] "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPI:MODE>mode)" "stp\\t%<w>2, %<w>3, [%0, %4]!" - [(set_attr "type" "store2") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "store2")] ) ;; ------------------------------------------------------------------- @@ -990,8 +966,7 @@ "@ sxtw\t%0, %w1 ldrsw\t%0, %1" - [(set_attr "type" "extend,load1") - (set_attr "mode" "DI")] + [(set_attr "type" "extend,load1")] ) (define_insn "*zero_extendsidi2_aarch64" @@ -1001,8 +976,7 @@ "@ uxtw\t%0, %w1 ldr\t%w0, %1" - [(set_attr "type" "extend,load1") - (set_attr "mode" "DI")] + [(set_attr "type" "extend,load1")] ) (define_expand "<ANY_EXTEND:optab><SHORT:mode><GPI:mode>2" @@ -1018,8 +992,7 @@ "@ sxt<SHORT:size>\t%<GPI:w>0, %w1 ldrs<SHORT:size>\t%<GPI:w>0, %1" - [(set_attr "type" "extend,load1") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "extend,load1")] ) (define_insn "*zero_extend<SHORT:mode><GPI:mode>2_aarch64" @@ -1030,8 +1003,7 @@ uxt<SHORT:size>\t%<GPI:w>0, %w1 ldr<SHORT:size>\t%w0, %1 ldr\t%<SHORT:size>0, %1" - [(set_attr "type" "extend,load1,load1") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "extend,load1,load1")] ) (define_expand "<optab>qihi2" @@ -1047,8 +1019,7 @@ "@ <su>xtb\t%w0, %w1 <ldrxt>b\t%w0, %1" - [(set_attr "type" "extend,load1") - (set_attr "mode" "HI")] + [(set_attr "type" "extend,load1")] ) ;; ------------------------------------------------------------------- @@ -1091,8 +1062,7 @@ add\\t%w0, %w1, %2 add\\t%w0, %w1, %w2 sub\\t%w0, %w1, #%n2" - [(set_attr "type" "alu_imm,alu_reg,alu_imm") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_imm,alu_reg,alu_imm")] ) ;; zero_extend version of above @@ -1107,8 +1077,7 @@ add\\t%w0, %w1, %2 add\\t%w0, %w1, %w2 sub\\t%w0, %w1, #%n2" - [(set_attr "type" "alu_imm,alu_reg,alu_imm") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_imm,alu_reg,alu_imm")] ) (define_insn "*adddi3_aarch64" @@ -1124,7 +1093,6 @@ sub\\t%x0, %x1, #%n2 add\\t%d0, %d1, %d2" [(set_attr "type" "alu_imm,alu_reg,alu_imm,alu_reg") - (set_attr "mode" "DI") (set_attr "simd" "*,*,*,yes")] ) @@ -1141,8 +1109,7 @@ adds\\t%<w>0, %<w>1, %<w>2 adds\\t%<w>0, %<w>1, %<w>2 subs\\t%<w>0, %<w>1, #%n2" - [(set_attr "type" "alus_reg,alus_imm,alus_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alus_reg,alus_imm,alus_imm")] ) ;; zero_extend version of above @@ -1159,8 +1126,7 @@ adds\\t%w0, %w1, %w2 adds\\t%w0, %w1, %w2 subs\\t%w0, %w1, #%n2" - [(set_attr "type" "alus_reg,alus_imm,alus_imm") - (set_attr "mode" "SI")] + [(set_attr "type" "alus_reg,alus_imm,alus_imm")] ) (define_insn "*adds_mul_imm_<mode>" @@ -1176,8 +1142,7 @@ (match_dup 3)))] "" "adds\\t%<w>0, %<w>3, %<w>1, lsl %p2" - [(set_attr "type" "alus_shift_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alus_shift_imm")] ) (define_insn "*subs_mul_imm_<mode>" @@ -1193,8 +1158,7 @@ (mult:GPI (match_dup 2) (match_dup 3))))] "" "subs\\t%<w>0, %<w>1, %<w>2, lsl %p3" - [(set_attr "type" "alus_shift_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alus_shift_imm")] ) (define_insn "*adds_<optab><ALLX:mode>_<GPI:mode>" @@ -1208,8 +1172,7 @@ (plus:GPI (ANY_EXTEND:GPI (match_dup 1)) (match_dup 2)))] "" "adds\\t%<GPI:w>0, %<GPI:w>2, %<GPI:w>1, <su>xt<ALLX:size>" - [(set_attr "type" "alus_ext") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "alus_ext")] ) (define_insn "*subs_<optab><ALLX:mode>_<GPI:mode>" @@ -1223,8 +1186,7 @@ (minus:GPI (match_dup 1) (ANY_EXTEND:GPI (match_dup 2))))] "" "subs\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size>" - [(set_attr "type" "alus_ext") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "alus_ext")] ) (define_insn "*adds_<optab><mode>_multp2" @@ -1244,8 +1206,7 @@ (match_dup 4)))] "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])" "adds\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2" - [(set_attr "type" "alus_ext") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alus_ext")] ) (define_insn "*subs_<optab><mode>_multp2" @@ -1265,8 +1226,7 @@ (const_int 0))))] "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])" "subs\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2" - [(set_attr "type" "alus_ext") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alus_ext")] ) (define_insn "*add<mode>3nr_compare0" @@ -1280,8 +1240,7 @@ cmn\\t%<w>0, %<w>1 cmn\\t%<w>0, %<w>1 cmp\\t%<w>0, #%n1" - [(set_attr "type" "alus_reg,alus_imm,alus_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alus_reg,alus_imm,alus_imm")] ) (define_insn "*compare_neg<mode>" @@ -1291,8 +1250,7 @@ (match_operand:GPI 1 "register_operand" "r")))] "" "cmn\\t%<w>1, %<w>0" - [(set_attr "type" "alus_reg") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alus_reg")] ) (define_insn "*add_<shift>_<mode>" @@ -1302,8 +1260,7 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "add\\t%<w>0, %<w>3, %<w>1, <shift> %2" - [(set_attr "type" "alu_shift_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alu_shift_imm")] ) ;; zero_extend version of above @@ -1315,8 +1272,7 @@ (match_operand:SI 3 "register_operand" "r"))))] "" "add\\t%w0, %w3, %w1, <shift> %2" - [(set_attr "type" "alu_shift_imm") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_shift_imm")] ) (define_insn "*add_mul_imm_<mode>" @@ -1326,8 +1282,7 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "add\\t%<w>0, %<w>3, %<w>1, lsl %p2" - [(set_attr "type" "alu_shift_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alu_shift_imm")] ) (define_insn "*add_<optab><ALLX:mode>_<GPI:mode>" @@ -1336,8 +1291,7 @@ (match_operand:GPI 2 "register_operand" "r")))] "" "add\\t%<GPI:w>0, %<GPI:w>2, %<GPI:w>1, <su>xt<ALLX:size>" - [(set_attr "type" "alu_ext") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "alu_ext")] ) ;; zero_extend version of above @@ -1348,8 +1302,7 @@ (match_operand:GPI 2 "register_operand" "r"))))] "" "add\\t%w0, %w2, %w1, <su>xt<SHORT:size>" - [(set_attr "type" "alu_ext") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_ext")] ) (define_insn "*add_<optab><ALLX:mode>_shft_<GPI:mode>" @@ -1360,8 +1313,7 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "add\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %2" - [(set_attr "type" "alu_ext") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "alu_ext")] ) ;; zero_extend version of above @@ -1374,8 +1326,7 @@ (match_operand:SI 3 "register_operand" "r"))))] "" "add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %2" - [(set_attr "type" "alu_ext") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_ext")] ) (define_insn "*add_<optab><ALLX:mode>_mult_<GPI:mode>" @@ -1386,8 +1337,7 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "add\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %p2" - [(set_attr "type" "alu_ext") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "alu_ext")] ) ;; zero_extend version of above @@ -1399,8 +1349,7 @@ (match_operand:SI 3 "register_operand" "r"))))] "" "add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %p2" - [(set_attr "type" "alu_ext") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_ext")] ) (define_insn "*add_<optab><mode>_multp2" @@ -1413,8 +1362,7 @@ (match_operand:GPI 4 "register_operand" "r")))] "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])" "add\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2" - [(set_attr "type" "alu_ext") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alu_ext")] ) ;; zero_extend version of above @@ -1429,8 +1377,7 @@ (match_operand:SI 4 "register_operand" "r"))))] "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])" "add\\t%w0, %w4, %w1, <su>xt%e3 %p2" - [(set_attr "type" "alu_ext") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_ext")] ) (define_insn "*add<mode>3_carryin" @@ -1442,8 +1389,7 @@ (match_operand:GPI 2 "register_operand" "r"))))] "" "adc\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "adc_reg") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "adc_reg")] ) ;; zero_extend version of above @@ -1457,8 +1403,7 @@ (match_operand:SI 2 "register_operand" "r")))))] "" "adc\\t%w0, %w1, %w2" - [(set_attr "type" "adc_reg") - (set_attr "mode" "SI")] + [(set_attr "type" "adc_reg")] ) (define_insn "*add<mode>3_carryin_alt1" @@ -1470,8 +1415,7 @@ (geu:GPI (reg:CC CC_REGNUM) (const_int 0))))] "" "adc\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "adc_reg") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "adc_reg")] ) ;; zero_extend version of above @@ -1485,8 +1429,7 @@ (geu:SI (reg:CC CC_REGNUM) (const_int 0)))))] "" "adc\\t%w0, %w1, %w2" - [(set_attr "type" "adc_reg") - (set_attr "mode" "SI")] + [(set_attr "type" "adc_reg")] ) (define_insn "*add<mode>3_carryin_alt2" @@ -1498,8 +1441,7 @@ (match_operand:GPI 2 "register_operand" "r")))] "" "adc\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "adc_reg") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "adc_reg")] ) ;; zero_extend version of above @@ -1513,8 +1455,7 @@ (match_operand:SI 2 "register_operand" "r"))))] "" "adc\\t%w0, %w1, %w2" - [(set_attr "type" "adc_reg") - (set_attr "mode" "SI")] + [(set_attr "type" "adc_reg")] ) (define_insn "*add<mode>3_carryin_alt3" @@ -1526,8 +1467,7 @@ (match_operand:GPI 1 "register_operand" "r")))] "" "adc\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "adc_reg") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "adc_reg")] ) ;; zero_extend version of above @@ -1541,8 +1481,7 @@ (match_operand:SI 1 "register_operand" "r"))))] "" "adc\\t%w0, %w1, %w2" - [(set_attr "type" "adc_reg") - (set_attr "mode" "SI")] + [(set_attr "type" "adc_reg")] ) (define_insn "*add_uxt<mode>_multp2" @@ -1557,8 +1496,7 @@ operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3]))); return \"add\t%<w>0, %<w>4, %<w>1, uxt%e3 %p2\";" - [(set_attr "type" "alu_ext") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alu_ext")] ) ;; zero_extend version of above @@ -1575,8 +1513,7 @@ operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3]))); return \"add\t%w0, %w4, %w1, uxt%e3 %p2\";" - [(set_attr "type" "alu_ext") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_ext")] ) (define_insn "subsi3" @@ -1585,8 +1522,7 @@ (match_operand:SI 2 "register_operand" "r")))] "" "sub\\t%w0, %w1, %w2" - [(set_attr "type" "alu_reg") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_reg")] ) ;; zero_extend version of above @@ -1597,8 +1533,7 @@ (match_operand:SI 2 "register_operand" "r"))))] "" "sub\\t%w0, %w1, %w2" - [(set_attr "type" "alu_reg") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_reg")] ) (define_insn "subdi3" @@ -1610,7 +1545,6 @@ sub\\t%x0, %x1, %x2 sub\\t%d0, %d1, %d2" [(set_attr "type" "alu_reg, neon_sub") - (set_attr "mode" "DI") (set_attr "simd" "*,yes")] ) @@ -1624,8 +1558,7 @@ (minus:GPI (match_dup 1) (match_dup 2)))] "" "subs\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "alus_reg") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alus_reg")] ) ;; zero_extend version of above @@ -1638,8 +1571,7 @@ (zero_extend:DI (minus:SI (match_dup 1) (match_dup 2))))] "" "subs\\t%w0, %w1, %w2" - [(set_attr "type" "alus_reg") - (set_attr "mode" "SI")] + [(set_attr "type" "alus_reg")] ) (define_insn "*sub_<shift>_<mode>" @@ -1650,8 +1582,7 @@ (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))))] "" "sub\\t%<w>0, %<w>3, %<w>1, <shift> %2" - [(set_attr "type" "alu_shift_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alu_shift_imm")] ) ;; zero_extend version of above @@ -1664,8 +1595,7 @@ (match_operand:QI 2 "aarch64_shift_imm_si" "n")))))] "" "sub\\t%w0, %w3, %w1, <shift> %2" - [(set_attr "type" "alu_shift_imm") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_shift_imm")] ) (define_insn "*sub_mul_imm_<mode>" @@ -1676,8 +1606,7 @@ (match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))))] "" "sub\\t%<w>0, %<w>3, %<w>1, lsl %p2" - [(set_attr "type" "alu_shift_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alu_shift_imm")] ) ;; zero_extend version of above @@ -1690,8 +1619,7 @@ (match_operand:QI 2 "aarch64_pwr_2_si" "n")))))] "" "sub\\t%w0, %w3, %w1, lsl %p2" - [(set_attr "type" "alu_shift_imm") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_shift_imm")] ) (define_insn "*sub_<optab><ALLX:mode>_<GPI:mode>" @@ -1701,8 +1629,7 @@ (match_operand:ALLX 2 "register_operand" "r"))))] "" "sub\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size>" - [(set_attr "type" "alu_ext") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "alu_ext")] ) ;; zero_extend version of above @@ -1714,8 +1641,7 @@ (match_operand:SHORT 2 "register_operand" "r")))))] "" "sub\\t%w0, %w1, %w2, <su>xt<SHORT:size>" - [(set_attr "type" "alu_ext") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_ext")] ) (define_insn "*sub_<optab><ALLX:mode>_shft_<GPI:mode>" @@ -1726,8 +1652,7 @@ (match_operand 3 "aarch64_imm3" "Ui3"))))] "" "sub\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size> %3" - [(set_attr "type" "alu_ext") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "alu_ext")] ) ;; zero_extend version of above @@ -1740,8 +1665,7 @@ (match_operand 3 "aarch64_imm3" "Ui3")))))] "" "sub\\t%w0, %w1, %w2, <su>xt<SHORT:size> %3" - [(set_attr "type" "alu_ext") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_ext")] ) (define_insn "*sub_<optab><mode>_multp2" @@ -1754,8 +1678,7 @@ (const_int 0))))] "aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])" "sub\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2" - [(set_attr "type" "alu_ext") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alu_ext")] ) ;; zero_extend version of above @@ -1770,8 +1693,7 @@ (const_int 0)))))] "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])" "sub\\t%w0, %w4, %w1, <su>xt%e3 %p2" - [(set_attr "type" "alu_ext") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_ext")] ) (define_insn "*sub<mode>3_carryin" @@ -1783,8 +1705,7 @@ (match_operand:GPI 2 "register_operand" "r")))] "" "sbc\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "adc_reg") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "adc_reg")] ) ;; zero_extend version of the above @@ -1798,8 +1719,7 @@ (match_operand:SI 2 "register_operand" "r"))))] "" "sbc\\t%w0, %w1, %w2" - [(set_attr "type" "adc_reg") - (set_attr "mode" "SI")] + [(set_attr "type" "adc_reg")] ) (define_insn "*sub_uxt<mode>_multp2" @@ -1814,8 +1734,7 @@ operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3]))); return \"sub\t%<w>0, %<w>4, %<w>1, uxt%e3 %p2\";" - [(set_attr "type" "alu_ext") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alu_ext")] ) ;; zero_extend version of above @@ -1832,8 +1751,7 @@ operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3]))); return \"sub\t%w0, %w4, %w1, uxt%e3 %p2\";" - [(set_attr "type" "alu_ext") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_ext")] ) (define_insn_and_split "absdi2" @@ -1864,8 +1782,7 @@ GEN_INT (63))))); DONE; } - [(set_attr "type" "alu_reg") - (set_attr "mode" "DI")] + [(set_attr "type" "alu_reg")] ) (define_insn "neg<mode>2" @@ -1876,8 +1793,7 @@ neg\\t%<w>0, %<w>1 neg\\t%<rtn>0<vas>, %<rtn>1<vas>" [(set_attr "type" "alu_reg, neon_neg<q>") - (set_attr "simd" "*,yes") - (set_attr "mode" "<MODE>")] + (set_attr "simd" "*,yes")] ) ;; zero_extend version of above @@ -1886,8 +1802,7 @@ (zero_extend:DI (neg:SI (match_operand:SI 1 "register_operand" "r"))))] "" "neg\\t%w0, %w1" - [(set_attr "type" "alu_reg") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_reg")] ) (define_insn "*ngc<mode>" @@ -1896,8 +1811,7 @@ (match_operand:GPI 1 "register_operand" "r")))] "" "ngc\\t%<w>0, %<w>1" - [(set_attr "type" "adc_reg") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "adc_reg")] ) (define_insn "*ngcsi_uxtw" @@ -1907,8 +1821,7 @@ (match_operand:SI 1 "register_operand" "r"))))] "" "ngc\\t%w0, %w1" - [(set_attr "type" "adc_reg") - (set_attr "mode" "SI")] + [(set_attr "type" "adc_reg")] ) (define_insn "*neg<mode>2_compare0" @@ -1919,8 +1832,7 @@ (neg:GPI (match_dup 1)))] "" "negs\\t%<w>0, %<w>1" - [(set_attr "type" "alus_reg") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alus_reg")] ) ;; zero_extend version of above @@ -1932,8 +1844,7 @@ (zero_extend:DI (neg:SI (match_dup 1))))] "" "negs\\t%w0, %w1" - [(set_attr "type" "alus_reg") - (set_attr "mode" "SI")] + [(set_attr "type" "alus_reg")] ) (define_insn "*neg_<shift><mode>3_compare0" @@ -1947,8 +1858,7 @@ (neg:GPI (ASHIFT:GPI (match_dup 1) (match_dup 2))))] "" "negs\\t%<w>0, %<w>1, <shift> %2" - [(set_attr "type" "alus_shift_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alus_shift_imm")] ) (define_insn "*neg_<shift>_<mode>2" @@ -1958,8 +1868,7 @@ (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))))] "" "neg\\t%<w>0, %<w>1, <shift> %2" - [(set_attr "type" "alu_shift_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alu_shift_imm")] ) ;; zero_extend version of above @@ -1971,8 +1880,7 @@ (match_operand:QI 2 "aarch64_shift_imm_si" "n")))))] "" "neg\\t%w0, %w1, <shift> %2" - [(set_attr "type" "alu_shift_imm") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_shift_imm")] ) (define_insn "*neg_mul_imm_<mode>2" @@ -1982,8 +1890,7 @@ (match_operand:QI 2 "aarch64_pwr_2_<mode>" "n"))))] "" "neg\\t%<w>0, %<w>1, lsl %p2" - [(set_attr "type" "alu_shift_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alu_shift_imm")] ) ;; zero_extend version of above @@ -1995,8 +1902,7 @@ (match_operand:QI 2 "aarch64_pwr_2_si" "n")))))] "" "neg\\t%w0, %w1, lsl %p2" - [(set_attr "type" "alu_shift_imm") - (set_attr "mode" "SI")] + [(set_attr "type" "alu_shift_imm")] ) (define_insn "mul<mode>3" @@ -2005,8 +1911,7 @@ (match_operand:GPI 2 "register_operand" "r")))] "" "mul\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "mul") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "mul")] ) ;; zero_extend version of above @@ -2017,8 +1922,7 @@ (match_operand:SI 2 "register_operand" "r"))))] "" "mul\\t%w0, %w1, %w2" - [(set_attr "type" "mul") - (set_attr "mode" "SI")] + [(set_attr "type" "mul")] ) (define_insn "*madd<mode>" @@ -2028,8 +1932,7 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "madd\\t%<w>0, %<w>1, %<w>2, %<w>3" - [(set_attr "type" "mla") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "mla")] ) ;; zero_extend version of above @@ -2041,8 +1944,7 @@ (match_operand:SI 3 "register_operand" "r"))))] "" "madd\\t%w0, %w1, %w2, %w3" - [(set_attr "type" "mla") - (set_attr "mode" "SI")] + [(set_attr "type" "mla")] ) (define_insn "*msub<mode>" @@ -2053,8 +1955,7 @@ "" "msub\\t%<w>0, %<w>1, %<w>2, %<w>3" - [(set_attr "type" "mla") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "mla")] ) ;; zero_extend version of above @@ -2067,8 +1968,7 @@ "" "msub\\t%w0, %w1, %w2, %w3" - [(set_attr "type" "mla") - (set_attr "mode" "SI")] + [(set_attr "type" "mla")] ) (define_insn "*mul<mode>_neg" @@ -2078,8 +1978,7 @@ "" "mneg\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "mul") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "mul")] ) ;; zero_extend version of above @@ -2091,8 +1990,7 @@ "" "mneg\\t%w0, %w1, %w2" - [(set_attr "type" "mul") - (set_attr "mode" "SI")] + [(set_attr "type" "mul")] ) (define_insn "<su_optab>mulsidi3" @@ -2101,8 +1999,7 @@ (ANY_EXTEND:DI (match_operand:SI 2 "register_operand" "r"))))] "" "<su>mull\\t%0, %w1, %w2" - [(set_attr "type" "<su>mull") - (set_attr "mode" "DI")] + [(set_attr "type" "<su>mull")] ) (define_insn "<su_optab>maddsidi4" @@ -2113,8 +2010,7 @@ (match_operand:DI 3 "register_operand" "r")))] "" "<su>maddl\\t%0, %w1, %w2, %3" - [(set_attr "type" "<su>mlal") - (set_attr "mode" "DI")] + [(set_attr "type" "<su>mlal")] ) (define_insn "<su_optab>msubsidi4" @@ -2126,8 +2022,7 @@ (match_operand:SI 2 "register_operand" "r")))))] "" "<su>msubl\\t%0, %w1, %w2, %3" - [(set_attr "type" "<su>mlal") - (set_attr "mode" "DI")] + [(set_attr "type" "<su>mlal")] ) (define_insn "*<su_optab>mulsidi_neg" @@ -2137,8 +2032,7 @@ (ANY_EXTEND:DI (match_operand:SI 2 "register_operand" "r"))))] "" "<su>mnegl\\t%0, %w1, %w2" - [(set_attr "type" "<su>mull") - (set_attr "mode" "DI")] + [(set_attr "type" "<su>mull")] ) (define_insn "<su>muldi3_highpart" @@ -2151,8 +2045,7 @@ (const_int 64))))] "" "<su>mulh\\t%0, %1, %2" - [(set_attr "type" "<su>mull") - (set_attr "mode" "DI")] + [(set_attr "type" "<su>mull")] ) (define_insn "<su_optab>div<mode>3" @@ -2161,8 +2054,7 @@ (match_operand:GPI 2 "register_operand" "r")))] "" "<su>div\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "<su>div") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "<su>div")] ) ;; zero_extend version of above @@ -2173,8 +2065,7 @@ (match_operand:SI 2 "register_operand" "r"))))] "" "<su>div\\t%w0, %w1, %w2" - [(set_attr "type" "<su>div") - (set_attr "mode" "SI")] + [(set_attr "type" "<su>div")] ) ;; ------------------------------------------------------------------- @@ -2190,8 +2081,7 @@ cmp\\t%<w>0, %<w>1 cmp\\t%<w>0, %<w>1 cmn\\t%<w>0, #%n1" - [(set_attr "type" "alus_reg,alus_imm,alus_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alus_reg,alus_imm,alus_imm")] ) (define_insn "*cmp<mode>" @@ -2202,8 +2092,7 @@ "@ fcmp\\t%<s>0, #0.0 fcmp\\t%<s>0, %<s>1" - [(set_attr "type" "fcmp<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "fcmp<s>")] ) (define_insn "*cmpe<mode>" @@ -2214,8 +2103,7 @@ "@ fcmpe\\t%<s>0, #0.0 fcmpe\\t%<s>0, %<s>1" - [(set_attr "type" "fcmp<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "fcmp<s>")] ) (define_insn "*cmp_swp_<shift>_reg<mode>" @@ -2226,8 +2114,7 @@ (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ")))] "" "cmp\\t%<w>2, %<w>0, <shift> %1" - [(set_attr "type" "alus_shift_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alus_shift_imm")] ) (define_insn "*cmp_swp_<optab><ALLX:mode>_reg<GPI:mode>" @@ -2237,8 +2124,7 @@ (match_operand:GPI 1 "register_operand" "r")))] "" "cmp\\t%<GPI:w>1, %<GPI:w>0, <su>xt<ALLX:size>" - [(set_attr "type" "alus_ext") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "alus_ext")] ) (define_insn "*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>" @@ -2250,8 +2136,7 @@ (match_operand:GPI 2 "register_operand" "r")))] "" "cmp\\t%<GPI:w>2, %<GPI:w>0, <su>xt<ALLX:size> %1" - [(set_attr "type" "alus_ext") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "alus_ext")] ) ;; ------------------------------------------------------------------- @@ -2290,8 +2175,7 @@ [(match_operand 2 "cc_register" "") (const_int 0)]))] "" "cset\\t%<w>0, %m1" - [(set_attr "type" "csel") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "csel")] ) ;; zero_extend version of the above @@ -2302,8 +2186,7 @@ [(match_operand 2 "cc_register" "") (const_int 0)])))] "" "cset\\t%w0, %m1" - [(set_attr "type" "csel") - (set_attr "mode" "SI")] + [(set_attr "type" "csel")] ) (define_insn "cstore<mode>_neg" @@ -2312,8 +2195,7 @@ [(match_operand 2 "cc_register" "") (const_int 0)])))] "" "csetm\\t%<w>0, %m1" - [(set_attr "type" "csel") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "csel")] ) ;; zero_extend version of the above @@ -2324,8 +2206,7 @@ [(match_operand 2 "cc_register" "") (const_int 0)]))))] "" "csetm\\t%w0, %m1" - [(set_attr "type" "csel") - (set_attr "mode" "SI")] + [(set_attr "type" "csel")] ) (define_expand "cmov<mode>6" @@ -2378,8 +2259,7 @@ csinc\\t%<w>0, %<w>4, <w>zr, %M1 mov\\t%<w>0, -1 mov\\t%<w>0, 1" - [(set_attr "type" "csel") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "csel")] ) ;; zero_extend version of above @@ -2402,8 +2282,7 @@ csinc\\t%w0, %w4, wzr, %M1 mov\\t%w0, -1 mov\\t%w0, 1" - [(set_attr "type" "csel") - (set_attr "mode" "SI")] + [(set_attr "type" "csel")] ) (define_insn "*cmov<mode>_insn" @@ -2415,8 +2294,7 @@ (match_operand:GPF 4 "register_operand" "w")))] "TARGET_FLOAT" "fcsel\\t%<s>0, %<s>3, %<s>4, %m1" - [(set_attr "type" "fcsel") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "fcsel")] ) (define_expand "mov<mode>cc" @@ -2464,8 +2342,8 @@ (match_operand:GPI 1 "register_operand" "r")))] "" "csinc\\t%<w>0, %<w>1, %<w>1, %M2" - [(set_attr "type" "csel") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "csel")] +) (define_insn "csinc3<mode>_insn" [(set (match_operand:GPI 0 "register_operand" "=r") @@ -2477,8 +2355,7 @@ (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))] "" "csinc\\t%<w>0, %<w>4, %<w>3, %M1" - [(set_attr "type" "csel") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "csel")] ) (define_insn "*csinv3<mode>_insn" @@ -2490,8 +2367,8 @@ (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))] "" "csinv\\t%<w>0, %<w>4, %<w>3, %M1" - [(set_attr "type" "csel") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "csel")] +) (define_insn "*csneg3<mode>_insn" [(set (match_operand:GPI 0 "register_operand" "=r") @@ -2502,8 +2379,8 @@ (match_operand:GPI 4 "aarch64_reg_or_zero" "rZ")))] "" "csneg\\t%<w>0, %<w>4, %<w>3, %M1" - [(set_attr "type" "csel") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "csel")] +) ;; ------------------------------------------------------------------- ;; Logical operations @@ -2515,8 +2392,8 @@ (match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>")))] "" "<logical>\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "logic_reg,logic_imm") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "logic_reg,logic_imm")] +) ;; zero_extend version of above (define_insn "*<optab>si3_uxtw" @@ -2526,8 +2403,8 @@ (match_operand:SI 2 "aarch64_logical_operand" "r,K"))))] "" "<logical>\\t%w0, %w1, %w2" - [(set_attr "type" "logic_reg,logic_imm") - (set_attr "mode" "SI")]) + [(set_attr "type" "logic_reg,logic_imm")] +) (define_insn "*and<mode>3_compare0" [(set (reg:CC_NZ CC_REGNUM) @@ -2539,8 +2416,7 @@ (and:GPI (match_dup 1) (match_dup 2)))] "" "ands\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "logics_reg,logics_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "logics_reg,logics_imm")] ) ;; zero_extend version of above @@ -2554,8 +2430,7 @@ (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))] "" "ands\\t%w0, %w1, %w2" - [(set_attr "type" "logics_reg,logics_imm") - (set_attr "mode" "SI")] + [(set_attr "type" "logics_reg,logics_imm")] ) (define_insn "*and_<SHIFT:optab><mode>3_compare0" @@ -2570,8 +2445,7 @@ (and:GPI (SHIFT:GPI (match_dup 1) (match_dup 2)) (match_dup 3)))] "" "ands\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2" - [(set_attr "type" "logics_shift_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "logics_shift_imm")] ) ;; zero_extend version of above @@ -2588,8 +2462,7 @@ (match_dup 3))))] "" "ands\\t%w0, %w3, %w1, <SHIFT:shift> %2" - [(set_attr "type" "logics_shift_imm") - (set_attr "mode" "SI")] + [(set_attr "type" "logics_shift_imm")] ) (define_insn "*<LOGICAL:optab>_<SHIFT:optab><mode>3" @@ -2600,8 +2473,8 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "<LOGICAL:logical>\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2" - [(set_attr "type" "logic_shift_imm") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "logic_shift_imm")] +) ;; zero_extend version of above (define_insn "*<LOGICAL:optab>_<SHIFT:optab>si3_uxtw" @@ -2613,16 +2486,16 @@ (match_operand:SI 3 "register_operand" "r"))))] "" "<LOGICAL:logical>\\t%w0, %w3, %w1, <SHIFT:shift> %2" - [(set_attr "type" "logic_shift_imm") - (set_attr "mode" "SI")]) + [(set_attr "type" "logic_shift_imm")] +) (define_insn "one_cmpl<mode>2" [(set (match_operand:GPI 0 "register_operand" "=r") (not:GPI (match_operand:GPI 1 "register_operand" "r")))] "" "mvn\\t%<w>0, %<w>1" - [(set_attr "type" "logic_reg") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "logic_reg")] +) (define_insn "*one_cmpl_<optab><mode>2" [(set (match_operand:GPI 0 "register_operand" "=r") @@ -2630,8 +2503,8 @@ (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))))] "" "mvn\\t%<w>0, %<w>1, <shift> %2" - [(set_attr "type" "logic_shift_imm") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "logic_shift_imm")] +) (define_insn "*<LOGICAL:optab>_one_cmpl<mode>3" [(set (match_operand:GPI 0 "register_operand" "=r") @@ -2640,8 +2513,8 @@ (match_operand:GPI 2 "register_operand" "r")))] "" "<LOGICAL:nlogical>\\t%<w>0, %<w>2, %<w>1" - [(set_attr "type" "logic_reg") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "logic_reg")] +) (define_insn "*and_one_cmpl<mode>3_compare0" [(set (reg:CC_NZ CC_REGNUM) @@ -2654,8 +2527,8 @@ (and:GPI (not:GPI (match_dup 1)) (match_dup 2)))] "" "bics\\t%<w>0, %<w>2, %<w>1" - [(set_attr "type" "logics_reg") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "logics_reg")] +) ;; zero_extend version of above (define_insn "*and_one_cmplsi3_compare0_uxtw" @@ -2669,8 +2542,8 @@ (zero_extend:DI (and:SI (not:SI (match_dup 1)) (match_dup 2))))] "" "bics\\t%w0, %w2, %w1" - [(set_attr "type" "logics_reg") - (set_attr "mode" "SI")]) + [(set_attr "type" "logics_reg")] +) (define_insn "*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3" [(set (match_operand:GPI 0 "register_operand" "=r") @@ -2681,8 +2554,8 @@ (match_operand:GPI 3 "register_operand" "r")))] "" "<LOGICAL:nlogical>\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2" - [(set_attr "type" "logics_shift_imm") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "logics_shift_imm")] +) (define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0" [(set (reg:CC_NZ CC_REGNUM) @@ -2699,8 +2572,8 @@ (match_dup 1) (match_dup 2))) (match_dup 3)))] "" "bics\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2" - [(set_attr "type" "logics_shift_imm") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "logics_shift_imm")] +) ;; zero_extend version of above (define_insn "*and_one_cmpl_<SHIFT:optab>si3_compare0_uxtw" @@ -2718,16 +2591,16 @@ (SHIFT:SI (match_dup 1) (match_dup 2))) (match_dup 3))))] "" "bics\\t%w0, %w3, %w1, <SHIFT:shift> %2" - [(set_attr "type" "logics_shift_imm") - (set_attr "mode" "SI")]) + [(set_attr "type" "logics_shift_imm")] +) (define_insn "clz<mode>2" [(set (match_operand:GPI 0 "register_operand" "=r") (clz:GPI (match_operand:GPI 1 "register_operand" "r")))] "" "clz\\t%<w>0, %<w>1" - [(set_attr "type" "clz") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "clz")] +) (define_expand "ffs<mode>2" [(match_operand:GPI 0 "register_operand") @@ -2749,16 +2622,16 @@ (unspec:GPI [(match_operand:GPI 1 "register_operand" "r")] UNSPEC_CLS))] "" "cls\\t%<w>0, %<w>1" - [(set_attr "type" "clz") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "clz")] +) (define_insn "rbit<mode>2" [(set (match_operand:GPI 0 "register_operand" "=r") (unspec:GPI [(match_operand:GPI 1 "register_operand" "r")] UNSPEC_RBIT))] "" "rbit\\t%<w>0, %<w>1" - [(set_attr "type" "rbit") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "rbit")] +) (define_expand "ctz<mode>2" [(match_operand:GPI 0 "register_operand") @@ -2779,8 +2652,8 @@ (const_int 0)))] "" "tst\\t%<w>0, %<w>1" - [(set_attr "type" "logics_reg") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "logics_reg")] +) (define_insn "*and_<SHIFT:optab><mode>3nr_compare0" [(set (reg:CC_NZ CC_REGNUM) @@ -2792,8 +2665,8 @@ (const_int 0)))] "" "tst\\t%<w>2, %<w>0, <SHIFT:shift> %1" - [(set_attr "type" "logics_shift_imm") - (set_attr "mode" "<MODE>")]) + [(set_attr "type" "logics_shift_imm")] +) ;; ------------------------------------------------------------------- ;; Shifts @@ -2894,8 +2767,7 @@ ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas> lsl\t%<w>0, %<w>1, %<w>2" [(set_attr "simd" "yes,yes,no") - (set_attr "type" "neon_shift_imm<q>, neon_shift_reg<q>,shift_reg") - (set_attr "mode" "*,*,<MODE>")] + (set_attr "type" "neon_shift_imm<q>, neon_shift_reg<q>,shift_reg")] ) ;; Logical right shift using SISD or Integer instruction @@ -2910,8 +2782,7 @@ # lsr\t%<w>0, %<w>1, %<w>2" [(set_attr "simd" "yes,yes,no") - (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg") - (set_attr "mode" "*,*,<MODE>")] + (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg")] ) (define_split @@ -2952,8 +2823,7 @@ # asr\t%<w>0, %<w>1, %<w>2" [(set_attr "simd" "yes,yes,no") - (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg") - (set_attr "mode" "*,*,<MODE>")] + (set_attr "type" "neon_shift_imm<q>,neon_shift_reg<q>,shift_reg")] ) (define_split @@ -3044,8 +2914,7 @@ (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "rUs<cmode>")))] "" "ror\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "shift_reg") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "shift_reg")] ) ;; zero_extend version of above @@ -3056,8 +2925,7 @@ (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss"))))] "" "<shift>\\t%w0, %w1, %w2" - [(set_attr "type" "shift_reg") - (set_attr "mode" "SI")] + [(set_attr "type" "shift_reg")] ) (define_insn "*ashl<mode>3_insn" @@ -3066,8 +2934,7 @@ (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss")))] "" "lsl\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "shift_reg") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "shift_reg")] ) (define_insn "*<optab><mode>3_insn" @@ -3079,8 +2946,7 @@ operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2])); return "<bfshift>\t%w0, %w1, %2, %3"; } - [(set_attr "type" "bfm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "bfm")] ) (define_insn "*extr<mode>5_insn" @@ -3092,8 +2958,7 @@ "UINTVAL (operands[3]) < GET_MODE_BITSIZE (<MODE>mode) && (UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (<MODE>mode))" "extr\\t%<w>0, %<w>1, %<w>2, %4" - [(set_attr "type" "shift_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "shift_imm")] ) ;; zero_extend version of the above @@ -3107,8 +2972,7 @@ "UINTVAL (operands[3]) < 32 && (UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)" "extr\\t%w0, %w1, %w2, %4" - [(set_attr "type" "shift_imm") - (set_attr "mode" "SI")] + [(set_attr "type" "shift_imm")] ) (define_insn "*ror<mode>3_insn" @@ -3120,8 +2984,7 @@ operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2])); return "ror\\t%<w>0, %<w>1, %3"; } - [(set_attr "type" "shift_imm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "shift_imm")] ) ;; zero_extend version of the above @@ -3135,8 +2998,7 @@ operands[3] = GEN_INT (32 - UINTVAL (operands[2])); return "ror\\t%w0, %w1, %3"; } - [(set_attr "type" "shift_imm") - (set_attr "mode" "SI")] + [(set_attr "type" "shift_imm")] ) (define_insn "*<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode>" @@ -3149,8 +3011,7 @@ operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2])); return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3"; } - [(set_attr "type" "bfm") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "bfm")] ) (define_insn "*zero_extend<GPI:mode>_lshr<SHORT:mode>" @@ -3163,8 +3024,7 @@ operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2])); return "ubfx\t%<GPI:w>0, %<GPI:w>1, %2, %3"; } - [(set_attr "type" "bfm") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "bfm")] ) (define_insn "*extend<GPI:mode>_ashr<SHORT:mode>" @@ -3177,8 +3037,7 @@ operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2])); return "sbfx\\t%<GPI:w>0, %<GPI:w>1, %2, %3"; } - [(set_attr "type" "bfm") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "bfm")] ) ;; ------------------------------------------------------------------- @@ -3201,8 +3060,7 @@ (match_operand 3 "const_int_operand" "n")))] "" "<su>bfx\\t%<w>0, %<w>1, %3, %2" - [(set_attr "type" "bfm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "bfm")] ) ;; Bitfield Insert (insv) @@ -3245,8 +3103,7 @@ || (UINTVAL (operands[2]) + UINTVAL (operands[1]) > GET_MODE_BITSIZE (<MODE>mode)))" "bfi\\t%<w>0, %<w>3, %2, %1" - [(set_attr "type" "bfm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "bfm")] ) (define_insn "*extr_insv_lower_reg<mode>" @@ -3260,8 +3117,7 @@ || (UINTVAL (operands[3]) + UINTVAL (operands[1]) > GET_MODE_BITSIZE (<MODE>mode)))" "bfxil\\t%<w>0, %<w>2, %3, %1" - [(set_attr "type" "bfm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "bfm")] ) (define_insn "*<optab><ALLX:mode>_shft_<GPI:mode>" @@ -3276,8 +3132,7 @@ : GEN_INT (<GPI:sizen> - UINTVAL (operands[2])); return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3"; } - [(set_attr "type" "bfm") - (set_attr "mode" "<GPI:MODE>")] + [(set_attr "type" "bfm")] ) ;; XXX We should match (any_extend (ashift)) here, like (and (ashift)) below @@ -3290,8 +3145,7 @@ "exact_log2 ((INTVAL (operands[3]) >> INTVAL (operands[2])) + 1) >= 0 && (INTVAL (operands[3]) & ((1 << INTVAL (operands[2])) - 1)) == 0" "ubfiz\\t%<w>0, %<w>1, %2, %P3" - [(set_attr "type" "bfm") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "bfm")] ) (define_insn "bswap<mode>2" @@ -3299,8 +3153,7 @@ (bswap:GPI (match_operand:GPI 1 "register_operand" "r")))] "" "rev\\t%<w>0, %<w>1" - [(set_attr "type" "rev") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "rev")] ) (define_insn "bswaphi2" @@ -3308,8 +3161,7 @@ (bswap:HI (match_operand:HI 1 "register_operand" "r")))] "" "rev16\\t%w0, %w1" - [(set_attr "type" "rev") - (set_attr "mode" "HI")] + [(set_attr "type" "rev")] ) ;; zero_extend version of above @@ -3318,8 +3170,7 @@ (zero_extend:DI (bswap:SI (match_operand:SI 1 "register_operand" "r"))))] "" "rev\\t%w0, %w1" - [(set_attr "type" "rev") - (set_attr "mode" "SI")] + [(set_attr "type" "rev")] ) ;; ------------------------------------------------------------------- @@ -3335,8 +3186,7 @@ FRINT))] "TARGET_FLOAT" "frint<frint_suffix>\\t%<s>0, %<s>1" - [(set_attr "type" "f_rint<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "f_rint<s>")] ) ;; frcvt floating-point round to integer and convert standard patterns. @@ -3347,9 +3197,7 @@ FCVT)))] "TARGET_FLOAT" "fcvt<frint_suffix><su>\\t%<GPI:w>0, %<GPF:s>1" - [(set_attr "type" "f_cvtf2i") - (set_attr "mode" "<GPF:MODE>") - (set_attr "mode2" "<GPI:MODE>")] + [(set_attr "type" "f_cvtf2i")] ) ;; fma - no throw @@ -3361,8 +3209,7 @@ (match_operand:GPF 3 "register_operand" "w")))] "TARGET_FLOAT" "fmadd\\t%<s>0, %<s>1, %<s>2, %<s>3" - [(set_attr "type" "fmac<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "fmac<s>")] ) (define_insn "fnma<mode>4" @@ -3372,8 +3219,7 @@ (match_operand:GPF 3 "register_operand" "w")))] "TARGET_FLOAT" "fmsub\\t%<s>0, %<s>1, %<s>2, %<s>3" - [(set_attr "type" "fmac<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "fmac<s>")] ) (define_insn "fms<mode>4" @@ -3383,8 +3229,7 @@ (neg:GPF (match_operand:GPF 3 "register_operand" "w"))))] "TARGET_FLOAT" "fnmsub\\t%<s>0, %<s>1, %<s>2, %<s>3" - [(set_attr "type" "fmac<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "fmac<s>")] ) (define_insn "fnms<mode>4" @@ -3394,8 +3239,7 @@ (neg:GPF (match_operand:GPF 3 "register_operand" "w"))))] "TARGET_FLOAT" "fnmadd\\t%<s>0, %<s>1, %<s>2, %<s>3" - [(set_attr "type" "fmac<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "fmac<s>")] ) ;; If signed zeros are ignored, -(a * b + c) = -a * b - c. @@ -3406,8 +3250,7 @@ (match_operand:GPF 3 "register_operand" "w"))))] "!HONOR_SIGNED_ZEROS (<MODE>mode) && TARGET_FLOAT" "fnmadd\\t%<s>0, %<s>1, %<s>2, %<s>3" - [(set_attr "type" "fmac<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "fmac<s>")] ) ;; ------------------------------------------------------------------- @@ -3419,9 +3262,7 @@ (float_extend:DF (match_operand:SF 1 "register_operand" "w")))] "TARGET_FLOAT" "fcvt\\t%d0, %s1" - [(set_attr "type" "f_cvt") - (set_attr "mode" "DF") - (set_attr "mode2" "SF")] + [(set_attr "type" "f_cvt")] ) (define_insn "truncdfsf2" @@ -3429,9 +3270,7 @@ (float_truncate:SF (match_operand:DF 1 "register_operand" "w")))] "TARGET_FLOAT" "fcvt\\t%s0, %d1" - [(set_attr "type" "f_cvt") - (set_attr "mode" "SF") - (set_attr "mode2" "DF")] + [(set_attr "type" "f_cvt")] ) (define_insn "fix_trunc<GPF:mode><GPI:mode>2" @@ -3439,9 +3278,7 @@ (fix:GPI (match_operand:GPF 1 "register_operand" "w")))] "TARGET_FLOAT" "fcvtzs\\t%<GPI:w>0, %<GPF:s>1" - [(set_attr "type" "f_cvtf2i") - (set_attr "mode" "<GPF:MODE>") - (set_attr "mode2" "<GPI:MODE>")] + [(set_attr "type" "f_cvtf2i")] ) (define_insn "fixuns_trunc<GPF:mode><GPI:mode>2" @@ -3449,9 +3286,7 @@ (unsigned_fix:GPI (match_operand:GPF 1 "register_operand" "w")))] "TARGET_FLOAT" "fcvtzu\\t%<GPI:w>0, %<GPF:s>1" - [(set_attr "type" "f_cvtf2i") - (set_attr "mode" "<GPF:MODE>") - (set_attr "mode2" "<GPI:MODE>")] + [(set_attr "type" "f_cvtf2i")] ) (define_insn "float<GPI:mode><GPF:mode>2" @@ -3459,9 +3294,7 @@ (float:GPF (match_operand:GPI 1 "register_operand" "r")))] "TARGET_FLOAT" "scvtf\\t%<GPF:s>0, %<GPI:w>1" - [(set_attr "type" "f_cvti2f") - (set_attr "mode" "<GPF:MODE>") - (set_attr "mode2" "<GPI:MODE>")] + [(set_attr "type" "f_cvti2f")] ) (define_insn "floatuns<GPI:mode><GPF:mode>2" @@ -3469,9 +3302,7 @@ (unsigned_float:GPF (match_operand:GPI 1 "register_operand" "r")))] "TARGET_FLOAT" "ucvtf\\t%<GPF:s>0, %<GPI:w>1" - [(set_attr "type" "f_cvt") - (set_attr "mode" "<GPF:MODE>") - (set_attr "mode2" "<GPI:MODE>")] + [(set_attr "type" "f_cvt")] ) ;; ------------------------------------------------------------------- @@ -3485,8 +3316,7 @@ (match_operand:GPF 2 "register_operand" "w")))] "TARGET_FLOAT" "fadd\\t%<s>0, %<s>1, %<s>2" - [(set_attr "type" "fadd<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "fadd<s>")] ) (define_insn "sub<mode>3" @@ -3496,8 +3326,7 @@ (match_operand:GPF 2 "register_operand" "w")))] "TARGET_FLOAT" "fsub\\t%<s>0, %<s>1, %<s>2" - [(set_attr "type" "fadd<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "fadd<s>")] ) (define_insn "mul<mode>3" @@ -3507,8 +3336,7 @@ (match_operand:GPF 2 "register_operand" "w")))] "TARGET_FLOAT" "fmul\\t%<s>0, %<s>1, %<s>2" - [(set_attr "type" "fmul<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "fmul<s>")] ) (define_insn "*fnmul<mode>3" @@ -3518,8 +3346,7 @@ (match_operand:GPF 2 "register_operand" "w")))] "TARGET_FLOAT" "fnmul\\t%<s>0, %<s>1, %<s>2" - [(set_attr "type" "fmul<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "fmul<s>")] ) (define_insn "div<mode>3" @@ -3529,8 +3356,7 @@ (match_operand:GPF 2 "register_operand" "w")))] "TARGET_FLOAT" "fdiv\\t%<s>0, %<s>1, %<s>2" - [(set_attr "type" "fdiv<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "fdiv<s>")] ) (define_insn "neg<mode>2" @@ -3538,8 +3364,7 @@ (neg:GPF (match_operand:GPF 1 "register_operand" "w")))] "TARGET_FLOAT" "fneg\\t%<s>0, %<s>1" - [(set_attr "type" "ffarith<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "ffarith<s>")] ) (define_insn "sqrt<mode>2" @@ -3547,8 +3372,7 @@ (sqrt:GPF (match_operand:GPF 1 "register_operand" "w")))] "TARGET_FLOAT" "fsqrt\\t%<s>0, %<s>1" - [(set_attr "type" "fsqrt<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "fsqrt<s>")] ) (define_insn "abs<mode>2" @@ -3556,8 +3380,7 @@ (abs:GPF (match_operand:GPF 1 "register_operand" "w")))] "TARGET_FLOAT" "fabs\\t%<s>0, %<s>1" - [(set_attr "type" "ffarith<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "ffarith<s>")] ) ;; Given that smax/smin do not specify the result when either input is NaN, @@ -3570,8 +3393,7 @@ (match_operand:GPF 2 "register_operand" "w")))] "TARGET_FLOAT" "fmaxnm\\t%<s>0, %<s>1, %<s>2" - [(set_attr "type" "f_minmax<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "f_minmax<s>")] ) (define_insn "smin<mode>3" @@ -3580,8 +3402,7 @@ (match_operand:GPF 2 "register_operand" "w")))] "TARGET_FLOAT" "fminnm\\t%<s>0, %<s>1, %<s>2" - [(set_attr "type" "f_minmax<s>") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "f_minmax<s>")] ) ;; ------------------------------------------------------------------- @@ -3614,7 +3435,6 @@ "reload_completed || reload_in_progress" "fmov\\t%x0, %d1" [(set_attr "type" "f_mrc") - (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -3626,7 +3446,6 @@ "reload_completed || reload_in_progress" "fmov\\t%x0, %1.d[1]" [(set_attr "type" "f_mrc") - (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -3637,7 +3456,6 @@ "reload_completed || reload_in_progress" "fmov\\t%0.d[1], %x1" [(set_attr "type" "f_mcr") - (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -3647,7 +3465,6 @@ "reload_completed || reload_in_progress" "fmov\\t%d0, %x1" [(set_attr "type" "f_mcr") - (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -3658,7 +3475,6 @@ "reload_completed || reload_in_progress" "fmov\\t%d0, %d1" [(set_attr "type" "f_mcr") - (set_attr "mode" "DI") (set_attr "length" "4") ]) @@ -3689,8 +3505,7 @@ (match_operand 2 "aarch64_valid_symref" "S")))] "" "add\\t%<w>0, %<w>1, :lo12:%a2" - [(set_attr "type" "alu_reg") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "alu_reg")] ) (define_insn "ldr_got_small_<mode>" @@ -3701,8 +3516,7 @@ UNSPEC_GOTSMALLPIC))] "" "ldr\\t%<w>0, [%1, #:got_lo12:%a2]" - [(set_attr "type" "load1") - (set_attr "mode" "<MODE>")] + [(set_attr "type" "load1")] ) (define_insn "ldr_got_small_sidi" @@ -3714,8 +3528,7 @@ UNSPEC_GOTSMALLPIC)))] "TARGET_ILP32" "ldr\\t%w0, [%1, #:got_lo12:%a2]" - [(set_attr "type" "load1") - (set_attr "mode" "DI")] + [(set_attr "type" "load1")] ) (define_insn "ldr_got_tiny" @@ -3724,8 +3537,7 @@ UNSPEC_GOTTINYPIC))] "" "ldr\\t%0, %L1" - [(set_attr "type" "load1") - (set_attr "mode" "DI")] + [(set_attr "type" "load1")] ) (define_insn "aarch64_load_tp_hard" @@ -3733,8 +3545,7 @@ (unspec:DI [(const_int 0)] UNSPEC_TLS))] "" "mrs\\t%0, tpidr_el0" - [(set_attr "type" "mrs") - (set_attr "mode" "DI")] + [(set_attr "type" "mrs")] ) ;; The TLS ABI specifically requires that the compiler does not schedule @@ -3768,7 +3579,6 @@ "" "adrp\\t%0, %A1\;ldr\\t%0, [%0, #%L1]" [(set_attr "type" "load1") - (set_attr "mode" "DI") (set_attr "length" "8")] ) @@ -3780,7 +3590,6 @@ "" "add\\t%0, %1, #%G2\;add\\t%0, %0, #%L2" [(set_attr "type" "alu_reg") - (set_attr "mode" "DI") (set_attr "length" "8")] ) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 12934233a48..03bb13612eb 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -27986,10 +27986,11 @@ arm_dbx_register_number (unsigned int regno) static rtx arm_dwarf_register_span (rtx rtl) { + enum machine_mode mode; unsigned regno; + rtx parts[8]; int nregs; int i; - rtx p; regno = REGNO (rtl); if (!IS_VFP_REGNUM (regno)) @@ -28002,15 +28003,33 @@ arm_dwarf_register_span (rtx rtl) corresponding D register. Until GDB supports this, we shall use the legacy encodings. We also use these encodings for D0-D15 for compatibility with older debuggers. */ - if (VFP_REGNO_OK_FOR_SINGLE (regno)) + mode = GET_MODE (rtl); + if (GET_MODE_SIZE (mode) < 8) return NULL_RTX; - nregs = GET_MODE_SIZE (GET_MODE (rtl)) / 8; - p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs)); - for (i = 0; i < nregs; i++) - XVECEXP (p, 0, i) = gen_rtx_REG (DImode, regno + i); + if (VFP_REGNO_OK_FOR_SINGLE (regno)) + { + nregs = GET_MODE_SIZE (mode) / 4; + for (i = 0; i < nregs; i += 2) + if (TARGET_BIG_END) + { + parts[i] = gen_rtx_REG (SImode, regno + i + 1); + parts[i + 1] = gen_rtx_REG (SImode, regno + i); + } + else + { + parts[i] = gen_rtx_REG (SImode, regno + i); + parts[i + 1] = gen_rtx_REG (SImode, regno + i + 1); + } + } + else + { + nregs = GET_MODE_SIZE (mode) / 8; + for (i = 0; i < nregs; i++) + parts[i] = gen_rtx_REG (DImode, regno + i); + } - return p; + return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nregs , parts)); } #if ARM_UNWIND_INFO diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 8e6bbd14dff..57bbc91ec26 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -3913,7 +3913,7 @@ ix86_option_override_internal (bool main_args_p, functions. */ else if (fast_math_flags_set_p (&global_options) && TARGET_SSE2_P (opts->x_ix86_isa_flags)) - ix86_fpmath = FPMATH_SSE; + opts->x_ix86_fpmath = FPMATH_SSE; else opts->x_ix86_fpmath = TARGET_FPMATH_DEFAULT_P (opts->x_ix86_isa_flags); diff --git a/gcc/config/i386/ssemath.h b/gcc/config/i386/ssemath.h index 4e4656fa0d1..83abfddfeb7 100644 --- a/gcc/config/i386/ssemath.h +++ b/gcc/config/i386/ssemath.h @@ -19,6 +19,10 @@ along with GCC; see the file COPYING3. If not see #undef TARGET_FPMATH_DEFAULT #define TARGET_FPMATH_DEFAULT (TARGET_SSE2 ? FPMATH_SSE : FPMATH_387) +#undef TARGET_FPMATH_DEFAULT_P +#define TARGET_FPMATH_DEFAULT_P(x) \ + (TARGET_SSE2_P(x) ? FPMATH_SSE : FPMATH_387) + #undef TARGET_SUBTARGET32_ISA_DEFAULT #define TARGET_SUBTARGET32_ISA_DEFAULT \ (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index d06d5747081..0aeb35aa6d6 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -3972,7 +3972,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, case DIV: /* Check for a reciprocal. */ if (float_mode_p - && ISA_HAS_FP4 + && ISA_HAS_FP_RECIP_RSQRT (mode) && flag_unsafe_math_optimizations && XEXP (x, 0) == CONST1_RTX (mode)) { diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 11687b8a053..021419c0a6a 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -882,13 +882,18 @@ struct mips_cpu_info { /* This is a catch all for other mips4 instructions: indexed load, the FP madd and msub instructions, and the FP recip and recip sqrt - instructions. */ + instructions. Note that this macro should only be used by other + ISA_HAS_* macros. */ #define ISA_HAS_FP4 ((ISA_MIPS4 \ - || (ISA_MIPS32R2 && TARGET_FLOAT64) \ + || ISA_MIPS32R2 \ || ISA_MIPS64 \ || ISA_MIPS64R2) \ && !TARGET_MIPS16) +/* ISA has floating-point indexed load and store instructions + (LWXC1, LDXC1, SWXC1 and SDXC1). */ +#define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4 + /* ISA has paired-single instructions. */ #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2) @@ -906,21 +911,34 @@ struct mips_cpu_info { #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */ -#define ISA_HAS_FP_MADD4_MSUB4 (ISA_HAS_FP4 \ - || (ISA_MIPS32R2 && !TARGET_MIPS16)) +#define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */ #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF /* ISA has floating-point nmadd and nmsub instructions 'd = -((a * b) [+-] c)'. */ -#define ISA_HAS_NMADD4_NMSUB4 (ISA_HAS_FP4 \ - || (ISA_MIPS32R2 && !TARGET_MIPS16)) +#define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4 /* ISA has floating-point nmadd and nmsub instructions 'c = -((a * b) [+-] c)'. */ #define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF +/* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The + MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when + doubles are stored in pairs of FPRs, so for safety's sake, we apply + this restriction to the MIPS IV ISA too. */ +#define ISA_HAS_FP_RECIP_RSQRT(MODE) \ + (((ISA_HAS_FP4 \ + && ((MODE) == SFmode \ + || ((TARGET_FLOAT64 \ + || ISA_MIPS32R2 \ + || ISA_MIPS64R2) \ + && (MODE) == DFmode))) \ + || (TARGET_SB1 \ + && (MODE) == V2SFmode)) \ + && !TARGET_MIPS16) + /* ISA has count leading zeroes/ones instruction (not implemented). */ #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ || ISA_MIPS32R2 \ @@ -991,11 +1009,7 @@ struct mips_cpu_info { 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. (prefx is a cop1x instruction, so can only be used if FP is enabled.) */ -#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \ - || ISA_MIPS32R2 \ - || ISA_MIPS64 \ - || ISA_MIPS64R2) \ - && !TARGET_MIPS16) +#define ISA_HAS_PREFETCHX ISA_HAS_FP4 /* True if trunc.w.s and trunc.w.d are real (not synthetic) instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 6991f203df4..1bd1ec5e2cc 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -881,15 +881,6 @@ (define_mode_attr sqrt_condition [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")]) -;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt -;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D -;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs, -;; so for safety's sake, we apply this restriction to all targets. -(define_mode_attr recip_condition - [(SF "ISA_HAS_FP4") - (DF "ISA_HAS_FP4 && TARGET_FLOAT64") - (V2SF "TARGET_SB1")]) - ;; This code iterator allows signed and unsigned widening multiplications ;; to use the same template. (define_code_iterator any_extend [sign_extend zero_extend]) @@ -2501,7 +2492,8 @@ "<divide_condition>" { if (const_1_operand (operands[1], <MODE>mode)) - if (!(<recip_condition> && flag_unsafe_math_optimizations)) + if (!(ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) + && flag_unsafe_math_optimizations)) operands[1] = force_reg (<MODE>mode, operands[1]); }) @@ -2539,7 +2531,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") (match_operand:ANYF 2 "register_operand" "f")))] - "<recip_condition> && flag_unsafe_math_optimizations" + "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations" { if (TARGET_FIX_SB1) return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; @@ -2674,7 +2666,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))] - "<recip_condition> && flag_unsafe_math_optimizations" + "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations" { if (TARGET_FIX_SB1) return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; @@ -2692,7 +2684,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "") (match_operand:ANYF 2 "register_operand" "f"))))] - "<recip_condition> && flag_unsafe_math_optimizations" + "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations" { if (TARGET_FIX_SB1) return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0"; @@ -4448,7 +4440,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d") (match_operand:P 2 "register_operand" "d"))))] - "ISA_HAS_FP4" + "ISA_HAS_LXC1_SXC1" "<ANYF:loadx>\t%0,%1(%2)" [(set_attr "type" "fpidxload") (set_attr "mode" "<ANYF:UNITMODE>")]) @@ -4457,7 +4449,7 @@ [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d") (match_operand:P 2 "register_operand" "d"))) (match_operand:ANYF 0 "register_operand" "f"))] - "ISA_HAS_FP4" + "ISA_HAS_LXC1_SXC1" "<ANYF:storex>\t%0,%1(%2)" [(set_attr "type" "fpidxstore") (set_attr "mode" "<ANYF:UNITMODE>")]) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 52879c8bf23..76b4f02381e 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -16665,6 +16665,13 @@ rs6000_cannot_change_mode_class (enum machine_mode from, if (TARGET_IEEEQUAD && (to == TFmode || from == TFmode)) return true; + /* TDmode in floating-mode registers must always go into a register + pair with the most significant word in the even-numbered register + to match ISA requirements. In little-endian mode, this does not + match subreg numbering, so we cannot allow subregs. */ + if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode)) + return true; + if (from_size < 8 || to_size < 8) return true; @@ -19607,6 +19614,39 @@ rs6000_split_multireg_move (rtx dst, rtx src) gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode)); + /* TDmode residing in FP registers is special, since the ISA requires that + the lower-numbered word of a register pair is always the most significant + word, even in little-endian mode. This does not match the usual subreg + semantics, so we cannnot use simplify_gen_subreg in those cases. Access + the appropriate constituent registers "by hand" in little-endian mode. + + Note we do not need to check for destructive overlap here since TDmode + can only reside in even/odd register pairs. */ + if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN) + { + rtx p_src, p_dst; + int i; + + for (i = 0; i < nregs; i++) + { + if (REG_P (src) && FP_REGNO_P (REGNO (src))) + p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i); + else + p_src = simplify_gen_subreg (reg_mode, src, mode, + i * reg_mode_size); + + if (REG_P (dst) && FP_REGNO_P (REGNO (dst))) + p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i); + else + p_dst = simplify_gen_subreg (reg_mode, dst, mode, + i * reg_mode_size); + + emit_insn (gen_rtx_SET (VOIDmode, p_dst, p_src)); + } + + return; + } + if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) { /* Move register range backwards, if we might have destructive diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 8a51afb3c86..977ef963411 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1497,9 +1497,10 @@ UNSPEC_VSX_SET))] "VECTOR_MEM_VSX_P (<MODE>mode)" { - if (INTVAL (operands[3]) == 0) + int idx_first = BYTES_BIG_ENDIAN ? 0 : 1; + if (INTVAL (operands[3]) == idx_first) return \"xxpermdi %x0,%x2,%x1,1\"; - else if (INTVAL (operands[3]) == 1) + else if (INTVAL (operands[3]) == 1 - idx_first) return \"xxpermdi %x0,%x1,%x2,0\"; else gcc_unreachable (); @@ -1514,8 +1515,12 @@ [(match_operand:QI 2 "u5bit_cint_operand" "i,i,i")])))] "VECTOR_MEM_VSX_P (<MODE>mode)" { + int fldDM; gcc_assert (UINTVAL (operands[2]) <= 1); - operands[3] = GEN_INT (INTVAL (operands[2]) << 1); + fldDM = INTVAL (operands[2]) << 1; + if (!BYTES_BIG_ENDIAN) + fldDM = 3 - fldDM; + operands[3] = GEN_INT (fldDM); return \"xxpermdi %x0,%x1,%x1,%3\"; } [(set_attr "type" "vecperm")]) @@ -1535,6 +1540,21 @@ (const_string "fpload"))) (set_attr "length" "4")]) +;; Optimize extracting element 1 from memory for little endian +(define_insn "*vsx_extract_<mode>_one_le" + [(set (match_operand:<VS_scalar> 0 "vsx_register_operand" "=ws,d,?wa") + (vec_select:<VS_scalar> + (match_operand:VSX_D 1 "indexed_or_indirect_operand" "Z,Z,Z") + (parallel [(const_int 1)])))] + "VECTOR_MEM_VSX_P (<MODE>mode) && !WORDS_BIG_ENDIAN" + "lxsd%U1x %x0,%y1" + [(set (attr "type") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (const_string "fpload"))) + (set_attr "length" "4")]) + ;; Extract a SF element from V4SF (define_insn_and_split "vsx_extract_v4sf" [(set (match_operand:SF 0 "vsx_register_operand" "=f,f") @@ -1555,7 +1575,7 @@ rtx op2 = operands[2]; rtx op3 = operands[3]; rtx tmp; - HOST_WIDE_INT ele = INTVAL (op2); + HOST_WIDE_INT ele = BYTES_BIG_ENDIAN ? INTVAL (op2) : 3 - INTVAL (op2); if (ele == 0) tmp = op1; diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index d5f7f15c1cc..6981ab6229a 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -720,7 +720,9 @@ got_mode_name:; /* Register SH specific RTL passes. */ extern opt_pass* make_pass_sh_treg_combine (gcc::context* ctx, bool split_insns, - const char* name); + const char* name); +extern opt_pass* make_pass_sh_optimize_sett_clrt (gcc::context* ctx, + const char* name); static void register_sh_passes (void) { @@ -744,6 +746,13 @@ register_sh_passes (void) reordering as this sometimes creates new opportunities. */ register_pass (make_pass_sh_treg_combine (g, true, "sh_treg_combine3"), PASS_POS_INSERT_AFTER, "split4", 1); + + /* Optimize sett and clrt insns, by e.g. removing them if the T bit value + is known after a conditional branch. + This must be done after basic blocks and branch conditions have + stabilized and won't be changed by further passes. */ + register_pass (make_pass_sh_optimize_sett_clrt (g, "sh_optimize_sett_clrt"), + PASS_POS_INSERT_BEFORE, "sched2", 1); } /* Implement TARGET_OPTION_OVERRIDE macro. Validate and override diff --git a/gcc/config/sh/sh_optimize_sett_clrt.cc b/gcc/config/sh/sh_optimize_sett_clrt.cc new file mode 100644 index 00000000000..abb75672e86 --- /dev/null +++ b/gcc/config/sh/sh_optimize_sett_clrt.cc @@ -0,0 +1,453 @@ +/* An SH specific RTL pass that tries to optimize clrt and sett insns. + Copyright (C) 2013 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "machmode.h" +#include "basic-block.h" +#include "df.h" +#include "rtl.h" +#include "insn-config.h" +#include "tree-pass.h" +#include "target.h" + +#include <vector> + +/* +This pass tries to eliminate unnecessary sett or clrt instructions in cases +where the ccreg value is already known to be the same as the constant set +would set it to. This is done as follows: + +Check every BB's insn and see if it's a sett or clrt. +Once a sett or clrt insn is hit, walk insns and predecessor basic blocks +backwards from that insn and determine all possible ccreg values from all +basic block paths. +Insns that set the ccreg value in some way (simple set, clobber etc) are +recorded. Conditional branches where one edge leads to the sett / clrt insn +are also recorded, since for each edge in the conditional branch the ccreg +value is known constant. +After collecting all possible ccreg values at the sett / clrt insn, check that +all the values are the same. If that value is the same as the sett / clrt +insn would set the ccreg to, the sett / clrt insn can be eliminated. +*/ + + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// Helper functions + +#define log_msg(...)\ + do { if (dump_file != NULL) fprintf (dump_file, __VA_ARGS__); } while (0) + +#define log_insn(i)\ + do { if (dump_file != NULL) print_rtl_single (dump_file, \ + (const_rtx)i); } while (0) + +#define log_rtx(r)\ + do { if (dump_file != NULL) print_rtl (dump_file, (const_rtx)r); } while (0) + +#define log_return(retval, ...)\ + do { if (dump_file != NULL) fprintf (dump_file, __VA_ARGS__); \ + return retval; } while (0) + +#define log_return_void(...)\ + do { if (dump_file != NULL) fprintf (dump_file, __VA_ARGS__); \ + return; } while (0) + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// RTL pass class + +class sh_optimize_sett_clrt : public rtl_opt_pass +{ +public: + sh_optimize_sett_clrt (gcc::context* ctx, const char* name); + virtual ~sh_optimize_sett_clrt (void); + virtual bool gate (void); + virtual unsigned int execute (void); + +private: + static const pass_data default_pass_data; + + struct ccreg_value + { + // The insn at which the ccreg value was determined. + rtx insn; + + // The basic block where the insn was discovered. + // Notice that the CFG might be invalid at late RTL stages and + // BLOCK_FOR_INSN might return null. Thus the basic block are recorded + // here while traversing them. + basic_block bb; + + // The value of ccreg. If NULL_RTX, the value is not known, e.g. if the + // ccreg is clobbered. + rtx value; + }; + + // Update the mode of the captured m_ccreg with the specified mode. + void update_ccreg_mode (machine_mode m); + + // Given an insn pattern, check if it sets the ccreg to a constant value + // of either zero or STORE_FLAG_VALUE. If so, return the value rtx, + // NULL_RTX otherwise. + rtx const_setcc_value (rtx pat) const; + + // Given a start insn and its basic block, recursively determine all + // possible ccreg values in all basic block paths that can lead to the + // start insn. + void find_last_ccreg_values (rtx start_insn, basic_block bb, + std::vector<ccreg_value>& values_out, + basic_block prev_visited_bb = NULL) const; + + // Given a cbranch insn, its basic block and another basic block, determine + // the value to which the ccreg will be set after jumping/falling through to + // the specified target basic block. + bool sh_cbranch_ccreg_value (rtx cbranch_insn, + basic_block cbranch_insn_bb, + basic_block branch_target_bb) const; + + // Check whether all of the ccreg values are the same. + static bool all_ccreg_values_equal (const std::vector<ccreg_value>& values); + + // Remove REG_DEAD and REG_UNUSED notes from insns of the specified + // ccreg_value entries. + void remove_ccreg_dead_unused_notes (std::vector<ccreg_value>& values) const; + + // rtx of the ccreg that is obtained from the target. + rtx m_ccreg; +}; + +const pass_data sh_optimize_sett_clrt::default_pass_data = +{ + RTL_PASS, // type + "", // name (overwritten by the constructor) + OPTGROUP_NONE, // optinfo_flags + true, // has_gate + true, // has_execute + TV_OPTIMIZE, // tv_id + 0, // properties_required + 0, // properties_provided + 0, // properties_destroyed + 0, // todo_flags_start + 0 // todo_flags_finish +}; + +sh_optimize_sett_clrt::sh_optimize_sett_clrt (gcc::context* ctx, + const char* name) +: rtl_opt_pass (default_pass_data, ctx), + m_ccreg (NULL_RTX) +{ + // Overwrite default name in pass_data base class. + this->name = name; +} + +sh_optimize_sett_clrt::~sh_optimize_sett_clrt (void) +{ +} + +bool +sh_optimize_sett_clrt::gate (void) +{ + return optimize > 0; +} + +unsigned int +sh_optimize_sett_clrt::execute (void) +{ + unsigned int ccr0 = INVALID_REGNUM; + unsigned int ccr1 = INVALID_REGNUM; + + if (targetm.fixed_condition_code_regs (&ccr0, &ccr1) + && ccr0 != INVALID_REGNUM) + { + // Initially create a reg rtx with VOIDmode. + // When the constant setcc is discovered, the mode is changed + // to the mode that is actually used by the target. + m_ccreg = gen_rtx_REG (VOIDmode, ccr0); + } + + if (m_ccreg == NULL_RTX) + log_return (0, "no ccreg.\n\n"); + + if (STORE_FLAG_VALUE != 1) + log_return (0, "unsupported STORE_FLAG_VALUE %d", STORE_FLAG_VALUE); + + log_msg ("ccreg: "); + log_rtx (m_ccreg); + log_msg (" STORE_FLAG_VALUE = %d\n", STORE_FLAG_VALUE); + + if (!df_regs_ever_live_p (ccr0)) + log_return (0, "ccreg never live\n\n"); + + // Output vector for find_known_ccreg_values. + std::vector<ccreg_value> ccreg_values; + ccreg_values.reserve (32); + + // Look for insns that set the ccreg to a constant value and see if it can + // be optimized. + basic_block bb; + FOR_EACH_BB_REVERSE (bb) + for (rtx next_i, i = NEXT_INSN (BB_HEAD (bb)); + i != NULL_RTX && i != BB_END (bb); i = next_i) + { + next_i = NEXT_INSN (i); + + if (!INSN_P (i) || !NONDEBUG_INSN_P (i)) + continue; + + rtx setcc_val = const_setcc_value (PATTERN (i)); + if (setcc_val != NULL_RTX) + { + update_ccreg_mode (GET_MODE (XEXP (PATTERN (i), 0))); + + log_msg ("\n\nfound const setcc insn in [bb %d]: \n", bb->index); + log_insn (i); + log_msg ("\n"); + + ccreg_values.clear (); + find_last_ccreg_values (PREV_INSN (i), bb, ccreg_values); + + log_msg ("number of ccreg values collected: %u\n", + (unsigned int)ccreg_values.size ()); + + // If all the collected values are equal and are equal to the + // constant value of the setcc insn, the setcc insn can be + // removed. + if (all_ccreg_values_equal (ccreg_values) + && rtx_equal_p (ccreg_values.front ().value, setcc_val)) + { + log_msg ("all values are "); + log_rtx (setcc_val); + log_msg ("\n"); + + delete_insn (i); + remove_ccreg_dead_unused_notes (ccreg_values); + } + } + } + + log_return (0, "\n\n"); +} + +void +sh_optimize_sett_clrt::update_ccreg_mode (machine_mode m) +{ + if (GET_MODE (m_ccreg) == m) + return; + + PUT_MODE (m_ccreg, m); + log_msg ("updated ccreg mode: "); + log_rtx (m_ccreg); + log_msg ("\n\n"); +} + +rtx +sh_optimize_sett_clrt::const_setcc_value (rtx pat) const +{ + if (GET_CODE (pat) == SET + && REG_P (XEXP (pat, 0)) && REGNO (XEXP (pat, 0)) == REGNO (m_ccreg) + && CONST_INT_P (XEXP (pat, 1)) + && (INTVAL (XEXP (pat, 1)) == 0 + || INTVAL (XEXP (pat, 1)) == STORE_FLAG_VALUE)) + return XEXP (pat, 1); + else + return NULL_RTX; +} + +bool +sh_optimize_sett_clrt +::sh_cbranch_ccreg_value (rtx cbranch_insn, basic_block cbranch_insn_bb, + basic_block branch_target_bb) const +{ + rtx pc_set_rtx = pc_set (cbranch_insn); + gcc_assert (pc_set_rtx != NULL_RTX); + gcc_assert (branch_target_bb != NULL); + + rtx cond = XEXP (XEXP (pc_set_rtx, 1), 0); + bool branch_if; + + if (GET_CODE (cond) == NE + && REG_P (XEXP (cond, 0)) && REGNO (XEXP (cond, 0)) == REGNO (m_ccreg) + && XEXP (cond, 1) == const0_rtx) + branch_if = true; + + else if (GET_CODE (cond) == EQ + && REG_P (XEXP (cond, 0)) && REGNO (XEXP (cond, 0)) == REGNO (m_ccreg) + && XEXP (cond, 1) == const0_rtx) + branch_if = false; + + else + gcc_unreachable (); + + if (branch_target_bb == BRANCH_EDGE (cbranch_insn_bb)->dest) + return branch_if; + else if (branch_target_bb == FALLTHRU_EDGE (cbranch_insn_bb)->dest) + return !branch_if; + else + gcc_unreachable (); +} + +void +sh_optimize_sett_clrt +::find_last_ccreg_values (rtx start_insn, basic_block bb, + std::vector<ccreg_value>& values_out, + basic_block prev_visited_bb) const +{ + if (start_insn == NULL_RTX) + return; + + log_msg ("looking for ccreg values in [bb %d]\n", bb->index); + + for (rtx i = start_insn; i != NULL_RTX && i != PREV_INSN (BB_HEAD (bb)); + i = PREV_INSN (i)) + { + if (!INSN_P (i)) + continue; + + if (reg_set_p (m_ccreg, i)) + { + const_rtx set_rtx = set_of (m_ccreg, i); + + ccreg_value v; + v.insn = i; + v.bb = bb; + v.value = set_rtx != NULL_RTX && GET_CODE (set_rtx) == SET + ? XEXP (set_rtx, 1) + : NULL_RTX; + + log_msg ("found setcc in [bb %d] in insn:\n", bb->index); + log_insn (i); + log_msg ("\nccreg value: "); + log_rtx (v.value); + log_msg ("\n"); + + values_out.push_back (v); + return; + } + + if (any_condjump_p (i) && onlyjump_p (i) && prev_visited_bb != NULL) + { + // For a conditional branch the ccreg value will be a known constant + // of either 0 or STORE_FLAG_VALUE after branching/falling through + // to one of the two successor BBs. Record the value for the BB + // where we came from. + log_msg ("found cbranch in [bb %d]:\n", bb->index); + log_insn (i); + + ccreg_value v; + v.insn = i; + v.bb = bb; + v.value = GEN_INT (sh_cbranch_ccreg_value (i, bb, prev_visited_bb)); + + log_msg (" branches to [bb %d] with ccreg value ", + prev_visited_bb->index); + log_rtx (v.value); + log_msg ("\n"); + + values_out.push_back (v); + return; + } + } + + // If here, we've walked up all the insns of the current basic block + // and none of them seems to modify the ccreg. + // In this case, check the predecessor basic blocks. + unsigned int pred_bb_count = 0; + + // If the current basic block is the same as the previous one, it's a loop. + // Don't try to recurse again, as this will result in an infinite loop. + if (bb != prev_visited_bb) + for (edge_iterator ei = ei_start (bb->preds); !ei_end_p (ei); ei_next (&ei)) + { + basic_block pred_bb = ei_edge (ei)->src; + if (pred_bb->index == ENTRY_BLOCK) + continue; + + pred_bb_count += 1; + find_last_ccreg_values (BB_END (pred_bb), pred_bb, values_out, bb); + } + + log_msg ("[bb %d] pred_bb_count = %u\n", bb->index, pred_bb_count); + + // If here, we've walked up all the predecessor basic blocks without finding + // anything setcc related. Add an entry for the last insn of the current + // basic block with the ccreg value being set to unknown (NULL_RTX). + if (pred_bb_count == 0) + { + log_msg ("unknown ccreg value for [bb %d]\n", bb->index); + + ccreg_value v; + v.insn = BB_END (bb); + v.bb = bb; + v.value = NULL_RTX; + + values_out.push_back (v); + } +} + +bool +sh_optimize_sett_clrt +::all_ccreg_values_equal (const std::vector<ccreg_value>& values) +{ + if (values.empty ()) + return false; + + rtx last_value = values.front ().value; + + // If the ccreg is modified in the insn but the exact value is not known + // the value rtx might be null. + if (last_value == NULL_RTX) + return false; + + for (std::vector<ccreg_value>::const_iterator i = values.begin (); + i != values.end (); ++i) + if (i->value == NULL_RTX || !rtx_equal_p (last_value, i->value)) + return false; + + return true; +} + +void +sh_optimize_sett_clrt +::remove_ccreg_dead_unused_notes (std::vector<ccreg_value>& values) const +{ + for (std::vector<ccreg_value>::iterator i = values.begin (); + i != values.end (); ++i) + { + if (i->insn == NULL_RTX) + continue; + + rtx n = find_regno_note (i->insn, REG_DEAD, REGNO (m_ccreg)); + if (n != NULL_RTX) + remove_note (i->insn, n); + + n = find_regno_note (i->insn, REG_UNUSED, REGNO (m_ccreg)); + if (n != NULL_RTX) + remove_note (i->insn, n); + } +} + +// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +// This allows instantiating the pass somewhere else without having to pull +// in a header file. +opt_pass* +make_pass_sh_optimize_sett_clrt (gcc::context* ctx, const char* name) +{ + return new sh_optimize_sett_clrt (ctx, name); +} diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh index 710bc873e75..405d3142253 100644 --- a/gcc/config/sh/t-sh +++ b/gcc/config/sh/t-sh @@ -29,6 +29,10 @@ sh_treg_combine.o: $(srcdir)/config/sh/sh_treg_combine.cc \ $(CONFIG_H) $(SYSTEM_H) $(TREE_H) $(TM_H) $(TM_P_H) coretypes.h $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $< +sh_optimize_sett_clrt.o: $(srcdir)/config/sh/sh_optimize_sett_clrt.cc \ + $(CONFIG_H) $(SYSTEM_H) $(TREE_H) $(TM_H) $(TM_P_H) coretypes.h + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $< + DEFAULT_ENDIAN = $(word 1,$(TM_ENDIAN_CONFIG)) OTHER_ENDIAN = $(word 2,$(TM_ENDIAN_CONFIG)) diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 13192c0aa21..410c8eeee03 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -10643,7 +10643,7 @@ sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, && TREE_CODE (arg1) == VECTOR_CST && TREE_CODE (arg2) == INTEGER_CST) { - bool overflow, overall_overflow = false; + bool overflow = false; wide_int result = arg2; wide_int tmp; unsigned i; @@ -10653,21 +10653,19 @@ sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree e0 = VECTOR_CST_ELT (arg0, i); tree e1 = VECTOR_CST_ELT (arg1, i); - tmp = wi::neg (e1, &overflow); - overall_overflow |= overall_overflow; - tmp = wi::add (e0, tmp, SIGNED, &overflow); - overall_overflow |= overall_overflow; - if (wi::neg_p (tmp)) - { - tmp = wi::neg (tmp, &overflow); - overall_overflow |= overall_overflow; - } + bool neg1_ovf, neg2_ovf, add1_ovf, add2_ovf; - result = wi::add (result, tmp, SIGNED, &overflow); - overall_overflow |= overall_overflow; + tmp = wi::neg (e1, &neg1_ovf); + tmp = wi::add (e0, tmp, SIGNED, &add1_ovf); + if (wi::neg_p (tmp)) + tmp = wi::neg (tmp, &neg2_ovf); + else + neg2_ovf = false; + result = wi::add (result, tmp, SIGNED, &add2_ovf); + overflow |= neg1_ovf | neg2_ovf | add1_ovf | add2_ovf; } - gcc_assert (!overall_overflow); + gcc_assert (!overflow); return wide_int_to_tree (rtype, result); } diff --git a/gcc/cse.c b/gcc/cse.c index cebb7a10bb8..15e582cd223 100644 --- a/gcc/cse.c +++ b/gcc/cse.c @@ -3296,8 +3296,8 @@ fold_rtx (rtx x, rtx insn) break; new_rtx = simplify_unary_operation (code, mode, - const_arg0 ? const_arg0 : folded_arg0, - mode_arg0); + const_arg0 ? const_arg0 : folded_arg0, + mode_arg0); } break; diff --git a/gcc/dbxout.c b/gcc/dbxout.c index 5da1e0d0e8a..bbd8be07eac 100644 --- a/gcc/dbxout.c +++ b/gcc/dbxout.c @@ -2315,6 +2315,10 @@ dbxout_type (tree type, int full) dbxout_type (TREE_TYPE (type), 0); break; + case POINTER_BOUNDS_TYPE: + /* No debug info for pointer bounds type supported yet. */ + break; + default: gcc_unreachable (); } diff --git a/gcc/dominance.c b/gcc/dominance.c index 3d88c0d3ed1..5ece3f68b94 100644 --- a/gcc/dominance.c +++ b/gcc/dominance.c @@ -227,7 +227,7 @@ calc_dfs_tree_nonrec (struct dom_info *di, basic_block bb, bool reverse) edge_iterator *stack; edge_iterator ei, einext; int sp; - /* Start block (ENTRY_BLOCK_PTR for forward problem, EXIT_BLOCK for backward + /* Start block (the entry block for forward problem, exit block for backward problem). */ basic_block en_block; /* Ending block. */ diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c index d31cab99012..3c1e0023c3f 100644 --- a/gcc/dwarf2out.c +++ b/gcc/dwarf2out.c @@ -18457,7 +18457,7 @@ gen_subprogram_die (tree decl, dw_die_ref context_die) gen_formal_parameter_pack_die (generic_decl_parm, parm, subr_die, &parm); - else if (parm) + else if (parm && !POINTER_BOUNDS_P (parm)) { dw_die_ref parm_die = gen_decl_die (parm, NULL, subr_die); @@ -18469,6 +18469,8 @@ gen_subprogram_die (tree decl, dw_die_ref context_die) parm = DECL_CHAIN (parm); } + else if (parm) + parm = DECL_CHAIN (parm); if (generic_decl_parm) generic_decl_parm = DECL_CHAIN (generic_decl_parm); @@ -19967,6 +19969,7 @@ gen_type_die_with_usage (tree type, dw_die_ref context_die, case FIXED_POINT_TYPE: case COMPLEX_TYPE: case BOOLEAN_TYPE: + case POINTER_BOUNDS_TYPE: /* No DIEs needed for fundamental types. */ break; @@ -20614,7 +20617,8 @@ dwarf2out_global_decl (tree decl) declarations, file-scope (extern) function declarations (which had no corresponding body) and file-scope tagged type declarations and definitions which have not yet been forced out. */ - if (TREE_CODE (decl) != FUNCTION_DECL || !DECL_INITIAL (decl)) + if ((TREE_CODE (decl) != FUNCTION_DECL || !DECL_INITIAL (decl)) + && !POINTER_BOUNDS_P (decl)) dwarf2out_decl (decl); } diff --git a/gcc/function.c b/gcc/function.c index fde4a8e6d07..5b33c46559b 100644 --- a/gcc/function.c +++ b/gcc/function.c @@ -6349,7 +6349,7 @@ thread_prologue_and_epilogue_insns (void) { unsigned i, last; - /* convert_jumps_to_returns may add to EXIT_BLOCK_PTR->preds + /* convert_jumps_to_returns may add to preds of the exit block (but won't remove). Stop at end of current preds. */ last = EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds); for (i = 0; i < last; i++) diff --git a/gcc/gdbhooks.py b/gcc/gdbhooks.py index baccd6b783e..f0a925c2b9c 100644 --- a/gcc/gdbhooks.py +++ b/gcc/gdbhooks.py @@ -383,6 +383,8 @@ class VecPrinter: return '0x%x' % long(self.gdbval) def children (self): + if long(self.gdbval) == 0: + return m_vecpfx = self.gdbval['m_vecpfx'] m_num = m_vecpfx['m_num'] m_vecdata = self.gdbval['m_vecdata'] diff --git a/gcc/gimple-fold.c b/gcc/gimple-fold.c index 18c0a5315ad..216318743ab 100644 --- a/gcc/gimple-fold.c +++ b/gcc/gimple-fold.c @@ -608,7 +608,6 @@ gimplify_and_update_call_from_tree (gimple_stmt_iterator *si_p, tree expr) gimple stmt, new_stmt; gimple_stmt_iterator i; gimple_seq stmts = NULL; - struct gimplify_ctx gctx; gimple laststore; tree reaching_vuse; @@ -616,8 +615,7 @@ gimplify_and_update_call_from_tree (gimple_stmt_iterator *si_p, tree expr) gcc_assert (is_gimple_call (stmt)); - push_gimplify_context (&gctx); - gctx.into_ssa = gimple_in_ssa_p (cfun); + push_gimplify_context (gimple_in_ssa_p (cfun)); lhs = gimple_call_lhs (stmt); if (lhs == NULL_TREE) diff --git a/gcc/gimplify-me.c b/gcc/gimplify-me.c index a7e9387b648..92542a9a2e9 100644 --- a/gcc/gimplify-me.c +++ b/gcc/gimplify-me.c @@ -45,7 +45,6 @@ force_gimple_operand_1 (tree expr, gimple_seq *stmts, gimple_predicate gimple_test_f, tree var) { enum gimplify_status ret; - struct gimplify_ctx gctx; location_t saved_location; *stmts = NULL; @@ -57,16 +56,13 @@ force_gimple_operand_1 (tree expr, gimple_seq *stmts, && (*gimple_test_f) (expr)) return expr; - push_gimplify_context (&gctx); - gimplify_ctxp->into_ssa = gimple_in_ssa_p (cfun); - gimplify_ctxp->allow_rhs_cond_expr = true; + push_gimplify_context (gimple_in_ssa_p (cfun), true); saved_location = input_location; input_location = UNKNOWN_LOCATION; if (var) { - if (gimplify_ctxp->into_ssa - && is_gimple_reg (var)) + if (gimple_in_ssa_p (cfun) && is_gimple_reg (var)) var = make_ssa_name (var, NULL); expr = build2 (MODIFY_EXPR, TREE_TYPE (var), var, expr); } @@ -160,10 +156,8 @@ gimple_regimplify_operands (gimple stmt, gimple_stmt_iterator *gsi_p) tree lhs; gimple_seq pre = NULL; gimple post_stmt = NULL; - struct gimplify_ctx gctx; - push_gimplify_context (&gctx); - gimplify_ctxp->into_ssa = gimple_in_ssa_p (cfun); + push_gimplify_context (gimple_in_ssa_p (cfun)); switch (gimple_code (stmt)) { diff --git a/gcc/gimplify.c b/gcc/gimplify.c index 5c71d2c3605..2b6de3e1732 100644 --- a/gcc/gimplify.c +++ b/gcc/gimplify.c @@ -89,6 +89,37 @@ enum omp_region_type ORT_TARGET = 32 }; +/* Gimplify hashtable helper. */ + +struct gimplify_hasher : typed_free_remove <elt_t> +{ + typedef elt_t value_type; + typedef elt_t compare_type; + static inline hashval_t hash (const value_type *); + static inline bool equal (const value_type *, const compare_type *); +}; + +struct gimplify_ctx +{ + struct gimplify_ctx *prev_context; + + vec<gimple> bind_expr_stack; + tree temps; + gimple_seq conditional_cleanups; + tree exit_label; + tree return_temp; + + vec<tree> case_labels; + /* The formal temporary table. Should this be persistent? */ + hash_table <gimplify_hasher> temp_htab; + + int conditions; + bool save_stack; + bool into_ssa; + bool allow_rhs_cond_expr; + bool in_cleanup_point_expr; +}; + struct gimplify_omp_ctx { struct gimplify_omp_ctx *outer_context; @@ -100,10 +131,9 @@ struct gimplify_omp_ctx bool combined_loop; }; -struct gimplify_ctx *gimplify_ctxp; +static struct gimplify_ctx *gimplify_ctxp; static struct gimplify_omp_ctx *gimplify_omp_ctxp; - /* Forward declaration. */ static enum gimplify_status gimplify_compound_expr (tree *, gimple_seq *, bool); @@ -134,14 +164,63 @@ gimplify_seq_add_seq (gimple_seq *dst_p, gimple_seq src) gsi_insert_seq_after_without_update (&si, src, GSI_NEW_STMT); } + +/* Pointer to a list of allocated gimplify_ctx structs to be used for pushing + and popping gimplify contexts. */ + +static struct gimplify_ctx *ctx_pool = NULL; + +/* Return a gimplify context struct from the pool. */ + +static inline struct gimplify_ctx * +ctx_alloc (void) +{ + struct gimplify_ctx * c = ctx_pool; + + if (c) + ctx_pool = c->prev_context; + else + c = XNEW (struct gimplify_ctx); + + memset (c, '\0', sizeof (*c)); + return c; +} + +/* Put gimplify context C back into the pool. */ + +static inline void +ctx_free (struct gimplify_ctx *c) +{ + c->prev_context = ctx_pool; + ctx_pool = c; +} + +/* Free allocated ctx stack memory. */ + +void +free_gimplify_stack (void) +{ + struct gimplify_ctx *c; + + while ((c = ctx_pool)) + { + ctx_pool = c->prev_context; + free (c); + } +} + + /* Set up a context for the gimplifier. */ void -push_gimplify_context (struct gimplify_ctx *c) +push_gimplify_context (bool in_ssa, bool rhs_cond_ok) { - memset (c, '\0', sizeof (*c)); + struct gimplify_ctx *c = ctx_alloc (); + c->prev_context = gimplify_ctxp; gimplify_ctxp = c; + gimplify_ctxp->into_ssa = in_ssa; + gimplify_ctxp->allow_rhs_cond_expr = rhs_cond_ok; } /* Tear down a context for the gimplifier. If BODY is non-null, then @@ -168,6 +247,7 @@ pop_gimplify_context (gimple body) if (c->temp_htab.is_created ()) c->temp_htab.dispose (); + ctx_free (c); } /* Push a GIMPLE_BIND tuple onto the stack of bindings. */ @@ -5726,7 +5806,6 @@ gimplify_scan_omp_clauses (tree *list_p, gimple_seq *pre_p, enum omp_region_type region_type) { struct gimplify_omp_ctx *ctx, *outer_ctx; - struct gimplify_ctx gctx; tree c; ctx = new_omp_context (region_type); @@ -5863,7 +5942,7 @@ gimplify_scan_omp_clauses (tree *list_p, gimple_seq *pre_p, omp_add_variable (ctx, OMP_CLAUSE_REDUCTION_PLACEHOLDER (c), GOVD_LOCAL | GOVD_SEEN); gimplify_omp_ctxp = ctx; - push_gimplify_context (&gctx); + push_gimplify_context (); OMP_CLAUSE_REDUCTION_GIMPLE_INIT (c) = NULL; OMP_CLAUSE_REDUCTION_GIMPLE_MERGE (c) = NULL; @@ -5872,7 +5951,7 @@ gimplify_scan_omp_clauses (tree *list_p, gimple_seq *pre_p, &OMP_CLAUSE_REDUCTION_GIMPLE_INIT (c)); pop_gimplify_context (gimple_seq_first_stmt (OMP_CLAUSE_REDUCTION_GIMPLE_INIT (c))); - push_gimplify_context (&gctx); + push_gimplify_context (); gimplify_and_add (OMP_CLAUSE_REDUCTION_MERGE (c), &OMP_CLAUSE_REDUCTION_GIMPLE_MERGE (c)); pop_gimplify_context @@ -5886,7 +5965,7 @@ gimplify_scan_omp_clauses (tree *list_p, gimple_seq *pre_p, && OMP_CLAUSE_LASTPRIVATE_STMT (c)) { gimplify_omp_ctxp = ctx; - push_gimplify_context (&gctx); + push_gimplify_context (); if (TREE_CODE (OMP_CLAUSE_LASTPRIVATE_STMT (c)) != BIND_EXPR) { tree bind = build3 (BIND_EXPR, void_type_node, NULL, @@ -6309,14 +6388,13 @@ gimplify_omp_parallel (tree *expr_p, gimple_seq *pre_p) tree expr = *expr_p; gimple g; gimple_seq body = NULL; - struct gimplify_ctx gctx; gimplify_scan_omp_clauses (&OMP_PARALLEL_CLAUSES (expr), pre_p, OMP_PARALLEL_COMBINED (expr) ? ORT_COMBINED_PARALLEL : ORT_PARALLEL); - push_gimplify_context (&gctx); + push_gimplify_context (); g = gimplify_and_return_first (OMP_PARALLEL_BODY (expr), &body); if (gimple_code (g) == GIMPLE_BIND) @@ -6346,14 +6424,13 @@ gimplify_omp_task (tree *expr_p, gimple_seq *pre_p) tree expr = *expr_p; gimple g; gimple_seq body = NULL; - struct gimplify_ctx gctx; gimplify_scan_omp_clauses (&OMP_TASK_CLAUSES (expr), pre_p, find_omp_clause (OMP_TASK_CLAUSES (expr), OMP_CLAUSE_UNTIED) ? ORT_UNTIED_TASK : ORT_TASK); - push_gimplify_context (&gctx); + push_gimplify_context (); g = gimplify_and_return_first (OMP_TASK_BODY (expr), &body); if (gimple_code (g) == GIMPLE_BIND) @@ -6751,8 +6828,7 @@ gimplify_omp_workshare (tree *expr_p, gimple_seq *pre_p) gimplify_scan_omp_clauses (&OMP_CLAUSES (expr), pre_p, ort); if (ort == ORT_TARGET || ort == ORT_TARGET_DATA) { - struct gimplify_ctx gctx; - push_gimplify_context (&gctx); + push_gimplify_context (); gimple g = gimplify_and_return_first (OMP_BODY (expr), &body); if (gimple_code (g) == GIMPLE_BIND) pop_gimplify_context (g); @@ -6987,7 +7063,6 @@ gimplify_transaction (tree *expr_p, gimple_seq *pre_p) tree expr = *expr_p, temp, tbody = TRANSACTION_EXPR_BODY (expr); gimple g; gimple_seq body = NULL; - struct gimplify_ctx gctx; int subcode = 0; /* Wrap the transaction body in a BIND_EXPR so we have a context @@ -7000,7 +7075,7 @@ gimplify_transaction (tree *expr_p, gimple_seq *pre_p) TRANSACTION_EXPR_BODY (expr) = bind; } - push_gimplify_context (&gctx); + push_gimplify_context (); temp = voidify_wrapper_expr (*expr_p, NULL); g = gimplify_and_return_first (TRANSACTION_EXPR_BODY (expr), &body); @@ -8358,7 +8433,6 @@ gimplify_body (tree fndecl, bool do_parms) location_t saved_location = input_location; gimple_seq parm_stmts, seq; gimple outer_bind; - struct gimplify_ctx gctx; struct cgraph_node *cgn; timevar_push (TV_TREE_GIMPLIFY); @@ -8368,7 +8442,7 @@ gimplify_body (tree fndecl, bool do_parms) default_rtl_profile (); gcc_assert (gimplify_ctxp == NULL); - push_gimplify_context (&gctx); + push_gimplify_context (); if (flag_openmp) { diff --git a/gcc/gimplify.h b/gcc/gimplify.h index 3f7e1b327a9..91000d1e6b7 100644 --- a/gcc/gimplify.h +++ b/gcc/gimplify.h @@ -48,39 +48,10 @@ enum gimplify_status { GS_OK = 0, /* We did something, maybe more to do. */ GS_ALL_DONE = 1 /* The expression is fully gimplified. */ }; -/* Gimplify hashtable helper. */ -struct gimplify_hasher : typed_free_remove <elt_t> -{ - typedef elt_t value_type; - typedef elt_t compare_type; - static inline hashval_t hash (const value_type *); - static inline bool equal (const value_type *, const compare_type *); -}; - -struct gimplify_ctx -{ - struct gimplify_ctx *prev_context; - - vec<gimple> bind_expr_stack; - tree temps; - gimple_seq conditional_cleanups; - tree exit_label; - tree return_temp; - - vec<tree> case_labels; - /* The formal temporary table. Should this be persistent? */ - hash_table <gimplify_hasher> temp_htab; - - int conditions; - bool save_stack; - bool into_ssa; - bool allow_rhs_cond_expr; - bool in_cleanup_point_expr; -}; - -extern struct gimplify_ctx *gimplify_ctxp; -extern void push_gimplify_context (struct gimplify_ctx *); +extern void free_gimplify_stack (void); +extern void push_gimplify_context (bool in_ssa = false, + bool rhs_cond_ok = false); extern void pop_gimplify_context (gimple); extern gimple gimple_current_bind_expr (void); extern vec<gimple> gimple_bind_expr_stack (void); diff --git a/gcc/graphite-scop-detection.c b/gcc/graphite-scop-detection.c index 0cfb5a59cc9..15c4c0f99ea 100644 --- a/gcc/graphite-scop-detection.c +++ b/gcc/graphite-scop-detection.c @@ -518,7 +518,7 @@ scopdet_basic_block_info (basic_block bb, loop_p outermost_loop, result.next = exit_e->dest; /* If we do not dominate result.next, remove it. It's either - the EXIT_BLOCK_PTR, or another bb dominates it and will + the exit block, or another bb dominates it and will call the scop detection for this bb. */ if (!dominated_by_p (CDI_DOMINATORS, result.next, bb)) result.next = NULL; diff --git a/gcc/ipa-split.c b/gcc/ipa-split.c index d7d6b8fd70f..2e8a062da6b 100644 --- a/gcc/ipa-split.c +++ b/gcc/ipa-split.c @@ -635,7 +635,7 @@ consider_split (struct split_point *current, bitmap non_ssa_vars, <retval> = tmp_var; return <retval> but return_bb can not be more complex than this. - If nothing is found, return EXIT_BLOCK_PTR. + If nothing is found, return the exit block. When there are multiple RETURN statement, chose one with return value, since that one is more likely shared by multiple code paths. diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c index 94b6e2559ef..4c88cca669d 100644 --- a/gcc/lra-constraints.c +++ b/gcc/lra-constraints.c @@ -269,7 +269,11 @@ in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class) typically moves that have many alternatives, and restricting reload pseudos for one alternative may lead to situations where other reload pseudos are no longer allocatable. */ - || INSN_UID (curr_insn) >= new_insn_uid_start) + || (INSN_UID (curr_insn) >= new_insn_uid_start + && curr_insn_set != NULL + && (OBJECT_P (SET_SRC (curr_insn_set)) + || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG + && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set))))))) /* When we don't know what class will be used finally for reload pseudos, we use ALL_REGS. */ return ((regno >= new_regno_start && rclass == ALL_REGS) @@ -381,21 +385,6 @@ init_curr_insn_input_reloads (void) curr_insn_input_reloads_num = 0; } -/* Change class of pseudo REGNO to NEW_CLASS. Print info about it - using TITLE. Output a new line if NL_P. */ -static void -change_class (int regno, enum reg_class new_class, - const char *title, bool nl_p) -{ - lra_assert (regno >= FIRST_PSEUDO_REGISTER); - if (lra_dump_file != NULL) - fprintf (lra_dump_file, "%s to class %s for r%d", - title, reg_class_names[new_class], regno); - setup_reg_classes (regno, new_class, NO_REGS, new_class); - if (lra_dump_file != NULL && nl_p) - fprintf (lra_dump_file, "\n"); -} - /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already created input reload pseudo (only if TYPE is not OP_OUT). The result pseudo is returned through RESULT_REG. Return TRUE if we @@ -442,7 +431,7 @@ get_reload_reg (enum op_type type, enum machine_mode mode, rtx original, dump_value_slim (lra_dump_file, original, 1); } if (new_class != lra_get_allocno_class (regno)) - change_class (regno, new_class, ", change", false); + lra_change_class (regno, new_class, ", change to", false); if (lra_dump_file != NULL) fprintf (lra_dump_file, "\n"); return false; @@ -667,7 +656,7 @@ narrow_reload_pseudo_class (rtx reg, enum reg_class cl) if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start) return; if (in_class_p (reg, cl, &rclass) && rclass != cl) - change_class (REGNO (reg), rclass, " Change", true); + lra_change_class (REGNO (reg), rclass, " Change to", true); } /* Generate reloads for matching OUT and INS (array of input operand @@ -1133,7 +1122,7 @@ process_addr_reg (rtx *loc, rtx *before, rtx *after, enum reg_class cl) } else if (new_class != NO_REGS && rclass != new_class) { - change_class (regno, new_class, " Change", true); + lra_change_class (regno, new_class, " Change to", true); return false; } else @@ -2796,7 +2785,7 @@ process_address (int nop, rtx *before, rtx *after) regno = REGNO (*ad.base_term); if (regno >= FIRST_PSEUDO_REGISTER && cl != lra_get_allocno_class (regno)) - change_class (regno, cl, " Change", true); + lra_change_class (regno, cl, " Change to", true); new_reg = SET_SRC (set); delete_insns_since (PREV_INSN (last_insn)); } @@ -3316,7 +3305,7 @@ curr_insn_transform (void) if (new_class != NO_REGS && get_reg_class (regno) != new_class) { lra_assert (ok_p); - change_class (regno, new_class, " Change", true); + lra_change_class (regno, new_class, " Change to", true); } } } @@ -3395,7 +3384,7 @@ curr_insn_transform (void) && lra_former_scratch_operand_p (curr_insn, i)) { int regno = REGNO (op); - change_class (regno, NO_REGS, " Change", true); + lra_change_class (regno, NO_REGS, " Change to", true); if (lra_get_regno_hard_regno (regno) >= 0) /* We don't have to mark all insn affected by the spilled pseudo as there is only one such insn, the @@ -3410,6 +3399,7 @@ curr_insn_transform (void) && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES && goal_alt[i] != NO_REGS && REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER + && regno < new_regno_start && ! lra_former_scratch_p (regno) && reg_renumber[regno] < 0 && (curr_insn_set == NULL_RTX diff --git a/gcc/lra-int.h b/gcc/lra-int.h index cb45c65d13a..c545d9d354f 100644 --- a/gcc/lra-int.h +++ b/gcc/lra-int.h @@ -33,16 +33,6 @@ along with GCC; see the file COPYING3. If not see base and index registers might require a reload too. */ #define LRA_MAX_INSN_RELOADS (MAX_RECOG_OPERANDS * 3) -/* Return the hard register which given pseudo REGNO assigned to. - Negative value means that the register got memory or we don't know - allocation yet. */ -static inline int -lra_get_regno_hard_regno (int regno) -{ - resize_reg_info (); - return reg_renumber[regno]; -} - typedef struct lra_live_range *lra_live_range_t; /* The structure describes program points where a given pseudo lives. @@ -394,6 +384,31 @@ extern void lra_eliminate_reg_if_possible (rtx *); +/* Return the hard register which given pseudo REGNO assigned to. + Negative value means that the register got memory or we don't know + allocation yet. */ +static inline int +lra_get_regno_hard_regno (int regno) +{ + resize_reg_info (); + return reg_renumber[regno]; +} + +/* Change class of pseudo REGNO to NEW_CLASS. Print info about it + using TITLE. Output a new line if NL_P. */ +static void inline +lra_change_class (int regno, enum reg_class new_class, + const char *title, bool nl_p) +{ + lra_assert (regno >= FIRST_PSEUDO_REGISTER); + if (lra_dump_file != NULL) + fprintf (lra_dump_file, "%s class %s for r%d", + title, reg_class_names[new_class], regno); + setup_reg_classes (regno, new_class, NO_REGS, new_class); + if (lra_dump_file != NULL && nl_p) + fprintf (lra_dump_file, "\n"); +} + /* Update insn operands which are duplication of NOP operand. The insn is represented by its LRA internal representation ID. */ static inline void diff --git a/gcc/lra.c b/gcc/lra.c index 0deae88e85a..f4791a2de8b 100644 --- a/gcc/lra.c +++ b/gcc/lra.c @@ -130,11 +130,13 @@ static void invalidate_insn_data_regno_info (lra_insn_recog_data_t, rtx, int); /* Expand all regno related info needed for LRA. */ static void -expand_reg_data (void) +expand_reg_data (int old) { resize_reg_info (); expand_reg_info (); ira_expand_reg_equiv (); + for (int i = (int) max_reg_num () - 1; i >= old; i--) + lra_change_class (i, ALL_REGS, " Set", true); } /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL @@ -178,7 +180,7 @@ lra_create_new_reg_with_unique_value (enum machine_mode md_mode, rtx original, title, REGNO (new_reg)); fprintf (lra_dump_file, "\n"); } - expand_reg_data (); + expand_reg_data (max_reg_num ()); setup_reg_classes (REGNO (new_reg), rclass, NO_REGS, rclass); return new_reg; } @@ -417,7 +419,7 @@ lra_emit_add (rtx x, rtx y, rtx z) /* Functions emit_... can create pseudos -- so expand the pseudo data. */ if (old != max_reg_num ()) - expand_reg_data (); + expand_reg_data (old); } /* The number of emitted reload insns so far. */ @@ -443,7 +445,7 @@ lra_emit_move (rtx x, rtx y) /* Function emit_move can create pseudos -- so expand the pseudo data. */ if (old != max_reg_num ()) - expand_reg_data (); + expand_reg_data (old); return; } lra_emit_add (x, XEXP (y, 0), XEXP (y, 1)); @@ -2238,6 +2240,10 @@ lra (FILE *f) init_insn_recog_data (); + /* We can not set up reload_in_progress because it prevents new + pseudo creation. */ + lra_in_progress = 1; + #ifdef ENABLE_CHECKING check_rtl (false); #endif @@ -2248,10 +2254,6 @@ lra (FILE *f) setup_reg_spill_flag (); - /* We can not set up reload_in_progress because it prevents new - pseudo creation. */ - lra_in_progress = 1; - /* Function remove_scratches can creates new pseudos for clobbers -- so set up lra_constraint_new_regno_start before its call to permit changing reg classes for pseudos created by this diff --git a/gcc/lto-cgraph.c b/gcc/lto-cgraph.c index d82759955d8..0f1a1c5e9a0 100644 --- a/gcc/lto-cgraph.c +++ b/gcc/lto-cgraph.c @@ -580,6 +580,7 @@ lto_output_varpool_node (struct lto_simple_output_block *ob, struct varpool_node && boundary_p && !DECL_EXTERNAL (node->decl), 1); /* in_other_partition. */ } + bp_pack_value (&bp, node->need_bounds_init, 1); streamer_write_bitpack (&bp); if (node->same_comdat_group && !boundary_p) { @@ -1150,6 +1151,7 @@ input_varpool_node (struct lto_file_decl_data *file_data, node->analyzed = bp_unpack_value (&bp, 1); node->used_from_other_partition = bp_unpack_value (&bp, 1); node->in_other_partition = bp_unpack_value (&bp, 1); + node->need_bounds_init = bp_unpack_value (&bp, 1); if (node->in_other_partition) { DECL_EXTERNAL (node->decl) = 1; diff --git a/gcc/omp-low.c b/gcc/omp-low.c index 17bf1dad0b7..a3bf71b6552 100644 --- a/gcc/omp-low.c +++ b/gcc/omp-low.c @@ -8349,11 +8349,10 @@ lower_omp_sections (gimple_stmt_iterator *gsi_p, omp_context *ctx) gimple_stmt_iterator tgsi; gimple stmt, new_stmt, bind, t; gimple_seq ilist, dlist, olist, new_body; - struct gimplify_ctx gctx; stmt = gsi_stmt (*gsi_p); - push_gimplify_context (&gctx); + push_gimplify_context (); dlist = NULL; ilist = NULL; @@ -8559,9 +8558,8 @@ lower_omp_single (gimple_stmt_iterator *gsi_p, omp_context *ctx) tree block; gimple t, bind, single_stmt = gsi_stmt (*gsi_p); gimple_seq bind_body, bind_body_tail = NULL, dlist; - struct gimplify_ctx gctx; - push_gimplify_context (&gctx); + push_gimplify_context (); block = make_node (BLOCK); bind = gimple_build_bind (NULL, NULL, block); @@ -8619,9 +8617,8 @@ lower_omp_master (gimple_stmt_iterator *gsi_p, omp_context *ctx) gimple stmt = gsi_stmt (*gsi_p), bind; location_t loc = gimple_location (stmt); gimple_seq tseq; - struct gimplify_ctx gctx; - push_gimplify_context (&gctx); + push_gimplify_context (); block = make_node (BLOCK); bind = gimple_build_bind (NULL, NULL, block); @@ -8686,9 +8683,8 @@ lower_omp_ordered (gimple_stmt_iterator *gsi_p, omp_context *ctx) { tree block; gimple stmt = gsi_stmt (*gsi_p), bind, x; - struct gimplify_ctx gctx; - push_gimplify_context (&gctx); + push_gimplify_context (); block = make_node (BLOCK); bind = gimple_build_bind (NULL, NULL, block); @@ -8732,7 +8728,6 @@ lower_omp_critical (gimple_stmt_iterator *gsi_p, omp_context *ctx) gimple stmt = gsi_stmt (*gsi_p), bind; location_t loc = gimple_location (stmt); gimple_seq tbody; - struct gimplify_ctx gctx; name = gimple_omp_critical_name (stmt); if (name) @@ -8785,7 +8780,7 @@ lower_omp_critical (gimple_stmt_iterator *gsi_p, omp_context *ctx) unlock = build_call_expr_loc (loc, unlock, 0); } - push_gimplify_context (&gctx); + push_gimplify_context (); block = make_node (BLOCK); bind = gimple_build_bind (NULL, NULL, block); @@ -8875,9 +8870,8 @@ lower_omp_for (gimple_stmt_iterator *gsi_p, omp_context *ctx) gimple stmt = gsi_stmt (*gsi_p), new_stmt; gimple_seq omp_for_body, body, dlist; size_t i; - struct gimplify_ctx gctx; - push_gimplify_context (&gctx); + push_gimplify_context (); lower_omp (gimple_omp_for_pre_body_ptr (stmt), ctx); @@ -9092,7 +9086,6 @@ create_task_copyfn (gimple task_stmt, omp_context *ctx) bool record_needs_remap = false, srecord_needs_remap = false; splay_tree_node n; struct omp_taskcopy_context tcctx; - struct gimplify_ctx gctx; location_t loc = gimple_location (task_stmt); child_fn = gimple_omp_task_copy_fn (task_stmt); @@ -9105,7 +9098,7 @@ create_task_copyfn (gimple task_stmt, omp_context *ctx) DECL_CONTEXT (t) = child_fn; /* Populate the function. */ - push_gimplify_context (&gctx); + push_gimplify_context (); push_cfun (child_cfun); bind = build3 (BIND_EXPR, void_type_node, NULL, NULL, NULL); @@ -9385,7 +9378,6 @@ lower_omp_taskreg (gimple_stmt_iterator *gsi_p, omp_context *ctx) gimple stmt = gsi_stmt (*gsi_p); gimple par_bind, bind, dep_bind = NULL; gimple_seq par_body, olist, ilist, par_olist, par_rlist, par_ilist, new_body; - struct gimplify_ctx gctx, dep_gctx; location_t loc = gimple_location (stmt); clauses = gimple_omp_taskreg_clauses (stmt); @@ -9410,7 +9402,7 @@ lower_omp_taskreg (gimple_stmt_iterator *gsi_p, omp_context *ctx) if (gimple_code (stmt) == GIMPLE_OMP_TASK && find_omp_clause (clauses, OMP_CLAUSE_DEPEND)) { - push_gimplify_context (&dep_gctx); + push_gimplify_context (); dep_bind = gimple_build_bind (NULL, NULL, make_node (BLOCK)); lower_depend_clauses (stmt, &dep_ilist, &dep_olist); } @@ -9418,7 +9410,7 @@ lower_omp_taskreg (gimple_stmt_iterator *gsi_p, omp_context *ctx) if (ctx->srecord_type) create_task_copyfn (stmt, ctx); - push_gimplify_context (&gctx); + push_gimplify_context (); par_olist = NULL; par_ilist = NULL; @@ -9508,7 +9500,6 @@ lower_omp_target (gimple_stmt_iterator *gsi_p, omp_context *ctx) gimple stmt = gsi_stmt (*gsi_p); gimple tgt_bind = NULL, bind; gimple_seq tgt_body = NULL, olist, ilist, new_body; - struct gimplify_ctx gctx; location_t loc = gimple_location (stmt); int kind = gimple_omp_target_kind (stmt); unsigned int map_cnt = 0; @@ -9523,7 +9514,7 @@ lower_omp_target (gimple_stmt_iterator *gsi_p, omp_context *ctx) tgt_body = gimple_omp_body (stmt); child_fn = ctx->cb.dst_fn; - push_gimplify_context (&gctx); + push_gimplify_context (); for (c = clauses; c ; c = OMP_CLAUSE_CHAIN (c)) switch (OMP_CLAUSE_CODE (c)) @@ -9809,8 +9800,7 @@ static void lower_omp_teams (gimple_stmt_iterator *gsi_p, omp_context *ctx) { gimple teams_stmt = gsi_stmt (*gsi_p); - struct gimplify_ctx gctx; - push_gimplify_context (&gctx); + push_gimplify_context (); tree block = make_node (BLOCK); gimple bind = gimple_build_bind (NULL, NULL, block); @@ -10103,10 +10093,8 @@ execute_lower_omp (void) if (all_contexts->root) { - struct gimplify_ctx gctx; - if (task_shared_vars) - push_gimplify_context (&gctx); + push_gimplify_context (); lower_omp (&body, NULL); if (task_shared_vars) pop_gimplify_context (NULL); diff --git a/gcc/opts.c b/gcc/opts.c index cd48c73267b..d282d6df507 100644 --- a/gcc/opts.c +++ b/gcc/opts.c @@ -809,10 +809,13 @@ finish_options (struct gcc_options *opts, struct gcc_options *opts_set, #else error_at (loc, "LTO support has not been enabled in this configuration"); #endif - if (!opts->x_flag_fat_lto_objects && !HAVE_LTO_PLUGIN) + if (!opts->x_flag_fat_lto_objects + && (!HAVE_LTO_PLUGIN + || (opts_set->x_flag_use_linker_plugin + && !opts->x_flag_use_linker_plugin))) { if (opts_set->x_flag_fat_lto_objects) - error_at (loc, "-fno-fat-lto-objects are supported only with linker plugin."); + error_at (loc, "-fno-fat-lto-objects are supported only with linker plugin"); opts->x_flag_fat_lto_objects = 1; } } diff --git a/gcc/plugin.c b/gcc/plugin.c index d7dcb5f4d36..61d7fde0175 100644 --- a/gcc/plugin.c +++ b/gcc/plugin.c @@ -452,6 +452,7 @@ register_callback (const char *plugin_name, case PLUGIN_EARLY_GIMPLE_PASSES_START: case PLUGIN_EARLY_GIMPLE_PASSES_END: case PLUGIN_NEW_PASS: + case PLUGIN_INCLUDE_FILE: { struct callback_info *new_callback; if (!callback) @@ -529,6 +530,7 @@ invoke_plugin_callbacks_full (int event, void *gcc_data) case PLUGIN_EARLY_GIMPLE_PASSES_START: case PLUGIN_EARLY_GIMPLE_PASSES_END: case PLUGIN_NEW_PASS: + case PLUGIN_INCLUDE_FILE: { /* Iterate over every callback registered with this event and call it. */ diff --git a/gcc/plugin.def b/gcc/plugin.def index 25a645854a7..154f01c0f80 100644 --- a/gcc/plugin.def +++ b/gcc/plugin.def @@ -97,6 +97,9 @@ DEFEVENT (PLUGIN_NEW_PASS) as a const char* pointer. */ DEFEVENT (PLUGIN_INCLUDE_FILE) +/* When adding a new hard-coded plugin event, don't forget to edit in + file plugin.c the functions register_callback and + invoke_plugin_callbacks_full accordingly! */ /* After the hard-coded events above, plugins can dynamically allocate events at run time. diff --git a/gcc/profile.c b/gcc/profile.c index 85671b30bc4..1d0e78ab4dc 100644 --- a/gcc/profile.c +++ b/gcc/profile.c @@ -1392,7 +1392,7 @@ find_spanning_tree (struct edge_list *el) union_groups (EXIT_BLOCK_PTR_FOR_FN (cfun), ENTRY_BLOCK_PTR_FOR_FN (cfun)); /* First add all abnormal edges to the tree unless they form a cycle. Also - add all edges to EXIT_BLOCK_PTR to avoid inserting profiling code behind + add all edges to the exit block to avoid inserting profiling code behind setting return value from function. */ for (i = 0; i < num_edges; i++) { diff --git a/gcc/real.c b/gcc/real.c index 536aa977eaf..93a956cbd17 100644 --- a/gcc/real.c +++ b/gcc/real.c @@ -58,14 +58,7 @@ Both of these requirements are easily satisfied. The largest target significand is 113 bits; we store at least 160. The smallest - denormal number fits in 17 exponent bits; we store 26. - - Note that the decimal string conversion routines are sensitive to - rounding errors. Since the raw arithmetic routines do not themselves - have guard digits or rounding, the computation of 10**exp can - accumulate more than a few digits of error. The previous incarnation - of real.c successfully used a 144-bit fraction; given the current - layout of REAL_VALUE_TYPE we're forced to expand to at least 160 bits. */ + denormal number fits in 17 exponent bits; we store 26. */ /* Used to classify two numbers simultaneously. */ @@ -2032,75 +2025,50 @@ real_from_string (REAL_VALUE_TYPE *r, const char *str) else { /* Decimal floating point. */ - const REAL_VALUE_TYPE *ten = ten_to_ptwo (0); - int d; + const char *cstr = str; + mpfr_t m; + bool inexact; - while (*str == '0') - str++; - while (ISDIGIT (*str)) + while (*cstr == '0') + cstr++; + if (*cstr == '.') { - d = *str++ - '0'; - do_multiply (r, r, ten); - if (d) - do_add (r, r, real_digit (d), 0); - } - if (*str == '.') - { - str++; - if (r->cl == rvc_zero) - { - while (*str == '0') - str++, exp--; - } - while (ISDIGIT (*str)) - { - d = *str++ - '0'; - do_multiply (r, r, ten); - if (d) - do_add (r, r, real_digit (d), 0); - exp--; - } + cstr++; + while (*cstr == '0') + cstr++; } /* If the mantissa is zero, ignore the exponent. */ - if (r->cl == rvc_zero) + if (!ISDIGIT (*cstr)) goto is_a_zero; - if (*str == 'e' || *str == 'E') + /* Nonzero value, possibly overflowing or underflowing. */ + mpfr_init2 (m, SIGNIFICAND_BITS); + inexact = mpfr_strtofr (m, str, NULL, 10, GMP_RNDZ); + /* The result should never be a NaN, and because the rounding is + toward zero should never be an infinity. */ + gcc_assert (!mpfr_nan_p (m) && !mpfr_inf_p (m)); + if (mpfr_zero_p (m) || mpfr_get_exp (m) < -MAX_EXP + 4) { - bool exp_neg = false; - - str++; - if (*str == '-') - { - exp_neg = true; - str++; - } - else if (*str == '+') - str++; - - d = 0; - while (ISDIGIT (*str)) - { - d *= 10; - d += *str - '0'; - if (d > MAX_EXP) - { - /* Overflowed the exponent. */ - if (exp_neg) - goto underflow; - else - goto overflow; - } - str++; - } - if (exp_neg) - d = -d; - exp += d; + mpfr_clear (m); + goto underflow; + } + else if (mpfr_get_exp (m) > MAX_EXP - 4) + { + mpfr_clear (m); + goto overflow; + } + else + { + real_from_mpfr (r, m, NULL_TREE, GMP_RNDZ); + /* 1 to 3 bits may have been shifted off (with a sticky bit) + because the hex digits used in real_from_mpfr did not + start with a digit 8 to f, but the exponent bounds above + should have avoided underflow or overflow. */ + gcc_assert (r->cl = rvc_normal); + /* Set a sticky bit if mpfr_strtofr was inexact. */ + r->sig[0] |= inexact; } - - if (exp) - times_pten (r, exp); } r->sign = sign; diff --git a/gcc/recog.c b/gcc/recog.c index b8073afb3a6..404d7a7355b 100644 --- a/gcc/recog.c +++ b/gcc/recog.c @@ -314,7 +314,9 @@ insn_invalid_p (rtx insn, bool in_group) clobbers. */ int icode = recog (pat, insn, (GET_CODE (pat) == SET - && ! reload_completed && ! reload_in_progress) + && ! reload_completed + && ! reload_in_progress + && ! lra_in_progress) ? &num_clobbers : 0); int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0; diff --git a/gcc/regcprop.c b/gcc/regcprop.c index 0fa0afbc824..9b52a6301f7 100644 --- a/gcc/regcprop.c +++ b/gcc/regcprop.c @@ -747,6 +747,7 @@ copyprop_hardreg_forward_1 (basic_block bb, struct value_data *vd) int n_ops, i, alt, predicated; bool is_asm, any_replacements; rtx set; + rtx link; bool replaced[MAX_RECOG_OPERANDS]; bool changed = false; struct kill_set_value_data ksvd; @@ -815,6 +816,23 @@ copyprop_hardreg_forward_1 (basic_block bb, struct value_data *vd) if (recog_op_alt[i][alt].earlyclobber) kill_value (recog_data.operand[i], vd); + /* If we have dead sets in the insn, then we need to note these as we + would clobbers. */ + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + { + if (REG_NOTE_KIND (link) == REG_UNUSED) + { + kill_value (XEXP (link, 0), vd); + /* Furthermore, if the insn looked like a single-set, + but the dead store kills the source value of that + set, then we can no-longer use the plain move + special case below. */ + if (set + && reg_overlap_mentioned_p (XEXP (link, 0), SET_SRC (set))) + set = NULL; + } + } + /* Special-case plain move instructions, since we may well be able to do the move from a different register class. */ if (set && REG_P (SET_SRC (set))) diff --git a/gcc/sched-int.h b/gcc/sched-int.h index 070404c4245..84b5cb58c96 100644 --- a/gcc/sched-int.h +++ b/gcc/sched-int.h @@ -70,7 +70,7 @@ struct common_sched_info_def /* Called to notify frontend, that new basic block is being added. The first parameter - new basic block. The second parameter - block, after which new basic block is being added, - or EXIT_BLOCK_PTR, if recovery block is being added, + or the exit block, if recovery block is being added, or NULL, if standalone block is being added. */ void (*add_block) (basic_block, basic_block); diff --git a/gcc/targhooks.c b/gcc/targhooks.c index 0a56eff68ef..c383520314f 100644 --- a/gcc/targhooks.c +++ b/gcc/targhooks.c @@ -142,7 +142,6 @@ default_promote_function_mode_always_promote (const_tree type, return promote_mode (type, mode, punsignedp); } - enum machine_mode default_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2) { @@ -276,7 +275,6 @@ default_cxx_guard_type (void) return long_long_integer_type_node; } - /* Returns the size of the cookie to use when allocating an array whose elements have the indicated TYPE. Assumes that it is already known that a cookie is needed. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 606e4de6979..b29070fb11f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,47 @@ +2013-11-21 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org> + + PR libfortran/59227 + * gfortran.dg/erf_3.F90: XFAIL on spu-* and ia64-*-linux*. + Make more generic for other platforms. + +2013-11-21 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/53976 + * gcc.target/sh/pr53976-1.c: New. + +2013-11-20 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org> + + PR libfortran/49024 + * gfortran.dg/erf_3.F90: New file. + +2013-11-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * gcc.target/powerpc/pr48258-1.c: Skip for little endian. + +2013-11-20 Vladimir Makarov <vmakarov@redhat.com> + + PR rtl-optimization/59133 + * gcc.target/i386/pr59133.c: New. + +2013-11-20 Joseph Myers <joseph@codesourcery.com> + + PR middle-end/21718 + * gcc.dg/float-exact-1.c: New test. + +2013-11-20 Richard Earnshaw <rearnsha@arm.com> + + PR rtl-optimization/54300 + * gcc.target/arm/pr54300.C: New test. + +2013-11-20 Diego Novillo <dnovillo@google.com> + + PR 59212 + * g++.dg/plugin/selfassign.c: Include stringpool.h + +2013-11-20 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> + + * gcc.target/powerpc/darwin-longlong.c (msw): Make endian-safe. + 2013-11-20 Dominik Vogt <vogt@linux.vnet.ibm.com> * gcc.target/s390/htm-1.c: Rename to ... diff --git a/gcc/testsuite/g++.dg/plugin/selfassign.c b/gcc/testsuite/g++.dg/plugin/selfassign.c index 2498153a273..cdab74a19ae 100644 --- a/gcc/testsuite/g++.dg/plugin/selfassign.c +++ b/gcc/testsuite/g++.dg/plugin/selfassign.c @@ -8,6 +8,7 @@ #include "coretypes.h" #include "tm.h" #include "tree.h" +#include "stringpool.h" #include "toplev.h" #include "basic-block.h" #include "gimple.h" diff --git a/gcc/testsuite/gcc.dg/float-exact-1.c b/gcc/testsuite/gcc.dg/float-exact-1.c new file mode 100644 index 00000000000..7e8f3f153ae --- /dev/null +++ b/gcc/testsuite/gcc.dg/float-exact-1.c @@ -0,0 +1,3177 @@ +/* Test exact conversion to binary floating-point types of + floating-point contents expressed in decimal. PR 21718. */ +/* { dg-do run } */ +/* { dg-options "-w" } */ + +/* For float (if IEEE binary32), double (if IEEE binary64) and long + double (if IEEE binary64, x86 extended or IEEE binary128) we test + half-way values and numbers close to those half-way values. */ + +#include <float.h> + +#if FLT_EVAL_METHOD == 0 \ + && FLT_MANT_DIG == 24 \ + && FLT_MIN_EXP == -125 \ + && FLT_MAX_EXP == 128 +# define FLT_OK +/* 0x0.8p-149 */ +static const float f1ae = 0, f1be = 0, f1ce = 0x1p-149f; +static const float f1a = +7.0064923216240853546186479164495806564013097093825788587853\ +4141944895541342930300743319094181060791015624999e-46f; +static const float f1b = +7.0064923216240853546186479164495806564013097093825788587853\ +4141944895541342930300743319094181060791015625e-46f; +static const float f1c = +7.0064923216240853546186479164495806564013097093825788587853\ +4141944895541342930300743319094181060791015625001e-46f; +/* 0x1.8p-149 */ +static const float f2ae = 0x1p-149f, f2be = 0x2p-149f, f2ce = 0x2p-149f; +static const float f2a = +2.1019476964872256063855943749348741969203929128147736576356\ +02425834686624028790902229957282543182373046874999e-45f; +static const float f2b = +2.1019476964872256063855943749348741969203929128147736576356\ +02425834686624028790902229957282543182373046875e-45f; +static const float f2c = +2.1019476964872256063855943749348741969203929128147736576356\ +02425834686624028790902229957282543182373046875001e-45f; +/* 0x1.000001p127 */ +static const float f3ae = 0x1p127f, f3be = 0x1p127f, f3ce = 0x1.000002p127f; +static const float f3a = +1.70141193601674033557522515689509748735999e+38f; +static const float f3b = +1.70141193601674033557522515689509748736e+38f; +static const float f3c = +1.70141193601674033557522515689509748736001e+38f; +#endif + +#if (FLT_EVAL_METHOD == 0 || FLT_EVAL_METHOD == 1) \ + && DBL_MANT_DIG == 53 \ + && DBL_MIN_EXP == -1021 \ + && DBL_MAX_EXP == 1024 +# define DBL_OK +/* 0x0.8p-1074 */ +static const double d1ae = 0, d1be = 0, d1ce = 0x1p-1074; +static const double d1a = +2.4703282292062327208828439643411068618252990130716238221279\ +284125033775363510437593264991818081799618989828234772285886\ +546332835517796989819938739800539093906315035659515570226392\ +290858392449105184435931802849936536152500319370457678249219\ +365623669863658480757001585769269903706311928279558551332927\ +834338409351978015531246597263579574622766465272827220056374\ +006485499977096599470454020828166226237857393450736339007967\ +761930577506740176324673600968951340535537458516661134223766\ +678604162159680461914467291840300530057530849048765391711386\ +591646239524912623653881879636239373280423891018672348497668\ +235089863388587925628302755995657524455507255189313690836254\ +779186948667994968324049705821028513185451396213837722826145\ +437693412532098591327667236328124999e-324; +static const double d1b = +2.4703282292062327208828439643411068618252990130716238221279\ +284125033775363510437593264991818081799618989828234772285886\ +546332835517796989819938739800539093906315035659515570226392\ +290858392449105184435931802849936536152500319370457678249219\ +365623669863658480757001585769269903706311928279558551332927\ +834338409351978015531246597263579574622766465272827220056374\ +006485499977096599470454020828166226237857393450736339007967\ +761930577506740176324673600968951340535537458516661134223766\ +678604162159680461914467291840300530057530849048765391711386\ +591646239524912623653881879636239373280423891018672348497668\ +235089863388587925628302755995657524455507255189313690836254\ +779186948667994968324049705821028513185451396213837722826145\ +437693412532098591327667236328125e-324; +static const double d1c = +2.4703282292062327208828439643411068618252990130716238221279\ +284125033775363510437593264991818081799618989828234772285886\ +546332835517796989819938739800539093906315035659515570226392\ +290858392449105184435931802849936536152500319370457678249219\ +365623669863658480757001585769269903706311928279558551332927\ +834338409351978015531246597263579574622766465272827220056374\ +006485499977096599470454020828166226237857393450736339007967\ +761930577506740176324673600968951340535537458516661134223766\ +678604162159680461914467291840300530057530849048765391711386\ +591646239524912623653881879636239373280423891018672348497668\ +235089863388587925628302755995657524455507255189313690836254\ +779186948667994968324049705821028513185451396213837722826145\ +437693412532098591327667236328125001e-324; +/* 0x1.8p-1074 */ +static const double d2ae = 0x1p-1074, d2be = 0x2p-1074, d2ce = 0x2p-1074; +static const double d2a = +7.4109846876186981626485318930233205854758970392148714663837\ +852375101326090531312779794975454245398856969484704316857659\ +638998506553390969459816219401617281718945106978546710679176\ +872575177347315553307795408549809608457500958111373034747658\ +096871009590975442271004757307809711118935784838675653998783\ +503015228055934046593739791790738723868299395818481660169122\ +019456499931289798411362062484498678713572180352209017023903\ +285791732520220528974020802906854021606612375549983402671300\ +035812486479041385743401875520901590172592547146296175134159\ +774938718574737870961645638908718119841271673056017045493004\ +705269590165763776884908267986972573366521765567941072508764\ +337560846003984904972149117463085539556354188641513168478436\ +313080237596295773983001708984374999e-324; +static const double d2b = +7.4109846876186981626485318930233205854758970392148714663837\ +852375101326090531312779794975454245398856969484704316857659\ +638998506553390969459816219401617281718945106978546710679176\ +872575177347315553307795408549809608457500958111373034747658\ +096871009590975442271004757307809711118935784838675653998783\ +503015228055934046593739791790738723868299395818481660169122\ +019456499931289798411362062484498678713572180352209017023903\ +285791732520220528974020802906854021606612375549983402671300\ +035812486479041385743401875520901590172592547146296175134159\ +774938718574737870961645638908718119841271673056017045493004\ +705269590165763776884908267986972573366521765567941072508764\ +337560846003984904972149117463085539556354188641513168478436\ +313080237596295773983001708984375e-324; +static const double d2c = +7.4109846876186981626485318930233205854758970392148714663837\ +852375101326090531312779794975454245398856969484704316857659\ +638998506553390969459816219401617281718945106978546710679176\ +872575177347315553307795408549809608457500958111373034747658\ +096871009590975442271004757307809711118935784838675653998783\ +503015228055934046593739791790738723868299395818481660169122\ +019456499931289798411362062484498678713572180352209017023903\ +285791732520220528974020802906854021606612375549983402671300\ +035812486479041385743401875520901590172592547146296175134159\ +774938718574737870961645638908718119841271673056017045493004\ +705269590165763776884908267986972573366521765567941072508764\ +337560846003984904972149117463085539556354188641513168478436\ +313080237596295773983001708984375001e-324; +/* 0x1.00000000000008p1023 */ +static const double d3ae = 0x1p1023, d3be = 0x1p1023, d3ce = 0x1.0000000000001p1023; +static const double d3a = +8.9884656743115805365666807213050294962762414131308158973971\ +342756154045415486693752413698006024096935349884403114202125\ +541629105369684531108613657287705365884742938136589844238179\ +474556051429647415148697857438797685859063890851407391008830\ +874765563025951597582513936655578157348020066364210154316532\ +161708031999e+307; +static const double d3b = +8.9884656743115805365666807213050294962762414131308158973971\ +342756154045415486693752413698006024096935349884403114202125\ +541629105369684531108613657287705365884742938136589844238179\ +474556051429647415148697857438797685859063890851407391008830\ +874765563025951597582513936655578157348020066364210154316532\ +161708032e+307; +static const double d3c = +8.9884656743115805365666807213050294962762414131308158973971\ +342756154045415486693752413698006024096935349884403114202125\ +541629105369684531108613657287705365884742938136589844238179\ +474556051429647415148697857438797685859063890851407391008830\ +874765563025951597582513936655578157348020066364210154316532\ +161708032001e+307; +#endif + +#if LDBL_MANT_DIG == 53 \ + && LDBL_MIN_EXP == -1021 \ + && LDBL_MAX_EXP == 1024 +# define LDBL_OK +/* 0x0.8p-1074 */ +static const long double ld1ae = 0, ld1be = 0, ld1ce = 0x1p-1074L; +static const long double ld1a = +2.4703282292062327208828439643411068618252990130716238221279\ +284125033775363510437593264991818081799618989828234772285886\ +546332835517796989819938739800539093906315035659515570226392\ +290858392449105184435931802849936536152500319370457678249219\ +365623669863658480757001585769269903706311928279558551332927\ +834338409351978015531246597263579574622766465272827220056374\ +006485499977096599470454020828166226237857393450736339007967\ +761930577506740176324673600968951340535537458516661134223766\ +678604162159680461914467291840300530057530849048765391711386\ +591646239524912623653881879636239373280423891018672348497668\ +235089863388587925628302755995657524455507255189313690836254\ +779186948667994968324049705821028513185451396213837722826145\ +437693412532098591327667236328124999e-324L; +static const long double ld1b = +2.4703282292062327208828439643411068618252990130716238221279\ +284125033775363510437593264991818081799618989828234772285886\ +546332835517796989819938739800539093906315035659515570226392\ +290858392449105184435931802849936536152500319370457678249219\ +365623669863658480757001585769269903706311928279558551332927\ +834338409351978015531246597263579574622766465272827220056374\ +006485499977096599470454020828166226237857393450736339007967\ +761930577506740176324673600968951340535537458516661134223766\ +678604162159680461914467291840300530057530849048765391711386\ +591646239524912623653881879636239373280423891018672348497668\ +235089863388587925628302755995657524455507255189313690836254\ +779186948667994968324049705821028513185451396213837722826145\ +437693412532098591327667236328125e-324L; +static const long double ld1c = +2.4703282292062327208828439643411068618252990130716238221279\ +284125033775363510437593264991818081799618989828234772285886\ +546332835517796989819938739800539093906315035659515570226392\ +290858392449105184435931802849936536152500319370457678249219\ +365623669863658480757001585769269903706311928279558551332927\ +834338409351978015531246597263579574622766465272827220056374\ +006485499977096599470454020828166226237857393450736339007967\ +761930577506740176324673600968951340535537458516661134223766\ +678604162159680461914467291840300530057530849048765391711386\ +591646239524912623653881879636239373280423891018672348497668\ +235089863388587925628302755995657524455507255189313690836254\ +779186948667994968324049705821028513185451396213837722826145\ +437693412532098591327667236328125001e-324L; +/* 0x1.8p-1074 */ +static const long double ld2ae = 0x1p-1074L, ld2be = 0x2p-1074L, ld2ce = 0x2p-1074L; +static const long double ld2a = +7.4109846876186981626485318930233205854758970392148714663837\ +852375101326090531312779794975454245398856969484704316857659\ +638998506553390969459816219401617281718945106978546710679176\ +872575177347315553307795408549809608457500958111373034747658\ +096871009590975442271004757307809711118935784838675653998783\ +503015228055934046593739791790738723868299395818481660169122\ +019456499931289798411362062484498678713572180352209017023903\ +285791732520220528974020802906854021606612375549983402671300\ +035812486479041385743401875520901590172592547146296175134159\ +774938718574737870961645638908718119841271673056017045493004\ +705269590165763776884908267986972573366521765567941072508764\ +337560846003984904972149117463085539556354188641513168478436\ +313080237596295773983001708984374999e-324L; +static const long double ld2b = +7.4109846876186981626485318930233205854758970392148714663837\ +852375101326090531312779794975454245398856969484704316857659\ +638998506553390969459816219401617281718945106978546710679176\ +872575177347315553307795408549809608457500958111373034747658\ +096871009590975442271004757307809711118935784838675653998783\ +503015228055934046593739791790738723868299395818481660169122\ +019456499931289798411362062484498678713572180352209017023903\ +285791732520220528974020802906854021606612375549983402671300\ +035812486479041385743401875520901590172592547146296175134159\ +774938718574737870961645638908718119841271673056017045493004\ +705269590165763776884908267986972573366521765567941072508764\ +337560846003984904972149117463085539556354188641513168478436\ +313080237596295773983001708984375e-324L; +static const long double ld2c = +7.4109846876186981626485318930233205854758970392148714663837\ +852375101326090531312779794975454245398856969484704316857659\ +638998506553390969459816219401617281718945106978546710679176\ +872575177347315553307795408549809608457500958111373034747658\ +096871009590975442271004757307809711118935784838675653998783\ +503015228055934046593739791790738723868299395818481660169122\ +019456499931289798411362062484498678713572180352209017023903\ +285791732520220528974020802906854021606612375549983402671300\ +035812486479041385743401875520901590172592547146296175134159\ +774938718574737870961645638908718119841271673056017045493004\ +705269590165763776884908267986972573366521765567941072508764\ +337560846003984904972149117463085539556354188641513168478436\ +313080237596295773983001708984375001e-324L; +/* 0x1.00000000000008p1023 */ +static const long double ld3ae = 0x1p1023L, ld3be = 0x1p1023L, ld3ce = 0x1.0000000000001p1023L; +static const long double ld3a = +8.9884656743115805365666807213050294962762414131308158973971\ +342756154045415486693752413698006024096935349884403114202125\ +541629105369684531108613657287705365884742938136589844238179\ +474556051429647415148697857438797685859063890851407391008830\ +874765563025951597582513936655578157348020066364210154316532\ +161708031999e+307L; +static const long double ld3b = +8.9884656743115805365666807213050294962762414131308158973971\ +342756154045415486693752413698006024096935349884403114202125\ +541629105369684531108613657287705365884742938136589844238179\ +474556051429647415148697857438797685859063890851407391008830\ +874765563025951597582513936655578157348020066364210154316532\ +161708032e+307L; +static const long double ld3c = +8.9884656743115805365666807213050294962762414131308158973971\ +342756154045415486693752413698006024096935349884403114202125\ +541629105369684531108613657287705365884742938136589844238179\ +474556051429647415148697857438797685859063890851407391008830\ +874765563025951597582513936655578157348020066364210154316532\ +161708032001e+307L; +#endif + +#if LDBL_MANT_DIG == 64 \ + && LDBL_MIN_EXP == -16381 \ + && LDBL_MAX_EXP == 16384 +# define LDBL_OK +/* 0x0.8p-16445 */ +static const long double ld1ae = 0, ld1be = 0, ld1ce = 0x1p-16445L; +static const long double ld1a = +1.8225997659412373012642029668097099081995254078467816718604\ +902435141858443166988684047803543129136025986236736736017655\ +509834928163110160849867540377949045027419112905889658392846\ +126319028167798783107812829917053644701598967767636342956203\ +999770864055077592691915230273843577112246476529298591341071\ +313110337661777304220340396298768698441131694859514066773321\ +059786469060001083813361460161387168195154228027648977594276\ +496061276605855817438145692314650177569263750801566422892936\ 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+588978890438298369667014685160756795261293064179236782450102\ +879817506411379585551974343148401888001113058696688771238532\ +123329163319380775763389985796856252232367435778523577763581\ +076318820356483011816956309162306010784749642144593052844981\ +144455778303480881727480293033710826466852650686573284449164\ +971550815761322623554550767170481569400661823142075309755585\ +825399262942161733431916879499819498306470556518202895225167\ +570891857833504708712937447726161123901897152190727519098753\ +173091256107155059564163182449945325514965354563242034921715\ +085079669416064946957897843700525314730377964740286745952320\ +848539618361767466769711132391357232984948881905511016501295\ +373458116601070538750219227472880922074079367616789330713051\ +392796054620611196686398104309732110578180612371988986941283\ +463409571752839755060102940634838880149410521082372514146698\ +949690555298417297141754693386954049385392552489950059242099\ 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+332988069951307480469935653061211574846012803370905284012473\ +025318540210297839541696998136885534223864988557670674501375\ +244470147903967779423817060038384764935662497442963759653206\ +786432859777470896394181997456033131032688720696203667198626\ +404895099030068466008555612541561023366202324622483939422567\ +021914882845352467305687811236417567525816955182834161603932\ +993065869465459807593704095390354125514253872107415823725124\ +7263969181696e+4931L; +static const long double ld3c = +5.9486574767861588257512740011252202817891302594919813725251\ +295428739285541899832559628345030434759848834258858109152060\ +168394580447354320917546191141469316674407503401251826592118\ +529247805068466318759038608659253988075214874609536526621357\ +456531393890166762179915866732524251539065872543957371571521\ +983821811625262362379785274802094595537134203491628334800642\ +100552410980148340419844099304716014319891796892117978584065\ +642215994189779833796388294931075153217985342401232585488548\ +183499573356819649604353341808627018653300000165159821533158\ +398534762310007133107769480816106094590754928301890268526601\ +948012303315011492834812113743989351274355589970363438128551\ +573643438403526566620300559126131289478114044934210031633528\ +263569989916613277150372804081100885766846923338387335735275\ +815690693627425316500993091757924061275520326543377826484801\ +260850814410014200240706874882235908793464063722267631785502\ +588978890438298369667014685160756795261293064179236782450102\ +879817506411379585551974343148401888001113058696688771238532\ +123329163319380775763389985796856252232367435778523577763581\ +076318820356483011816956309162306010784749642144593052844981\ +144455778303480881727480293033710826466852650686573284449164\ +971550815761322623554550767170481569400661823142075309755585\ +825399262942161733431916879499819498306470556518202895225167\ +570891857833504708712937447726161123901897152190727519098753\ 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+069029644904642077575045157730600577875158390703330602738631\ +860629283284285902868412268522486164537842820453011183015531\ +669082023505889165928251243784395957824980999247118276540195\ +068956031183236585108415603897481193085040746824934727777986\ +761703484626902903260925660927239810711484175954901422619731\ +922057229492660554293614771979793133433085936212830723862399\ +334585740422370252249982159238980361966177481883090934546250\ +903836442278836769393445168381535656636696931116641217099763\ +249205106142470169654056239769609880390474141835446455366216\ +163044493526155530766380018725181852858797332884069215206429\ +253933800732703242020102754246055713369281324885855415528125\ +659581759080256206862639693790603663547070031814664699862085\ +124026740519096394950750536940374610036575208929959836461615\ +919280191863569472772191938255564055565023733812663112274784\ +824733213440763947293874467915896768018331324730250697015099\ +463062533087218087488410166157459583569488345783974179340987\ +151815108212218686575226398710276498737521494877861721916239\ +286780194943271811625644415312213945242110591353818534254974\ +082884162962499579444882831630967263044313008877192427542802\ +154833385005287431176015973444837288763406349559772586733139\ +508290944276618724455216038372331277739377332938820061159422\ +131545699737995079186343848189545551446309662717473667598998\ +332988069951307480469935653061211574846012803370905284012473\ +025318540210297839541696998136885534223864988557670674501375\ +244470147903967779423817060038384764935662497442963759653206\ +786432859777470896394181997456033131032688720696203667198626\ +404895099030068466008555612541561023366202324622483939422567\ +021914882845352467305687811236417567525816955182834161603932\ +993065869465459807593704095390354125514253872107415823725124\ +7263969181696001e+4931L; +#endif + +#if LDBL_MANT_DIG == 113 \ + && LDBL_MIN_EXP == -16381 \ + && LDBL_MAX_EXP == 16384 +# define LDBL_OK +/* 0x0.8p-16494 */ +static const long double ld1ae = 0, ld1be = 0, ld1ce = 0x1p-16494L; +static const long double ld1a = +3.2375875597190125554622194791138232762497846690173405048449\ +421945985197700620596855088357456383249701279390707384240598\ +382936099431912710233425550359863089915213963553756674672083\ +673128192358701197242632527769951957277781260855740340354110\ +173441284912381364143945515141786687806740155311932822963199\ +131134959539539338316310328556057915323285980341541664226172\ +265348802632447238304822896568757017013159021750199744350376\ +278243566840330589397015778833566517337174685312047058426075\ +688036665697114219175258344917835835984013214761767520398571\ +735519302688914468501077605843338555214753050109407568139932\ +147308502166696009676987494125921676927574464221699654264839\ +192243410627511520570610765229732327315423820550872393685221\ +676561948307418196052769717057382723931306989375320957256133\ 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+955460820122006976717445739825352919058005528371183277021250\ +186916447745609162301667393077050176560656798672598371789181\ +232542195795945358691713761483976100058707499929103557275695\ +937295677892604799308353051124627278706035295473126217205599\ +530746756205492173148619619059839609108464715691924592576481\ +382126740168148453274964955074129767533813576349605298268179\ +068244338581354855186516322703199278802275718580352103754433\ +240982354636196477238624205575823556321375833700666021556412\ +182358152808745703724362178773168996492870519432472065091133\ +11767578125001e-4966L; +/* 0x1.8p-16494 */ +static const long double ld2ae = 0x1p-16494L, ld2be = 0x2p-16494L, ld1ce = 0x2p-16494L; +static const long double ld2a = +9.7127626791570376663866584373414698287493540070520215145348\ +265837955593101861790565265072369149749103838172122152721795\ +148808298295738130700276651079589269745641890661270024016251\ +019384577076103591727897583309855871833343782567221021062330\ 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+530194161044123524750036105635809277947168629873067749519842\ +957433509350316508339628224443809642374220084876711715865698\ +238309708050571369447923974325750197314968509790081061483804\ +453550810603239090298082506325805730097187923044635197024326\ +966746334305257051886113456387761013622870382593208533889592\ +238925214891289068690048585049758987775121620114117517878005\ +875020040085404765102967971726139392362711332104766149529294\ +277730971232752039868784363740304437529370880909321409176692\ +668840956756850124527879832299559696177391050297700824622043\ +866382460366020930152337219476058757174016585113549831063750\ +560749343236827486905002179231150529681970396017795115367543\ +697626587387836076075141284451928300176122499787310671827087\ +811887033677814397925059153373881836118105886419378651616798\ +592240268616476519445858857179518827325394147075773777729444\ +146380220504445359824894865222389302601440729048815894804537\ +204733015744064565559548968109597836406827155741056311263299\ +722947063908589431715872616727470668964127501101998064669236\ +547074458426237111173086536319506989478611558297416195273399\ +35302734375001e-4966L; +/* 0x1.00000000000000000000000000008p16383 */ +static const long double ld3ae = 0x1p16383L, ld3be = 0x1p16383L, ld3ce = 0x1.0000000000000000000000000001p16383L; +static const long double ld3a = +5.9486574767861588254287966331400362266521016077566321470782\ +537912717956830282749074200158904838100315216442070246474582\ +902003466452178519493817532236893426065414065500349426609921\ +035191682920005861156266113904955955975156868485667432573303\ +878926292023832306985858165533616318247459636179261303962505\ +904914506095247123433601806274279678546351097459236573913920\ +031119173565521719790447288258729779003490433862818295682642\ +966216118764004792730459319737327354906008978235133081179386\ +661103577408353480771246949457853166617701522167422003413661\ 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+562328802846445391417036742140146906572447511494124473885963\ +235217227016424204095604485308686968373890645296189932416571\ +281295736247619241329068636405743573306087991776733585972793\ +132869616481671565021096885870153734254648327143225051745267\ +530463119926261147612098111086806545372953526471421579845285\ +862975776235466663857936867536855924718593170503922894779577\ +706239977813334283740751103082483280516469722321753891088699\ +714361755511843803441649441302693703577359971743834932539197\ +595873998629500074441134301810890941848881837426270390549007\ +490141375766653241037340192392236932759127069111401216220596\ +540958515892047794438580629374176225297401789362125586732528\ +367695144980519774116001979888033796577336271850743828263427\ +598863925843301048044096576340652808516459551933515596083641\ +0468395384831999e+4931L; +static const long double ld3b = +5.9486574767861588254287966331400362266521016077566321470782\ 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+714361755511843803441649441302693703577359971743834932539197\ +595873998629500074441134301810890941848881837426270390549007\ +490141375766653241037340192392236932759127069111401216220596\ +540958515892047794438580629374176225297401789362125586732528\ +367695144980519774116001979888033796577336271850743828263427\ +598863925843301048044096576340652808516459551933515596083641\ +0468395384832e+4931L; +static const long double ld3c = +5.9486574767861588254287966331400362266521016077566321470782\ +537912717956830282749074200158904838100315216442070246474582\ +902003466452178519493817532236893426065414065500349426609921\ +035191682920005861156266113904955955975156868485667432573303\ +878926292023832306985858165533616318247459636179261303962505\ +904914506095247123433601806274279678546351097459236573913920\ +031119173565521719790447288258729779003490433862818295682642\ +966216118764004792730459319737327354906008978235133081179386\ +661103577408353480771246949457853166617701522167422003413661\ +284349262437896929014552545611813747697933241007066137144800\ +742052491919942298834913628182656296203230288447275444631994\ +418174246363265098248611943128819168942591708210157385631417\ +956400560296628065072016801065604053356267458749418972817500\ +860163920552394032596390414022010839803056885484295371329659\ +344624001094572196271168792142488910586863048428263135994222\ +918660801863635503541746352435642903327106245556596971697306\ +154375736529491499973297647239267168544491542059174479409314\ +453930981788080813637734358380528957486229480817553751111130\ +404254432007093360403147894746265072027252334199618554793914\ +408408563073872776198001518686536858983411123156743992398602\ +085226973929708268146742705557350571330511483380748376403472\ +416543579901056379914358020396036857647833383066531875675143\ +906511120597222727322243981995901699031025427175941279288823\ +868963521340475095965307606235778429805072284801680535137734\ +383642104178041358430293569208331406005130704155581295151191\ +023575851522079817808333970280354640050199344622016227349001\ +158400930280667186488774262251890453600109065837537684194570\ +764422774923245437306731669764159584659798151950637627762794\ +773771743234047950402370403351226180108444229650943701626484\ +199813157683590670152514287926030050893275989087988431157294\ +053225152320381185461962202878894704210605536874860744635921\ +856800920799848781308318732102232154544901177747472418520161\ +539850654183977571241391795912749098112352006092865789718049\ +308722403022684428414862730635213534446271587083620368851394\ +539053886621230946713996355227159995125430034494483477708852\ +290917108703653719242299789100268057863851224567265334616704\ +172517852701300018859009181286438758473871366303386211559752\ +189988549719766361306120241141163757479824826687017385967199\ +730649217746155593260923125994938678356692052428393066501806\ +030161358556419313420716683771612548240263459903320490075985\ +482955242306590857238462197972208846146747634114611463194143\ +127229709932188005016692926586196070737427116881065809283735\ +578248117685225847553587906225824731173075427424421056682930\ +008434666477496431516691881829440430197100204332606435934395\ +919650053069892524027974091575173698894803107552411683630872\ +565514028274910395383420510115859479233531504702656455261624\ +525121293886827716275308028935388238178963278225114817400178\ +138358373030159940110845417191798464503817960506134575572552\ +914585335913528444536373142082490326061583126796147603336390\ +503084982226891516248370317420733394038771780044922478150880\ +480334844447412365553656029955296322473008695074712792828366\ +405738282245039545396582938290818627301780773130202921675326\ +417583673495241569334204568141534153408474297319168484568799\ +451491133718839097374713416523361939237171154953070144389353\ +699828605993755613252573941610133829557167740458222617685028\ +690018342727148122013513056358815140027414679795450105000784\ +206522215604435223172005007036171570530334304897008809135848\ +675229547083561399988252552429769084290516103080260036003448\ +294799988351419108088251107290628711358276092795741489822211\ +879153727229891058795497426373608319405317602924241055836665\ +412584135657242160003706626205312971822953452930840783143003\ +733239017808969394445195220787737174218027747221253900890536\ +730326425051240764874006627032589076376990325467270006751475\ +463920721323985366812116303998245085483206258613663624851716\ +293180303624443281556295689730668616708901429287181381627670\ +203893651414675005136379365959571811951919653635887567699289\ +348324076406793991923217469674198904524716009847788439650157\ +995310043698774137542541699134940585662745702625097983274489\ +141416414789061652098131796728731652650516767112149192122453\ +562328802846445391417036742140146906572447511494124473885963\ +235217227016424204095604485308686968373890645296189932416571\ +281295736247619241329068636405743573306087991776733585972793\ +132869616481671565021096885870153734254648327143225051745267\ +530463119926261147612098111086806545372953526471421579845285\ +862975776235466663857936867536855924718593170503922894779577\ +706239977813334283740751103082483280516469722321753891088699\ +714361755511843803441649441302693703577359971743834932539197\ +595873998629500074441134301810890941848881837426270390549007\ +490141375766653241037340192392236932759127069111401216220596\ +540958515892047794438580629374176225297401789362125586732528\ +367695144980519774116001979888033796577336271850743828263427\ +598863925843301048044096576340652808516459551933515596083641\ +0468395384832001e+4931L; +#endif + +extern void abort (void); +extern void exit (int); + +int +main (void) +{ +#ifdef FLT_OK + if (f1a != f1ae + || f1b != f1be + || f1c != f1ce + || f2a != f2ae + || f2b != f2be + || f2c != f2ce + || f3a != f3ae + || f3b != f3be + || f3c != f3ce) + abort (); +#endif +#ifdef DBL_OK + if (d1a != d1ae + || d1b != d1be + || d1c != d1ce + || d2a != d2ae + || d2b != d2be + || d2c != d2ce + || d3a != d3ae + || d3b != d3be + || d3c != d3ce) + abort (); +#endif +#ifdef LDBL_OK + if (ld1a != ld1ae + || ld1b != ld1be + || ld1c != ld1ce + || ld2a != ld2ae + || ld2b != ld2be + || ld2c != ld2ce + || ld3a != ld3ae + || ld3b != ld3be + || ld3c != ld3ce) + abort (); +#endif + exit (0); +} diff --git a/gcc/testsuite/gcc.target/arm/pr54300.C b/gcc/testsuite/gcc.target/arm/pr54300.C new file mode 100644 index 00000000000..eb1a74e36cf --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr54300.C @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include <arm_neon.h> +#include <stdlib.h> + +struct __attribute__ ((aligned(8))) _v16u8_ { + uint8x16_t val; + _v16u8_( const int16x8_t &src) { val = vreinterpretq_u8_s16(src); } + operator int16x8_t () const { return vreinterpretq_s16_u8(val); } +}; +typedef struct _v16u8_ v16u8; + +struct __attribute__ ((aligned(4))) _v8u8_ { + uint8x8_t val; + _v8u8_( const uint8x8_t &src) { val = src; } + operator int16x4_t () const { return vreinterpret_s16_u8(val); } +}; +typedef struct _v8u8_ v8u8; + +typedef v16u8 v8i16; +typedef int32x4_t v4i32; +typedef const short cv1i16; +typedef const unsigned char cv1u8; +typedef const v8i16 cv8i16; + +static inline __attribute__((always_inline)) v8u8 zero_64(){ return vdup_n_u8( 0 ); } + +static inline __attribute__((always_inline)) v8i16 loadlo_8i16( cv8i16* p ){ + return vcombine_s16( vld1_s16( (cv1i16 *)p ), zero_64() ); +} +static inline __attribute__((always_inline)) v8i16 _loadlo_8i16( cv8i16* p, int offset ){ + return loadlo_8i16( (cv8i16*)(&((cv1u8*)p)[offset]) ); +} + +void __attribute__((noinline)) +test(unsigned short *_Inp, int32_t *_Out, + unsigned int s1v, unsigned int dv0, + unsigned int smask_v) +{ + int32x4_t c = vdupq_n_s32(0); + + for(unsigned int sv=0 ; sv!=dv0 ; sv=(sv+s1v)&smask_v ) + { + int32x4_t s; + s = vmovl_s16( vget_low_s16( _loadlo_8i16( (cv8i16*) _Inp, sv ) ) ); + c = vaddq_s32( c, s ); + } + vst1q_s32( _Out, c ); +} + +main() +{ + unsigned short a[4] = {1, 2, 3, 4}; + int32_t b[4] = {0, 0, 0, 0}; + test(a, b, 1, 1, ~0); + if (b[0] != 1 || b[1] != 2 || b[2] != 3 || b[3] != 4) + abort(); +} diff --git a/gcc/testsuite/gcc.target/i386/pr59133.c b/gcc/testsuite/gcc.target/i386/pr59133.c new file mode 100644 index 00000000000..ef8ef741de9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr59133.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -ffast-math -march=core-avx2" } */ + +#define XX 0 +#define YY 1 +#define ZZ 2 +#define DIM 3 +typedef float matrix[DIM][DIM]; +typedef float rvec[DIM]; +extern int det (matrix); +extern void foo(matrix); + +void bar1 (int n,int *index,rvec x[],matrix trans) +{ + float xt,yt,zt; + int i,ii; + + for(i=0; (i<n); i++) { + ii=index ? index[i] : i; + xt=x[ii][XX]; + yt=x[ii][YY]; + zt=x[ii][ZZ]; + x[ii][XX]=trans[XX][XX]*xt+trans[XX][YY]*yt+trans[XX][ZZ]*zt; + x[ii][YY]=trans[YY][XX]*xt+trans[YY][YY]*yt+trans[YY][ZZ]*zt; + x[ii][ZZ]=trans[ZZ][XX]*xt+trans[ZZ][YY]*yt+trans[ZZ][ZZ]*zt; + } +} + + +void bar2 (int n, rvec x[]) +{ + int m; + matrix trans; + + foo (trans); + + if (det (trans) < 0) { + for(m=0; (m<DIM); m++) + trans[ZZ][m] = -trans[ZZ][m]; + } + bar1 (n,(int*) 0,x,trans); +} diff --git a/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c b/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c index 0692b3d8069..14b56d0828b 100644 --- a/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c @@ -11,7 +11,11 @@ int msw(long long in) int i[2]; } ud; ud.ll = in; +#ifdef __LITTLE_ENDIAN__ + return ud.i[1]; +#else return ud.i[0]; +#endif } int main() diff --git a/gcc/testsuite/gcc.target/powerpc/pr48258-1.c b/gcc/testsuite/gcc.target/powerpc/pr48258-1.c index 4f37815d384..3ccbf7693d9 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr48258-1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr48258-1.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-O3 -mcpu=power7 -mabi=altivec -ffast-math -fno-unroll-loops" } */ /* { dg-final { scan-assembler-times "xvaddsp" 3 } } */ diff --git a/gcc/testsuite/gcc.target/sh/pr53976-1.c b/gcc/testsuite/gcc.target/sh/pr53976-1.c new file mode 100644 index 00000000000..4893b0668a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/pr53976-1.c @@ -0,0 +1,41 @@ +/* Check that the SH specific sh_optimize_sett_clrt RTL optimization pass + works as expected. */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */ +/* { dg-final { scan-assembler-times "clrt" 2 } } */ +/* { dg-final { scan-assembler-times "sett" 1 } } */ + +long long +test_00 (long long a, long long b, long long c, int d) +{ + /* One of the blocks should have a clrt and the other one should not. */ + if (d > 5) + return a + b; + else + return a + c; +} + +long long +test_01 (long long a, long long b) +{ + /* Must see a clrt because T bit is undefined at function entry. */ + return a + b; +} + +int +test_02 (const char* a) +{ + /* Must not see a sett after the inlined strlen. */ + return __builtin_strlen (a); +} + +int +test_03 (int a, int b, int c, int d) +{ + /* One of the blocks should have a sett and the other one should not. */ + if (d > 4) + return a + b + 1; + else + return a + c + 1; +} diff --git a/gcc/testsuite/gfortran.dg/erf_3.F90 b/gcc/testsuite/gfortran.dg/erf_3.F90 new file mode 100644 index 00000000000..d9d65898984 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/erf_3.F90 @@ -0,0 +1,53 @@ +! { dg-do run { xfail spu-*-* ia64-*-linux* } } +! { dg-options "-fno-range-check -ffree-line-length-none -O0" } +! { dg-add-options ieee } +! +! Check that simplification functions and runtime library agree on ERF, +! ERFC and ERFC_SCALED, for quadruple-precision. +! +! XFAILed for SPU targets because our library implementation of +! the double-precision erf/erfc functions is not accurate enough. +! +! XFAILed for IA64 Linux because of a glibc bug: +! http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59227 + +program test + use, intrinsic :: iso_fortran_env + implicit none + + ! QP will be the largest supported real kind, possibly real(kind=16) + integer, parameter :: qp = real_kinds(ubound(real_kinds,dim=1)) + real(kind=qp) :: x + +#define CHECK(a) \ + x = a ; \ + call check(erf(real(a,kind=qp)), erf(x)) ; \ + call check(erfc(real(a,kind=qp)), erfc(x)) ; \ + call check(erfc_scaled(real(a,kind=qp)), erfc_scaled(x)) + + CHECK(0.0) + CHECK(0.9) + CHECK(1.9) + CHECK(10.) + CHECK(11.) + CHECK(12.) + CHECK(13.) + CHECK(14.) + CHECK(49.) + CHECK(190.) + + CHECK(-0.0) + CHECK(-0.9) + CHECK(-1.9) + CHECK(-19.) + CHECK(-190.) + +contains + + subroutine check (a, b) + real(kind=qp), intent(in) :: a, b + print *, abs(a-b) / spacing(a) + if (abs(a - b) > 10 * spacing(a)) call abort + end subroutine + +end program test diff --git a/gcc/tree-cfgcleanup.c b/gcc/tree-cfgcleanup.c index 4e5adc28a06..5ae70abc29e 100644 --- a/gcc/tree-cfgcleanup.c +++ b/gcc/tree-cfgcleanup.c @@ -237,7 +237,7 @@ cleanup_control_flow_bb (basic_block bb) the start of the successor block. As a precondition, we require that BB be not equal to - ENTRY_BLOCK_PTR. */ + the entry block. */ static bool tree_forwarder_block_p (basic_block bb, bool phi_wanted) @@ -250,7 +250,7 @@ tree_forwarder_block_p (basic_block bb, bool phi_wanted) /* If PHI_WANTED is false, BB must not have any PHI nodes. Otherwise, BB must have PHI nodes. */ || gimple_seq_empty_p (phi_nodes (bb)) == phi_wanted - /* BB may not be a predecessor of EXIT_BLOCK_PTR. */ + /* BB may not be a predecessor of the exit block. */ || single_succ (bb) == EXIT_BLOCK_PTR_FOR_FN (cfun) /* Nor should this be an infinite loop. */ || single_succ (bb) == bb diff --git a/gcc/tree-inline.c b/gcc/tree-inline.c index b95a1885216..e905ab8ebf1 100644 --- a/gcc/tree-inline.c +++ b/gcc/tree-inline.c @@ -2431,9 +2431,10 @@ copy_cfg_body (copy_body_data * id, gcov_type count, int frequency_scale, /* Register specific tree functions. */ gimple_register_cfg_hooks (); - /* If we are inlining just region of the function, make sure to connect new entry - to ENTRY_BLOCK_PTR. Since new entry can be part of loop, we must compute - frequency and probability of ENTRY_BLOCK_PTR based on the frequencies and + /* If we are inlining just region of the function, make sure to connect + new entry to ENTRY_BLOCK_PTR_FOR_FN (cfun). Since new entry can be + part of loop, we must compute frequency and probability of + ENTRY_BLOCK_PTR_FOR_FN (cfun) based on the frequencies and probabilities of edges incoming from nonduplicated region. */ if (new_entry) { @@ -4517,7 +4518,6 @@ optimize_inline_calls (tree fn) copy_body_data id; basic_block bb; int last = n_basic_blocks_for_fn (cfun); - struct gimplify_ctx gctx; bool inlined_p = false; /* Clear out ID. */ @@ -4538,7 +4538,7 @@ optimize_inline_calls (tree fn) id.transform_lang_insert_block = NULL; id.statements_to_fold = pointer_set_create (); - push_gimplify_context (&gctx); + push_gimplify_context (); /* We make no attempts to keep dominance info up-to-date. */ free_dominance_info (CDI_DOMINATORS); diff --git a/gcc/tree-loop-distribution.c b/gcc/tree-loop-distribution.c index 0afa52aff1e..b4ca2119d1e 100644 --- a/gcc/tree-loop-distribution.c +++ b/gcc/tree-loop-distribution.c @@ -480,6 +480,7 @@ typedef struct partition_s data_reference_p main_dr; data_reference_p secondary_dr; tree niter; + bool plus_one; } *partition_t; @@ -703,13 +704,16 @@ generate_loops_for_partition (struct loop *loop, partition_t partition, /* Build the size argument for a memory operation call. */ static tree -build_size_arg_loc (location_t loc, data_reference_p dr, tree nb_iter) +build_size_arg_loc (location_t loc, data_reference_p dr, tree nb_iter, + bool plus_one) { - tree size; - size = fold_build2_loc (loc, MULT_EXPR, sizetype, - fold_convert_loc (loc, sizetype, nb_iter), + tree size = fold_convert_loc (loc, sizetype, nb_iter); + if (plus_one) + size = size_binop (PLUS_EXPR, size, size_one_node); + size = fold_build2_loc (loc, MULT_EXPR, sizetype, size, TYPE_SIZE_UNIT (TREE_TYPE (DR_REF (dr)))); - return fold_convert_loc (loc, size_type_node, size); + size = fold_convert_loc (loc, size_type_node, size); + return size; } /* Build an address argument for a memory operation call. */ @@ -781,7 +785,8 @@ generate_memset_builtin (struct loop *loop, partition_t partition) /* The new statements will be placed before LOOP. */ gsi = gsi_last_bb (loop_preheader_edge (loop)->src); - nb_bytes = build_size_arg_loc (loc, partition->main_dr, partition->niter); + nb_bytes = build_size_arg_loc (loc, partition->main_dr, partition->niter, + partition->plus_one); nb_bytes = force_gimple_operand_gsi (&gsi, nb_bytes, true, NULL_TREE, false, GSI_CONTINUE_LINKING); mem = build_addr_arg_loc (loc, partition->main_dr, nb_bytes); @@ -837,7 +842,8 @@ generate_memcpy_builtin (struct loop *loop, partition_t partition) /* The new statements will be placed before LOOP. */ gsi = gsi_last_bb (loop_preheader_edge (loop)->src); - nb_bytes = build_size_arg_loc (loc, partition->main_dr, partition->niter); + nb_bytes = build_size_arg_loc (loc, partition->main_dr, partition->niter, + partition->plus_one); nb_bytes = force_gimple_operand_gsi (&gsi, nb_bytes, true, NULL_TREE, false, GSI_CONTINUE_LINKING); dest = build_addr_arg_loc (loc, partition->main_dr, nb_bytes); @@ -980,11 +986,13 @@ classify_partition (loop_p loop, struct graph *rdg, partition_t partition) tree nb_iter; data_reference_p single_load, single_store; bool volatiles_p = false; + bool plus_one = false; partition->kind = PKIND_NORMAL; partition->main_dr = NULL; partition->secondary_dr = NULL; partition->niter = NULL_TREE; + partition->plus_one = false; EXECUTE_IF_SET_IN_BITMAP (partition->stmts, 0, i, bi) { @@ -1047,13 +1055,12 @@ classify_partition (loop_p loop, struct graph *rdg, partition_t partition) if (!single_store) return; - if (!dominated_by_p (CDI_DOMINATORS, single_exit (loop)->src, - gimple_bb (DR_STMT (single_store)))) - nb_iter = number_of_latch_executions (loop); - else - nb_iter = number_of_exit_cond_executions (loop); + nb_iter = number_of_latch_executions (loop); if (!nb_iter || nb_iter == chrec_dont_know) return; + if (dominated_by_p (CDI_DOMINATORS, single_exit (loop)->src, + gimple_bb (DR_STMT (single_store)))) + plus_one = true; if (single_store && !single_load) { @@ -1075,6 +1082,7 @@ classify_partition (loop_p loop, struct graph *rdg, partition_t partition) partition->kind = PKIND_MEMSET; partition->main_dr = single_store; partition->niter = nb_iter; + partition->plus_one = plus_one; } else if (single_store && single_load) { @@ -1132,6 +1140,7 @@ classify_partition (loop_p loop, struct graph *rdg, partition_t partition) partition->main_dr = single_store; partition->secondary_dr = single_load; partition->niter = nb_iter; + partition->plus_one = plus_one; } } diff --git a/gcc/tree-scalar-evolution.h b/gcc/tree-scalar-evolution.h index 8846fbe50cc..fc87251cabe 100644 --- a/gcc/tree-scalar-evolution.h +++ b/gcc/tree-scalar-evolution.h @@ -40,8 +40,8 @@ extern bool simple_iv (struct loop *, struct loop *, tree, struct affine_iv_d *, bool); extern tree compute_overall_effect_of_inner_loop (struct loop *, tree); -/* Returns the basic block preceding LOOP or ENTRY_BLOCK_PTR when the - loop is function's body. */ +/* Returns the basic block preceding LOOP, or the CFG entry block when + the loop is function's body. */ static inline basic_block block_before_loop (loop_p loop) diff --git a/gcc/tree-ssa-forwprop.c b/gcc/tree-ssa-forwprop.c index e8a92ed6c16..a12c8e0c6ff 100644 --- a/gcc/tree-ssa-forwprop.c +++ b/gcc/tree-ssa-forwprop.c @@ -2996,6 +2996,69 @@ combine_conversions (gimple_stmt_iterator *gsi) return 0; } +/* Combine VIEW_CONVERT_EXPRs with their defining statement. */ + +static bool +simplify_vce (gimple_stmt_iterator *gsi) +{ + gimple stmt = gsi_stmt (*gsi); + tree type = TREE_TYPE (gimple_assign_lhs (stmt)); + + /* Drop useless VIEW_CONVERT_EXPRs. */ + tree op = TREE_OPERAND (gimple_assign_rhs1 (stmt), 0); + if (useless_type_conversion_p (type, TREE_TYPE (op))) + { + gimple_assign_set_rhs1 (stmt, op); + update_stmt (stmt); + return true; + } + + if (TREE_CODE (op) != SSA_NAME) + return false; + + gimple def_stmt = SSA_NAME_DEF_STMT (op); + if (!is_gimple_assign (def_stmt)) + return false; + + tree def_op = gimple_assign_rhs1 (def_stmt); + switch (gimple_assign_rhs_code (def_stmt)) + { + CASE_CONVERT: + /* Strip integral conversions that do not change the precision. */ + if ((INTEGRAL_TYPE_P (TREE_TYPE (op)) + || POINTER_TYPE_P (TREE_TYPE (op))) + && (INTEGRAL_TYPE_P (TREE_TYPE (def_op)) + || POINTER_TYPE_P (TREE_TYPE (def_op))) + && (TYPE_PRECISION (TREE_TYPE (op)) + == TYPE_PRECISION (TREE_TYPE (def_op)))) + { + TREE_OPERAND (gimple_assign_rhs1 (stmt), 0) = def_op; + update_stmt (stmt); + return true; + } + break; + + case VIEW_CONVERT_EXPR: + /* Series of VIEW_CONVERT_EXPRs on register operands can + be contracted. */ + if (TREE_CODE (TREE_OPERAND (def_op, 0)) == SSA_NAME) + { + if (useless_type_conversion_p (type, + TREE_TYPE (TREE_OPERAND (def_op, 0)))) + gimple_assign_set_rhs1 (stmt, TREE_OPERAND (def_op, 0)); + else + TREE_OPERAND (gimple_assign_rhs1 (stmt), 0) + = TREE_OPERAND (def_op, 0); + update_stmt (stmt); + return true; + } + + default:; + } + + return false; +} + /* Combine an element access with a shuffle. Returns true if there were any changes made, else it returns false. */ @@ -3493,6 +3556,8 @@ ssa_forward_propagate_and_combine (void) changed = did_something != 0; } + else if (code == VIEW_CONVERT_EXPR) + changed = simplify_vce (&gsi); else if (code == VEC_PERM_EXPR) { int did_something = simplify_permutation (&gsi); diff --git a/gcc/tree-ssa-loop-ch.c b/gcc/tree-ssa-loop-ch.c index df45c286790..2e80649fe2d 100644 --- a/gcc/tree-ssa-loop-ch.c +++ b/gcc/tree-ssa-loop-ch.c @@ -243,6 +243,16 @@ copy_loop_headers (void) are not now, since there was the loop exit condition. */ split_edge (loop_preheader_edge (loop)); split_edge (loop_latch_edge (loop)); + + /* We peeled off one iteration of the loop thus we can lower + the maximum number of iterations if we have a previously + recorded value for that. */ + widest_int max; + if (get_max_loop_iterations (loop, &max)) + { + max -= 1; + loop->nb_iterations_upper_bound = max; + } } update_ssa (TODO_update_ssa); diff --git a/gcc/tree-ssa-propagate.c b/gcc/tree-ssa-propagate.c index b9db34c5057..b45ff4755c2 100644 --- a/gcc/tree-ssa-propagate.c +++ b/gcc/tree-ssa-propagate.c @@ -503,7 +503,7 @@ ssa_prop_init (void) cfg_blocks.safe_grow_cleared (20); /* Initially assume that every edge in the CFG is not executable. - (including the edges coming out of ENTRY_BLOCK_PTR). */ + (including the edges coming out of the entry block). */ FOR_ALL_BB (bb) { gimple_stmt_iterator si; diff --git a/gcc/tree-ssa-tail-merge.c b/gcc/tree-ssa-tail-merge.c index 35b8bbe0497..2e1df69b7bd 100644 --- a/gcc/tree-ssa-tail-merge.c +++ b/gcc/tree-ssa-tail-merge.c @@ -309,6 +309,7 @@ stmt_local_def (gimple stmt) def_operand_p def_p; if (gimple_has_side_effects (stmt) + || stmt_could_throw_p (stmt) || gimple_vdef (stmt) != NULL_TREE) return false; diff --git a/gcc/tree-vect-loop-manip.c b/gcc/tree-vect-loop-manip.c index 8ac1d92f995..57d8a7211cb 100644 --- a/gcc/tree-vect-loop-manip.c +++ b/gcc/tree-vect-loop-manip.c @@ -1400,151 +1400,6 @@ find_loop_location (struct loop *loop) } -/* This function builds ni_name = number of iterations loop executes - on the loop preheader. If SEQ is given the stmt is instead emitted - there. */ - -static tree -vect_build_loop_niters (loop_vec_info loop_vinfo, gimple_seq seq) -{ - tree ni_name, var; - gimple_seq stmts = NULL; - edge pe; - struct loop *loop = LOOP_VINFO_LOOP (loop_vinfo); - tree ni = unshare_expr (LOOP_VINFO_NITERS (loop_vinfo)); - - var = create_tmp_var (TREE_TYPE (ni), "niters"); - ni_name = force_gimple_operand (ni, &stmts, false, var); - - pe = loop_preheader_edge (loop); - if (stmts) - { - if (seq) - gimple_seq_add_seq (&seq, stmts); - else - { - basic_block new_bb = gsi_insert_seq_on_edge_immediate (pe, stmts); - gcc_assert (!new_bb); - } - } - - return ni_name; -} - - -/* This function generates the following statements: - - ni_name = number of iterations loop executes - ratio = ni_name / vf - ratio_mult_vf_name = ratio * vf - - and places them at the loop preheader edge or in COND_EXPR_STMT_LIST - if that is non-NULL. */ - -void -vect_generate_tmps_on_preheader (loop_vec_info loop_vinfo, - tree *ni_name_ptr, - tree *ratio_mult_vf_name_ptr, - tree *ratio_name_ptr, - gimple_seq cond_expr_stmt_list) -{ - - edge pe; - basic_block new_bb; - gimple_seq stmts; - tree ni_name, ni_minus_gap_name; - tree var; - tree ratio_name; - tree ratio_mult_vf_name; - struct loop *loop = LOOP_VINFO_LOOP (loop_vinfo); - tree ni = LOOP_VINFO_NITERS (loop_vinfo); - int vf = LOOP_VINFO_VECT_FACTOR (loop_vinfo); - tree log_vf; - - pe = loop_preheader_edge (loop); - - /* Generate temporary variable that contains - number of iterations loop executes. */ - - ni_name = vect_build_loop_niters (loop_vinfo, cond_expr_stmt_list); - log_vf = build_int_cst (TREE_TYPE (ni), exact_log2 (vf)); - - /* If epilogue loop is required because of data accesses with gaps, we - subtract one iteration from the total number of iterations here for - correct calculation of RATIO. */ - if (LOOP_VINFO_PEELING_FOR_GAPS (loop_vinfo)) - { - ni_minus_gap_name = fold_build2 (MINUS_EXPR, TREE_TYPE (ni_name), - ni_name, - build_one_cst (TREE_TYPE (ni_name))); - if (!is_gimple_val (ni_minus_gap_name)) - { - var = create_tmp_var (TREE_TYPE (ni), "ni_gap"); - - stmts = NULL; - ni_minus_gap_name = force_gimple_operand (ni_minus_gap_name, &stmts, - true, var); - if (cond_expr_stmt_list) - gimple_seq_add_seq (&cond_expr_stmt_list, stmts); - else - { - pe = loop_preheader_edge (loop); - new_bb = gsi_insert_seq_on_edge_immediate (pe, stmts); - gcc_assert (!new_bb); - } - } - } - else - ni_minus_gap_name = ni_name; - - /* Create: ratio = ni >> log2(vf) */ - - ratio_name = fold_build2 (RSHIFT_EXPR, TREE_TYPE (ni_minus_gap_name), - ni_minus_gap_name, log_vf); - if (!is_gimple_val (ratio_name)) - { - var = create_tmp_var (TREE_TYPE (ni), "bnd"); - - stmts = NULL; - ratio_name = force_gimple_operand (ratio_name, &stmts, true, var); - if (cond_expr_stmt_list) - gimple_seq_add_seq (&cond_expr_stmt_list, stmts); - else - { - pe = loop_preheader_edge (loop); - new_bb = gsi_insert_seq_on_edge_immediate (pe, stmts); - gcc_assert (!new_bb); - } - } - - /* Create: ratio_mult_vf = ratio << log2 (vf). */ - - ratio_mult_vf_name = fold_build2 (LSHIFT_EXPR, TREE_TYPE (ratio_name), - ratio_name, log_vf); - if (!is_gimple_val (ratio_mult_vf_name)) - { - var = create_tmp_var (TREE_TYPE (ni), "ratio_mult_vf"); - - stmts = NULL; - ratio_mult_vf_name = force_gimple_operand (ratio_mult_vf_name, &stmts, - true, var); - if (cond_expr_stmt_list) - gimple_seq_add_seq (&cond_expr_stmt_list, stmts); - else - { - pe = loop_preheader_edge (loop); - new_bb = gsi_insert_seq_on_edge_immediate (pe, stmts); - gcc_assert (!new_bb); - } - } - - *ni_name_ptr = ni_name; - *ratio_mult_vf_name_ptr = ratio_mult_vf_name; - *ratio_name_ptr = ratio_name; - - return; -} - /* Function vect_can_advance_ivs_p In case the number of iterations that LOOP iterates is unknown at compile @@ -1762,10 +1617,10 @@ vect_update_ivs_after_vectorizer (loop_vec_info loop_vinfo, tree niters, test. */ void -vect_do_peeling_for_loop_bound (loop_vec_info loop_vinfo, tree *ratio, +vect_do_peeling_for_loop_bound (loop_vec_info loop_vinfo, + tree ni_name, tree ratio_mult_vf_name, unsigned int th, bool check_profitability) { - tree ni_name, ratio_mult_vf_name; struct loop *loop = LOOP_VINFO_LOOP (loop_vinfo); struct loop *new_loop; edge update_e; @@ -1781,15 +1636,6 @@ vect_do_peeling_for_loop_bound (loop_vec_info loop_vinfo, tree *ratio, initialize_original_copy_tables (); - /* Generate the following variables on the preheader of original loop: - - ni_name = number of iteration the original loop executes - ratio = ni_name / vf - ratio_mult_vf_name = ratio * vf */ - vect_generate_tmps_on_preheader (loop_vinfo, &ni_name, - &ratio_mult_vf_name, ratio, - cond_expr_stmt_list); - loop_num = loop->num; new_loop = slpeel_tree_peel_loop_to_edge (loop, single_exit (loop), @@ -2025,11 +1871,11 @@ vect_update_inits_of_drs (loop_vec_info loop_vinfo, tree niters) peeling is recorded in LOOP_VINFO_UNALIGNED_DR. */ void -vect_do_peeling_for_alignment (loop_vec_info loop_vinfo, +vect_do_peeling_for_alignment (loop_vec_info loop_vinfo, tree ni_name, unsigned int th, bool check_profitability) { struct loop *loop = LOOP_VINFO_LOOP (loop_vinfo); - tree niters_of_prolog_loop, ni_name; + tree niters_of_prolog_loop; tree n_iters; tree wide_prolog_niters; struct loop *new_loop; @@ -2043,7 +1889,8 @@ vect_do_peeling_for_alignment (loop_vec_info loop_vinfo, initialize_original_copy_tables (); - ni_name = vect_build_loop_niters (loop_vinfo, NULL); + gimple_seq stmts = NULL; + gsi_insert_seq_on_edge_immediate (loop_preheader_edge (loop), stmts); niters_of_prolog_loop = vect_gen_niters_for_prolog_loop (loop_vinfo, ni_name, &bound); diff --git a/gcc/tree-vect-loop.c b/gcc/tree-vect-loop.c index 8883852a08a..915664dab07 100644 --- a/gcc/tree-vect-loop.c +++ b/gcc/tree-vect-loop.c @@ -5572,6 +5572,110 @@ vect_loop_kill_debug_uses (struct loop *loop, gimple stmt) } } + +/* This function builds ni_name = number of iterations. Statements + are queued onto SEQ. */ + +static tree +vect_build_loop_niters (loop_vec_info loop_vinfo, gimple_seq *seq) +{ + tree ni_name, var; + gimple_seq stmts = NULL; + tree ni = unshare_expr (LOOP_VINFO_NITERS (loop_vinfo)); + + var = create_tmp_var (TREE_TYPE (ni), "niters"); + ni_name = force_gimple_operand (ni, &stmts, false, var); + + if (stmts) + gimple_seq_add_seq (seq, stmts); + + return ni_name; +} + + +/* This function generates the following statements: + + ni_name = number of iterations loop executes + ratio = ni_name / vf + ratio_mult_vf_name = ratio * vf + + and places them in COND_EXPR_STMT_LIST. */ + +static void +vect_generate_tmps_on_preheader (loop_vec_info loop_vinfo, + tree ni_name, + tree *ratio_mult_vf_name_ptr, + tree *ratio_name_ptr, + gimple_seq *cond_expr_stmt_list) +{ + gimple_seq stmts; + tree ni_minus_gap_name; + tree var; + tree ratio_name; + tree ratio_mult_vf_name; + tree ni = LOOP_VINFO_NITERS (loop_vinfo); + int vf = LOOP_VINFO_VECT_FACTOR (loop_vinfo); + tree log_vf; + + log_vf = build_int_cst (TREE_TYPE (ni), exact_log2 (vf)); + + /* If epilogue loop is required because of data accesses with gaps, we + subtract one iteration from the total number of iterations here for + correct calculation of RATIO. */ + if (LOOP_VINFO_PEELING_FOR_GAPS (loop_vinfo)) + { + ni_minus_gap_name = fold_build2 (MINUS_EXPR, TREE_TYPE (ni_name), + ni_name, + build_one_cst (TREE_TYPE (ni_name))); + if (!is_gimple_val (ni_minus_gap_name)) + { + var = create_tmp_var (TREE_TYPE (ni), "ni_gap"); + + stmts = NULL; + ni_minus_gap_name = force_gimple_operand (ni_minus_gap_name, &stmts, + true, var); + gimple_seq_add_seq (cond_expr_stmt_list, stmts); + } + } + else + ni_minus_gap_name = ni_name; + + /* Create: ratio = ni >> log2(vf) */ + + ratio_name = fold_build2 (RSHIFT_EXPR, TREE_TYPE (ni_minus_gap_name), + ni_minus_gap_name, log_vf); + if (!is_gimple_val (ratio_name)) + { + var = create_tmp_var (TREE_TYPE (ni), "bnd"); + + stmts = NULL; + ratio_name = force_gimple_operand (ratio_name, &stmts, true, var); + gimple_seq_add_seq (cond_expr_stmt_list, stmts); + } + *ratio_name_ptr = ratio_name; + + /* Create: ratio_mult_vf = ratio << log2 (vf). */ + + if (ratio_mult_vf_name_ptr) + { + ratio_mult_vf_name = fold_build2 (LSHIFT_EXPR, TREE_TYPE (ratio_name), + ratio_name, log_vf); + if (!is_gimple_val (ratio_mult_vf_name)) + { + var = create_tmp_var (TREE_TYPE (ni), "ratio_mult_vf"); + + stmts = NULL; + ratio_mult_vf_name = force_gimple_operand (ratio_mult_vf_name, &stmts, + true, var); + gimple_seq_add_seq (cond_expr_stmt_list, stmts); + } + *ratio_mult_vf_name_ptr = ratio_mult_vf_name; + } + + return; +} + + /* Function vect_transform_loop. The analysis phase has determined that the loop is vectorizable. @@ -5636,11 +5740,18 @@ vect_transform_loop (loop_vec_info loop_vinfo) } /* Peel the loop if there are data refs with unknown alignment. - Only one data ref with unknown store is allowed. */ + Only one data ref with unknown store is allowed. + This clobbers LOOP_VINFO_NITERS but retains the original + in LOOP_VINFO_NITERS_UNCHANGED. So we cannot avoid re-computing + niters. */ if (LOOP_PEELING_FOR_ALIGNMENT (loop_vinfo)) { - vect_do_peeling_for_alignment (loop_vinfo, th, check_profitability); + gimple_seq stmts = NULL; + tree ni_name = vect_build_loop_niters (loop_vinfo, &stmts); + gsi_insert_seq_on_edge_immediate (loop_preheader_edge (loop), stmts); + vect_do_peeling_for_alignment (loop_vinfo, ni_name, + th, check_profitability); check_profitability = false; } @@ -5655,16 +5766,27 @@ vect_transform_loop (loop_vec_info loop_vinfo) if ((int) tree_ctz (LOOP_VINFO_NITERS (loop_vinfo)) < exact_log2 (vectorization_factor) || LOOP_VINFO_PEELING_FOR_GAPS (loop_vinfo)) - vect_do_peeling_for_loop_bound (loop_vinfo, &ratio, - th, check_profitability); + { + tree ni_name, ratio_mult_vf; + gimple_seq stmts = NULL; + ni_name = vect_build_loop_niters (loop_vinfo, &stmts); + vect_generate_tmps_on_preheader (loop_vinfo, ni_name, &ratio_mult_vf, + &ratio, &stmts); + gsi_insert_seq_on_edge_immediate (loop_preheader_edge (loop), stmts); + vect_do_peeling_for_loop_bound (loop_vinfo, ni_name, ratio_mult_vf, + th, check_profitability); + } else if (LOOP_VINFO_NITERS_KNOWN_P (loop_vinfo)) ratio = build_int_cst (TREE_TYPE (LOOP_VINFO_NITERS (loop_vinfo)), LOOP_VINFO_INT_NITERS (loop_vinfo) / vectorization_factor); else { - tree ni_name, ratio_mult_vf; - vect_generate_tmps_on_preheader (loop_vinfo, &ni_name, &ratio_mult_vf, - &ratio, NULL); + tree ni_name; + gimple_seq stmts = NULL; + ni_name = vect_build_loop_niters (loop_vinfo, &stmts); + vect_generate_tmps_on_preheader (loop_vinfo, ni_name, NULL, + &ratio, &stmts); + gsi_insert_seq_on_edge_immediate (loop_preheader_edge (loop), stmts); } /* 1) Make sure the loop header has exactly two entries diff --git a/gcc/tree-vectorizer.h b/gcc/tree-vectorizer.h index 1634d7fa7f5..1297fab6cfe 100644 --- a/gcc/tree-vectorizer.h +++ b/gcc/tree-vectorizer.h @@ -937,11 +937,10 @@ extern void slpeel_make_loop_iterate_ntimes (struct loop *, tree); extern bool slpeel_can_duplicate_loop_p (const struct loop *, const_edge); struct loop *slpeel_tree_duplicate_loop_to_edge_cfg (struct loop *, edge); extern void vect_loop_versioning (loop_vec_info, unsigned int, bool); -extern void vect_generate_tmps_on_preheader (loop_vec_info, tree *, tree *, - tree *, gimple_seq); -extern void vect_do_peeling_for_loop_bound (loop_vec_info, tree *, +extern void vect_do_peeling_for_loop_bound (loop_vec_info, tree, tree, unsigned int, bool); -extern void vect_do_peeling_for_alignment (loop_vec_info, unsigned int, bool); +extern void vect_do_peeling_for_alignment (loop_vec_info, tree, + unsigned int, bool); extern LOC find_loop_location (struct loop *); extern bool vect_can_advance_ivs_p (loop_vec_info); diff --git a/gcc/varpool.c b/gcc/varpool.c index 06b93a30d5f..f79cf49cc55 100644 --- a/gcc/varpool.c +++ b/gcc/varpool.c @@ -205,6 +205,8 @@ dump_varpool_node (FILE *f, struct varpool_node *node) fprintf (f, " initialized"); if (node->output) fprintf (f, " output"); + if (node->need_bounds_init) + fprintf (f, " need-bounds-init"); if (TREE_READONLY (node->decl)) fprintf (f, " read-only"); if (ctor_for_folding (node->decl) != error_mark_node) |