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author | belagod <belagod@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-11-13 15:07:27 +0000 |
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committer | belagod <belagod@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-11-13 15:07:27 +0000 |
commit | 8a0ffa1de325dbe7a0bb2cb1a8dcf6e4adbc45b2 (patch) | |
tree | f7b2fd45d1b4be178fe79d81ac861da1d6af5197 /gcc | |
parent | e76492cb8b4b18b94fb458d48a4e935b41b32d3e (diff) | |
download | gcc-8a0ffa1de325dbe7a0bb2cb1a8dcf6e4adbc45b2.tar.gz |
2013-11-13 Tejas Belagod <tejas.belagod@arm.com>
gcc/
* config/aarch64/aarch64-simd.md (vec_extract): New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@204747 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 4 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 16 |
2 files changed, 20 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 331e61cd6a9..8f989267084 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2013-11-13 Tejas Belagod <tejas.belagod@arm.com> + * config/aarch64/aarch64-simd.md (vec_extract): New. + +2013-11-13 Tejas Belagod <tejas.belagod@arm.com> + * config/aarch64/aarch64-simd.md (vec_set<mode>): Add w -> w option to the constraint. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index df4ef9592dc..0b16b057e78 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4582,3 +4582,19 @@ (set_attr "simd_mode" "<MODE>")] ) +;; Standard pattern name vec_extract<mode>. + +(define_insn "vec_extract<mode>" + [(set (match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "=r, w, Utv") + (vec_select:<VEL> + (match_operand:VALL 1 "register_operand" "w, w, w") + (parallel [(match_operand:SI 2 "immediate_operand" "i,i,i")])))] + "TARGET_SIMD" + "@ + umov\\t%<vw>0, %1.<Vetype>[%2] + dup\\t%<Vetype>0, %1.<Vetype>[%2] + st1\\t{%1.<Vetype>}[%2], %0" + [(set_attr "simd_type" "simd_movgp, simd_dup, simd_store1s") + (set_attr "type" "neon_to_gp<q>, neon_dup<q>, neon_store1_one_lane<q>") + (set_attr "simd_mode" "<MODE>")] +) |