2007-04-04 Chen Liqin <liqin@sunnorth.com.cn>

        * config/score/crti.asm: Change _bss_start to __bss_start.
        * config/score/score.h (CONDITIONAL_REGISTER_USAGE): Added.
        (OUTGOING_REG_PARM_STACK_SPACE) update.
        * config/score/score.opt: add options to make backend support
        score5, score5u, score7 and score7d.
        * config/score/score.md: Likewise.
        * config/score/misc.md: Likewise.
        * config/score/mac.md: Likewise.
        * doc/invoke.texi: Likewise.
        * doc/md.texi: update constraints define.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@123490 138bc75d-0d04-0410-961f-82ee72b054a4

9 files changed, 112 insertions, 66 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e3b491aea99..00d1e9e96a9 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2007-04-04  Chen Liqin  <liqin@sunnorth.com.cn>
+
+        * config/score/crti.asm: Change _bss_start to __bss_start.
+        * config/score/score.h (CONDITIONAL_REGISTER_USAGE): Added.
+        (OUTGOING_REG_PARM_STACK_SPACE) update.
+        * config/score/score.opt: add options to make backend support
+        score5, score5u, score7 and score7d.
+        * config/score/score.md: Likewise.
+        * config/score/misc.md: Likewise.
+        * config/score/mac.md: Likewise.
+        * doc/invoke.texi: Likewise.
+        * doc/md.texi: update constraints define.
+
 2007-04-03  Richard Henderson  <rth@redhat.com>
 
 	* expr.c (store_expr): If get_signed_or_unsigned_type doesn't yield
diff --git a/gcc/config/score/crti.asm b/gcc/config/score/crti.asm
index 8c6bca0e0cd..88b9526f0e2 100644
--- a/gcc/config/score/crti.asm
+++ b/gcc/config/score/crti.asm
@@ -43,8 +43,8 @@
         .mask   0x00000000, 0
 _start:
         la      r28, _gp
-        la      r8, _bss_start
-        la      r9, _bss_end__
+        la      r8, __bss_start
+        la      r9, __bss_end__
         sub!    r9, r8
         srli!   r9, 2
         addi    r9, -1
@@ -91,8 +91,8 @@ _fini:
         .mask   0x00000000,0
 _start:
         la      r28, _gp
-        la      r8, _bss_start
-        la      r9, _bss_end__
+        la      r8, __bss_start
+        la      r9, __bss_end__
         sub!    r9, r8
         srli!   r9, 2
         addi    r9, -1
diff --git a/gcc/config/score/mac.md b/gcc/config/score/mac.md
index ca7889d4185..88550c73e59 100644
--- a/gcc/config/score/mac.md
+++ b/gcc/config/score/mac.md
@@ -26,7 +26,7 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
         (smax:SI (match_operand:SI 1 "register_operand" "d")
                  (match_operand:SI 2 "register_operand" "d")))]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
   "max     %0, %1, %2"
   [(set_attr "type" "arith")
    (set_attr "mode" "SI")])
@@ -35,7 +35,7 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
         (smin:SI (match_operand:SI 1 "register_operand" "d")
                  (match_operand:SI 2 "register_operand" "d")))]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
   "min     %0, %1, %2"
   [(set_attr "type" "arith")
    (set_attr "mode" "SI")])
@@ -43,7 +43,7 @@
 (define_insn "abssi2"
   [(set (match_operand:SI 0 "register_operand" "=d")
         (abs:SI (match_operand:SI 1 "register_operand" "d")))]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
   "abs     %0, %1"
   [(set_attr "type" "arith")
    (set_attr "mode" "SI")])
@@ -51,7 +51,7 @@
 (define_insn "clzsi2"
   [(set (match_operand:SI 0 "register_operand" "=d")
         (clz:SI (match_operand:SI 1 "register_operand" "d")))]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
   "clz     %0, %1"
   [(set_attr "type" "arith")
    (set_attr "mode" "SI")])
@@ -59,7 +59,7 @@
 (define_insn "sffs"
   [(set (match_operand:SI 0 "register_operand" "=d")
         (unspec:SI [(match_operand:SI 1 "register_operand" "d")] SFFS))]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
   "bitrev  %0, %1, r0\;clz     %0, %0\;addi    %0, 0x1"
   [(set_attr "type" "arith")
    (set_attr "mode" "SI")])
@@ -67,7 +67,7 @@
 (define_expand "ffssi2"
   [(set (match_operand:SI 0 "register_operand")
         (ffs:SI (match_operand:SI 1 "register_operand")))]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
 {
   emit_insn (gen_sffs (operands[0], operands[1]));
   emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CC_NZmode, CC_REGNUM),
@@ -85,7 +85,7 @@
         (match_operand:SI 1 "register_operand" ""))
    (set (match_operand:SI 2 "hireg_operand" "")
         (match_operand:SI 3 "register_operand" ""))]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
   [(parallel
        [(set (match_dup 0) (match_dup 1))
         (set (match_dup 2) (match_dup 3))])])
@@ -95,7 +95,7 @@
         (match_operand:SI 1 "register_operand" ""))
    (set (match_operand:SI 2 "loreg_operand" "")
         (match_operand:SI 3 "register_operand" ""))]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
   [(parallel
        [(set (match_dup 2) (match_dup 3))
         (set (match_dup 0) (match_dup 1))])])
@@ -106,7 +106,7 @@
              (match_operand:SI 1 "register_operand" "d"))
         (set (match_operand:SI 2 "hireg_operand" "=h")
              (match_operand:SI 3 "register_operand" "d"))])]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
   "mtcehl  %3, %1"
   [(set_attr "type" "fce")
    (set_attr "mode" "SI")])
@@ -117,7 +117,7 @@
                           (match_operand:SI 3 "register_operand" "d,d,d"))
                  (match_operand:SI 1 "register_operand" "0,d,l")))
    (clobber (reg:SI HI_REGNUM))]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
   "@
    mad     %2, %3
    mtcel%S1 %1\;mad     %2, %3
@@ -130,7 +130,7 @@
                   (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
                            (match_operand:SI 3 "register_operand" "d,d,d"))))
    (clobber (reg:SI HI_REGNUM))]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
   "@
    msb     %2, %3
    mtcel%S1 %1\;msb     %2, %3
@@ -143,7 +143,7 @@
                   (sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))
                   (sign_extend:DI (match_operand:SI 3 "register_operand" "d")))
                  (match_operand:DI 1 "register_operand" "0")))]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
   "mad     %2, %3"
   [(set_attr "mode" "DI")])
 
@@ -153,7 +153,7 @@
                   (zero_extend:DI (match_operand:SI 2 "register_operand" "%d"))
                   (zero_extend:DI (match_operand:SI 3 "register_operand" "d")))
                  (match_operand:DI 1 "register_operand" "0")))]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
   "madu    %2, %3"
   [(set_attr "mode" "DI")])
 
@@ -164,7 +164,7 @@
          (mult:DI
           (sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))
           (sign_extend:DI (match_operand:SI 3 "register_operand" "d")))))]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
   "msb     %2, %3"
   [(set_attr "mode" "DI")])
 
@@ -176,6 +176,6 @@
                    (match_operand:SI 2 "register_operand" "%d"))
                   (zero_extend:DI
                    (match_operand:SI 3 "register_operand" "d")))))]
-  "TARGET_MAC"
+  "TARGET_MAC || TARGET_SCORE7D"
   "msbu    %2, %3"
   [(set_attr "mode" "DI")])
diff --git a/gcc/config/score/misc.md b/gcc/config/score/misc.md
index a4f817040f1..5da7240c687 100644
--- a/gcc/config/score/misc.md
+++ b/gcc/config/score/misc.md
@@ -111,7 +111,7 @@
         (zero_extract (match_operand:SI 1 "memory_operand" "")
                       (match_operand:SI 2 "immediate_operand" "")
                       (match_operand:SI 3 "immediate_operand" "")))]
-  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN"
+  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
 {
   if (mdx_unaligned_load (operands))
     DONE;
@@ -124,7 +124,7 @@
                       (match_operand:SI 1 "immediate_operand" "")
                       (match_operand:SI 2 "immediate_operand" ""))
         (match_operand:SI 3 "register_operand" ""))]
-  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN"
+  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
 {
   if (mdx_unaligned_store (operands))
     DONE;
@@ -137,7 +137,7 @@
         (sign_extract (match_operand:SI 1 "memory_operand" "")
                       (match_operand:SI 2 "immediate_operand" "")
                       (match_operand:SI 3 "immediate_operand" "")))]
-  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN"
+  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
 {
   if (mdx_unaligned_load (operands))
     DONE;
@@ -150,7 +150,7 @@
                    (match_operand:BLK 1 "general_operand"))
               (use (match_operand:SI 2 ""))
               (use (match_operand:SI 3 "const_int_operand"))])]
-  "!TARGET_SCORE5U"
+  "!TARGET_SCORE5U && TARGET_ULS"
 {
   if (mdx_block_move (operands))
     DONE;
@@ -164,7 +164,7 @@
                  (match_operand:SI 2 "const_simm12" "")))
    (set (match_operand:QI 3 "register_operand" "=d")
         (mem:QI (match_dup 1)))]
-  "!TARGET_SCORE5U"
+  ""
   "lbu     %3, [%1]+, %2"
   [(set_attr "type" "load")
    (set_attr "mode" "QI")])
@@ -175,7 +175,7 @@
                  (match_operand:SI 2 "const_simm12" "")))
    (set (match_operand:HI 3 "register_operand" "=d")
         (mem:HI (match_dup 1)))]
-  "!TARGET_SCORE5U"
+  ""
   "lhu     %3, [%1]+, %2"
   [(set_attr "type" "load")
    (set_attr "mode" "HI")])
@@ -186,7 +186,7 @@
                  (match_operand:SI 2 "const_simm12" "")))
    (set (match_operand:SI 3 "register_operand" "=d")
         (mem:SI (match_dup 1)))]
-  "!TARGET_SCORE5U"
+  ""
   "lw      %3, [%1]+, %2"
   [(set_attr "type" "load")
    (set_attr "mode" "SI")])
@@ -197,7 +197,7 @@
                  (match_operand:SI 2 "const_simm12" "")))
    (set (mem:QI (match_dup 1))
         (match_operand:QI 3 "register_operand" "d"))]
-  "!TARGET_SCORE5U"
+  ""
   "sb      %3, [%1]+, %2"
   [(set_attr "type" "store")
    (set_attr "mode" "QI")])
@@ -208,7 +208,7 @@
                  (match_operand:SI 2 "const_simm12" "")))
    (set (mem:HI (match_dup 1))
         (match_operand:HI 3 "register_operand" "d"))]
-  "!TARGET_SCORE5U"
+  ""
   "sh      %3, [%1]+, %2"
   [(set_attr "type" "store")
    (set_attr "mode" "HI")])
@@ -219,7 +219,7 @@
                  (match_operand:SI 2 "const_simm12" "")))
    (set (mem:SI (match_dup 1))
         (match_operand:SI 3 "register_operand" "d"))]
-  "!TARGET_SCORE5U"
+  ""
   "sw      %3, [%1]+, %2"
   [(set_attr "type" "store")
    (set_attr "mode" "SI")])
@@ -231,7 +231,7 @@
    (set (match_operand:QI 3 "register_operand" "=d")
         (mem:QI (plus:SI (match_dup 1)
                          (match_dup 2))))]
-  "!TARGET_SCORE5U"
+  ""
   "lbu     %3, [%1, %2]+"
   [(set_attr "type" "load")
    (set_attr "mode" "QI")])
@@ -243,7 +243,7 @@
    (set (match_operand:HI 3 "register_operand" "=d")
         (mem:HI (plus:SI (match_dup 1)
                          (match_dup 2))))]
-  "!TARGET_SCORE5U"
+  ""
   "lhu     %3, [%1, %2]+"
   [(set_attr "type" "load")
    (set_attr "mode" "HI")])
@@ -255,7 +255,7 @@
    (set (match_operand:SI 3 "register_operand" "=d")
         (mem:SI (plus:SI (match_dup 1)
                          (match_dup 2))))]
-  "!TARGET_SCORE5U"
+  ""
   "lw      %3, [%1, %2]+"
   [(set_attr "type" "load")
    (set_attr "mode" "SI")])
@@ -267,7 +267,7 @@
    (set (mem:QI (plus:SI (match_dup 1)
                          (match_dup 2)))
         (match_operand:QI 3 "register_operand" "d"))]
-  "!TARGET_SCORE5U"
+  ""
   "sb      %3, [%1, %2]+"
   [(set_attr "type" "store")
    (set_attr "mode" "QI")])
@@ -279,7 +279,7 @@
    (set (mem:HI (plus:SI (match_dup 1)
                          (match_dup 2)))
         (match_operand:HI 3 "register_operand" "d"))]
-  "!TARGET_SCORE5U"
+  ""
   "sh      %3, [%1, %2]+"
   [(set_attr "type" "store")
    (set_attr "mode" "HI")])
@@ -291,7 +291,7 @@
    (set (mem:SI (plus:SI (match_dup 1)
                          (match_dup 2)))
         (match_operand:SI 3 "register_operand" "d"))]
-  "!TARGET_SCORE5U"
+  ""
   "sw      %3, [%1, %2]+"
   [(set_attr "type" "store")
    (set_attr "mode" "SI")])
@@ -302,7 +302,7 @@
                  (const_int 4)))
    (set (reg:SI LC_REGNUM)
         (unspec:SI [(mem:BLK (match_dup 1))] LCB))]
-  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN"
+  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
   "lcb     [%1]+"
   [(set_attr "type" "load")
    (set_attr "mode" "SI")])
@@ -316,7 +316,7 @@
                     (reg:SI LC_REGNUM)] LCW))
    (set (reg:SI LC_REGNUM)
         (unspec:SI [(mem:BLK (match_dup 1))] LCB))]
-  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN"
+  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
   "lcw     %2, [%1]+"
   [(set_attr "type" "load")
    (set_attr "mode" "SI")])
@@ -328,7 +328,7 @@
    (set (match_operand:SI 2 "register_operand" "=d")
         (unspec:SI [(mem:BLK (match_dup 1))
                     (reg:SI LC_REGNUM)] LCE))]
-  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN"
+  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
   "lce     %2, [%1]+"
   [(set_attr "type" "load")
    (set_attr "mode" "SI")])
@@ -341,7 +341,7 @@
         (unspec:BLK [(match_operand:SI 2 "register_operand" "d")] SCB))
    (set (reg:SI SC_REGNUM)
         (unspec:SI [(match_dup 2)] SCLC))]
-  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN"
+  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
   "scb     %2, [%1]+"
   [(set_attr "type" "store")
    (set_attr "mode" "SI")])
@@ -355,7 +355,7 @@
                      (reg:SI SC_REGNUM)] SCW))
    (set (reg:SI SC_REGNUM)
         (unspec:SI [(match_dup 2)] SCLC))]
-  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN"
+  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
   "scw     %2, [%1]+"
   [(set_attr "type" "store")
    (set_attr "mode" "SI")])
@@ -366,7 +366,7 @@
                  (const_int 4)))
    (set (mem:BLK (match_dup 1))
         (unspec:BLK [(reg:SI SC_REGNUM)] SCE))]
-  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN"
+  "!TARGET_SCORE5U && !TARGET_LITTLE_ENDIAN && TARGET_ULS"
   "sce     [%1]+"
   [(set_attr "type" "store")
    (set_attr "mode" "SI")])
diff --git a/gcc/config/score/score.h b/gcc/config/score/score.h
index 3fd079221c1..eb3b4f5ecf9 100644
--- a/gcc/config/score/score.h
+++ b/gcc/config/score/score.h
@@ -38,7 +38,9 @@ extern GTY(()) rtx cmp_op1;
 
 #undef ASM_SPEC
 #define ASM_SPEC \
-  "%{!mel:-EB} %{mel:-EL} %{mscore5u:-SCORE5U} %{mscore7:-SCORE7} %{G*}"
+  "%{!mel:-EB} %{mel:-EL} %{mscore5:-SCORE5} %{mscore5u:-SCORE5U} \
+   %{mscore7:%{!mmac:-SCORE7}} %{mscore7:%{mmac:-SCORE7D}} \
+   %{mscore7d:-SCORE7D} %{G*}"
 
 #undef LINK_SPEC
 #define LINK_SPEC                "%{!mel:-EB} %{mel:-EL} %{G*}"
@@ -286,6 +288,16 @@ extern GTY(()) rtx cmp_op1;
   128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,        \
   144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159        }
 
+/* Macro to conditionally modify fixed_regs/call_used_regs.  */
+#define PIC_OFFSET_TABLE_REGNUM          29
+
+#define CONDITIONAL_REGISTER_USAGE                     \
+{                                                      \
+   if (!flag_pic)                                      \
+     fixed_regs[PIC_OFFSET_TABLE_REGNUM] =             \
+     call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0;      \
+}
+
 #define HARD_REGNO_NREGS(REGNO, MODE) \
   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 
@@ -534,7 +546,7 @@ enum reg_class
    If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
    of this macro is to determine whether the space is included in
    `current_function_outgoing_args_size'.  */
-#define OUTGOING_REG_PARM_STACK_SPACE 1
+#define OUTGOING_REG_PARM_STACK_SPACE   1
 
 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
 
diff --git a/gcc/config/score/score.md b/gcc/config/score/score.md
index 63934692638..7d3352947f0 100644
--- a/gcc/config/score/score.md
+++ b/gcc/config/score/score.md
@@ -1511,7 +1511,7 @@
    (use (match_operand 2 "" ""))    ; max iterations
    (use (match_operand 3 "" ""))    ; loop level
    (use (match_operand 4 "" ""))]   ; label
-  ""
+  "!TARGET_NHWLOOP"
   {
     if (INTVAL (operands[3]) > 1)
       FAIL;
@@ -1539,6 +1539,6 @@
                  (const_int -1)))
    (clobber (reg:CC CC_REGNUM))
 ]
-  ""
+  "!TARGET_NHWLOOP"
   "bcnz %1"
   [(set_attr "type" "branch")])
diff --git a/gcc/config/score/score.opt b/gcc/config/score/score.opt
index 38992d191be..419a5458aed 100644
--- a/gcc/config/score/score.opt
+++ b/gcc/config/score/score.opt
@@ -27,10 +27,22 @@ mel
 Target RejectNegative Report Mask(LITTLE_ENDIAN)
 Generate little-endian code
 
+mnhwloop
+Target RejectNegative Report Mask(NHWLOOP)
+Disable bcnz instruction
+
+muls
+Target RejectNegative Report Mask(ULS)
+Enable unaligned load/store instruction
+
 mmac
 Target RejectNegative Report Mask(MAC)
 Enable mac instruction
 
+mscore5
+Target RejectNegative Report Mask(SCORE5)
+Support SCORE 5 ISA
+
 mscore5u
 Target RejectNegative Report Mask(SCORE5U)
 Support SCORE 5U ISA
@@ -39,3 +51,6 @@ mscore7
 Target RejectNegative Report Mask(SCORE7)
 Support SCORE 7 ISA
 
+mscore7d
+Target RejectNegative Report Mask(SCORE7D)
+Support SCORE 7D ISA
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e66977af95f..09f6b67196a 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -709,9 +709,11 @@ See RS/6000 and PowerPC Options.
 -mwarn-framesize  -mwarn-dynamicstack  -mstack-size -mstack-guard}
 
 @emph{Score Options}
-@gccoptlist{-mel -mel @gol
+@gccoptlist{-meb -mel @gol
+-mnhwloop @gol
+-muls @gol
 -mmac @gol
--mscore5u -mscore7}
+-mscore5 -mscore5u -mscore7 -mscore7d}
 
 @emph{SH Options}
 @gccoptlist{-m1  -m2  -m2e  -m3  -m3e @gol
@@ -12924,17 +12926,29 @@ The @var{stack-guard} option can only be used in conjunction with @var{stack-siz
 These options are defined for Score implementations:
 
 @table @gcctabopt
-@item -mel
-@opindex -mel
-Compile code for little endian mode.
-
 @item -meb
 @opindex meb
 Compile code for big endian mode.  This is the default.
 
+@item -mel
+@opindex -mel
+Compile code for little endian mode. 
+
+@item -mnhwloop
+@opindex -mnhwloop
+Disable generate bcnz instruction.
+
+@item -muls
+@opindex -muls
+Enable generate unaligned load and store instruction.
+
 @item -mmac
 @opindex mmac
-Enable the use of multiply-accumulate instructions. Disabled by default.
+Enable the use of multiply-accumulate instructions. Disabled by default. 
+
+@item -mscore5
+@opindex mscore5
+Specify the SCORE5 as the target architecture.
 
 @item -mscore5u
 @opindex mscore5u
@@ -12942,7 +12956,11 @@ Specify the SCORE5U of the target architecture.
 
 @item -mscore7
 @opindex mscore7
-Specify the SCORE7 of the target architecture. This is the default.
+Specify the SCORE7 as the target architecture. This is the default.
+
+@item -mscore7d
+@opindex mscore7d
+Specify the SCORE7D as the target architecture.
 @end table
 
 @node SH Options
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 01bcb59fe49..2c60ace37f4 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -2903,7 +2903,7 @@ cp3 registers.
 cp1 + cp2 + cp3 registers.
 
 @item I
-Unsigned 15 bit integer (in the range 0 to 32767).
+High 16-bit constant (32-bit constant with 16 LSBs zero).
 
 @item J
 Unsigned 5 bit integer (in the range 0 to 31).
@@ -2920,18 +2920,6 @@ Unsigned 14 bit integer (in the range 0 to 16383).
 @item N
 Signed 14 bit integer (in the range @minus{}8192 to 8191).
 
-@item O
-Signed 15 bit integer (in the range @minus{}16384 to 16383).
-
-@item P
-Signed 12 bit integer (in the range @minus{}2048 to 2047).
-
-@item J
-An integer constant with exactly a single bit set.
-
-@item Q
-An integer constant.
-
 @item Z
 Any SYMBOL_REF.
 @end table