diff options
| author | uweigand <uweigand@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-05-09 17:37:42 +0000 |
|---|---|---|
| committer | uweigand <uweigand@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-05-09 17:37:42 +0000 |
| commit | 1ca361fdc5eab22baf4c5eda2686df93de41c5c0 (patch) | |
| tree | bf4487808f8035868c6c1ec52448699ebcd87e1c /gcc | |
| parent | 8e6e481dc5749d0ff94bbec334f623a9dc267dea (diff) | |
| download | gcc-1ca361fdc5eab22baf4c5eda2686df93de41c5c0.tar.gz | |
2005-05-09 Adrian Straetling <straetling@de.ibm.com>
* config/s390/s390.h: Move xxx_REGNUM definitions to s390.md.
* config/s390/s390.md: ("SIBCALL_REGNUM", "BASE_REGNUM",
"RETURN_REGNUM", "CC_REGNUM", "TP_REGNUM"): New constants.
Replace every occurrence of '(reg:<MODE> 33)' by '(reg:<MODE>
CC_REGNUM)'.
("get_tp_64", "get_tp_31", "set_tp_64", "set_tp_31"): Replace
'(reg:<MODE> 36)' by '(reg:<MODE> TP_REGNUM)'.
("*sibcall_br", "*sibcall_value_br"): Replace '(reg:DI 1)' by '(reg:DI
REG_SC)'.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@99459 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 12 | ||||
| -rw-r--r-- | gcc/config/s390/s390.h | 6 | ||||
| -rw-r--r-- | gcc/config/s390/s390.md | 694 |
3 files changed, 368 insertions, 344 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f0a8c6b4e3b..ddc10d75b79 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,17 @@ 2005-05-09 Adrian Straetling <straetling@de.ibm.com> + * config/s390/s390.h: Move xxx_REGNUM definitions to s390.md. + * config/s390/s390.md: ("SIBCALL_REGNUM", "BASE_REGNUM", + "RETURN_REGNUM", "CC_REGNUM", "TP_REGNUM"): New constants. + Replace every occurrence of '(reg:<MODE> 33)' by '(reg:<MODE> + CC_REGNUM)'. + ("get_tp_64", "get_tp_31", "set_tp_64", "set_tp_31"): Replace + '(reg:<MODE> 36)' by '(reg:<MODE> TP_REGNUM)'. + ("*sibcall_br", "*sibcall_value_br"): Replace '(reg:DI 1)' by '(reg:DI + REG_SC)'. + +2005-05-09 Adrian Straetling <straetling@de.ibm.com> + * config/s390/s390.md: ("gf") New mode attribute. ("fixuns_truncdfdi2", "fixuns_truncdfsi2", "fixuns_truncsfdi2", "fixuns_truncsfsi2"): Merge. diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h index 329a7a7f708..06c8bc435d2 100644 --- a/gcc/config/s390/s390.h +++ b/gcc/config/s390/s390.h @@ -253,12 +253,6 @@ if (INTEGRAL_MODE_P (MODE) && \ #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X))) -#define SIBCALL_REGNUM 1 -#define BASE_REGNUM 13 -#define RETURN_REGNUM 14 -#define CC_REGNUM 33 -#define TP_REGNUM 36 - /* Set up fixed registers and calling convention: GPRs 0-5 are always call-clobbered, diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 0d876421003..3feb8c2dfee 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -145,6 +145,24 @@ (UNSPECV_SET_TP 500) ]) +;; +;; Registers +;; + +(define_constants + [ + ; Sibling call register. + (SIBCALL_REGNUM 1) + ; Literal pool base register. + (BASE_REGNUM 13) + ; Return address register. + (RETURN_REGNUM 14) + ; Condition code register. + (CC_REGNUM 33) + ; Thread local storage pointer register. + (TP_REGNUM 36) + ]) + ;; Instruction operand type as used in the Principles of Operation. ;; Used to determine defaults for length and other attribute values. @@ -317,7 +335,7 @@ ;; (define_expand "cmp<mode>" - [(set (reg:CC 33) + [(set (reg:CC CC_REGNUM) (compare:CC (match_operand:GPR 0 "register_operand" "") (match_operand:GPR 1 "general_operand" "")))] "" @@ -328,7 +346,7 @@ }) (define_expand "cmp<mode>" - [(set (reg:CC 33) + [(set (reg:CC CC_REGNUM) (compare:CC (match_operand:FPR 0 "register_operand" "") (match_operand:FPR 1 "general_operand" "")))] "TARGET_HARD_FLOAT" @@ -342,7 +360,7 @@ ; Test-under-Mask instructions (define_insn "*tmqi_mem" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") (match_operand:QI 1 "immediate_operand" "n,n")) (match_operand:QI 2 "immediate_operand" "n,n")))] @@ -353,7 +371,7 @@ [(set_attr "op_type" "SI,SIY")]) (define_insn "*tmdi_reg" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") (match_operand:DI 1 "immediate_operand" "N0HD0,N1HD0,N2HD0,N3HD0")) @@ -369,7 +387,7 @@ [(set_attr "op_type" "RI")]) (define_insn "*tmsi_reg" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) (match_operand:SI 2 "immediate_operand" "n,n")))] @@ -381,7 +399,7 @@ [(set_attr "op_type" "RI")]) (define_insn "*tm<mode>_full" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:HQI 0 "register_operand" "d") (match_operand:HQI 1 "immediate_operand" "n")))] "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))" @@ -392,7 +410,7 @@ ; Load-and-Test instructions (define_insn "*tstdi_sign" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) (const_int 32)) (const_int 32)) (match_operand:DI 1 "const0_operand" ""))) @@ -403,7 +421,7 @@ [(set_attr "op_type" "RRE")]) (define_insn "*tstdi" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "register_operand" "d") (match_operand:DI 1 "const0_operand" ""))) (set (match_operand:DI 2 "register_operand" "=d") @@ -413,7 +431,7 @@ [(set_attr "op_type" "RRE")]) (define_insn "*tstdi_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "register_operand" "d") (match_operand:DI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" @@ -421,7 +439,7 @@ [(set_attr "op_type" "RRE")]) (define_insn "*tstdi_cconly_31" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "register_operand" "d") (match_operand:DI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" @@ -431,7 +449,7 @@ (define_insn "*tstsi" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") (match_operand:SI 1 "const0_operand" ""))) (set (match_operand:SI 2 "register_operand" "=d,d,d") @@ -444,7 +462,7 @@ [(set_attr "op_type" "RR,RS,RSY")]) (define_insn "*tstsi_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") (match_operand:SI 1 "const0_operand" ""))) (clobber (match_scratch:SI 2 "=X,d,d"))] @@ -456,7 +474,7 @@ [(set_attr "op_type" "RR,RS,RSY")]) (define_insn "*tstsi_cconly2" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 0 "register_operand" "d") (match_operand:SI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode)" @@ -464,7 +482,7 @@ [(set_attr "op_type" "RR")]) (define_insn "*tst<mode>CCT" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") (match_operand:HQI 1 "const0_operand" ""))) (set (match_operand:HQI 2 "register_operand" "=d,d,0") @@ -477,7 +495,7 @@ [(set_attr "op_type" "RS,RSY,RI")]) (define_insn "*tsthiCCT_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") (match_operand:HI 1 "const0_operand" ""))) (clobber (match_scratch:HI 2 "=d,d,X"))] @@ -489,7 +507,7 @@ [(set_attr "op_type" "RS,RSY,RI")]) (define_insn "*tstqiCCT_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") (match_operand:QI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCTmode)" @@ -500,7 +518,7 @@ [(set_attr "op_type" "SI,SIY,RI")]) (define_insn "*tst<mode>" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:HQI 0 "s_operand" "Q,S") (match_operand:HQI 1 "const0_operand" ""))) (set (match_operand:HQI 2 "register_operand" "=d,d") @@ -512,7 +530,7 @@ [(set_attr "op_type" "RS,RSY")]) (define_insn "*tst<mode>_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:HQI 0 "s_operand" "Q,S") (match_operand:HQI 1 "const0_operand" ""))) (clobber (match_scratch:HQI 2 "=d,d"))] @@ -526,7 +544,7 @@ ; Compare (equality) instructions (define_insn "*cmpdi_cct" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q") (match_operand:DI 1 "general_operand" "d,K,m,BQ")))] "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" @@ -538,7 +556,7 @@ [(set_attr "op_type" "RRE,RI,RXY,SS")]) (define_insn "*cmpsi_cct" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q") (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))] "s390_match_ccmode (insn, CCTmode)" @@ -554,7 +572,7 @@ ; Compare (signed) instructions (define_insn "*cmpdi_ccs_sign" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) (match_operand:DI 0 "register_operand" "d,d")))] "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" @@ -564,7 +582,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*cmpdi_ccs" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "register_operand" "d,d,d") (match_operand:DI 1 "general_operand" "d,K,m")))] "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" @@ -575,7 +593,7 @@ [(set_attr "op_type" "RRE,RI,RXY")]) (define_insn "*cmpsi_ccs_sign" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) (match_operand:SI 0 "register_operand" "d,d")))] "s390_match_ccmode(insn, CCSRmode)" @@ -585,7 +603,7 @@ [(set_attr "op_type" "RX,RXY")]) (define_insn "*cmpsi_ccs" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 0 "register_operand" "d,d,d,d") (match_operand:SI 1 "general_operand" "d,K,R,T")))] "s390_match_ccmode(insn, CCSmode)" @@ -600,7 +618,7 @@ ; Compare (unsigned) instructions (define_insn "*cmpdi_ccu_zero" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) (match_operand:DI 0 "register_operand" "d,d")))] "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" @@ -610,7 +628,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*cmpdi_ccu" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ") (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))] "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" @@ -622,7 +640,7 @@ [(set_attr "op_type" "RRE,RXY,SS,SS")]) (define_insn "*cmpsi_ccu" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ") (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))] "s390_match_ccmode (insn, CCUmode)" @@ -635,7 +653,7 @@ [(set_attr "op_type" "RR,RX,RXY,SS,SS")]) (define_insn "*cmphi_ccu" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ") (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))] "s390_match_ccmode (insn, CCUmode) @@ -648,7 +666,7 @@ [(set_attr "op_type" "RS,RSY,SS,SS")]) (define_insn "*cmpqi_ccu" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] "s390_match_ccmode (insn, CCUmode) @@ -666,7 +684,7 @@ ; Block compare (CLC) instruction patterns. (define_insn "*clc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:BLK 0 "memory_operand" "Q") (match_operand:BLK 1 "memory_operand" "Q"))) (use (match_operand 2 "const_int_operand" "n"))] @@ -676,7 +694,7 @@ [(set_attr "op_type" "SS")]) (define_split - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand 0 "memory_operand" "") (match_operand 1 "memory_operand" "")))] "reload_completed @@ -700,7 +718,7 @@ ; (DF|SF) instructions (define_insn "*cmp<mode>_ccs_0" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:FPR 0 "register_operand" "f") (match_operand:FPR 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" @@ -709,7 +727,7 @@ (set_attr "type" "fsimp<mode>")]) (define_insn "*cmp<mode>_ccs_0_ibm" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:FPR 0 "register_operand" "f") (match_operand:FPR 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" @@ -718,7 +736,7 @@ (set_attr "type" "fsimp<mode>")]) (define_insn "*cmp<mode>_ccs" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:FPR 0 "register_operand" "f,f") (match_operand:FPR 1 "general_operand" "f,R")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" @@ -729,7 +747,7 @@ (set_attr "type" "fsimp<mode>")]) (define_insn "*cmp<mode>_ccs_ibm" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:FPR 0 "register_operand" "f,f") (match_operand:FPR 1 "general_operand" "f,R")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" @@ -999,7 +1017,7 @@ [(parallel [(set (match_operand:DI 0 "register_operand" "") (match_operand:QI 1 "address_operand" "")) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "TARGET_64BIT && preferred_la_operand_p (operands[1], const0_rtx)" [(set (match_dup 0) (match_dup 1))] @@ -1012,7 +1030,7 @@ [(set (match_dup 0) (plus:DI (match_dup 0) (match_operand:DI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "TARGET_64BIT && !reg_overlap_mentioned_p (operands[0], operands[2]) && preferred_la_operand_p (operands[1], operands[2])" @@ -1128,7 +1146,7 @@ [(parallel [(set (match_operand:SI 0 "register_operand" "") (match_operand:QI 1 "address_operand" "")) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "!TARGET_64BIT && preferred_la_operand_p (operands[1], const0_rtx)" [(set (match_dup 0) (match_dup 1))] @@ -1141,7 +1159,7 @@ [(set (match_dup 0) (plus:SI (match_dup 0) (match_operand:SI 2 "nonmemory_operand" ""))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "!TARGET_64BIT && !reg_overlap_mentioned_p (operands[0], operands[2]) && preferred_la_operand_p (operands[1], operands[2])" @@ -1163,7 +1181,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (and:SI (match_operand:QI 1 "address_operand" "p") (const_int 2147483647))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT" "#" "&& reload_completed" @@ -1310,7 +1328,7 @@ (define_insn "*movstricthi" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) (match_operand:HI 1 "memory_operand" "Q,S")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "@ icm\t%0,3,%S1 @@ -1735,11 +1753,11 @@ (reg:QI 0) (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) (clobber (scratch:P)) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel [(set (match_operand:P 0 "register_operand" "") (minus:P (match_dup 4) (match_dup 5))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "" { operands[4] = gen_reg_rtx (Pmode); @@ -1755,7 +1773,7 @@ (reg:QI 0) (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) (clobber (match_scratch:P 1 "=a")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "srst\t%0,%1\;jo\t.-4" [(set_attr "length" "8") @@ -1848,7 +1866,7 @@ (match_operand:BLK 1 "memory_operand" "")) (use (match_operand 2 "general_operand" "")) (use (match_dup 3)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "" { enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; @@ -1880,7 +1898,7 @@ (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))) (use (match_dup 2)) (use (match_dup 3)) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "mvcle\t%0,%1,0\;jo\t.-4" [(set_attr "length" "8") @@ -1893,7 +1911,7 @@ (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))) (use (match_dup 2)) (use (match_dup 3)) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT" "mvcle\t%0,%1,0\;jo\t.-4" [(set_attr "length" "8") @@ -1921,7 +1939,7 @@ (use (match_operand 1 "nonmemory_operand" "")) (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) (clobber (match_dup 2)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "" "operands[2] = gen_rtx_SCRATCH (Pmode);") @@ -1931,7 +1949,7 @@ (use (match_operand 1 "nonmemory_operand" "n,a,a")) (use (match_operand 2 "immediate_operand" "X,R,X")) (clobber (match_scratch 3 "=X,X,&a")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) && GET_MODE (operands[3]) == Pmode" "#" @@ -1943,12 +1961,12 @@ (use (match_operand 1 "const_int_operand" "")) (use (match_operand 2 "immediate_operand" "")) (clobber (scratch)) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (const_int 0)) (use (match_dup 1)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") (define_split @@ -1957,14 +1975,14 @@ (use (match_operand 1 "register_operand" "")) (use (match_operand 2 "memory_operand" "")) (clobber (scratch)) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(unspec [(match_dup 1) (match_dup 2) (const_int 0)] UNSPEC_EXECUTE) (set (match_dup 0) (const_int 0)) (use (const_int 1)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "") (define_split @@ -1973,7 +1991,7 @@ (use (match_operand 1 "register_operand" "")) (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) (clobber (match_operand 2 "register_operand" "")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed && TARGET_CPU_ZARCH" [(set (match_dup 2) (label_ref (match_dup 3))) (parallel @@ -1981,7 +1999,7 @@ (label_ref (match_dup 3))] UNSPEC_EXECUTE) (set (match_dup 0) (const_int 0)) (use (const_int 1)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "operands[3] = gen_label_rtx ();") ; Clear a block of arbitrary length. @@ -1993,7 +2011,7 @@ (const_int 0)) (use (match_operand 1 "general_operand" "")) (use (match_dup 2)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "" { enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; @@ -2019,7 +2037,7 @@ (const_int 0)) (use (match_dup 2)) (use (match_operand:TI 1 "register_operand" "d")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "mvcle\t%0,%1,0\;jo\t.-4" [(set_attr "length" "8") @@ -2031,7 +2049,7 @@ (const_int 0)) (use (match_dup 2)) (use (match_operand:DI 1 "register_operand" "d")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT" "mvcle\t%0,%1,0\;jo\t.-4" [(set_attr "length" "8") @@ -2056,7 +2074,7 @@ (define_expand "cmpmem_short" [(parallel - [(set (reg:CCU 33) + [(set (reg:CCU CC_REGNUM) (compare:CCU (match_operand:BLK 0 "memory_operand" "") (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "nonmemory_operand" "")) @@ -2066,7 +2084,7 @@ "operands[3] = gen_rtx_SCRATCH (Pmode);") (define_insn "*cmpmem_short" - [(set (reg:CCU 33) + [(set (reg:CCU CC_REGNUM) (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q") (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))) (use (match_operand 2 "nonmemory_operand" "n,a,a")) @@ -2078,7 +2096,7 @@ [(set_attr "type" "cs")]) (define_split - [(set (reg:CCU 33) + [(set (reg:CCU CC_REGNUM) (compare:CCU (match_operand:BLK 0 "memory_operand" "") (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "const_int_operand" "")) @@ -2086,12 +2104,12 @@ (clobber (scratch))] "reload_completed" [(parallel - [(set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) + [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) (use (match_dup 2))])] "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") (define_split - [(set (reg:CCU 33) + [(set (reg:CCU CC_REGNUM) (compare:CCU (match_operand:BLK 0 "memory_operand" "") (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "register_operand" "")) @@ -2101,12 +2119,12 @@ [(parallel [(unspec [(match_dup 2) (match_dup 3) (const_int 0)] UNSPEC_EXECUTE) - (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) + (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) (use (const_int 1))])] "") (define_split - [(set (reg:CCU 33) + [(set (reg:CCU CC_REGNUM) (compare:CCU (match_operand:BLK 0 "memory_operand" "") (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "register_operand" "")) @@ -2117,7 +2135,7 @@ (parallel [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) (label_ref (match_dup 4))] UNSPEC_EXECUTE) - (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) + (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) (use (const_int 1))])] "operands[4] = gen_label_rtx ();") @@ -2127,7 +2145,7 @@ [(parallel [(clobber (match_dup 2)) (clobber (match_dup 3)) - (set (reg:CCU 33) + (set (reg:CCU CC_REGNUM) (compare:CCU (match_operand:BLK 0 "memory_operand" "") (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "general_operand" "")) @@ -2159,7 +2177,7 @@ (define_insn "*cmpmem_long_64" [(clobber (match_operand:TI 0 "register_operand" "=d")) (clobber (match_operand:TI 1 "register_operand" "=d")) - (set (reg:CCU 33) + (set (reg:CCU CC_REGNUM) (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))) (use (match_dup 2)) @@ -2172,7 +2190,7 @@ (define_insn "*cmpmem_long_31" [(clobber (match_operand:DI 0 "register_operand" "=d")) (clobber (match_operand:DI 1 "register_operand" "=d")) - (set (reg:CCU 33) + (set (reg:CCU CC_REGNUM) (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))) (use (match_dup 2)) @@ -2189,17 +2207,17 @@ [(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] UNSPEC_CMPINT)) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "#" "reload_completed" [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) (parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) - (clobber (reg:CC 33))])]) + (clobber (reg:CC CC_REGNUM))])]) (define_insn_and_split "*cmpint_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] UNSPEC_CMPINT) (const_int 0))) @@ -2222,17 +2240,17 @@ [(set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] UNSPEC_CMPINT))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "#" "&& reload_completed" [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) (parallel [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) - (clobber (reg:CC 33))])]) + (clobber (reg:CC CC_REGNUM))])]) (define_insn_and_split "*cmpint_sign_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:DI (ashift:DI (subreg:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] UNSPEC_CMPINT) 0) @@ -2262,7 +2280,7 @@ (define_insn "*sethigh<mode>si" [(set (match_operand:SI 0 "register_operand" "=d,d") (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "@ icm\t%0,<icm_hi>,%S1 @@ -2272,7 +2290,7 @@ (define_insn "*sethighqidi_64" [(set (match_operand:DI 0 "register_operand" "=d") (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "icmh\t%0,8,%S1" [(set_attr "op_type" "RSY")]) @@ -2280,7 +2298,7 @@ (define_insn "*sethighqidi_31" [(set (match_operand:DI 0 "register_operand" "=d,d") (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT" "@ icm\t%0,8,%S1 @@ -2292,14 +2310,14 @@ (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") (match_operand 2 "const_int_operand" "n") (const_int 0))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" "#" "&& reload_completed" [(parallel [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] { operands[2] = GEN_INT (32 - INTVAL (operands[2])); @@ -2311,14 +2329,14 @@ (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") (match_operand 2 "const_int_operand" "n") (const_int 0))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" "#" "&& reload_completed" [(parallel [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] { operands[2] = GEN_INT (32 - INTVAL (operands[2])); @@ -2401,16 +2419,16 @@ (define_insn_and_split "*extendqidi2_short_displ" [(set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (match_operand:QI 1 "s_operand" "Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT" "#" "&& reload_completed" [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "") ; @@ -2451,16 +2469,16 @@ (define_insn_and_split "*extendqisi2_short_displ" [(set (match_operand:SI 0 "register_operand" "=d") (sign_extend:SI (match_operand:QI 1 "s_operand" "Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_LONG_DISPLACEMENT" "#" "&& reload_completed" [(parallel [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "") ; @@ -2549,7 +2567,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) (const_int 2147483647))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "#" "&& reload_completed" @@ -2582,7 +2600,7 @@ [(set (match_operand:GPR 0 "register_operand" "") (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "") (const_int 2147483647))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT && reload_completed" [(set (match_dup 0) (and:GPR (match_dup 1) @@ -2616,14 +2634,14 @@ (define_insn_and_split "*zero_extendhisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH" "#" "&& reload_completed" [(set (match_dup 0) (const_int 0)) (parallel [(set (strict_low_part (match_dup 2)) (match_dup 1)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "operands[2] = gen_lowpart (HImode, operands[0]);") (define_insn_and_split "*zero_extendqisi2_31" @@ -2719,7 +2737,7 @@ [(set (match_operand:GPR 0 "register_operand" "=d") (fix:GPR (match_operand:FPR 1 "register_operand" "f"))) (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "c<GPR:gf><FPR:de>br\t%0,%h2,%1" [(set_attr "op_type" "RRE") @@ -2761,7 +2779,7 @@ (use (match_operand:DI 2 "immediate_operand" "m")) (use (match_operand:DI 3 "immediate_operand" "m")) (use (match_operand:BLK 4 "memory_operand" "m")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" { output_asm_insn ("sd\t%1,%2", operands); @@ -2843,7 +2861,7 @@ (float:DF (match_operand:SI 1 "register_operand" "d"))) (use (match_operand:DI 2 "immediate_operand" "m")) (use (match_operand:BLK 3 "memory_operand" "m")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" { output_asm_insn ("st\t%1,%N3", operands); @@ -2937,7 +2955,7 @@ (define_insn "extendsfdf2_ibm" [(set (match_operand:DF 0 "register_operand" "=f,f") (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ sdr\t%0,%0\;ler\t%0,%1 @@ -2965,19 +2983,19 @@ [(set (match_operand:TI 0 "register_operand" "=&d") (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "general_operand" "do") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "#" "&& reload_completed" [(parallel - [(set (reg:CCL1 33) + [(set (reg:CCL1 CC_REGNUM) (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) (match_dup 7))) (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) (parallel [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5)) - (ltu:DI (reg:CCL1 33) (const_int 0)))) - (clobber (reg:CC 33))])] + (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)))) + (clobber (reg:CC CC_REGNUM))])] "operands[3] = operand_subword (operands[0], 0, 0, TImode); operands[4] = operand_subword (operands[1], 0, 0, TImode); operands[5] = operand_subword (operands[2], 0, 0, TImode); @@ -2993,7 +3011,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d") (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) (match_operand:DI 1 "register_operand" "0,0"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "@ agfr\t%0,%2 @@ -3001,7 +3019,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_zero_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) (match_operand:DI 1 "register_operand" "0,0")) (const_int 0))) @@ -3014,7 +3032,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_zero_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) (match_operand:DI 1 "register_operand" "0,0")) (const_int 0))) @@ -3029,7 +3047,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d") (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) (match_operand:DI 1 "register_operand" "0,0"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "@ algfr\t%0,%2 @@ -3037,7 +3055,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_imm_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") (match_operand:DI 2 "const_int_operand" "K")) (const_int 0))) @@ -3050,7 +3068,7 @@ [(set_attr "op_type" "RI")]) (define_insn "*adddi3_carry1_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (match_dup 1))) @@ -3063,7 +3081,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_carry1_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (match_dup 1))) @@ -3075,7 +3093,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_carry2_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (match_dup 2))) @@ -3088,7 +3106,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_carry2_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (match_dup 2))) @@ -3100,7 +3118,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -3113,7 +3131,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -3125,7 +3143,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_cconly2" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) (clobber (match_scratch:DI 0 "=d,d"))] @@ -3139,7 +3157,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d,d") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") (match_operand:DI 2 "general_operand" "d,K,m") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "@ agr\t%0,%2 @@ -3151,19 +3169,19 @@ [(set (match_operand:DI 0 "register_operand" "=&d") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") (match_operand:DI 2 "general_operand" "do") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT && TARGET_CPU_ZARCH" "#" "&& reload_completed" [(parallel - [(set (reg:CCL1 33) + [(set (reg:CCL1 CC_REGNUM) (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) (match_dup 7))) (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) (parallel [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) - (ltu:SI (reg:CCL1 33) (const_int 0)))) - (clobber (reg:CC 33))])] + (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)))) + (clobber (reg:CC CC_REGNUM))])] "operands[3] = operand_subword (operands[0], 0, 0, DImode); operands[4] = operand_subword (operands[1], 0, 0, DImode); operands[5] = operand_subword (operands[2], 0, 0, DImode); @@ -3175,25 +3193,25 @@ [(set (match_operand:DI 0 "register_operand" "=&d") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") (match_operand:DI 2 "general_operand" "do") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_CPU_ZARCH" "#" "&& reload_completed" [(parallel [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel - [(set (reg:CCL1 33) + [(set (reg:CCL1 CC_REGNUM) (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) (match_dup 7))) (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) (set (pc) - (if_then_else (ltu (reg:CCL1 33) (const_int 0)) + (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) (pc) (label_ref (match_dup 9)))) (parallel [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (match_dup 9)] "operands[3] = operand_subword (operands[0], 0, 0, DImode); operands[4] = operand_subword (operands[1], 0, 0, DImode); @@ -3208,7 +3226,7 @@ [(set (match_operand:DI 0 "register_operand" "") (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "general_operand" ""))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "" "") @@ -3217,7 +3235,7 @@ ; (define_insn "*addsi3_imm_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") (match_operand:SI 2 "const_int_operand" "K")) (const_int 0))) @@ -3229,7 +3247,7 @@ [(set_attr "op_type" "RI")]) (define_insn "*addsi3_carry1_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 1))) @@ -3243,7 +3261,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_carry1_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 1))) @@ -3256,7 +3274,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_carry2_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 2))) @@ -3270,7 +3288,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_carry2_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 2))) @@ -3283,7 +3301,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -3297,7 +3315,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -3310,7 +3328,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_cconly2" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) (clobber (match_scratch:SI 0 "=d,d,d"))] @@ -3325,7 +3343,7 @@ [(set (match_operand:SI 0 "register_operand" "=d,d") (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) (match_operand:SI 1 "register_operand" "0,0"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "@ ah\t%0,%2 @@ -3336,7 +3354,7 @@ [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:SI 2 "general_operand" "d,K,R,T"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "@ ar\t%0,%2 @@ -3354,7 +3372,7 @@ [(set (match_operand:FPR 0 "register_operand" "=f,f") (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") (match_operand:FPR 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_FLOAT" "") @@ -3362,7 +3380,7 @@ [(set (match_operand:FPR 0 "register_operand" "=f,f") (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") (match_operand:FPR 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ a<de>br\t%0,%2 @@ -3371,7 +3389,7 @@ (set_attr "type" "fsimp<mode>")]) (define_insn "*add<mode>3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") (match_operand:FPR 2 "general_operand" "f,R")) (match_operand:FPR 3 "const0_operand" ""))) @@ -3385,7 +3403,7 @@ (set_attr "type" "fsimp<mode>")]) (define_insn "*add<mode>3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") (match_operand:FPR 2 "general_operand" "f,R")) (match_operand:FPR 3 "const0_operand" ""))) @@ -3401,7 +3419,7 @@ [(set (match_operand:FPR 0 "register_operand" "=f,f") (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") (match_operand:FPR 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ a<de>r\t%0,%2 @@ -3422,19 +3440,19 @@ [(set (match_operand:TI 0 "register_operand" "=&d") (minus:TI (match_operand:TI 1 "register_operand" "0") (match_operand:TI 2 "general_operand" "do") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "#" "&& reload_completed" [(parallel - [(set (reg:CCL2 33) + [(set (reg:CCL2 CC_REGNUM) (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) (match_dup 7))) (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) (parallel [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) - (gtu:DI (reg:CCL2 33) (const_int 0)))) - (clobber (reg:CC 33))])] + (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) + (clobber (reg:CC CC_REGNUM))])] "operands[3] = operand_subword (operands[0], 0, 0, TImode); operands[4] = operand_subword (operands[1], 0, 0, TImode); operands[5] = operand_subword (operands[2], 0, 0, TImode); @@ -3450,7 +3468,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d") (minus:DI (match_operand:DI 1 "register_operand" "0,0") (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "@ sgfr\t%0,%2 @@ -3458,7 +3476,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_zero_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) (const_int 0))) @@ -3471,7 +3489,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_zero_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) (const_int 0))) @@ -3486,7 +3504,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d") (minus:DI (match_operand:DI 1 "register_operand" "0,0") (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "@ slgfr\t%0,%2 @@ -3494,7 +3512,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_borrow_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m")) (match_dup 1))) @@ -3507,7 +3525,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_borrow_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m")) (match_dup 1))) @@ -3519,7 +3537,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -3532,7 +3550,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_cc2" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m"))) (set (match_operand:DI 0 "register_operand" "=d,d") @@ -3544,7 +3562,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -3556,7 +3574,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_cconly2" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m"))) (clobber (match_scratch:DI 0 "=d,d"))] @@ -3570,7 +3588,7 @@ [(set (match_operand:DI 0 "register_operand" "=d,d") (minus:DI (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "@ sgr\t%0,%2 @@ -3581,19 +3599,19 @@ [(set (match_operand:DI 0 "register_operand" "=&d") (minus:DI (match_operand:DI 1 "register_operand" "0") (match_operand:DI 2 "general_operand" "do") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT && TARGET_CPU_ZARCH" "#" "&& reload_completed" [(parallel - [(set (reg:CCL2 33) + [(set (reg:CCL2 CC_REGNUM) (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) (match_dup 7))) (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) (parallel [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) - (gtu:SI (reg:CCL2 33) (const_int 0)))) - (clobber (reg:CC 33))])] + (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) + (clobber (reg:CC CC_REGNUM))])] "operands[3] = operand_subword (operands[0], 0, 0, DImode); operands[4] = operand_subword (operands[1], 0, 0, DImode); operands[5] = operand_subword (operands[2], 0, 0, DImode); @@ -3605,25 +3623,25 @@ [(set (match_operand:DI 0 "register_operand" "=&d") (minus:DI (match_operand:DI 1 "register_operand" "0") (match_operand:DI 2 "general_operand" "do") ) ) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_CPU_ZARCH" "#" "&& reload_completed" [(parallel [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel - [(set (reg:CCL2 33) + [(set (reg:CCL2 CC_REGNUM) (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) (match_dup 7))) (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) (set (pc) - (if_then_else (gtu (reg:CCL2 33) (const_int 0)) + (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) (pc) (label_ref (match_dup 9)))) (parallel [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (match_dup 9)] "operands[3] = operand_subword (operands[0], 0, 0, DImode); operands[4] = operand_subword (operands[1], 0, 0, DImode); @@ -3638,7 +3656,7 @@ [(set (match_operand:DI 0 "register_operand" "") (minus:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "general_operand" ""))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "" "") @@ -3647,7 +3665,7 @@ ; (define_insn "*subsi3_borrow_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 1))) @@ -3661,7 +3679,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*subsi3_borrow_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 1))) @@ -3674,7 +3692,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*subsi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -3688,7 +3706,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*subsi3_cc2" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 1 "register_operand" "0,0,0") (match_operand:SI 2 "general_operand" "d,R,T"))) (set (match_operand:SI 0 "register_operand" "=d,d,d") @@ -3701,7 +3719,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*subsi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -3714,7 +3732,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*subsi3_cconly2" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (match_operand:SI 1 "register_operand" "0,0,0") (match_operand:SI 2 "general_operand" "d,R,T"))) (clobber (match_scratch:SI 0 "=d,d,d"))] @@ -3729,7 +3747,7 @@ [(set (match_operand:SI 0 "register_operand" "=d,d") (minus:SI (match_operand:SI 1 "register_operand" "0,0") (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "@ sh\t%0,%2 @@ -3740,7 +3758,7 @@ [(set (match_operand:SI 0 "register_operand" "=d,d,d") (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") (match_operand:SI 2 "general_operand" "d,R,T"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "@ sr\t%0,%2 @@ -3758,7 +3776,7 @@ [(set (match_operand:FPR 0 "register_operand" "=f,f") (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") (match_operand:FPR 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_FLOAT" "") @@ -3766,7 +3784,7 @@ [(set (match_operand:FPR 0 "register_operand" "=f,f") (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") (match_operand:FPR 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ s<de>br\t%0,%2 @@ -3775,7 +3793,7 @@ (set_attr "type" "fsimp<mode>")]) (define_insn "*sub<mode>3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0") (match_operand:FPR 2 "general_operand" "f,R")) (match_operand:FPR 3 "const0_operand" ""))) @@ -3789,7 +3807,7 @@ (set_attr "type" "fsimp<mode>")]) (define_insn "*sub<mode>3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0") (match_operand:FPR 2 "general_operand" "f,R")) (match_operand:FPR 3 "const0_operand" ""))) @@ -3805,7 +3823,7 @@ [(set (match_operand:FPR 0 "register_operand" "=f,f") (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") (match_operand:FPR 2 "general_operand" "f,R"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ s<de>r\t%0,%2 @@ -3823,7 +3841,7 @@ ; (define_insn "*add<mode>3_alc_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0") (match_operand:GPR 2 "general_operand" "d,m")) @@ -3842,7 +3860,7 @@ (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0") (match_operand:GPR 2 "general_operand" "d,m")) (match_operand:GPR 3 "s390_alc_comparison" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_CPU_ZARCH" "@ alc<g>r\t%0,%2 @@ -3850,7 +3868,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*sub<mode>3_slb_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") (match_operand:GPR 2 "general_operand" "d,m")) @@ -3869,7 +3887,7 @@ (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") (match_operand:GPR 2 "general_operand" "d,m")) (match_operand:GPR 3 "s390_slb_comparison" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_CPU_ZARCH" "@ slb<g>r\t%0,%2 @@ -3894,7 +3912,7 @@ (define_insn_and_split "*scond<mode>" [(set (match_operand:GPR 0 "register_operand" "=&d") (match_operand:GPR 1 "s390_alc_comparison" "")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_CPU_ZARCH" "#" "&& reload_completed" @@ -3902,13 +3920,13 @@ (parallel [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0)) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "") (define_insn_and_split "*scond<mode>_neg" [(set (match_operand:GPR 0 "register_operand" "=&d") (match_operand:GPR 1 "s390_slb_comparison" "")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_CPU_ZARCH" "#" "&& reload_completed" @@ -3916,10 +3934,10 @@ (parallel [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) (match_dup 1))) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel [(set (match_dup 0) (neg:GPR (match_dup 0))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "") @@ -4559,7 +4577,7 @@ ; (define_insn "*anddi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -4572,7 +4590,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*anddi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -4591,7 +4609,7 @@ "%d,o,0,0,0,0,0,0,0,0") (match_operand:DI 2 "general_operand" "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT && s390_logical_operator_ok_p (operands)" "@ # @@ -4609,18 +4627,18 @@ (define_split [(set (match_operand:DI 0 "s_operand" "") (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") (define_expand "anddi3" [(set (match_operand:DI 0 "nonimmediate_operand" "") (and:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "general_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "s390_expand_logical_operator (AND, DImode, operands); DONE;") @@ -4629,7 +4647,7 @@ ; (define_insn "*andsi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -4643,7 +4661,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*andsi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -4663,7 +4681,7 @@ "%d,o,0,0,0,0,0,0,0") (match_operand:SI 2 "general_operand" "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ # @@ -4681,7 +4699,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ nr\t%0,%2 @@ -4693,18 +4711,18 @@ (define_split [(set (match_operand:SI 0 "s_operand" "") (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") (define_expand "andsi3" [(set (match_operand:SI 0 "nonimmediate_operand" "") (and:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:SI 2 "general_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "s390_expand_logical_operator (AND, SImode, operands); DONE;") @@ -4716,7 +4734,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ nr\t%0,%2 @@ -4729,7 +4747,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ nr\t%0,%2 @@ -4740,18 +4758,18 @@ (define_split [(set (match_operand:HI 0 "s_operand" "") (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") (define_expand "andhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "") (and:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:HI 2 "general_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "s390_expand_logical_operator (AND, HImode, operands); DONE;") @@ -4763,7 +4781,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ nr\t%0,%2 @@ -4777,7 +4795,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") (match_operand:QI 2 "general_operand" "d,n,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ nr\t%0,%2 @@ -4789,7 +4807,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "") (and:QI (match_operand:QI 1 "nonimmediate_operand" "") (match_operand:QI 2 "general_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "s390_expand_logical_operator (AND, QImode, operands); DONE;") @@ -4802,7 +4820,7 @@ (and:BLK (match_dup 0) (match_operand:BLK 1 "memory_operand" "Q"))) (use (match_operand 2 "const_int_operand" "n")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "nc\t%O0(%2,%R0),%S1" [(set_attr "op_type" "SS")]) @@ -4811,14 +4829,14 @@ [(set (match_operand 0 "memory_operand" "") (and (match_dup 0) (match_operand 1 "memory_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed && GET_MODE (operands[0]) == GET_MODE (operands[1]) && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" [(parallel [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) (use (match_dup 2)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] { operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); operands[0] = adjust_address (operands[0], BLKmode, 0); @@ -4831,20 +4849,20 @@ (and:BLK (match_dup 0) (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "const_int_operand" "")) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel [(set (match_operand:BLK 3 "memory_operand" "") (and:BLK (match_dup 3) (match_operand:BLK 4 "memory_operand" ""))) (use (match_operand 5 "const_int_operand" "")) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) (use (match_dup 8)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") @@ -4859,7 +4877,7 @@ ; (define_insn "*iordi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -4872,7 +4890,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*iordi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -4888,7 +4906,7 @@ (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") (match_operand:DI 2 "general_operand" "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT && s390_logical_operator_ok_p (operands)" "@ oihh\t%0,%i2 @@ -4904,18 +4922,18 @@ (define_split [(set (match_operand:DI 0 "s_operand" "") (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") (define_expand "iordi3" [(set (match_operand:DI 0 "nonimmediate_operand" "") (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "general_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "s390_expand_logical_operator (IOR, DImode, operands); DONE;") @@ -4924,7 +4942,7 @@ ; (define_insn "*iorsi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -4938,7 +4956,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*iorsi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -4954,7 +4972,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q") (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0") (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ oilh\t%0,%i2 @@ -4970,7 +4988,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ or\t%0,%2 @@ -4982,18 +5000,18 @@ (define_split [(set (match_operand:SI 0 "s_operand" "") (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") (define_expand "iorsi3" [(set (match_operand:SI 0 "nonimmediate_operand" "") (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:SI 2 "general_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "s390_expand_logical_operator (IOR, SImode, operands); DONE;") @@ -5005,7 +5023,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ or\t%0,%2 @@ -5018,7 +5036,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ or\t%0,%2 @@ -5029,18 +5047,18 @@ (define_split [(set (match_operand:HI 0 "s_operand" "") (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") (define_expand "iorhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "") (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:HI 2 "general_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "s390_expand_logical_operator (IOR, HImode, operands); DONE;") @@ -5052,7 +5070,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ or\t%0,%2 @@ -5066,7 +5084,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") (match_operand:QI 2 "general_operand" "d,n,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" "@ or\t%0,%2 @@ -5078,7 +5096,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "") (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") (match_operand:QI 2 "general_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "s390_expand_logical_operator (IOR, QImode, operands); DONE;") @@ -5091,7 +5109,7 @@ (ior:BLK (match_dup 0) (match_operand:BLK 1 "memory_operand" "Q"))) (use (match_operand 2 "const_int_operand" "n")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "oc\t%O0(%2,%R0),%S1" [(set_attr "op_type" "SS")]) @@ -5100,14 +5118,14 @@ [(set (match_operand 0 "memory_operand" "") (ior (match_dup 0) (match_operand 1 "memory_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed && GET_MODE (operands[0]) == GET_MODE (operands[1]) && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" [(parallel [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) (use (match_dup 2)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] { operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); operands[0] = adjust_address (operands[0], BLKmode, 0); @@ -5120,20 +5138,20 @@ (ior:BLK (match_dup 0) (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "const_int_operand" "")) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel [(set (match_operand:BLK 3 "memory_operand" "") (ior:BLK (match_dup 3) (match_operand:BLK 4 "memory_operand" ""))) (use (match_operand 5 "const_int_operand" "")) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) (use (match_dup 8)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") @@ -5148,7 +5166,7 @@ ; (define_insn "*xordi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -5161,7 +5179,7 @@ [(set_attr "op_type" "RRE,RXY")]) (define_insn "*xordi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -5176,7 +5194,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q") (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT && s390_logical_operator_ok_p (operands)" "@ xgr\t%0,%2 @@ -5188,18 +5206,18 @@ (define_split [(set (match_operand:DI 0 "s_operand" "") (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") (define_expand "xordi3" [(set (match_operand:DI 0 "nonimmediate_operand" "") (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") (match_operand:DI 2 "general_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "s390_expand_logical_operator (XOR, DImode, operands); DONE;") @@ -5208,7 +5226,7 @@ ; (define_insn "*xorsi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -5222,7 +5240,7 @@ [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*xorsi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) @@ -5238,7 +5256,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q") (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "s390_logical_operator_ok_p (operands)" "@ xr\t%0,%2 @@ -5251,18 +5269,18 @@ (define_split [(set (match_operand:SI 0 "s_operand" "") (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") (define_expand "xorsi3" [(set (match_operand:SI 0 "nonimmediate_operand" "") (xor:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:SI 2 "general_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "s390_expand_logical_operator (XOR, SImode, operands); DONE;") @@ -5274,7 +5292,7 @@ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "s390_logical_operator_ok_p (operands)" "@ xr\t%0,%2 @@ -5285,18 +5303,18 @@ (define_split [(set (match_operand:HI 0 "s_operand" "") (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed" [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") (define_expand "xorhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "") (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") (match_operand:HI 2 "general_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "s390_expand_logical_operator (XOR, HImode, operands); DONE;") @@ -5308,7 +5326,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q") (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:QI 2 "general_operand" "d,n,n,Q"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "s390_logical_operator_ok_p (operands)" "@ xr\t%0,%2 @@ -5321,7 +5339,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "") (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") (match_operand:QI 2 "general_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "s390_expand_logical_operator (XOR, QImode, operands); DONE;") @@ -5334,7 +5352,7 @@ (xor:BLK (match_dup 0) (match_operand:BLK 1 "memory_operand" "Q"))) (use (match_operand 2 "const_int_operand" "n")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "xc\t%O0(%2,%R0),%S1" [(set_attr "op_type" "SS")]) @@ -5343,14 +5361,14 @@ [(set (match_operand 0 "memory_operand" "") (xor (match_dup 0) (match_operand 1 "memory_operand" ""))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "reload_completed && GET_MODE (operands[0]) == GET_MODE (operands[1]) && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" [(parallel [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) (use (match_dup 2)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] { operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); operands[0] = adjust_address (operands[0], BLKmode, 0); @@ -5363,20 +5381,20 @@ (xor:BLK (match_dup 0) (match_operand:BLK 1 "memory_operand" ""))) (use (match_operand 2 "const_int_operand" "")) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel [(set (match_operand:BLK 3 "memory_operand" "") (xor:BLK (match_dup 3) (match_operand:BLK 4 "memory_operand" ""))) (use (match_operand 5 "const_int_operand" "")) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[3], operands[2]) && s390_offset_p (operands[1], operands[4], operands[2]) && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" [(parallel [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) (use (match_dup 8)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") @@ -5389,7 +5407,7 @@ [(set (match_operand:BLK 0 "memory_operand" "=Q") (const_int 0)) (use (match_operand 1 "const_int_operand" "n")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" "xc\t%O0(%1,%R0),%S0" [(set_attr "op_type" "SS")]) @@ -5399,18 +5417,18 @@ [(set (match_operand:BLK 0 "memory_operand" "") (const_int 0)) (use (match_operand 1 "const_int_operand" "")) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel [(set (match_operand:BLK 2 "memory_operand" "") (const_int 0)) (use (match_operand 3 "const_int_operand" "")) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "s390_offset_p (operands[0], operands[2], operands[1]) && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" [(parallel [(set (match_dup 4) (const_int 0)) (use (match_dup 5)) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") @@ -5427,12 +5445,12 @@ [(parallel [(set (match_operand:DSI 0 "register_operand" "=d") (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "" "") (define_insn "*negdi2_sign_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "d") 0) (const_int 32)) (const_int 32))) @@ -5446,13 +5464,13 @@ (define_insn "*negdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "lcgfr\t%0,%1" [(set_attr "op_type" "RRE")]) (define_insn "*neg<mode>2_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) (const_int 0))) (set (match_operand:GPR 0 "register_operand" "=d") @@ -5462,7 +5480,7 @@ [(set_attr "op_type" "RR<E>")]) (define_insn "*neg<mode>2_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) (const_int 0))) (clobber (match_scratch:GPR 0 "=d"))] @@ -5473,7 +5491,7 @@ (define_insn "*neg<mode>2" [(set (match_operand:GPR 0 "register_operand" "=d") (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "lc<g>r\t%0,%1" [(set_attr "op_type" "RR<E>")]) @@ -5481,24 +5499,24 @@ (define_insn_and_split "*negdi2_31" [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (match_operand:DI 1 "register_operand" "d"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT" "#" "&& reload_completed" [(parallel [(set (match_dup 2) (neg:SI (match_dup 3))) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (parallel - [(set (reg:CCAP 33) + [(set (reg:CCAP CC_REGNUM) (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) (set (match_dup 4) (neg:SI (match_dup 5)))]) (set (pc) - (if_then_else (ne (reg:CCAP 33) (const_int 0)) + (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) (pc) (label_ref (match_dup 6)))) (parallel [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) - (clobber (reg:CC 33))]) + (clobber (reg:CC CC_REGNUM))]) (match_dup 6)] "operands[2] = operand_subword (operands[0], 0, 0, DImode); operands[3] = operand_subword (operands[1], 0, 0, DImode); @@ -5514,12 +5532,12 @@ [(parallel [(set (match_operand:FPR 0 "register_operand" "=f") (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_FLOAT" "") (define_insn "*neg<mode>2_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f")) (match_operand:FPR 2 "const0_operand" ""))) (set (match_operand:FPR 0 "register_operand" "=f") @@ -5530,7 +5548,7 @@ (set_attr "type" "fsimp<mode>")]) (define_insn "*neg<mode>2_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f")) (match_operand:FPR 2 "const0_operand" ""))) (clobber (match_scratch:FPR 0 "=f"))] @@ -5542,7 +5560,7 @@ (define_insn "*neg<mode>2" [(set (match_operand:FPR 0 "register_operand" "=f") (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "lc<de>br\t%0,%1" [(set_attr "op_type" "RRE") @@ -5551,7 +5569,7 @@ (define_insn "*neg<mode>2_ibm" [(set (match_operand:FPR 0 "register_operand" "=f") (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "lc<de>r\t%0,%1" [(set_attr "op_type" "RR") @@ -5567,7 +5585,7 @@ ; (define_insn "*absdi2_sign_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "d") 0) (const_int 32)) (const_int 32))) @@ -5581,13 +5599,13 @@ (define_insn "*absdi2_sign" [(set (match_operand:DI 0 "register_operand" "=d") (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "lpgfr\t%0,%1" [(set_attr "op_type" "RRE")]) (define_insn "*abs<mode>2_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) (const_int 0))) (set (match_operand:GPR 0 "register_operand" "=d") @@ -5597,7 +5615,7 @@ [(set_attr "op_type" "RR<E>")]) (define_insn "*abs<mode>2_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) (const_int 0))) (clobber (match_scratch:GPR 0 "=d"))] @@ -5608,7 +5626,7 @@ (define_insn "abs<mode>2" [(set (match_operand:GPR 0 "register_operand" "=d") (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "lp<g>r\t%0,%1" [(set_attr "op_type" "RR<E>")]) @@ -5621,12 +5639,12 @@ [(parallel [(set (match_operand:FPR 0 "register_operand" "=f") (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "TARGET_HARD_FLOAT" "") (define_insn "*abs<mode>2_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f")) (match_operand:FPR 2 "const0_operand" ""))) (set (match_operand:FPR 0 "register_operand" "=f") @@ -5637,7 +5655,7 @@ (set_attr "type" "fsimp<mode>")]) (define_insn "*abs<mode>2_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f")) (match_operand:FPR 2 "const0_operand" ""))) (clobber (match_scratch:FPR 0 "=f"))] @@ -5649,7 +5667,7 @@ (define_insn "*abs<mode>2" [(set (match_operand:FPR 0 "register_operand" "=f") (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "lp<de>br\t%0,%1" [(set_attr "op_type" "RRE") @@ -5658,7 +5676,7 @@ (define_insn "*abs<mode>2_ibm" [(set (match_operand:FPR 0 "register_operand" "=f") (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "lp<de>r\t%0,%1" [(set_attr "op_type" "RR") @@ -5673,7 +5691,7 @@ ; (define_insn "*negabsdi2_sign_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "d") 0) (const_int 32)) (const_int 32)))) @@ -5688,13 +5706,13 @@ [(set (match_operand:DI 0 "register_operand" "=d") (neg:DI (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "lngfr\t%0,%1" [(set_attr "op_type" "RRE")]) (define_insn "*negabs<mode>2_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) (const_int 0))) (set (match_operand:GPR 0 "register_operand" "=d") @@ -5704,7 +5722,7 @@ [(set_attr "op_type" "RR<E>")]) (define_insn "*negabs<mode>2_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) (const_int 0))) (clobber (match_scratch:GPR 0 "=d"))] @@ -5715,7 +5733,7 @@ (define_insn "*negabs<mode>2" [(set (match_operand:GPR 0 "register_operand" "=d") (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "ln<g>r\t%0,%1" [(set_attr "op_type" "RR<E>")]) @@ -5725,7 +5743,7 @@ ; (define_insn "*negabs<mode>2_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) (match_operand:FPR 2 "const0_operand" ""))) (set (match_operand:FPR 0 "register_operand" "=f") @@ -5736,7 +5754,7 @@ (set_attr "type" "fsimp<mode>")]) (define_insn "*negabs<mode>2_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) (match_operand:FPR 2 "const0_operand" ""))) (clobber (match_scratch:FPR 0 "=f"))] @@ -5748,7 +5766,7 @@ (define_insn "*negabs<mode>2" [(set (match_operand:FPR 0 "register_operand" "=f") (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "ln<de>br\t%0,%1" [(set_attr "op_type" "RRE") @@ -5786,7 +5804,7 @@ [(set (match_operand:INT 0 "register_operand" "") (xor:INT (match_operand:INT 1 "register_operand" "") (const_int -1))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "" "") @@ -5851,12 +5869,12 @@ [(set (match_operand:DI 0 "register_operand" "") (ashiftrt:DI (match_operand:DI 1 "register_operand" "") (match_operand:SI 2 "shift_count_operand" ""))) - (clobber (reg:CC 33))])] + (clobber (reg:CC CC_REGNUM))])] "" "") (define_insn "*ashrdi3_cc_31" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "shift_count_operand" "Y")) (const_int 0))) @@ -5868,7 +5886,7 @@ (set_attr "atype" "reg")]) (define_insn "*ashrdi3_cconly_31" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "shift_count_operand" "Y")) (const_int 0))) @@ -5882,14 +5900,14 @@ [(set (match_operand:DI 0 "register_operand" "=d") (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") (match_operand:SI 2 "shift_count_operand" "Y"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_64BIT" "srda\t%0,%Y2" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) (define_insn "*ashrdi3_cc_64" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") (match_operand:SI 2 "shift_count_operand" "Y")) (const_int 0))) @@ -5901,7 +5919,7 @@ (set_attr "atype" "reg")]) (define_insn "*ashrdi3_cconly_64" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") (match_operand:SI 2 "shift_count_operand" "Y")) (const_int 0))) @@ -5915,7 +5933,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") (match_operand:SI 2 "shift_count_operand" "Y"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" "srag\t%0,%1,%Y2" [(set_attr "op_type" "RSE") @@ -5940,7 +5958,7 @@ ; (define_insn "*ashrsi3_cc" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "shift_count_operand" "Y")) (const_int 0))) @@ -5953,7 +5971,7 @@ (define_insn "*ashrsi3_cconly" - [(set (reg 33) + [(set (reg CC_REGNUM) (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "shift_count_operand" "Y")) (const_int 0))) @@ -5967,7 +5985,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "shift_count_operand" "Y"))) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "" "sra\t%0,%Y2" [(set_attr "op_type" "RS") @@ -5996,7 +6014,7 @@ (define_insn "*cjump_64" [(set (pc) (if_then_else - (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) + (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) (label_ref (match_operand 0 "" "")) (pc)))] "TARGET_CPU_ZARCH" @@ -6015,7 +6033,7 @@ (define_insn "*cjump_31" [(set (pc) (if_then_else - (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) + (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) (label_ref (match_operand 0 "" "")) (pc)))] "!TARGET_CPU_ZARCH" @@ -6037,7 +6055,7 @@ (define_insn "*cjump_long" [(set (pc) (if_then_else - (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) + (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) (match_operand 0 "address_operand" "U") (pc)))] "" @@ -6061,7 +6079,7 @@ (define_insn "*icjump_64" [(set (pc) (if_then_else - (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) + (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) (pc) (label_ref (match_operand 0 "" ""))))] "TARGET_CPU_ZARCH" @@ -6080,7 +6098,7 @@ (define_insn "*icjump_31" [(set (pc) (if_then_else - (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) + (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) (pc) (label_ref (match_operand 0 "" ""))))] "!TARGET_CPU_ZARCH" @@ -6102,7 +6120,7 @@ (define_insn "*icjump_long" [(set (pc) (if_then_else - (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) + (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) (pc) (match_operand 0 "address_operand" "U")))] "" @@ -6140,7 +6158,7 @@ }) (define_insn "*trap" - [(trap_if (match_operator 0 "s390_comparison" [(reg 33) (const_int 0)]) + [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) (const_int 0))] "" "j%C0\t.+2"; @@ -6183,7 +6201,7 @@ (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:SI 3 "=X,&1")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_CPU_ZARCH" { if (which_alternative != 0) @@ -6196,12 +6214,12 @@ "&& reload_completed && (! REG_P (operands[2]) || ! rtx_equal_p (operands[1], operands[2]))" - [(parallel [(set (reg:CCAN 33) + [(parallel [(set (reg:CCAN CC_REGNUM) (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) (const_int 0))) (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) (set (match_dup 2) (match_dup 3)) - (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) + (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) (label_ref (match_dup 0)) (pc)))] "" @@ -6221,7 +6239,7 @@ (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:SI 3 "=X,&1")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_CPU_ZARCH" { if (which_alternative != 0) @@ -6234,12 +6252,12 @@ "&& reload_completed && (! REG_P (operands[2]) || ! rtx_equal_p (operands[1], operands[2]))" - [(parallel [(set (reg:CCAN 33) + [(parallel [(set (reg:CCAN CC_REGNUM) (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) (const_int 0))) (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) (set (match_dup 2) (match_dup 3)) - (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) + (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) (label_ref (match_dup 0)) (pc)))] "" @@ -6262,7 +6280,7 @@ (set (match_operand:SI 2 "register_operand" "=1,?*m*d") (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:SI 3 "=X,&1")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "!TARGET_CPU_ZARCH" { if (get_attr_op_type (insn) == OP_TYPE_RR) @@ -6286,7 +6304,7 @@ (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d") (plus:DI (match_dup 1) (const_int -1))) (clobber (match_scratch:DI 3 "=X,&1")) - (clobber (reg:CC 33))] + (clobber (reg:CC CC_REGNUM))] "TARGET_64BIT" { if (which_alternative != 0) @@ -6299,12 +6317,12 @@ "&& reload_completed && (! REG_P (operands[2]) || ! rtx_equal_p (operands[1], operands[2]))" - [(parallel [(set (reg:CCAN 33) + [(parallel [(set (reg:CCAN CC_REGNUM) (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) (const_int 0))) (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) (set (match_dup 2) (match_dup 3)) - (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) + (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) (label_ref (match_dup 0)) (pc)))] "" @@ -6499,7 +6517,7 @@ }) (define_insn "*sibcall_br" - [(call (mem:QI (reg 1)) + [(call (mem:QI (reg SIBCALL_REGNUM)) (match_operand 0 "const_int_operand" "n"))] "SIBLING_CALL_P (insn) && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" @@ -6540,7 +6558,7 @@ (define_insn "*sibcall_value_br" [(set (match_operand 0 "" "") - (call (mem:QI (reg 1)) + (call (mem:QI (reg SIBCALL_REGNUM)) (match_operand 1 "const_int_operand" "n")))] "SIBLING_CALL_P (insn) && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" @@ -6685,29 +6703,29 @@ ;; (define_expand "get_tp_64" - [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI 36))] + [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))] "TARGET_64BIT" "") (define_expand "get_tp_31" - [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI 36))] + [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))] "!TARGET_64BIT" "") (define_expand "set_tp_64" - [(set (reg:DI 36) (match_operand:DI 0 "nonimmediate_operand" "")) - (set (reg:DI 36) (unspec_volatile:DI [(reg:DI 36)] UNSPECV_SET_TP))] + [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" "")) + (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))] "TARGET_64BIT" "") (define_expand "set_tp_31" - [(set (reg:SI 36) (match_operand:SI 0 "nonimmediate_operand" "")) - (set (reg:SI 36) (unspec_volatile:SI [(reg:SI 36)] UNSPECV_SET_TP))] + [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" "")) + (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))] "!TARGET_64BIT" "") (define_insn "*set_tp" - [(set (reg 36) (unspec_volatile [(reg 36)] UNSPECV_SET_TP))] + [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] "" "" [(set_attr "type" "none") |