diff options
| author | alalaw01 <alalaw01@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-06-03 11:56:24 +0000 |
|---|---|---|
| committer | alalaw01 <alalaw01@138bc75d-0d04-0410-961f-82ee72b054a4> | 2014-06-03 11:56:24 +0000 |
| commit | 6bfe261eda9367880dd4fa9bd79a9d721ab4a8c3 (patch) | |
| tree | 836146a4bce19c2ad78a707453735fb5fbf1a177 /gcc | |
| parent | 5f5fccf784ad7a3096d02687435060f8232c9198 (diff) | |
| download | gcc-6bfe261eda9367880dd4fa9bd79a9d721ab4a8c3.tar.gz | |
Detect EXT patterns to vec_perm_const, use for EXT intrinsics.
(part 2, fix ICE at -O0)
* config/aarch64/aarch64.c (aarch64_evpc_ext): allow and handle
location == 0.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211177 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 8 |
2 files changed, 9 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1f09b046bb5..b35b44492d8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2014-06-03 Alan Lawrence <alan.lawrence@arm.com> + * config/aarch64/aarch64.c (aarch64_evpc_ext): allow and handle + location == 0. + +2014-06-03 Alan Lawrence <alan.lawrence@arm.com> + * config/aarch64/aarch64-simd.md (aarch64_rev<REVERSE:rev-op><mode>): New pattern. * config/aarch64/aarch64.c (aarch64_evpc_rev): New function. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 65ef84a8ffa..961e5c95f8c 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -9018,9 +9018,6 @@ aarch64_evpc_ext (struct expand_vec_perm_d *d) return false; } - /* The mid-end handles masks that just return one of the input vectors. */ - gcc_assert (location != 0); - switch (d->vmode) { case V16QImode: gen = gen_aarch64_extv16qi; break; @@ -9041,7 +9038,10 @@ aarch64_evpc_ext (struct expand_vec_perm_d *d) if (d->testing_p) return true; - if (BYTES_BIG_ENDIAN) + /* The case where (location == 0) is a no-op for both big- and little-endian, + and is removed by the mid-end at optimization levels -O1 and higher. */ + + if (BYTES_BIG_ENDIAN && (location != 0)) { /* After setup, we want the high elements of the first vector (stored at the LSB end of the register), and the low elements of the second |