diff options
| author | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-01-24 21:42:50 +0000 |
|---|---|---|
| committer | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-01-24 21:42:50 +0000 |
| commit | 87918c3722a7ef922b1d014dc6f653404df29847 (patch) | |
| tree | 2404b0c422ca8db1b8999f95a60501ce6042bcca /gcc | |
| parent | 0b84cbdd0454d94702f4611b0680a36db35f86f9 (diff) | |
| download | gcc-87918c3722a7ef922b1d014dc6f653404df29847.tar.gz | |
* config/mips/irix-csr.c: New file.
* config/mips/t-iris6 (irix-csr.o): New rule to build it.
(EXTRA_MULTILIB_PARTS): Add irix-csr.o.
* config/mips/iris6.h (ENDFILE_SPEC): Include it in n32 and n64
executables.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@94186 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/mips/iris6.h | 3 | ||||
| -rw-r--r-- | gcc/config/mips/irix-csr.c | 17 | ||||
| -rw-r--r-- | gcc/config/mips/t-iris6 | 6 |
4 files changed, 33 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 62ae65354a6..1e659d01948 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2005-01-24 Richard Sandiford <rsandifo@redhat.com> + + * config/mips/irix-csr.c: New file. + * config/mips/t-iris6 (irix-csr.o): New rule to build it. + (EXTRA_MULTILIB_PARTS): Add irix-csr.o. + * config/mips/iris6.h (ENDFILE_SPEC): Include it in n32 and n64 + executables. + 2005-01-24 Eric Botcazou <ebotcazou@libertysurf.fr> PR bootstrap/19364 diff --git a/gcc/config/mips/iris6.h b/gcc/config/mips/iris6.h index 9ce17f82bac..bf3bbc39b28 100644 --- a/gcc/config/mips/iris6.h +++ b/gcc/config/mips/iris6.h @@ -97,7 +97,8 @@ Boston, MA 02111-1307, USA. */ #undef ENDFILE_SPEC #define ENDFILE_SPEC \ - "crtend.o%s irix-crtn.o%s \ + "%{!shared:%{mabi=n32|mabi=64:irix-csr.o%s}} \ + crtend.o%s irix-crtn.o%s \ %{!shared: \ %{mabi=32:crtn.o%s}\ %{mabi=n32:%{mips4:/usr/lib32/mips4/crtn.o%s}\ diff --git a/gcc/config/mips/irix-csr.c b/gcc/config/mips/irix-csr.c new file mode 100644 index 00000000000..ef37345cd73 --- /dev/null +++ b/gcc/config/mips/irix-csr.c @@ -0,0 +1,17 @@ +#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 +#include <sys/fpu.h> + +/* n32 and n64 applications usually run with the MIPS IV Flush to Zero + bit set. Clear it here so that gcc-generated code will handle + subnormals correctly by default. */ + +static void __attribute__((constructor)) +clear_flush_to_zero (void) +{ + union fpc_csr csr; + + csr.fc_word = get_fpc_csr (); + csr.fc_struct.flush = 0; + set_fpc_csr (csr.fc_word); +} +#endif diff --git a/gcc/config/mips/t-iris6 b/gcc/config/mips/t-iris6 index 254480cb43f..93837887f46 100644 --- a/gcc/config/mips/t-iris6 +++ b/gcc/config/mips/t-iris6 @@ -19,3 +19,9 @@ tp-bit.c: $(srcdir)/config/fp-bit.c echo '# define TFLOAT' >> tp-bit.c cat $(srcdir)/config/fp-bit.c >> tp-bit.c echo '#endif' >> tp-bit.c + +$(T)irix-csr.o: $(srcdir)/config/mips/irix-csr.c $(GCC_PASSES) + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ + -c -o $@ $< + +EXTRA_MULTILIB_PARTS += irix-csr.o |