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| author | wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-10-08 00:39:09 +0000 |
|---|---|---|
| committer | wilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-10-08 00:39:09 +0000 |
| commit | 46894cb34838ae83fa820967b980e47e0d6f979b (patch) | |
| tree | 080c383566f254b0a6a5d13455a71d59d47eb972 /gcc | |
| parent | c2876841862f411e6d7757ec92fd395d8f3449aa (diff) | |
| download | gcc-46894cb34838ae83fa820967b980e47e0d6f979b.tar.gz | |
Fix gcc.dg/vect/vect-shift-1.c failure.
* config/ia64/vect.md (ashl<mode>3, ashr<mode>3, lshr<mode>3): Use
DImode not VECINT24 for operand 2.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@105113 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 3 | ||||
| -rw-r--r-- | gcc/config/ia64/vect.md | 6 |
2 files changed, 6 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a16029498b7..86ba1b278df 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,8 @@ 2005-10-07 James E. Wilson <wilson@specifix.com> + * config/ia64/vect.md (ashl<mode>3, ashr<mode>3, lshr<mode>3): Use + DImode not VECINT24 for operand 2. + PR target/23644 * doc/invoke.texi (IA-64 Options, item -mtune): Renamed from -mtune-arch. diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md index 3d4669bc8bc..94380bfcc49 100644 --- a/gcc/config/ia64/vect.md +++ b/gcc/config/ia64/vect.md @@ -318,7 +318,7 @@ [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") (ashift:VECINT24 (match_operand:VECINT24 1 "gr_register_operand" "r") - (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))] + (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] "" "pshl<vecsize> %0 = %1, %2" [(set_attr "itanium_class" "mmshf")]) @@ -327,7 +327,7 @@ [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") (ashiftrt:VECINT24 (match_operand:VECINT24 1 "gr_register_operand" "r") - (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))] + (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] "" "pshr<vecsize> %0 = %1, %2" [(set_attr "itanium_class" "mmshf")]) @@ -336,7 +336,7 @@ [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") (lshiftrt:VECINT24 (match_operand:VECINT24 1 "gr_register_operand" "r") - (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))] + (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] "" "pshr<vecsize>.u %0 = %1, %2" [(set_attr "itanium_class" "mmshf")]) |