Removal of -fforce-mem.

OKed by Richard Henderson.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@101666 138bc75d-0d04-0410-961f-82ee72b054a4

10 files changed, 32 insertions, 115 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 396befc69af..a75e4d4f847 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2005-07-06  Fariborz Jahanian <fjahanian@apple.com>
+
+        * doc/invoke.texi: Update -fforce-mem documentation.
+        * dojump.c (compare_from_rtx,do_compare_rtx_and_jump): Remove 
+        code for -fforce-mem.
+        * expmed.c: (store_bit_field,store_fixed_bit_field,
+        extract_bit_field): Ditto.
+        * expr.c: (convert_move): Ditto.
+        * optabs.c: (expand_binop,expand_twoval_unop,expand_twoval_binop,
+        expand_unop,emit_unop_insn,prepare_cmp_insn,emit_conditional_move,
+        emit_conditional_add,expand_float,expand_fix): Ditto.
+        * opts.c: (decode_options): Remove setting of flag_force_mem flag.
+        (common_handle_option): Issue warning when -fforce-mem specified.
+
 2005-07-06  Paul Brook  <paul@codesourcery.com>
 
 	* aclocal.m4: Work around a bug in AC_PATH_PROGS when its last
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index a979900ac52..f1ce356d0d5 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -102,7 +102,7 @@ of the same kind; for example, if you specify @option{-L} more than once,
 the directories are searched in the order specified.
 
 Many options have long names starting with @samp{-f} or with
-@samp{-W}---for example, @option{-fforce-mem},
+@samp{-W}---for example, 
 @option{-fstrength-reduce}, @option{-Wformat} and so on.  Most of
 these have both positive and negative forms; the negative form of
 @option{-ffoo} would be @option{-fno-foo}.  This manual documents
@@ -302,7 +302,7 @@ Objective-C and Objective-C++ Dialects}.
 -fcse-skip-blocks  -fcx-limited-range  -fdata-sections @gol
 -fdelayed-branch  -fdelete-null-pointer-checks -fearly-inlining @gol
 -fexpensive-optimizations  -ffast-math  -ffloat-store @gol
--fforce-addr  -fforce-mem  -ffunction-sections @gol
+-fforce-addr  -ffunction-sections @gol
 -fgcse  -fgcse-lm  -fgcse-sm  -fgcse-las  -fgcse-after-reload @gol
 -floop-optimize -fcrossjumping  -fif-conversion  -fif-conversion2 @gol
 -finline-functions  -finline-limit=@var{n}  -fkeep-inline-functions @gol
@@ -4322,7 +4322,6 @@ also turns on the following optimization flags:
 -fstrength-reduce @gol
 -frerun-cse-after-loop  -frerun-loop-opt @gol
 -fcaller-saves @gol
--fforce-mem @gol
 -fpeephole2 @gol
 -fschedule-insns  -fschedule-insns2 @gol
 -fsched-interblock  -fsched-spec @gol
@@ -4399,15 +4398,12 @@ Force memory operands to be copied into registers before doing
 arithmetic on them.  This produces better code by making all memory
 references potential common subexpressions.  When they are not common
 subexpressions, instruction combination should eliminate the separate
-register-load.
-
-Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
+register-load. This option is now a nop and will be removed in 4.2.
 
 @item -fforce-addr
 @opindex fforce-addr
 Force memory address constants to be copied into registers before
-doing arithmetic on them.  This may produce better code just as
-@option{-fforce-mem} may.
+doing arithmetic on them.
 
 @item -fomit-frame-pointer
 @opindex fomit-frame-pointer
diff --git a/gcc/dojump.c b/gcc/dojump.c
index c955f5d5fb3..741c30a8dca 100644
--- a/gcc/dojump.c
+++ b/gcc/dojump.c
@@ -761,12 +761,6 @@ compare_from_rtx (rtx op0, rtx op1, enum rtx_code code, int unsignedp,
       code = swap_condition (code);
     }
 
-  if (flag_force_mem)
-    {
-      op0 = force_not_mem (op0);
-      op1 = force_not_mem (op1);
-    }
-
   do_pending_stack_adjust ();
 
   code = unsignedp ? unsigned_condition (code) : code;
@@ -830,12 +824,6 @@ do_compare_rtx_and_jump (rtx op0, rtx op1, enum rtx_code code, int unsignedp,
       code = swap_condition (code);
     }
 
-  if (flag_force_mem)
-    {
-      op0 = force_not_mem (op0);
-      op1 = force_not_mem (op1);
-    }
-
   do_pending_stack_adjust ();
 
   code = unsignedp ? unsigned_condition (code) : code;
diff --git a/gcc/expmed.c b/gcc/expmed.c
index f6f35b91c77..e54f0430cf5 100644
--- a/gcc/expmed.c
+++ b/gcc/expmed.c
@@ -408,14 +408,6 @@ store_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
 	}
     }
 
-  if (flag_force_mem)
-    {
-      int old_generating_concat_p = generating_concat_p;
-      generating_concat_p = 0;
-      value = force_not_mem (value);
-      generating_concat_p = old_generating_concat_p;
-    }
-
   /* If the target is a register, overwriting the entire object, or storing
      a full-word or multi-word field can be done with just a SUBREG.
 
@@ -633,8 +625,6 @@ store_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
 
       /* If this machine's insv can only insert into a register, copy OP0
 	 into a register and save it back later.  */
-      /* This used to check flag_force_mem, but that was a serious
-	 de-optimization now that flag_force_mem is enabled by -O2.  */
       if (MEM_P (op0)
 	  && ! ((*insn_data[(int) CODE_FOR_insv].operand[0].predicate)
 		(op0, VOIDmode)))
@@ -902,7 +892,7 @@ store_fixed_bit_field (rtx op0, unsigned HOST_WIDE_INT offset,
   /* Now clear the chosen bits in OP0,
      except that if VALUE is -1 we need not bother.  */
 
-  subtarget = (REG_P (op0) || ! flag_force_mem) ? op0 : 0;
+  subtarget = op0;
 
   if (! all_one)
     {
@@ -1449,8 +1439,7 @@ extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
 
 	  unit = GET_MODE_BITSIZE (maxmode);
 
-	  if (xtarget == 0
-	      || (flag_force_mem && MEM_P (xtarget)))
+	  if (xtarget == 0)
 	    xtarget = xspec_target = gen_reg_rtx (tmode);
 
 	  if (GET_MODE (xtarget) != maxmode)
@@ -1577,8 +1566,7 @@ extract_bit_field (rtx str_rtx, unsigned HOST_WIDE_INT bitsize,
 
 	  unit = GET_MODE_BITSIZE (maxmode);
 
-	  if (xtarget == 0
-	      || (flag_force_mem && MEM_P (xtarget)))
+	  if (xtarget == 0)
 	    xtarget = xspec_target = gen_reg_rtx (tmode);
 
 	  if (GET_MODE (xtarget) != maxmode)
diff --git a/gcc/expr.c b/gcc/expr.c
index a3c1b6ad917..2a1ecab51e8 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -642,9 +642,6 @@ convert_move (rtx to, rtx from, int unsignedp)
       if ((code = can_extend_p (to_mode, from_mode, unsignedp))
 	  != CODE_FOR_nothing)
 	{
-	  if (flag_force_mem)
-	    from = force_not_mem (from);
-
 	  emit_unop_insn (code, to, from, equiv_code);
 	  return;
 	}
diff --git a/gcc/optabs.c b/gcc/optabs.c
index 2ed499e441f..60c491870a8 100644
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -1030,21 +1030,6 @@ expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1,
 
   class = GET_MODE_CLASS (mode);
 
-  if (flag_force_mem)
-    {
-      /* Load duplicate non-volatile operands once.  */
-      if (rtx_equal_p (op0, op1) && ! volatile_refs_p (op0))
-	{
-	  op0 = force_not_mem (op0);
-	  op1 = op0;
-	}
-      else
-	{
-	  op0 = force_not_mem (op0);
-	  op1 = force_not_mem (op1);
-	}
-    }
-
   /* If subtracting an integer constant, convert this into an addition of
      the negated constant.  */
 
@@ -1871,9 +1856,6 @@ expand_twoval_unop (optab unoptab, rtx op0, rtx targ0, rtx targ1,
 
   class = GET_MODE_CLASS (mode);
 
-  if (flag_force_mem)
-    op0 = force_not_mem (op0);
-
   if (!targ0)
     targ0 = gen_reg_rtx (mode);
   if (!targ1)
@@ -1966,12 +1948,6 @@ expand_twoval_binop (optab binoptab, rtx op0, rtx op1, rtx targ0, rtx targ1,
 
   class = GET_MODE_CLASS (mode);
 
-  if (flag_force_mem)
-    {
-      op0 = force_not_mem (op0);
-      op1 = force_not_mem (op1);
-    }
-
   /* If we are inside an appropriately-short loop and we are optimizing,
      force expensive constants into a register.  */
   if (CONSTANT_P (op0) && optimize
@@ -2358,9 +2334,6 @@ expand_unop (enum machine_mode mode, optab unoptab, rtx op0, rtx target,
 
   class = GET_MODE_CLASS (mode);
 
-  if (flag_force_mem)
-    op0 = force_not_mem (op0);
-
   if (unoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
     {
       int icode = (int) unoptab->handlers[(int) mode].insn_code;
@@ -2987,19 +2960,12 @@ emit_unop_insn (int icode, rtx target, rtx op0, enum rtx_code code)
 
   temp = target;
 
-  /* Sign and zero extension from memory is often done specially on
-     RISC machines, so forcing into a register here can pessimize
-     code.  */
-  if (flag_force_mem && code != SIGN_EXTEND && code != ZERO_EXTEND)
-    op0 = force_not_mem (op0);
-
   /* Now, if insn does not accept our operands, put them into pseudos.  */
 
   if (!insn_data[icode].operand[1].predicate (op0, mode0))
     op0 = copy_to_mode_reg (mode0, op0);
 
-  if (!insn_data[icode].operand[0].predicate (temp, GET_MODE (temp))
-      || (flag_force_mem && MEM_P (temp)))
+  if (!insn_data[icode].operand[0].predicate (temp, GET_MODE (temp)))
     temp = gen_reg_rtx (GET_MODE (temp));
 
   pat = GEN_FCN (icode) (temp, op0);
@@ -3415,21 +3381,6 @@ prepare_cmp_insn (rtx *px, rtx *py, enum rtx_code *pcomparison, rtx size,
 
   class = GET_MODE_CLASS (mode);
 
-  if (mode != BLKmode && flag_force_mem)
-    {
-      /* Load duplicate non-volatile operands once.  */
-      if (rtx_equal_p (x, y) && ! volatile_refs_p (x))
-	{
-	  x = force_not_mem (x);
-	  y = x;
-	}
-      else
-	{
-	  x = force_not_mem (x);
-	  y = force_not_mem (y);
-	}
-    }
-
   /* If we are inside an appropriately-short loop and we are optimizing,
      force expensive constants into a register.  */
   if (CONSTANT_P (x) && optimize
@@ -3916,12 +3867,6 @@ emit_conditional_move (rtx target, enum rtx_code code, rtx op0, rtx op1,
   if (icode == CODE_FOR_nothing)
     return 0;
 
-  if (flag_force_mem)
-    {
-      op2 = force_not_mem (op2);
-      op3 = force_not_mem (op3);
-    }
-
   if (!target)
     target = gen_reg_rtx (mode);
 
@@ -4050,12 +3995,6 @@ emit_conditional_add (rtx target, enum rtx_code code, rtx op0, rtx op1,
   if (icode == CODE_FOR_nothing)
     return 0;
 
-  if (flag_force_mem)
-    {
-      op2 = force_not_mem (op2);
-      op3 = force_not_mem (op3);
-    }
-
   if (!target)
     target = gen_reg_rtx (mode);
 
@@ -4379,9 +4318,6 @@ expand_float (rtx to, rtx from, int unsignedp)
       rtx temp;
       REAL_VALUE_TYPE offset;
 
-      if (flag_force_mem)
-	from = force_not_mem (from);
-
       /* Look for a usable floating mode FMODE wider than the source and at
 	 least as wide as the target.  Using FMODE will avoid rounding woes
 	 with unsigned values greater than the signed maximum value.  */
@@ -4489,9 +4425,6 @@ expand_float (rtx to, rtx from, int unsignedp)
       if (GET_MODE_SIZE (GET_MODE (from)) < GET_MODE_SIZE (SImode))
 	from = convert_to_mode (SImode, from, unsignedp);
 
-      if (flag_force_mem)
-	from = force_not_mem (from);
-
       libfunc = tab->handlers[GET_MODE (to)][GET_MODE (from)].libfunc;
       gcc_assert (libfunc);
 
@@ -4609,9 +4542,6 @@ expand_fix (rtx to, rtx from, int unsignedp)
 	  lab1 = gen_label_rtx ();
 	  lab2 = gen_label_rtx ();
 
-	  if (flag_force_mem)
-	    from = force_not_mem (from);
-
 	  if (fmode != GET_MODE (from))
 	    from = convert_to_mode (fmode, from, 0);
 
@@ -4678,9 +4608,6 @@ expand_fix (rtx to, rtx from, int unsignedp)
       libfunc = tab->handlers[GET_MODE (to)][GET_MODE (from)].libfunc;
       gcc_assert (libfunc);
 
-      if (flag_force_mem)
-	from = force_not_mem (from);
-
       start_sequence ();
 
       value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
diff --git a/gcc/opts.c b/gcc/opts.c
index 195626fa264..e5e490d16eb 100644
--- a/gcc/opts.c
+++ b/gcc/opts.c
@@ -560,7 +560,6 @@ decode_options (unsigned int argc, const char **argv)
       flag_rerun_cse_after_loop = 1;
       flag_rerun_loop_opt = 1;
       flag_caller_saves = 1;
-      flag_force_mem = 1;
       flag_peephole2 = 1;
 #ifdef INSN_SCHEDULING
       flag_schedule_insns = 1;
@@ -1042,6 +1041,10 @@ common_handle_option (size_t scode, const char *arg, int value)
       flag_pedantic_errors = pedantic = 1;
       break;
 
+    case OPT_fforce_mem:
+      warning (0, "-f[no-]force-mem is nop and option will be removed in 4.2");
+      break;
+
     default:
       /* If the flag was handled in a standard way, assume the lack of
 	 processing here is intentional.  */
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b70b33024a9..445ac810b40 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2005-07-06  Fariborz Jahanian <fjahanian@apple.com>
+
+	* gcc.dg/20030324-1.c: Remove -fforce-mem option.
+	* gcc.dg/980816-1.c: Ditto.
+
 2005-07-06  Jeff Law  <law@redhat.com>
 
 	* gcc.c-torture/compile/pr21356.c: New test.
diff --git a/gcc/testsuite/gcc.dg/20030324-1.c b/gcc/testsuite/gcc.dg/20030324-1.c
index 7e46d040ee2..f141bafa927 100644
--- a/gcc/testsuite/gcc.dg/20030324-1.c
+++ b/gcc/testsuite/gcc.dg/20030324-1.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-options "-O -fstrength-reduce -fstrict-aliasing -fforce-mem -fgcse" } */
+/* { dg-options "-O -fstrength-reduce -fstrict-aliasing -fgcse" } */
 
 /* PR optimization/10087 */
 /* Contributed by Peter van Hoof <p.van-hoof@qub.ac.uk> */
diff --git a/gcc/testsuite/gcc.dg/980816-1.c b/gcc/testsuite/gcc.dg/980816-1.c
index 8581d999dbd..d4f59c40c53 100644
--- a/gcc/testsuite/gcc.dg/980816-1.c
+++ b/gcc/testsuite/gcc.dg/980816-1.c
@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-options -fno-force-mem } */
 
 int
 div_and_round_double (lden_orig, hden_orig)