diff options
| author | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-11-12 15:23:33 +0000 |
|---|---|---|
| committer | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-11-12 15:23:33 +0000 |
| commit | 9456798d72d0e81a2a553287f436dcb05cff175a (patch) | |
| tree | 1e80106d0c4f828b72deb6e782c20d788c0dd818 /libgcc/config | |
| parent | e89aee4174fe58eaba553027558144a0f423960c (diff) | |
| download | gcc-9456798d72d0e81a2a553287f436dcb05cff175a.tar.gz | |
[./]
2013-11-12 Basile Starynkevitch <basile@starynkevitch.net>
{{merge with trunk GCC 4.9 svn rev 204695; previous trunk merge
was 202773; very unstable...}}
[gcc/]
2013-11-11 Basile Starynkevitch <basile@starynkevitch.net>
{{merge with trunk GCC 4.9 svn rev 204695; very unstable}}
* melt-runtime.h (MELT_VERSION_STRING): Bump to "1.0.1+".
* melt-run.proto.h: Update copyright years.
include tree-cfg.h instead of tree-flow.h for GCC 4.9.
* melt-runtime.cc: Include tree-cfg.h not tree-flow.h for GCC 4.9.
(meltgc_walk_gimple_seq): Fatal error with GCC 4.9 since the
walk_use_def_chains function disappeared from GCC...
* melt/xtramelt-ana-gimple.melt (walk_gimple_seq)
(walk_gimple_seq_unique_tree): issue some #warning-s for GCC 4.9
because walk_use_def_chains function disappeared from GCC...
* melt/xtramelt-probe.melt (probe_docmd): Issue an error since
currently the MELT probe is not usable with GCC 4.9....
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@204705 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'libgcc/config')
329 files changed, 25842 insertions, 48 deletions
diff --git a/libgcc/config/arc/asm.h b/libgcc/config/arc/asm.h new file mode 100644 index 00000000000..56356a4000c --- /dev/null +++ b/libgcc/config/arc/asm.h @@ -0,0 +1,30 @@ +/* Assembler macros for the Synopsys DesignWare ARC CPU. + + Copyright (C) 1994, 1995, 1997, 2004, 2007-2013 + Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#define FUNC(X) .type X,@function +#define ENDFUNC(X) .size X, .-X diff --git a/libgcc/config/arc/crtg.S b/libgcc/config/arc/crtg.S new file mode 100644 index 00000000000..6014f045881 --- /dev/null +++ b/libgcc/config/arc/crtg.S @@ -0,0 +1,52 @@ +/* Code to start and stop profiling for the Synopsys DesignWare ARC CPU. + + Copyright (C) 1994, 1995, 1997, 2004, 2007-2013 + Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + + .section .init + .global _init + .global _fini + .global __monstartup + mov_s r0,_init + mov_s r1,_fini + jl __monstartup + + .section .__arc_profile_desc, "a" + .global __arc_profile_desc_secstart + .balign 4 +__arc_profile_desc_secstart: + .section .__arc_profile_forward, "a" + .global __arc_profile_forward_secstart + .balign 4 +__arc_profile_forward_secstart: + .section .__arc_profile_counters, "aw" + .global __arc_profile_counters_secstart + .balign 4 +__arc_profile_counters_secstart: + + .section .fini + .global _mcleanup + jl _mcleanup diff --git a/libgcc/config/arc/crtgend.S b/libgcc/config/arc/crtgend.S new file mode 100644 index 00000000000..5db637a0c08 --- /dev/null +++ b/libgcc/config/arc/crtgend.S @@ -0,0 +1,34 @@ +/* Code to start and stop profiling for the Synopsys DesignWare ARC CPU. + + Copyright (C) 1994, 1995, 1997, 2004, 2007-2013 + Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + + .section .__arc_profile_desc, "a" + .global __arc_profile_desc_secend +__arc_profile_desc_secend: + .section .__arc_profile_forward, "a" + .global __arc_profile_forward_secend +__arc_profile_forward_secend: diff --git a/libgcc/config/arc/crti.S b/libgcc/config/arc/crti.S new file mode 100644 index 00000000000..1f3dfe14734 --- /dev/null +++ b/libgcc/config/arc/crti.S @@ -0,0 +1,42 @@ +/* .fini/.init stack frame setup for the Synopsys DesignWare ARC CPU. + + Copyright (C) 1994, 1995, 1997, 2004, 2007-2013 + Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +# This file contains the stack frame setup for contents of the .fini and +# .init sections. + + .section .init + .global _init + .word 0 +_init: + push_s blink + + .section .fini + .global _fini + .word 0 +_fini: + push_s blink diff --git a/libgcc/config/arc/crtn.S b/libgcc/config/arc/crtn.S new file mode 100644 index 00000000000..1962d3c27cd --- /dev/null +++ b/libgcc/config/arc/crtn.S @@ -0,0 +1,39 @@ +/* Ensure .fini/.init return for the Synopsys DesignWare ARC CPU. + + Copyright (C) 1994, 1995, 1997, 2004, 2007-2013 + Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +# This file just makes sure that the .fini and .init sections do in +# fact return. This file is the last thing linked into any executable. + + .section .init + pop_s blink + j_s [blink] + + + .section .fini + pop_s blink + j_s [blink] diff --git a/libgcc/config/arc/divtab-arc700.c b/libgcc/config/arc/divtab-arc700.c new file mode 100644 index 00000000000..dba0b4e3928 --- /dev/null +++ b/libgcc/config/arc/divtab-arc700.c @@ -0,0 +1,70 @@ +/* Copyright (C) 2004, 2006, 2007-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 3, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file into combinations with other programs, +and to distribute those combinations without any restriction coming +from the use of this file. (The General Public License restrictions +do apply in other respects; for example, they cover modification of +the file, and distribution when not linked into a combine +executable.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +/* Calculate division table for ARC700 integer division + Contributed by Joern Rennecke + joern.rennecke@arc.com */ + +#include <stdio.h> +#include <math.h> + +int +main () +{ + int i, j; + unsigned x; + double q, r, err, max_err = -1; + + puts("/* This table has been generated by divtab-arc700.c. */"); + puts("\ +/* 1/512 .. 1/256, normalized. There is a leading 1 in bit 31.\n\ + For powers of two, we list unnormalized numbers instead. The values\n\ + for powers of 2 are loaded, but not used. The value for 1 is actually\n\ + the first instruction after .Lmuldiv. */\n\ + .balign 4"); + puts (".Ldivtab:\n"); + for (i = 256; i >= 2; --i) + { + j = i < 0 ? -i : i; + if (j & (j-1)) + while (j < 128) + j += j; + else + /* Power of two. */ + j *= 128; + q = 4.*(1<<30)*128/j; + r = ceil (q); + printf ("\t.long\t0x%X\n", (unsigned) r); + err = r - q; + if (err > max_err) + max_err = err; + } +#if 0 + printf ("\t/* maximum error: %f */\n", max_err); +#endif + exit (0); +} diff --git a/libgcc/config/arc/dp-hack.h b/libgcc/config/arc/dp-hack.h new file mode 100644 index 00000000000..fcbd89cf9d7 --- /dev/null +++ b/libgcc/config/arc/dp-hack.h @@ -0,0 +1,101 @@ +/* Copyright (C) 2007-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* This file selects the double-precision parts of fp-bit.c that are + still needed for some ARC hardware variants; it also renames functions + that duplicate asm-coded functionality so that their results can be + used to compare with the optimized versions for debugging. */ + +#define FINE_GRAINED_LIBRARIES +#define ARC_DP_DEBUG 1 +#if !defined (__ARC_NORM__) || ARC_DP_DEBUG +#define L_pack_df +#define L_unpack_df +#define L_make_df +#define L_thenan_df +#define L_sf_to_df +#endif +#ifndef __ARC_NORM__ +#define L_addsub_df +#elif ARC_DP_DEBUG +#define L_addsub_df +#define __adddf3 __adddf3_c +#define __subdf3 __subdf3_c +#endif +#ifndef __ARC_NORM__ +#define L_mul_df +#define L_div_df +#elif (!defined (__ARC700__) && !defined (__ARC_MUL64__) \ + && !defined(__ARC_MUL32BY16__)) +#define L_mul_df +#define L_div_df +#undef QUIET_NAN +#define QUIET_NAN 0xfffffffffffffLL +#elif ARC_DP_DEBUG +#define L_mul_df +#define __muldf3 __muldf3_c +#define L_div_df +#define __divdf3 __divdf3_c +#endif +#ifndef __ARC_NORM__ +#define L_df_to_sf +#define L_si_to_df +#define L_df_to_si +#define L_tf_to_usi /* need to defined this instead of df_to_usi */ +#define L_usi_to_df +#elif ARC_DP_DEBUG +#define L_df_to_sf +#define __truncdfsf2 __truncdfsf2_c +#define L_si_to_df +#define __floatsidf __floatsidf_c +#define L_df_to_si +#define __fixdfsi __fixdfsi_c +#define L_tf_to_usi +#define __fixunsdfsi __fixunsdfsi_c +#define L_usi_to_df +#define __floatunsidf __floatunsidf_c +#endif +#ifndef __ARC_NORM__ +#define L_fpcmp_parts_df +#define L_compare_df +#define L_eq_df +#define L_ne_df +#define L_gt_df +#define L_ge_df +#define L_lt_df +#define L_le_df +#define L_unord_df +#define L_negate_df +#elif ARC_DP_DEBUG +#define L_fpcmp_parts_df +#define L_eq_df +#define __eqdf2 __eqdf2_c +#define L_gt_df +#define __gtdf2 __gtdf2_c +#define L_ge_df +#define __gedf2 __gedf2_c +#define L_unord_df +#define __unorddf2 __unorddf2_c +#endif diff --git a/libgcc/config/arc/fp-hack.h b/libgcc/config/arc/fp-hack.h new file mode 100644 index 00000000000..7b1298ac1c8 --- /dev/null +++ b/libgcc/config/arc/fp-hack.h @@ -0,0 +1,85 @@ +/* Copyright (C) 2007-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* This file selects the single-precision parts of fp-bit.c that are + still needed for some ARC hardware variants; it also renames functions + that duplicate asm-coded functionality so that their results can be + used to compare with the optimized versions for debugging. */ + +#define ARC_FP_DEBUG 1 +#define FINE_GRAINED_LIBRARIES +#if !defined (__ARC_NORM__) || ARC_FP_DEBUG +#define L_pack_sf +#define L_unpack_sf +#define L_make_sf +#define L_thenan_sf +#endif +#ifndef __ARC_NORM__ +#define L_addsub_sf +#define L_mul_sf +#define L_div_sf +#define L_sf_to_df +#define L_si_to_sf +#define L_sf_to_si +#define L_usi_to_sf +#elif ARC_FP_DEBUG +#define L_addsub_sf +#define __addsf3 __addsf3_c +#define __subsf3 __subsf3_c +#define L_mul_sf +#define __mulsf3 __mulsf3_c +#define L_div_sf +#define __divsf3 __divsf3_c +#define L_sf_to_df +#define __extendsfdf2 __extendsfdf2_c +#define L_si_to_sf +#define __floatsisf __floatsisf_c +#define L_sf_to_si +#define __fixsfsi __fixsfsi_c +#define L_usi_to_sf +#define __floatunsisf __floatunsisf_c +#endif +#ifndef __ARC_NORM__ +#define L_fpcmp_parts_sf +#define L_compare_sf +#define L_eq_sf +#define L_ne_sf +#define L_gt_sf +#define L_ge_sf +#define L_lt_sf +#define L_le_sf +#define L_unord_sf +#define L_negate_sf +#elif ARC_FP_DEBUG +#define L_fpcmp_parts_sf +#define L_eq_sf +#define __eqsf2 __eqsf2_c +#define L_gt_sf +#define __gtsf2 __gtsf2_c +#define L_ge_sf +#define __gesf2 __gesf2_c +#define L_unord_sf +#define __unordsf2 __unordsf2_c +#endif diff --git a/libgcc/config/arc/gmon/atomic.h b/libgcc/config/arc/gmon/atomic.h new file mode 100644 index 00000000000..857b85cefb3 --- /dev/null +++ b/libgcc/config/arc/gmon/atomic.h @@ -0,0 +1,26 @@ +/* Copyright (C) 2007-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* File deliberately left blank. */ diff --git a/libgcc/config/arc/gmon/auxreg.h b/libgcc/config/arc/gmon/auxreg.h new file mode 100644 index 00000000000..10efa169eed --- /dev/null +++ b/libgcc/config/arc/gmon/auxreg.h @@ -0,0 +1,35 @@ +/* Copyright (C) 2007-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#define LP_START 0x02 +#define LP_END 0x03 +#define IDENTITY 0x04 +#define STATUS32 0x0a +#define COUNT0 0x21 /* Timer 0 count */ +#define CONTROL0 0x22 /* Timer 0 control */ +#define LIMIT0 0x23 /* Timer 0 limit */ +#define INT_VECTOR_BASE 0x25 +#define D_CACHE_BUILD 0x72 +#define DC_FLDL 0x4c diff --git a/libgcc/config/arc/gmon/dcache_linesz.S b/libgcc/config/arc/gmon/dcache_linesz.S new file mode 100644 index 00000000000..402a8331943 --- /dev/null +++ b/libgcc/config/arc/gmon/dcache_linesz.S @@ -0,0 +1,55 @@ +/* This file contains code to do profiling. + + Copyright (C) 2007-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "../asm.h" +#include "auxreg.h" +/* This file contains code to do profiling. */ + .weak __profile_timer_cycles + .global __profile_timer_cycles + .set __profile_timer_cycles, 200 + .text + ; For Arctangent-A5, if no data cache is present, a read of the + ; cache build register returns the ID register. For ARC600 and + ; later, the version field will be zero. + .global __dcache_linesz + .balign 4 +__dcache_linesz: + lr r12,[D_CACHE_BUILD] + extb_s r0,r12 + breq_s r0,0,.Lsz_nocache + brge r0,0x20,.Lsz_havecache + lr r0,[IDENTITY] + breq r12,r0,.Lsz_nocache +.Lsz_havecache: + lsr_s r12,r12,16 + mov_s r0,16 + bmsk_s r12,r12,3 + asl_s r0,r0,r12 + j_s [blink] +.Lsz_nocache: + mov_s r0,1 + j_s [blink] diff --git a/libgcc/config/arc/gmon/gmon.c b/libgcc/config/arc/gmon/gmon.c new file mode 100644 index 00000000000..098351f1664 --- /dev/null +++ b/libgcc/config/arc/gmon/gmon.c @@ -0,0 +1,450 @@ +/*- + * Copyright (c) 1983, 1992, 1993 + * The Regents of the University of California. All rights reserved. + * Copyright (C) 2007-2013 Free Software Foundation, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#if 0 +#include <sys/param.h> +#include <sys/time.h> +#endif +#include <sys/gmon.h> +#include <sys/gmon_out.h> + +#include <stddef.h> +#include <errno.h> +#include <stdio.h> +#include <fcntl.h> +#include <unistd.h> + +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <unistd.h> +#if 0 +#include <libc-internal.h> +#include <not-cancel.h> + +#ifdef USE_IN_LIBIO +# include <wchar.h> +#endif +#endif +#define internal_function +#define weak_alias(fun,aliasid) extern __typeof(fun) aliasid __attribute__ ((weak, alias (#fun))); +#define __libc_enable_secure 0 + +/* Head of basic-block list or NULL. */ +struct __bb *__bb_head attribute_hidden; + +struct gmonparam _gmonparam attribute_hidden = { GMON_PROF_OFF }; + +/* + * See profil(2) where this is described: + */ +static int s_scale; +#define SCALE_1_TO_1 0x10000L + +#define ERR(s) write (STDERR_FILENO, s, sizeof (s) - 1) + +void moncontrol (int mode); +void __moncontrol (int mode); +static void write_hist (int fd) internal_function; +static void write_call_graph (int fd) internal_function; +static void write_bb_counts (int fd) internal_function; + +/* + * Control profiling + * profiling is what mcount checks to see if + * all the data structures are ready. + */ +void +__moncontrol (int mode) +{ + struct gmonparam *p = &_gmonparam; + + /* Don't change the state if we ran into an error. */ + if (p->state == GMON_PROF_ERROR) + return; + + if (mode) + { + /* start */ + __profil((void *) p->kcount, p->kcountsize, p->lowpc, s_scale); + p->state = GMON_PROF_ON; + } + else + { + /* stop */ + __profil(NULL, 0, 0, 0); + p->state = GMON_PROF_OFF; + } +} +weak_alias (__moncontrol, moncontrol) + + +void +__monstartup (u_long lowpc, u_long highpc) +{ + register int o; + char *cp; + struct gmonparam *p = &_gmonparam; + int linesz; + + /* + * round lowpc and highpc to multiples of the density we're using + * so the rest of the scaling (here and in gprof) stays in ints. + */ + p->lowpc = ROUNDDOWN(lowpc, HISTFRACTION * sizeof(HISTCOUNTER)); + if (sizeof *p->froms % sizeof(HISTCOUNTER) != 0) + { + p->highpc = ROUNDUP(highpc, HISTFRACTION * sizeof(HISTCOUNTER)); + p->textsize = p->highpc - p->lowpc; + p->kcountsize = ROUNDUP((p->textsize + HISTFRACTION - 1) / HISTFRACTION, + sizeof (*p->froms)); + } + else + { + /* Avoid odd scales by rounding up highpc to get kcountsize rounded. */ + p->textsize = ROUNDUP (highpc - p->lowpc, + HISTFRACTION * sizeof (*p->froms)); + p->highpc = p->lowpc + p->textsize; + p->kcountsize = p->textsize / HISTFRACTION; + } + p->hashfraction = HASHFRACTION; + p->log_hashfraction = -1; + /* The following test must be kept in sync with the corresponding + test in mcount.c. */ + if ((HASHFRACTION & (HASHFRACTION - 1)) == 0) { + /* if HASHFRACTION is a power of two, mcount can use shifting + instead of integer division. Precompute shift amount. */ + p->log_hashfraction = ffs(p->hashfraction * sizeof(*p->froms)) - 1; + } + p->tolimit = p->textsize * ARCDENSITY / 100; + if (p->tolimit < MINARCS) + p->tolimit = MINARCS; + else if (p->tolimit > MAXARCS) + p->tolimit = MAXARCS; + p->tossize = p->tolimit * sizeof(struct tostruct); + + /* p->kcount must not share cache lines with the adjacent data, because + we use uncached accesses while profiling. */ + linesz = __dcache_linesz (); + cp = calloc (ROUNDUP (p->kcountsize, linesz) + p->tossize + + (linesz - 1), 1); + if (! cp) + { + ERR("monstartup: out of memory\n"); + p->tos = NULL; + p->state = GMON_PROF_ERROR; + /* In case we loose the error state due to a race, + prevent invalid writes also by clearing tolimit. */ + p->tolimit = 0; + return; + } + p->tos = (struct tostruct *)cp; + cp += p->tossize; + cp = (char *) ROUNDUP ((ptrdiff_t) cp, linesz); + p->kcount = (HISTCOUNTER *)cp; + cp += ROUNDUP (p->kcountsize, linesz); + + p->tos[0].link = 0; + + o = p->highpc - p->lowpc; + if (p->kcountsize < (u_long) o) + { +#ifndef hp300 + s_scale = ((float)p->kcountsize / o ) * SCALE_1_TO_1; +#else + /* avoid floating point operations */ + int quot = o / p->kcountsize; + + if (quot >= 0x10000) + s_scale = 1; + else if (quot >= 0x100) + s_scale = 0x10000 / quot; + else if (o >= 0x800000) + s_scale = 0x1000000 / (o / (p->kcountsize >> 8)); + else + s_scale = 0x1000000 / ((o << 8) / p->kcountsize); +#endif + } else + s_scale = SCALE_1_TO_1; + + __moncontrol(1); +} +weak_alias (__monstartup, monstartup) + + +static void +internal_function +write_hist (int fd) +{ + u_char tag = GMON_TAG_TIME_HIST; + struct arc_gmon_hist_hdr thdr __attribute__ ((aligned (__alignof__ (char *)))); + int r; + + if (_gmonparam.kcountsize > 0) + { + *(char **) thdr.low_pc = (char *) _gmonparam.lowpc; + *(char **) thdr.high_pc = (char *) _gmonparam.highpc; + *(int32_t *) thdr.hist_size = (_gmonparam.kcountsize + / sizeof (HISTCOUNTER)); + *(int32_t *) thdr.prof_rate = __profile_frequency (); + strncpy (thdr.dimen, "seconds", sizeof (thdr.dimen)); + thdr.dimen_abbrev = 's'; + + r = write (fd, &tag, sizeof tag); + if (r != sizeof tag) + return; + r = write (fd, &thdr, sizeof thdr); + if (r != sizeof thdr) + return; + r = write (fd,_gmonparam.kcount, _gmonparam.kcountsize); + if ((unsigned) r != _gmonparam.kcountsize) + return; + } +} + + +static void +internal_function +write_call_graph (int fd) +{ +#define NARCS_PER_WRITE 64 +#define BYTES_PER_ARC (1 + sizeof (struct gmon_cg_arc_record)) +#define BYTES_PER_WRITE (BYTES_PER_ARC * NARCS_PER_WRITE) + ARCINDEX to_index; + u_long frompc, selfpc, count; + char buffer[BYTES_PER_WRITE], *p; + u_long *prof_desc = __arc_profile_desc_secstart; + u_long *prof_count = __arc_profile_counters_secstart; + u_long *prof_desc_end = __arc_profile_desc_secend; + u_long *prof_forward = __arc_profile_forward_secstart; + + for (p = buffer; p < buffer + BYTES_PER_WRITE; p += BYTES_PER_ARC) + *p = GMON_TAG_CG_ARC; + p = buffer; + frompc = *prof_desc++ & -2; + while (prof_desc < prof_desc_end) + { + selfpc = *prof_desc++; + if (selfpc & 1) + { + frompc = selfpc & -2; + selfpc = *prof_desc++; + } + count = *prof_count++; + if (selfpc) + { + struct arc + { + char *frompc; + char *selfpc; + int32_t count; + } + arc; + + if (!count) + continue; + arc.frompc = (char *) frompc; + arc.selfpc = (char *) selfpc; + arc.count = count; + memcpy (p + 1, &arc, sizeof arc); + p += 1 + sizeof arc; + + if (p == buffer + BYTES_PER_WRITE) + { + write (fd, buffer, BYTES_PER_WRITE); + p = buffer; + } + } + else + { + for (to_index = count; + to_index != 0; + to_index = _gmonparam.tos[to_index].link) + { + struct arc + { + char *frompc; + char *selfpc; + int32_t count; + } + arc; + + arc.frompc = (char *) frompc; + arc.selfpc = (char *) _gmonparam.tos[to_index].selfpc; + arc.count = _gmonparam.tos[to_index].count; + memcpy (p + 1, &arc, sizeof arc); + p += 1 + sizeof arc; + + if (p == buffer + BYTES_PER_WRITE) + { + write (fd, buffer, BYTES_PER_WRITE); + p = buffer; + } + } + } + } + while (prof_forward < __arc_profile_forward_secend) + { + /* ??? The 'call count' is actually supposed to be a fixed point + factor, with 16 bits each before and after the point. + It would be much nicer if we figured out the actual number + of calls to the caller, and multiplied that with the fixed point + factor to arrive at the estimated calls for the callee. */ + memcpy (p + 1, prof_forward, 3 * sizeof *prof_forward); + prof_forward += 3; + p += 1 + 3 * sizeof *prof_forward; + if (p == buffer + BYTES_PER_WRITE) + { + write (fd, buffer, BYTES_PER_WRITE); + p = buffer; + } + } + if (p != buffer) + write (fd, buffer, p - buffer); +} + + +static void +internal_function +write_bb_counts (int fd) +{ + struct __bb *grp; + u_char tag = GMON_TAG_BB_COUNT; + size_t ncounts; + size_t i; + + struct { unsigned long address; long count; } bbbody[8]; + size_t nfilled; + + /* Write each group of basic-block info (all basic-blocks in a + compilation unit form a single group). */ + + for (grp = __bb_head; grp; grp = grp->next) + { + ncounts = grp->ncounts; + write (fd, &tag, 1); + write (fd, &ncounts, sizeof ncounts); + for (nfilled = i = 0; i < ncounts; ++i) + { + if (nfilled == sizeof (bbbody) / sizeof (bbbody[0])) + { + write (fd, bbbody, sizeof bbbody); + nfilled = 0; + } + + bbbody[nfilled].address = grp->addresses[i]; + bbbody[nfilled++].count = grp->counts[i]; + } + if (nfilled > 0) + write (fd, bbbody, nfilled * sizeof bbbody[0]); + } +} + + +static void +write_gmon (void) +{ + struct gmon_hdr ghdr __attribute__ ((aligned (__alignof__ (int)))); + int fd = -1; + char *env; + +#ifndef O_NOFOLLOW +# define O_NOFOLLOW 0 +#endif + + env = getenv ("GMON_OUT_PREFIX"); + if (env != NULL && !__libc_enable_secure) + { + size_t len = strlen (env); + char buf[len + 20]; + snprintf (buf, sizeof (buf), "%s.%u", env, getpid ()); + fd = open (buf, O_CREAT|O_TRUNC|O_WRONLY|O_NOFOLLOW, 0666); + } + + if (fd == -1) + { + fd = open ("gmon.out", O_CREAT|O_TRUNC|O_WRONLY|O_NOFOLLOW, + 0666); + if (fd < 0) + { + perror ("_mcleanup: gmon.out"); + return; + } + } + + /* write gmon.out header: */ + memset (&ghdr, '\0', sizeof (struct gmon_hdr)); + memcpy (&ghdr.cookie[0], GMON_MAGIC, sizeof (ghdr.cookie)); + *(int32_t *) ghdr.version = GMON_VERSION; + write (fd, &ghdr, sizeof (struct gmon_hdr)); + + /* write PC histogram: */ + write_hist (fd); + + /* write call-graph: */ + write_call_graph (fd); + + /* write basic-block execution counts: */ + write_bb_counts (fd); + + close (fd); +} + + +void +__write_profiling (void) +{ + int save = _gmonparam.state; + _gmonparam.state = GMON_PROF_OFF; + if (save == GMON_PROF_ON) + write_gmon (); + _gmonparam.state = save; +} +#ifndef SHARED +/* This symbol isn't used anywhere in the DSO and it is not exported. + This would normally mean it should be removed to get the same API + in static libraries. But since profiling is special in static libs + anyway we keep it. But not when building the DSO since some + quality assurance tests will otherwise trigger. */ +weak_alias (__write_profiling, write_profiling) +#endif + + +void +_mcleanup (void) +{ + __moncontrol (0); + + if (_gmonparam.state != GMON_PROF_ERROR) + write_gmon (); + + /* free the memory. */ + if (_gmonparam.tos != NULL) + free (_gmonparam.tos); +} diff --git a/libgcc/config/arc/gmon/machine-gmon.h b/libgcc/config/arc/gmon/machine-gmon.h new file mode 100644 index 00000000000..25ad0dd2882 --- /dev/null +++ b/libgcc/config/arc/gmon/machine-gmon.h @@ -0,0 +1,65 @@ +/* Copyright (C) 2007-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#ifndef MACHINE_GMON_H +#define MACHINE_GMON_H + +/* We can't fake out own <sys/types.h> header because the newlib / uclibc + headers in GCC_FOR_TARGET take precedence. */ + +#define __BEGIN_DECLS +#define __END_DECLS + +#define __THROW + +extern int __dcache_linesz (void); + +#define _MCOUNT_DECL(countp, selfpc) \ + static inline void _mcount_internal (void *countp, u_long selfpc) + +extern void _mcount (void); +extern void _mcount_call (void); + +/* N.B.: the calling point might be a sibcall, thus blink does not necessarily + hold the caller's address. r8 doesn't hold the caller's address, either, + but rather a pointer to the counter data structure associated with the + caller. + This function must be compiled with optimization turned on in order to + enable a sibcall for the final call to selfpc; this is important when trying + to profile a program with deep tail-recursion that would get a stack + overflow otherwise. */ +#define MCOUNT \ +void \ +_mcount_call (void) \ +{ \ + register void *countp __asm("r8"); \ + register u_long selfpc __asm("r9"); \ + _mcount_internal (countp, selfpc); \ + ((void (*)(void)) selfpc) (); \ +} + +extern int __profil (u_short *,size_t, size_t, u_int); + +#endif /* MACHINE_GMON_H */ diff --git a/libgcc/config/arc/gmon/mcount.c b/libgcc/config/arc/gmon/mcount.c new file mode 100644 index 00000000000..c99dcd7bd7e --- /dev/null +++ b/libgcc/config/arc/gmon/mcount.c @@ -0,0 +1,206 @@ +/*- + * Copyright (c) 1983, 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Copyright (C) 2007-2013 Free Software Foundation, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#if !defined(lint) && !defined(KERNEL) && defined(LIBC_SCCS) +static char sccsid[] = "@(#)mcount.c 8.1 (Berkeley) 6/4/93"; +#endif + +#if 0 +#include <unistd.h> +#include <sys/param.h> +#endif +#include <sys/gmon.h> + +/* This file provides the machine-dependent definitions of the _MCOUNT_DECL + and MCOUNT macros. */ +#include <machine-gmon.h> + +#include <atomic.h> + +/* + * mcount is called on entry to each function compiled with the profiling + * switch set. _mcount(), which is declared in a machine-dependent way + * with _MCOUNT_DECL, does the actual work and is either inlined into a + * C routine or called by an assembly stub. In any case, this magic is + * taken care of by the MCOUNT definition in <machine/profile.h>. + * + * _mcount updates data structures that represent traversals of the + * program's call graph edges. frompc and selfpc are the return + * address and function address that represents the given call graph edge. + * + * Note: the original BSD code used the same variable (frompcindex) for + * both frompcindex and frompc. Any reasonable, modern compiler will + * perform this optimization. + */ +_MCOUNT_DECL(count_ptr, selfpc) /* _mcount; may be static, inline, etc */ +{ + register ARCINDEX *frompcindex; + register struct tostruct *top, *prevtop; + register struct gmonparam *p; + register ARCINDEX toindex; + + /* Check for nested function trampoline. */ + if (selfpc & 2) + selfpc = *(u_long *) (selfpc + 10); + + p = &_gmonparam; + /* + * check that we are profiling + * and that we aren't recursively invoked. + */ +#if 0 + if (catomic_compare_and_exchange_bool_acq (&p->state, GMON_PROF_BUSY, + GMON_PROF_ON)) + return; +#elif defined (__ARC700__) +/* ??? This could temporarily lose the ERROR / OFF condition in a race, + but doing an actual compare_and_exchange would be too costly. It would + be better if we had a semaphore independent of the 'sticky' state, but + then we could run into ABI compatibility problems with the size of struct + gmonparam. */ + { + u_long old_state; + + __asm ("ex %0,%1": "=r" (old_state), "+m" (p->state) + : "0" (GMON_PROF_BUSY)); + if (old_state != GMON_PROF_ON) + { + switch (old_state) + { + case GMON_PROF_OFF: + __asm ("ex %0,%1": "+r" (old_state), "+m" (p->state)); + if (old_state == GMON_PROF_BUSY + /* Switching off while we say we are busy while profiling + was actually already switched off is all right. */ + || old_state == GMON_PROF_OFF) + break; + /* It is not clear if we should allow switching on + profiling at this point, and how to handle further races. + For now, record an error in this case. */ + /* Fall through. */ + default: /* We expect here only GMON_PROF_ERROR. */ + p->state = GMON_PROF_ERROR; + break; + case GMON_PROF_BUSY: break; + } + return; + } + } +#else /* ??? No semaphore primitives available. */ + if (p->state != GMON_PROF_ON) + return; + p->state = GMON_PROF_BUSY; +#endif + + frompcindex = count_ptr; + toindex = *frompcindex; + if (toindex == 0) { + /* + * first time traversing this arc + */ + toindex = ++p->tos[0].link; + if (toindex >= (ARCINDEX) p->tolimit) + /* halt further profiling */ + goto overflow; + + *frompcindex = toindex; + top = &p->tos[toindex]; + top->selfpc = selfpc; + top->count = 1; + top->link = 0; + goto done; + } + top = &p->tos[toindex]; + if (top->selfpc == selfpc) { + /* + * arc at front of chain; usual case. + */ + top->count++; + goto done; + } + /* + * have to go looking down chain for it. + * top points to what we are looking at, + * prevtop points to previous top. + * we know it is not at the head of the chain. + */ + for (; /* goto done */; ) { + if (top->link == 0) { + /* + * top is end of the chain and none of the chain + * had top->selfpc == selfpc. + * so we allocate a new tostruct + * and link it to the head of the chain. + */ + toindex = ++p->tos[0].link; + if (toindex >= (ARCINDEX) p->tolimit) + goto overflow; + + top = &p->tos[toindex]; + top->selfpc = selfpc; + top->count = 1; + top->link = *frompcindex; + *frompcindex = toindex; + goto done; + } + /* + * otherwise, check the next arc on the chain. + */ + prevtop = top; + top = &p->tos[top->link]; + if (top->selfpc == selfpc) { + /* + * there it is. + * increment its count + * move it to the head of the chain. + */ + top->count++; + toindex = prevtop->link; + prevtop->link = top->link; + top->link = *frompcindex; + *frompcindex = toindex; + goto done; + } + + } +done: + p->state = GMON_PROF_ON; + return; +overflow: + p->state = GMON_PROF_ERROR; + return; +} + +/* + * Actual definition of mcount function. Defined in <machine/profile.h>, + * which is included by <sys/gmon.h>. + */ +MCOUNT diff --git a/libgcc/config/arc/gmon/prof-freq-stub.S b/libgcc/config/arc/gmon/prof-freq-stub.S new file mode 100644 index 00000000000..dc9ec681b36 --- /dev/null +++ b/libgcc/config/arc/gmon/prof-freq-stub.S @@ -0,0 +1,40 @@ +/* This file contains code to do profiling. + + Copyright (C) 2007-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "../asm.h" +/* This file contains code to do profiling. */ + .weak __profile_frequency_value + .global __profile_frequency_value + .set __profile_frequency_value, 1000 + .text + .balign 4 + .global __profile_frequency + FUNC(__profile_frequency) +__profile_frequency: + mov_s r0,__profile_frequency_value + j_s [blink] + ENDFUNC(__profile_frequency) diff --git a/libgcc/config/arc/gmon/prof-freq.c b/libgcc/config/arc/gmon/prof-freq.c new file mode 100644 index 00000000000..39395b1acd3 --- /dev/null +++ b/libgcc/config/arc/gmon/prof-freq.c @@ -0,0 +1,60 @@ +/* Return frequency of ticks reported by profil. Generic version. */ +/*- + * Copyright (c) 1983, 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Copyright (C) 2007-2013 Free Software Foundation, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <sys/types.h> +#include <sys/time.h> +#if 0 +#include <libc-internal.h> +#else +#include "sys/gmon.h" +#endif + +int +__profile_frequency (void) +{ + /* + * Discover the tick frequency of the machine if something goes wrong, + * we return 0, an impossible hertz. + */ + struct itimerval tim; + + tim.it_interval.tv_sec = 0; + tim.it_interval.tv_usec = 1; + tim.it_value.tv_sec = 0; + tim.it_value.tv_usec = 0; + setitimer(ITIMER_REAL, &tim, 0); + setitimer(ITIMER_REAL, 0, &tim); + if (tim.it_interval.tv_usec < 2) + return 0; + return (1000000 / tim.it_interval.tv_usec); +} diff --git a/libgcc/config/arc/gmon/profil.S b/libgcc/config/arc/gmon/profil.S new file mode 100644 index 00000000000..3835fe37944 --- /dev/null +++ b/libgcc/config/arc/gmon/profil.S @@ -0,0 +1,153 @@ +/* This file contains code to do profiling. + + Copyright (C) 2007-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "../asm.h" +#include "auxreg.h" +/* This file contains code to do profiling. */ + .weak __profile_timer_cycles + .global __profile_timer_cycles + .set __profile_timer_cycles, 200 + + .section .bss + .global __profil_offset + .align 4 + .type __profil_offset, @object + .size __profil_offset, 4 +__profil_offset: + .zero 4 + + .text + .global __dcache_linesz + .global __profil + FUNC(__profil) +.Lstop_profiling: + sr r0,[CONTROL0] + j_s [blink] + .balign 4 +__profil: +.Lprofil: + breq_s r0,0,.Lstop_profiling + ; r0: buf r1: bufsiz r2: offset r3: scale + bxor.f r3,r3,15; scale must be 0x8000, i.e. 1/2; generate 0. + push_s blink + lsr_s r2,r2,1 + mov_s r8,r0 + flag.ne 1 ; halt if wrong scale + sub_s r0,r0,r2 + st r0,[__profil_offset] + bl __dcache_linesz + pop_s blink + bbit1.d r0,0,nocache + mov_s r0,r8 +#ifdef __ARC700__ + add_s r1,r1,31 + lsr.f lp_count,r1,5 + lpne 2f + sr r0,[DC_FLDL] + add_s r0,r0,32 +#else /* !__ARC700__ */ +# FIX ME: set up loop according to cache line size + lr r12,[D_CACHE_BUILD] + sub_s r0,r0,16 + sub_s r1,r1,1 + lsr_s r12,r12,16 + asr_s r1,r1,4 + bmsk_s r12,r12,3 + asr_s r1,r1,r12 + add.f lp_count,r1,1 + mov_s r1,16 + asl_s r1,r1,r12 + lpne 2f + add r0,r0,r1 + sr r0,[DC_FLDL] +#endif /* __ARC700__ */ +2: b_s .Lcounters_cleared +nocache: +.Lcounters_cleared: + lr r1,[INT_VECTOR_BASE] ; disable timer0 interrupts + sr r3,[CONTROL0] + sr r3,[COUNT0] +0: ld_s r0,[pcl,1f-0b+((0b-.Lprofil) & 2)] ; 1f@GOTOFF +0: ld_s r12,[pcl,1f+4-0b+((0b-.Lprofil) & 2)] ; 1f@GOTOFF + 4 + st_s r0,[r1,24]; timer0 uses vector3 + st_s r12,[r1,24+4]; timer0 uses vector3 + ;sr 10000,[LIMIT0] + sr __profile_timer_cycles,[LIMIT0] + mov_s r12,3 ; enable timer interrupts; count only when not halted. + sr r12,[CONTROL0] + lr r12,[STATUS32] + bset_s r12,r12,1 ; allow level 1 interrupts + flag r12 + mov_s r0,0 + j_s [blink] + .balign 4 +1: j __profil_irq + ENDFUNC(__profil) + + FUNC(__profil_irq) + .balign 4 ; make final jump unaligned to avoid delay penalty + .balign 32,0,12 ; make sure the code spans no more that two cache lines + nop_s +__profil_irq: + push_s r0 + ld r0,[__profil_offset] + push_s r1 + lsr r1,ilink1,2 + push_s r2 + ldw.as.di r2,[r0,r1] + add1 r0,r0,r1 + ld_s r1,[sp,4] + add_s r2,r2,1 + bbit1 r2,16,nostore + stw.di r2,[r0] +nostore:ld.ab r2,[sp,8] + pop_s r0 + j.f [ilink1] + ENDFUNC(__profil_irq) + +; could save one cycle if the counters were allocated at link time and +; the contents of __profil_offset were pre-computed at link time, like this: +#if 0 +; __profil_offset needs to be PROVIDEd as __profile_base-text/4 + .global __profil_offset + .balign 4 +__profil_irq: + push_s r0 + lsr r0,ilink1,2 + add1 r0,__profil_offset,r0 + push_s r1 + ldw.di r1,[r0] + + + add_s r1,r1,1 + bbit1 r1,16,nostore + stw.di r1,[r0] +nostore:pop_s r1 + pop_s r0 + j [ilink1] +#endif /* 0 */ diff --git a/libgcc/config/arc/gmon/sys/gmon.h b/libgcc/config/arc/gmon/sys/gmon.h new file mode 100644 index 00000000000..03171136281 --- /dev/null +++ b/libgcc/config/arc/gmon/sys/gmon.h @@ -0,0 +1,217 @@ +/*- + * Copyright (c) 1982, 1986, 1992, 1993 + * The Regents of the University of California. All rights reserved. + * Copyright (C) 2007-2013 Free Software Foundation, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)gmon.h 8.2 (Berkeley) 1/4/94 + */ + +#ifndef _SYS_GMON_H +#define _SYS_GMON_H 1 + +#if 0 +#include <features.h> +#include <sys/types.h> +#else +#include <sys/types.h> +#include "machine-gmon.h" +#define attribute_hidden __attribute__ ((visibility("hidden"))) +#endif + +#include <stdint.h> + +/* + * See gmon_out.h for gmon.out format. + */ + +/* structure emitted by "gcc -a". This must match struct bb in + gcc/libgcc2.c. It is OK for gcc to declare a longer structure as + long as the members below are present. */ +struct __bb +{ + long zero_word; + const char *filename; + long *counts; + long ncounts; + struct __bb *next; + const unsigned long *addresses; +}; + +extern struct __bb *__bb_head; + +/* + * histogram counters are unsigned shorts (according to the kernel). + */ +#define HISTCOUNTER unsigned short + +/* + * fraction of text space to allocate for histogram counters here, 1/2 + */ +#define HISTFRACTION 2 + +/* + * Fraction of text space to allocate for from hash buckets. + * The value of HASHFRACTION is based on the minimum number of bytes + * of separation between two subroutine call points in the object code. + * Given MIN_SUBR_SEPARATION bytes of separation the value of + * HASHFRACTION is calculated as: + * + * HASHFRACTION = MIN_SUBR_SEPARATION / (2 * sizeof(short) - 1); + * + * For example, on the VAX, the shortest two call sequence is: + * + * calls $0,(r0) + * calls $0,(r0) + * + * which is separated by only three bytes, thus HASHFRACTION is + * calculated as: + * + * HASHFRACTION = 3 / (2 * 2 - 1) = 1 + * + * Note that the division above rounds down, thus if MIN_SUBR_FRACTION + * is less than three, this algorithm will not work! + * + * In practice, however, call instructions are rarely at a minimal + * distance. Hence, we will define HASHFRACTION to be 2 across all + * architectures. This saves a reasonable amount of space for + * profiling data structures without (in practice) sacrificing + * any granularity. + */ +#define HASHFRACTION 2 + +/* + * Percent of text space to allocate for tostructs. + * This is a heuristic; we will fail with a warning when profiling programs + * with a very large number of very small functions, but that's + * normally OK. + * 2 is probably still a good value for normal programs. + * Profiling a test case with 64000 small functions will work if + * you raise this value to 3 and link statically (which bloats the + * text size, thus raising the number of arcs expected by the heuristic). + */ +#define ARCDENSITY 3 + +/* + * Always allocate at least this many tostructs. This + * hides the inadequacy of the ARCDENSITY heuristic, at least + * for small programs. + */ +#define MINARCS 50 + +/* + * The type used to represent indices into gmonparam.tos[]. + */ +#define ARCINDEX u_long + +/* + * Maximum number of arcs we want to allow. + * Used to be max representable value of ARCINDEX minus 2, but now + * that ARCINDEX is a long, that's too large; we don't really want + * to allow a 48 gigabyte table. + * The old value of 1<<16 wasn't high enough in practice for large C++ + * programs; will 1<<20 be adequate for long? FIXME + */ +#define MAXARCS (1 << 20) + +struct tostruct { + u_long selfpc; + long count; + ARCINDEX link; +}; + +/* + * a raw arc, with pointers to the calling site and + * the called site and a count. + */ +struct rawarc { + u_long raw_frompc; + u_long raw_selfpc; + long raw_count; +}; + +/* + * general rounding functions. + */ +#define ROUNDDOWN(x,y) (((x)/(y))*(y)) +#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y)) + +/* + * The profiling data structures are housed in this structure. + */ +struct gmonparam { + long int state; + u_short *kcount; + u_long kcountsize; + ARCINDEX *froms; + u_long fromssize; + struct tostruct *tos; + u_long tossize; + long tolimit; + u_long lowpc; + u_long highpc; + u_long textsize; + u_long hashfraction; + long log_hashfraction; +}; +extern struct gmonparam _gmonparam; + +/* + * Possible states of profiling. + */ +#define GMON_PROF_ON 0 +#define GMON_PROF_BUSY 1 +#define GMON_PROF_ERROR 2 +#define GMON_PROF_OFF 3 + +/* + * Sysctl definitions for extracting profiling information from the kernel. + */ +#define GPROF_STATE 0 /* int: profiling enabling variable */ +#define GPROF_COUNT 1 /* struct: profile tick count buffer */ +#define GPROF_FROMS 2 /* struct: from location hash bucket */ +#define GPROF_TOS 3 /* struct: destination/count structure */ +#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */ + +__BEGIN_DECLS + +/* Set up data structures and start profiling. */ +extern void __monstartup (u_long __lowpc, u_long __highpc) __THROW; +extern void monstartup (u_long __lowpc, u_long __highpc) __THROW; + +/* Clean up profiling and write out gmon.out. */ +extern void _mcleanup (void) __THROW; + +extern void __write_profiling (void); +extern int attribute_hidden __profile_frequency (void); + +extern u_long __arc_profile_desc_secstart[], __arc_profile_desc_secend[]; +extern u_long __arc_profile_forward_secstart[], __arc_profile_forward_secend[]; +extern u_long __arc_profile_counters_secstart[]; + +__END_DECLS + +#endif /* sys/gmon.h */ diff --git a/libgcc/config/arc/gmon/sys/gmon_out.h b/libgcc/config/arc/gmon/sys/gmon_out.h new file mode 100644 index 00000000000..ae38145b145 --- /dev/null +++ b/libgcc/config/arc/gmon/sys/gmon_out.h @@ -0,0 +1,55 @@ +/* Copyright (C) 2007-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#define GMON_TAG_TIME_HIST 0 +#define GMON_TAG_CG_ARC 1 +#define GMON_TAG_BB_COUNT 2 + +#define GMON_MAGIC "gmon" +#define GMON_VERSION 1 + +struct arc_gmon_hist_hdr +{ + char low_pc[4]; + char high_pc[4]; + char hist_size[4]; + char prof_rate[4]; + char dimen[15]; + char dimen_abbrev; +}; + +struct gmon_cg_arc_record +{ + char afrompc[4]; + char selfpc[4]; + char count[4]; +}; + +struct gmon_hdr +{ + char cookie[4]; + char version[4]; + char c[12]; +}; diff --git a/libgcc/config/arc/ieee-754/adddf3.S b/libgcc/config/arc/ieee-754/adddf3.S new file mode 100644 index 00000000000..d0a3b43359e --- /dev/null +++ b/libgcc/config/arc/ieee-754/adddf3.S @@ -0,0 +1,524 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" +#if 0 /* DEBUG */ + .global __adddf3 + .balign 4 +__adddf3: + push_s blink + push_s r2 + push_s r3 + push_s r0 + bl.d __adddf3_c + push_s r1 + ld_s r2,[sp,12] + ld_s r3,[sp,8] + st_s r0,[sp,12] + st_s r1,[sp,8] + pop_s r1 + bl.d __adddf3_asm + pop_s r0 + pop_s r3 + pop_s r2 + pop_s blink + cmp r0,r2 + cmp.eq r1,r3 + jeq_s [blink] + bl abort + .global __subdf3 + .balign 4 +__subdf3: + push_s blink + push_s r2 + push_s r3 + push_s r0 + bl.d __subdf3_c + push_s r1 + ld_s r2,[sp,12] + ld_s r3,[sp,8] + st_s r0,[sp,12] + st_s r1,[sp,8] + pop_s r1 + bl.d __subdf3_asm + pop_s r0 + pop_s r3 + pop_s r2 + pop_s blink + cmp r0,r2 + cmp.eq r1,r3 + jeq_s [blink] + bl abort +#define __adddf3 __adddf3_asm +#define __subdf3 __subdf3_asm +#endif /* DEBUG */ +/* N.B. This is optimized for ARC700. + ARC600 has very different scheduling / instruction selection criteria. */ + +/* inputs: DBL0, DBL1 (r0-r3) + output: DBL0 (r0, r1) + clobber: r2-r10, r12, flags + All NaN highword bits must be 1. NaN low word is random. */ + + .balign 4 + .global __adddf3 + .global __subdf3 + .long 0x7ff00000 ; exponent mask + FUNC(__adddf3) + FUNC(__subdf3) +__subdf3: + bxor_l DBL1H,DBL1H,31 +__adddf3: + ld r9,[pcl,-8] + bmsk r4,DBL0H,30 + xor r10,DBL0H,DBL1H + and r6,DBL1H,r9 + sub.f r12,r4,r6 + asr_s r12,r12,20 + blo .Ldbl1_gt + brhs r4,r9,.Linf_nan + brhs r12,32,.Large_shift + brne r12,0,.Lsmall_shift + brge r10,0,.Ladd_same_exp ; r12 == 0 + +/* After subtracting, we need to normalize; when shifting to place the + leading 1 into position for the implicit 1 and adding that to DBL0H, + we increment the exponent. Thus, we have to subtract one more than + the shift count from the exponent beforehand. Iff the exponent drops thus + below zero (before adding in the fraction with the leading one), we have + generated a denormal number. Denormal handling is basicallly reducing the + shift count so that we produce a zero exponent instead; however, this way + the shift count can become zero (if we started out with exponent 1). + Therefore, a simple min operation is not good enough, since we don't + want to handle a zero normalizing shift in the main path. + On the plus side, we don't need to check for denorm input, the result + of subtracing these looks just the same as denormals generated during + subtraction. */ + bmsk r7,DBL1H,30 + cmp r4,r7 + cmp.eq DBL0L,DBL1L + blo .L_rsub_same_exp + sub.f DBL0L,DBL0L,DBL1L + bmsk r12,DBL0H,19 + bic DBL1H,DBL0H,r12 + sbc.f r4,r4,r7 + beq_l .Large_cancel + norm DBL1L,r4 + b.d .Lsub_done_same_exp + sub r12,DBL1L,9 + + .balign 4 +.Linf_nan: + ; If both inputs are inf, but with different signs, the result is NaN. + asr r12,r10,31 + or_s DBL1H,DBL1H,r12 + j_s.d [blink] + or.eq DBL0H,DBL0H,DBL1H + + .balign 4 +.L_rsub_same_exp: + rsub.f DBL0L,DBL0L,DBL1L + bmsk r12,DBL1H,19 + bic_s DBL1H,DBL1H,r12 + sbc.f r4,r7,r4 + beq_l .Large_cancel + norm DBL1L,r4 + + sub r12,DBL1L,9 +.Lsub_done_same_exp: + asl_s r12,r12,20 + sub_s DBL1L,DBL1L,10 + sub DBL0H,DBL1H,r12 + xor.f 0,DBL0H,DBL1H + bmi .Ldenorm +.Lpast_denorm: + neg_s r12,DBL1L + lsr r7,DBL0L,r12 + asl r12,r4,DBL1L + asl_s DBL0L,DBL0L,DBL1L + add_s r12,r12,r7 + j_s.d [blink] + add_l DBL0H,DBL0H,r12 + .balign 4 +.Ladd_same_exp: + /* This is a special case because we can't test for need to shift + down by checking if bit 20 of DBL0H changes. OTOH, here we know + that we always need to shift down. */ + ; The implicit 1 of DBL0 is not shifted together with the + ; fraction, thus effectively doubled, compensating for not setting + ; implicit1 for DBL1 + add_s r12,DBL0L,DBL1L + lsr.f 0,r12,2 ; round to even + breq r6,0,.Ldenorm_add + adc.f DBL0L,DBL0L,DBL1L + sub r7,DBL1H,DBL0H + sub1 r7,r7,r9 ; boost exponent by 2/2 + rrc DBL0L,DBL0L + asr.f r7,r7 ; DBL1.fraction/2 - DBL0.fraction/2 ; exp++ + add.cs.f DBL0L,DBL0L,0x80000000 + add_l DBL0H,DBL0H,r7 ; DBL0.implicit1 not shifted for DBL1.implicit1 + add.cs DBL0H,DBL0H,1 + bic.f 0,r9,DBL0H ; check for overflow -> infinity. + jne_l [blink] + and DBL0H,DBL0H,0xfff00000 + j_s.d [blink] + mov_s DBL0L,0 + .balign 4 +.Large_shift: + brhs r12,55,.Lret_dbl0 + bmsk_s DBL1H,DBL1H,19 + brne r6,0,.Lno_denorm_large_shift + brhi.d r12,33,.Lfixed_denorm_large_shift + sub_s r12,r12,1 + breq r12,31, .Lfixed_denorm_small_shift +.Lshift32: + mov_s r12,DBL1L + mov_s DBL1L,DBL1H + brlt.d r10,0,.Lsub + mov_s DBL1H,0 + b_s .Ladd +.Ldenorm_add: + cmp_s r12,DBL1L + mov_s DBL0L,r12 + j_s.d [blink] + adc DBL0H,r4,DBL1H + +.Lret_dbl0: + j_s [blink] + .balign 4 +.Lsmall_shift: + breq.d r6,0,.Ldenorm_small_shift + bmsk_s DBL1H,DBL1H,19 + bset_s DBL1H,DBL1H,20 +.Lfixed_denorm_small_shift: + neg r8,r12 + asl r4,DBL1H,r8 + lsr_l DBL1H,DBL1H,r12 + lsr r5,DBL1L,r12 + asl r12,DBL1L,r8 + brge.d r10,0,.Ladd + or DBL1L,r4,r5 +/* subtract, abs(DBL0) > abs(DBL1) */ +/* DBL0H, DBL0L: original values + DBL1H, DBL1L: fraction with explicit leading 1, shifted into place + r4: orig. DBL0H & 0x7fffffff + r6: orig. DBL1H & 0x7ff00000 + r9: 0x7ff00000 + r10: orig. DBL0H ^ DBL1H + r12: guard bits */ + .balign 4 +.Lsub: + neg.f r12,r12 + mov_s r7,DBL1H + bmsk r5,DBL0H,19 + sbc.f DBL0L,DBL0L,DBL1L + bic DBL1H,DBL0H,r5 + bset r5,r5,20 + sbc.f r4,r5,r7 + beq_l .Large_cancel_sub + norm DBL1L,r4 + bmsk r6,DBL1H,30 +.Lsub_done: + sub_s DBL1L,DBL1L,9 + breq DBL1L,1,.Lsub_done_noshift + asl r5,DBL1L,20 + sub_s DBL1L,DBL1L,1 + brlo r6,r5,.Ldenorm_sub + sub DBL0H,DBL1H,r5 +.Lpast_denorm_sub: + neg_s DBL1H,DBL1L + lsr r6,r12,DBL1H + asl_s r12,r12,DBL1L + and r8,r6,1 + add1.f 0,r8,r12 + add.ne.f r12,r12,r12 + asl r8,DBL0L,DBL1L + lsr r12,DBL0L,DBL1H + adc.f DBL0L,r8,r6 + asl r5,r4,DBL1L + add_s DBL0H,DBL0H,r12 + j_s.d [blink] + adc DBL0H,DBL0H,r5 + + .balign 4 +.Lno_denorm_large_shift: + breq.d r12,32,.Lshift32 + bset_l DBL1H,DBL1H,20 +.Lfixed_denorm_large_shift: + neg r8,r12 + asl r4,DBL1H,r8 + lsr r5,DBL1L,r12 + asl.f 0,DBL1L,r8 + lsr DBL1L,DBL1H,r12 + or r12,r4,r5 + tst.eq r12,1 + or.ne r12,r12,2 + brlt.d r10,0,.Lsub + mov_s DBL1H,0 + b_l .Ladd + + ; If a denorm is produced without shifting, we have an exact result - + ; no need for rounding. + .balign 4 +.Ldenorm_sub: + lsr DBL1L,r6,20 + xor DBL0H,r6,DBL1H + brne.d DBL1L,1,.Lpast_denorm_sub + sub_s DBL1L,DBL1L,1 +.Lsub_done_noshift: + add.f 0,r12,r12 + btst.eq DBL0L,0 + cmp.eq r12,r12 + add.cs.f DBL0L,DBL0L,1 + bclr r4,r4,20 + j_s.d [blink] + adc DBL0H,DBL1H,r4 + + .balign 4 +.Ldenorm_small_shift: + brne.d r12,1,.Lfixed_denorm_small_shift + sub_l r12,r12,1 + brlt r10,0,.Lsub +.Ladd: ; bit 20 of DBL1H is clear and bit 0 of r12 does not matter + add.f DBL0L,DBL0L,DBL1L + add_s DBL1H,DBL1H,DBL0H + add.cs DBL1H,DBL1H,1 + xor_l DBL0H,DBL0H,DBL1H + bbit0 DBL0H,20,.Lno_shiftdown + lsr.f DBL0H,DBL1H + and r4,DBL0L,2 + bmsk DBL0H,DBL0H,18 + sbc DBL0H,DBL1H,DBL0H + rrc.f DBL0L,DBL0L + or.f r12,r12,r4 + cmp.eq r12,r12 + add.cs.f DBL0L,DBL0L,1 + bic.f 0,r9,DBL0H ; check for generating infinity with possible ... + jne.d [blink] ; ... non-zero fraction + add.cs DBL0H,DBL0H,1 + mov_s DBL0L,0 + bmsk DBL1H,DBL0H,19 + j_s.d [blink] + bic_s DBL0H,DBL0H,DBL1H +.Lno_shiftdown: + mov_s DBL0H,DBL1H + add.f 0,r12,r12 + btst.eq DBL0L,0 + cmp.eq r12,r12 + add.cs.f DBL0L,DBL0L,1 + j_s.d [blink] + add.cs DBL0H,DBL0H,1 + .balign 4 +.Ldenorm: + bmsk DBL0H,DBL1H,30 + lsr r12,DBL0H,20 + xor_s DBL0H,DBL0H,DBL1H + sub_l DBL1L,r12,1 + bgt .Lpast_denorm + j_s.d [blink] + add_l DBL0H,DBL0H,r4 + + .balign 4 +.Large_cancel: + ;DBL0L: mantissa DBL1H: sign & exponent + norm.f DBL1L,DBL0L + bmsk DBL0H,DBL1H,30 + add_s DBL1L,DBL1L,22 + mov.mi DBL1L,21 + add_s r12,DBL1L,1 + asl_s r12,r12,20 + beq_s .Lret0 + brhs.d DBL0H,r12,.Lpast_denorm_large_cancel + sub DBL0H,DBL1H,r12 + bmsk DBL0H,DBL1H,30 + lsr r12,DBL0H,20 + xor_s DBL0H,DBL0H,DBL1H + sub.f DBL1L,r12,1 + jle [blink] +.Lpast_denorm_large_cancel: + rsub.f r7,DBL1L,32 + lsr r7,DBL0L,r7 + asl_s DBL0L,DBL0L,DBL1L + mov.ls r7,DBL0L + add_s DBL0H,DBL0H,r7 + j_s.d [blink] + mov.ls DBL0L,0 +.Lret0: + j_s.d [blink] + mov_l DBL0H,0 + +/* r4:DBL0L:r12 : unnormalized result fraction + DBL1H: result sign and exponent */ +/* When seeing large cancellation, only the topmost guard bit might be set. */ + .balign 4 +.Large_cancel_sub: + norm.f DBL1L,DBL0L + bpnz.d 0f + bmsk DBL0H,DBL1H,30 + mov r5,22<<20 + bne.d 1f + mov_s DBL1L,21 + bset r5,r5,5+20 + add_s DBL1L,DBL1L,32 + brne r12,0,1f + j_s.d [blink] + mov_l DBL0H,0 + .balign 4 +0: add r5,DBL1L,23 + asl r5,r5,20 + add_s DBL1L,DBL1L,22 +1: brlo DBL0H,r5,.Ldenorm_large_cancel_sub + sub DBL0H,DBL1H,r5 +.Lpast_denorm_large_cancel_sub: + rsub.f r7,DBL1L,32 + lsr r12,r12,r7 + lsr r7,DBL0L,r7 + asl_s DBL0L,DBL0L,DBL1L + add.ge DBL0H,DBL0H,r7 + add_s DBL0L,DBL0L,r12 + add.lt DBL0H,DBL0H,DBL0L + mov.eq DBL0L,r12 + j_s.d [blink] + mov.lt DBL0L,0 + .balign 4 +.Ldenorm_large_cancel_sub: + lsr r5,DBL0H,20 + xor_s DBL0H,DBL0H,DBL1H + brgt.d r5,1,.Lpast_denorm_large_cancel_sub + sub DBL1L,r5,1 + j_l [blink] ; denorm, no shift -> no rounding needed. + +/* r4: DBL0H & 0x7fffffff + r6: DBL1H & 0x7ff00000 + r9: 0x7ff00000 + r10: sign difference + r12: shift count (negative) */ + .balign 4 +.Ldbl1_gt: + brhs r6,r9,.Lret_dbl1 ; inf or NaN + neg r8,r12 + brhs r8,32,.Large_shift_dbl0 +.Lsmall_shift_dbl0: + breq.d r6,0,.Ldenorm_small_shift_dbl0 + bmsk_s DBL0H,DBL0H,19 + bset_s DBL0H,DBL0H,20 +.Lfixed_denorm_small_shift_dbl0: + asl r4,DBL0H,r12 + lsr DBL0H,DBL0H,r8 + lsr r5,DBL0L,r8 + asl r12,DBL0L,r12 + brge.d r10,0,.Ladd_dbl1_gt + or DBL0L,r4,r5 +/* subtract, abs(DBL0) < abs(DBL1) */ +/* DBL0H, DBL0L: fraction with explicit leading 1, shifted into place + DBL1H, DBL1L: original values + r6: orig. DBL1H & 0x7ff00000 + r9: 0x7ff00000 + r12: guard bits */ + .balign 4 +.Lrsub: + neg.f r12,r12 + bmsk r7,DBL1H,19 + mov_s r5,DBL0H + sbc.f DBL0L,DBL1L,DBL0L + bic DBL1H,DBL1H,r7 + bset r7,r7,20 + sbc.f r4,r7,r5 + beq_l .Large_cancel_sub + norm DBL1L,r4 + b_l .Lsub_done ; note: r6 is already set up. + +.Lret_dbl1: + mov_s DBL0H,DBL1H + j_s.d [blink] + mov_l DBL0L,DBL1L + .balign 4 +.Ldenorm_small_shift_dbl0: + sub.f r8,r8,1 + bne.d .Lfixed_denorm_small_shift_dbl0 + add_s r12,r12,1 + brlt r10,0,.Lrsub +.Ladd_dbl1_gt: ; bit 20 of DBL0H is clear and bit 0 of r12 does not matter + add.f DBL0L,DBL0L,DBL1L + add_s DBL0H,DBL0H,DBL1H + add.cs DBL0H,DBL0H,1 + xor DBL1H,DBL0H,DBL1H + bbit0 DBL1H,20,.Lno_shiftdown_dbl1_gt + lsr.f DBL1H,DBL0H + and r4,DBL0L,2 + bmsk DBL1H,DBL1H,18 + sbc DBL0H,DBL0H,DBL1H + rrc.f DBL0L,DBL0L + or.f r12,r12,r4 + cmp.eq r12,r12 + add.cs.f DBL0L,DBL0L,1 + bic.f 0,r9,DBL0H ; check for generating infinity with possible ... + jne.d [blink] ; ... non-zero fraction + add.cs DBL0H,DBL0H,1 + mov_s DBL0L,0 + bmsk DBL1H,DBL0H,19 + j_s.d [blink] + bic_s DBL0H,DBL0H,DBL1H +.Lno_shiftdown_dbl1_gt: + add.f 0,r12,r12 + btst.eq DBL0L,0 + cmp.eq r12,r12 + add.cs.f DBL0L,DBL0L,1 + j_s.d [blink] + add.cs DBL0H,DBL0H,1 + + .balign 4 +.Large_shift_dbl0: + brhs r8,55,.Lret_dbl1 + bmsk_s DBL0H,DBL0H,19 + brne r6,0,.Lno_denorm_large_shift_dbl0 + add_s r12,r12,1 + brne.d r8,33,.Lfixed_denorm_large_shift_dbl0 + sub r8,r8,1 + bset_s DBL0H,DBL0H,20 +.Lshift32_dbl0: + mov_s r12,DBL0L + mov_s DBL0L,DBL0H + brlt.d r10,0,.Lrsub + mov_s DBL0H,0 + b_s .Ladd_dbl1_gt + + .balign 4 +.Lno_denorm_large_shift_dbl0: + breq.d r8,32,.Lshift32_dbl0 + bset_l DBL0H,DBL0H,20 +.Lfixed_denorm_large_shift_dbl0: + asl r4,DBL0H,r12 + lsr r5,DBL0L,r8 + asl.f 0,DBL0L,r12 + lsr DBL0L,DBL0H,r8 + or r12,r4,r5 + tst.eq r12,1 + or.ne r12,r12,2 + brlt.d r10,0,.Lrsub + mov_s DBL0H,0 + b_l .Ladd_dbl1_gt + ENDFUNC(__adddf3) + ENDFUNC(__subdf3) diff --git a/libgcc/config/arc/ieee-754/addsf3.S b/libgcc/config/arc/ieee-754/addsf3.S new file mode 100644 index 00000000000..996a9732be1 --- /dev/null +++ b/libgcc/config/arc/ieee-754/addsf3.S @@ -0,0 +1,344 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" +#if 0 /* DEBUG */ + .global __addsf3 + FUNC(__addsf3) + .balign 4 +__addsf3: + push_s blink + push_s r1 + bl.d __addsf3_c + push_s r0 + ld_s r1,[sp,4] + st_s r0,[sp,4] + bl.d __addsf3_asm + pop_s r0 + pop_s r1 + pop_s blink + cmp r0,r1 + jeq_s [blink] + bl abort + ENDFUNC(__addsf3) + .global __subsf3 + FUNC(__subsf3) + .balign 4 +__subsf3: + push_s blink + push_s r1 + bl.d __subsf3_c + push_s r0 + ld_s r1,[sp,4] + st_s r0,[sp,4] + bl.d __subsf3_asm + pop_s r0 + pop_s r1 + pop_s blink + cmp r0,r1 + jeq_s [blink] + bl abort + ENDFUNC(__subsf3) +#define __addsf3 __addsf3_asm +#define __subsf3 __subsf3_asm +#endif /* DEBUG */ +/* N.B. This is optimized for ARC700. + ARC600 has very different scheduling / instruction selection criteria. */ + +/* inputs: r0, r1 + output: r0 + clobber: r1-r10, r12, flags */ + + .balign 4 + .global __addsf3 + .global __subsf3 + FUNC(__addsf3) + FUNC(__subsf3) + .long 0x7f800000 ; exponent mask +__subsf3: + bxor_l r1,r1,31 +__addsf3: + ld r9,[pcl,-8] + bmsk r4,r0,30 + xor r10,r0,r1 + and r6,r1,r9 + sub.f r12,r4,r6 + asr_s r12,r12,23 + blo .Ldbl1_gt + brhs r4,r9,.Linf_nan + brne r12,0,.Lsmall_shift + brge r10,0,.Ladd_same_exp ; r12 == 0 +/* After subtracting, we need to normalize; when shifting to place the + leading 1 into position for the implicit 1 and adding that to DBL0, + we increment the exponent. Thus, we have to subtract one more than + the shift count from the exponent beforehand. Iff the exponent drops thus + below zero (before adding in the fraction with the leading one), we have + generated a denormal number. Denormal handling is basicallly reducing the + shift count so that we produce a zero exponent instead; FWIW, this way + the shift count can become zero (if we started out with exponent 1). + On the plus side, we don't need to check for denorm input, the result + of subtracing these looks just the same as denormals generated during + subtraction. */ + bmsk r7,r1,30 + breq r4,r7,.Lret0 + sub.f r5,r4,r7 + lsr r12,r4,23 + neg.cs r5,r5 + norm r3,r5 + bmsk r2,r0,22 + sub_s r3,r3,6 + min r12,r12,r3 + bic r1,r0,r2 + sub_s r3,r12,1 + asl_s r12,r12,23 + asl r2,r5,r3 + sub_s r1,r1,r12 + add_s r0,r1,r2 + j_s.d [blink] + bxor.cs r0,r0,31 + .balign 4 +.Linf_nan: + ; If both inputs are inf, but with different signs, the result is NaN. + asr r12,r10,31 + or_s r1,r1,r12 + j_s.d [blink] + or.eq r0,r0,r1 + .balign 4 +.Ladd_same_exp: + /* This is a special case because we can't test for need to shift + down by checking if bit 23 of DBL0 changes. OTOH, here we know + that we always need to shift down. */ + ; adding the two floating point numbers together makes the sign + ; cancel out and apear as carry; the exponent is doubled, and the + ; fraction also in need of shifting left by one. The two implicit + ; ones of the sources make an implicit 1 of the result, again + ; non-existent in a place shifted by one. + add.f r0,r0,r1 + btst_s r0,1 + breq r6,0,.Ldenorm_add + add.ne r0,r0,1 ; round to even. + rrc r0,r0 + bmsk r1,r9,23 + add r0,r0,r1 ; increment exponent + bic.f 0,r9,r0; check for overflow -> infinity. + jne_l [blink] + mov_s r0,r9 + j_s.d [blink] + bset.cs r0,r0,31 + +.Ldenorm_add: + j_s.d [blink] + add r0,r4,r1 + +.Lret_dbl0: + j_s [blink] + + .balign 4 +.Lsmall_shift: + brhi r12,25,.Lret_dbl0 + breq.d r6,0,.Ldenorm_small_shift + bmsk_s r1,r1,22 + bset_s r1,r1,23 +.Lfixed_denorm_small_shift: + neg r8,r12 + asl r5,r1,r8 + brge.d r10,0,.Ladd + lsr_l r1,r1,r12 +/* subtract, abs(DBL0) > abs(DBL1) */ +/* DBL0: original values + DBL1: fraction with explicit leading 1, shifted into place + r4: orig. DBL0 & 0x7fffffff + r6: orig. DBL1 & 0x7f800000 + r9: 0x7f800000 + r10: orig. DBL0H ^ DBL1H + r5 : guard bits */ + .balign 4 +.Lsub: + neg.f r12,r5 + bmsk r3,r0,22 + bset r5,r3,23 + sbc.f r4,r5,r1 + beq.d .Large_cancel_sub + bic r7,r0,r3 + norm r3,r4 + bmsk r6,r7,30 +.Lsub_done: + sub_s r3,r3,6 + breq r3,1,.Lsub_done_noshift + asl r5,r3,23 + sub_l r3,r3,1 + brlo r6,r5,.Ldenorm_sub + sub r0,r7,r5 + neg_s r1,r3 + lsr.f r2,r12,r1 + asl_s r12,r12,r3 + btst_s r2,0 + bmsk.eq.f r12,r12,30 + asl r5,r4,r3 + add_s r0,r0,r2 + adc.ne r0,r0,0 + j_s.d [blink] + add_l r0,r0,r5 + +.Lret0: + j_s.d [blink] + mov_l r0,0 + + .balign 4 +.Ldenorm_small_shift: + brne.d r12,1,.Lfixed_denorm_small_shift + sub_s r12,r12,1 + brlt.d r10,0,.Lsub + mov_s r5,r12 ; zero r5, and align following code +.Ladd: ; Both bit 23 of DBL1 and bit 0 of r5 are clear. + bmsk r2,r0,22 + add_s r2,r2,r1 + bbit0.d r2,23,.Lno_shiftdown + add_s r0,r0,r1 + bic.f 0,r9,r0; check for overflow -> infinity; eq : infinity + bmsk r1,r2,22 + lsr.ne.f r2,r2,2; cc: even ; hi: might round down + lsr.ne r1,r1,1 + rcmp.hi r5,1; hi : round down + bclr.hi r0,r0,0 + j_l.d [blink] + sub_s r0,r0,r1 + +/* r4: DBL0H & 0x7fffffff + r6: DBL1H & 0x7f800000 + r9: 0x7f800000 + r10: sign difference + r12: shift count (negative) */ + .balign 4 +.Ldbl1_gt: + brhs r6,r9,.Lret_dbl1 ; inf or NaN + neg r8,r12 + brhi r8,25,.Lret_dbl1 +.Lsmall_shift_dbl0: + breq.d r6,0,.Ldenorm_small_shift_dbl0 + bmsk_s r0,r0,22 + bset_s r0,r0,23 +.Lfixed_denorm_small_shift_dbl0: + asl r5,r0,r12 + brge.d r10,0,.Ladd_dbl1_gt + lsr r0,r0,r8 +/* subtract, abs(DBL0) < abs(DBL1) */ +/* DBL0: fraction with explicit leading 1, shifted into place + DBL1: original value + r6: orig. DBL1 & 0x7f800000 + r9: 0x7f800000 + r5: guard bits */ + .balign 4 +.Lrsub: + neg.f r12,r5 + bmsk r5,r1,22 + bic r7,r1,r5 + bset r5,r5,23 + sbc.f r4,r5,r0 + bne.d .Lsub_done ; note: r6 is already set up. + norm r3,r4 + /* Fall through */ + +/* r4:r12 : unnormalized result fraction + r7: result sign and exponent */ +/* When seeing large cancellation, only the topmost guard bit might be set. */ + .balign 4 +.Large_cancel_sub: + breq_s r12,0,.Lret0 + sub r0,r7,24<<23 + xor.f 0,r0,r7 ; test if exponent is negative + tst.pl r9,r0 ; test if exponent is zero + jpnz [blink] ; return if non-denormal result + bmsk r6,r7,30 + lsr r3,r6,23 + xor r0,r6,r7 + sub_s r3,r3,24-22 + j_s.d [blink] + bset r0,r0,r3 + + ; If a denorm is produced, we have an exact result - + ; no need for rounding. + .balign 4 +.Ldenorm_sub: + sub r3,r6,1 + lsr.f r3,r3,23 + xor r0,r6,r7 + neg_s r1,r3 + asl.ne r4,r4,r3 + lsr_s r12,r12,r1 + add_s r0,r0,r4 + j_s.d [blink] + add.ne r0,r0,r12 + + .balign 4 +.Lsub_done_noshift: + add.f 0,r12,r12 + btst.eq r4,0 + bclr r4,r4,23 + add r0,r7,r4 + j_s.d [blink] + adc.ne r0,r0,0 + + .balign 4 +.Lno_shiftdown: + add.f 0,r5,r5 + btst.eq r0,0 + cmp.eq r5,r5 + j_s.d [blink] + add.cs r0,r0,1 + +.Lret_dbl1: + j_s.d [blink] + mov_l r0,r1 + .balign 4 +.Ldenorm_small_shift_dbl0: + sub.f r8,r8,1 + bne.d .Lfixed_denorm_small_shift_dbl0 + add_s r12,r12,1 + brlt.d r10,0,.Lrsub + mov r5,0 +.Ladd_dbl1_gt: ; both bit 23 of DBL0 and bit 0 of r5 are clear. + bmsk r2,r1,22 + add_s r2,r2,r0 + bbit0.d r2,23,.Lno_shiftdown_dbl1_gt + add_s r0,r1,r0 + bic.f 0,r9,r0; check for overflow -> infinity; eq : infinity + bmsk r1,r2,22 + lsr.ne.f r2,r2,2; cc: even ; hi: might round down + lsr.ne r1,r1,1 + rcmp.hi r5,1; hi : round down + bclr.hi r0,r0,0 + j_l.d [blink] + sub_s r0,r0,r1 + + .balign 4 +.Lno_shiftdown_dbl1_gt: + add.f 0,r5,r5 + btst.eq r0,0 + cmp.eq r5,r5 + j_s.d [blink] + add.cs r0,r0,1 + ENDFUNC(__addsf3) + ENDFUNC(__subsf3) diff --git a/libgcc/config/arc/ieee-754/arc-ieee-754.h b/libgcc/config/arc/ieee-754/arc-ieee-754.h new file mode 100644 index 00000000000..22fcb81bfa2 --- /dev/null +++ b/libgcc/config/arc/ieee-754/arc-ieee-754.h @@ -0,0 +1,56 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#ifdef __LITTLE_ENDIAN__ +#define DBL0L r0 +#define DBL0H r1 +#define DBL1L r2 +#define DBL1H r3 +#else +#define DBL0L r1 +#define DBL0H r0 +#define DBL1L r3 +#define DBL1H r2 +#endif +#define add_l add +#define asr_l asr +#define j_l j +#define jne_l jne +#define jeq_l jeq +#define or_l or +#define mov_l mov +#define b_l b +#define beq_l beq +#define bne_l bne +#define brne_l brne +#define bset_l bset +#define sub_l sub +#define sub1_l sub1 +#define lsr_l lsr +#define xor_l xor +#define bic_l bic +#define bmsk_l bmsk +#define bxor_l bxor +#define bcs_s blo_s diff --git a/libgcc/config/arc/ieee-754/arc600-dsp/divdf3.S b/libgcc/config/arc/ieee-754/arc600-dsp/divdf3.S new file mode 100644 index 00000000000..e54d31d87d1 --- /dev/null +++ b/libgcc/config/arc/ieee-754/arc600-dsp/divdf3.S @@ -0,0 +1,421 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* + to calculate a := b/x as b*y, with y := 1/x: + - x is in the range [1..2) + - calculate 15..18 bit inverse y0 using a table of approximating polynoms. + Precision is higher for polynoms used to evaluate input with larger + value. + - Do one newton-raphson iteration step to double the precision, + then multiply this with the divisor + -> more time to decide if dividend is subnormal + - the worst error propagation is on the side of the value range + with the least initial defect, thus giving us about 30 bits precision. + The truncation error for the either is less than 1 + x/2 ulp. + A 31 bit inverse can be simply calculated by using x with implicit 1 + and chaining the multiplies. For a 32 bit inverse, we multiply y0^2 + with the bare fraction part of x, then add in y0^2 for the implicit + 1 of x. + - If calculating a 31 bit inverse, the systematic error is less than + -1 ulp; likewise, for 32 bit, it is less than -2 ulp. + - If we calculate our seed with a 32 bit fraction, we can archive a + tentative result strictly better than -2 / +2.5 (1) ulp/128, i.e. we + only need to take the step to calculate the 2nd stage rest and + rounding adjust 1/32th of the time. However, if we use a 20 bit + fraction for the seed, the negative error can exceed -2 ulp/128, (2) + thus for a simple add / tst check, we need to do the 2nd stage + rest calculation/ rounding adjust 1/16th of the time. + (1): The inexactness of the 32 bit inverse contributes an error in the + range of (-1 .. +(1+x/2) ) ulp/128. Leaving out the low word of the + rest contributes an error < +1/x ulp/128 . In the interval [1,2), + x/2 + 1/x <= 1.5 . + (2): Unless proven otherwise. I have not actually looked for an + example where -2 ulp/128 is exceeded, and my calculations indicate + that the excess, if existent, is less than -1/512 ulp. + ??? The algorithm is still based on the ARC700 optimized code. + Maybe we could make better use of 32x16 bit multiply, or 64 bit multiply + results. + */ +#include "../arc-ieee-754.h" +#define mlo acc2 +#define mhi acc1 +#define mul64(b,c) mullw 0,b,c` machlw 0,b,c +#define mulu64(b,c) mululw 0,b,c` machulw 0,b,c + +/* N.B. fp-bit.c does double rounding on denormal numbers. */ +#if 0 /* DEBUG */ + .global __divdf3 + FUNC(__divdf3) + .balign 4 +__divdf3: + push_s blink + push_s r2 + push_s r3 + push_s r0 + bl.d __divdf3_c + push_s r1 + ld_s r2,[sp,12] + ld_s r3,[sp,8] + st_s r0,[sp,12] + st_s r1,[sp,8] + pop_s r1 + bl.d __divdf3_asm + pop_s r0 + pop_s r3 + pop_s r2 + pop_s blink + cmp r0,r2 + cmp.eq r1,r3 + jeq_s [blink] + and r12,DBL0H,DBL1H + bic.f 0,0x7ff80000,r12 ; both NaN -> OK + jeq_s [blink] + bl abort + ENDFUNC(__divdf3) +#define __divdf3 __divdf3_asm +#endif /* DEBUG */ + + FUNC(__divdf3) + .balign 4 +.L7ff00000: + .long 0x7ff00000 +.Ldivtab: + .long 0xfc0fffe1 + .long 0xf46ffdfb + .long 0xed1ffa54 + .long 0xe61ff515 + .long 0xdf7fee75 + .long 0xd91fe680 + .long 0xd2ffdd52 + .long 0xcd1fd30c + .long 0xc77fc7cd + .long 0xc21fbbb6 + .long 0xbcefaec0 + .long 0xb7efa100 + .long 0xb32f92bf + .long 0xae8f83b7 + .long 0xaa2f7467 + .long 0xa5ef6479 + .long 0xa1cf53fa + .long 0x9ddf433e + .long 0x9a0f3216 + .long 0x965f2091 + .long 0x92df0f11 + .long 0x8f6efd05 + .long 0x8c1eeacc + .long 0x88eed876 + .long 0x85dec615 + .long 0x82eeb3b9 + .long 0x800ea10b + .long 0x7d3e8e0f + .long 0x7a8e7b3f + .long 0x77ee6836 + .long 0x756e5576 + .long 0x72fe4293 + .long 0x709e2f93 + .long 0x6e4e1c7f + .long 0x6c0e095e + .long 0x69edf6c5 + .long 0x67cde3a5 + .long 0x65cdd125 + .long 0x63cdbe25 + .long 0x61ddab3f + .long 0x600d991f + .long 0x5e3d868c + .long 0x5c6d7384 + .long 0x5abd615f + .long 0x590d4ecd + .long 0x576d3c83 + .long 0x55dd2a89 + .long 0x545d18e9 + .long 0x52dd06e9 + .long 0x516cf54e + .long 0x4ffce356 + .long 0x4e9cd1ce + .long 0x4d3cbfec + .long 0x4becae86 + .long 0x4aac9da4 + .long 0x496c8c73 + .long 0x483c7bd3 + .long 0x470c6ae8 + .long 0x45dc59af + .long 0x44bc4915 + .long 0x43ac3924 + .long 0x428c27fb + .long 0x418c187a + .long 0x407c07bd + +__divdf3_support: /* This label makes debugger output saner. */ + .balign 4 +.Ldenorm_dbl1: + brge r6, \ + 0x43500000,.Linf_NaN ; large number / denorm -> Inf + bmsk.f r12,DBL1H,19 + mov.eq r12,DBL1L + mov.eq DBL1L,0 + sub.eq r7,r7,32 + norm.f r11,r12 ; flag for x/0 -> Inf check + beq_s .Linf_NaN + mov.mi r11,0 + add.pl r11,r11,1 + add_s r12,r12,r12 + asl r8,r12,r11 + rsub r12,r11,31 + lsr r12,DBL1L,r12 + tst_s DBL1H,DBL1H + or r8,r8,r12 + lsr r4,r8,26 + lsr DBL1H,r8,12 + ld.as r4,[r10,r4] + bxor.mi DBL1H,DBL1H,31 + sub r11,r11,11 + asl DBL1L,DBL1L,r11 + sub r11,r11,1 + mulu64 (r4,r8) + sub r7,r7,r11 + b.d .Lpast_denorm_dbl1 + asl r7,r7,20 + +.Linf_NaN: + tst_s DBL0L,DBL0L ; 0/0 -> NaN + xor_s DBL1H,DBL1H,DBL0H + bclr.eq.f DBL0H,DBL0H,31 + bmsk DBL0H,DBL1H,30 + xor_s DBL0H,DBL0H,DBL1H + sub.eq DBL0H,DBL0H,1 + mov_s DBL0L,0 + j_s.d [blink] + or DBL0H,DBL0H,r9 + .balign 4 +.Lret0_2: + xor_s DBL1H,DBL1H,DBL0H + mov_s DBL0L,0 + bmsk DBL0H,DBL1H,30 + j_s.d [blink] + xor_s DBL0H,DBL0H,DBL1H + .balign 4 + .global __divdf3 +/* N.B. the spacing between divtab and the sub3 to get its address must + be a multiple of 8. */ +__divdf3: + asl r8,DBL1H,12 + lsr r4,r8,26 + sub3 r10,pcl,51;(.-.Ldivtab) >> 3 + ld.as r9,[pcl,-104]; [pcl,(-((.-.L7ff00000) >> 2))] ; 0x7ff00000 + ld.as r4,[r10,r4] + lsr r12,DBL1L,20 + and.f r7,DBL1H,r9 + or r8,r8,r12 + mulu64 (r4,r8) + beq.d .Ldenorm_dbl1 +.Lpast_denorm_dbl1: + and.f r6,DBL0H,r9 + breq.d r7,r9,.Linf_nan_dbl1 + asl r4,r4,12 + sub r4,r4,mhi + mululw 0,r4,r4 + machulw r5,r4,r4 + bne.d .Lnormal_dbl0 + lsr r8,r8,1 + + .balign 4 +.Ldenorm_dbl0: + bmsk.f r12,DBL0H,19 + ; wb stall + mov.eq r12,DBL0L + sub.eq r6,r6,32 + norm.f r11,r12 ; flag for 0/x -> 0 check + brge r7, \ + 0x43500000, .Lret0_2 ; denorm/large number -> 0 + beq_s .Lret0_2 + mov.mi r11,0 + add.pl r11,r11,1 + asl r12,r12,r11 + sub r6,r6,r11 + add.f 0,r6,31 + lsr r10,DBL0L,r6 + mov.mi r10,0 + add r6,r6,11+32 + neg.f r11,r6 + asl DBL0L,DBL0L,r11 + mov.pl DBL0L,0 + sub r6,r6,32-1 + b.d .Lpast_denorm_dbl0 + asl r6,r6,20 + + .balign 4 +.Linf_nan_dbl1: ; 0/Inf -> NaN Inf/Inf -> NaN x/Inf-> 0 x/NaN -> NaN + or.f 0,r6,DBL0L + cmp.ne r6,r9 + not_s DBL0L,DBL1H + sub_s.ne DBL0L,DBL0L,DBL0L + tst_s DBL0H,DBL0H + add_s DBL0H,DBL1H,DBL0L + j_s.d [blink] + bxor.mi DBL0H,DBL0H,31 + + .balign 4 +.Lnormal_dbl0: + breq.d r6,r9,.Linf_nan_dbl0 + asl r12,DBL0H,11 + lsr r10,DBL0L,21 +.Lpast_denorm_dbl0: + bset r8,r8,31 + mulu64 (r5,r8) + add_s r12,r12,r10 + bset r5,r12,31 + cmp r5,r8 + cmp.eq DBL0L,DBL1L + lsr.cc r5,r5,1 + sub r4,r4,mhi ; u1.31 inverse, about 30 bit + mululw 0,r5,r4 + machulw r11,r5,r4 ; result fraction highpart + lsr r8,r8,2 ; u3.29 + add r5,r6, /* wait for immediate */ \ + 0x3fe00000 + mulu64 (r11,r8) ; u-28.31 + asl_s DBL1L,DBL1L,9 ; u-29.23:9 + sbc r6,r5,r7 + mov r12,mlo ; u-28.31 + mulu64 (r11,DBL1L) ; mhi: u-28.23:9 + add.cs DBL0L,DBL0L,DBL0L + asl_s DBL0L,DBL0L,6 ; u-26.25:7 + asl r10,r11,23 + sub_l DBL0L,DBL0L,r12 + lsr r7,r11,9 + sub r5,DBL0L,mhi ; rest msw ; u-26.31:0 + mul64 (r5,r4) ; mhi: result fraction lowpart + xor.f 0,DBL0H,DBL1H + and DBL0H,r6,r9 + add_s DBL0H,DBL0H,r7 + bclr r12,r9,20 ; 0x7fe00000 + brhs.d r6,r12,.Linf_denorm + bxor.mi DBL0H,DBL0H,31 + add.f r12,mhi,0x11 + asr r9,r12,5 + sub.mi DBL0H,DBL0H,1 + add.f DBL0L,r9,r10 + tst r12,0x1c + jne.d [blink] + add.cs DBL0H,DBL0H,1 + /* work out exact rounding if we fall through here. */ + /* We know that the exact result cannot be represented in double + precision. Find the mid-point between the two nearest + representable values, multiply with the divisor, and check if + the result is larger than the dividend. Since we want to know + only the sign bit, it is sufficient to calculate only the + highpart of the lower 64 bits. */ + mulu64 (r11,DBL1L) ; rest before considering r12 in r5 : -mlo + sub.f DBL0L,DBL0L,1 + asl r12,r9,2 ; u-22.30:2 + sub.cs DBL0H,DBL0H,1 + sub.f r12,r12,2 + mov r10,mlo ; rest before considering r12 in r5 : -r10 + mululw 0,r12,DBL1L + machulw r7,r12,DBL1L ; mhi: u-51.32 + asl r5,r5,25 ; s-51.7:25 + lsr r10,r10,7 ; u-51.30:2 + mulu64 (r12,r8) ; mlo: u-51.31:1 + sub r5,r5,r10 + add.mi r5,r5,DBL1L ; signed multiply adjust for r12*DBL1L + bset r7,r7,0 ; make sure that the result is not zero, and that + sub r5,r5,r7 ; a highpart zero appears negative + sub.f r5,r5,mlo ; rest msw + add.pl.f DBL0L,DBL0L,1 + j_s.d [blink] + add.eq DBL0H,DBL0H,1 + +.Linf_nan_dbl0: + tst_s DBL1H,DBL1H + j_s.d [blink] + bxor.mi DBL0H,DBL0H,31 + .balign 4 +.Linf_denorm: + lsr r12,r6,28 + brlo.d r12,0xc,.Linf +.Ldenorm: + asr r6,r6,20 + neg r9,r6 + mov_s DBL0H,0 + brhs.d r9,54,.Lret0 + bxor.mi DBL0H,DBL0H,31 + add r12,mhi,1 + and r12,r12,-4 + rsub r7,r6,5 + asr r10,r12,28 + bmsk r4,r12,27 + min r7,r7,31 + asr DBL0L,r4,r7 + add DBL1H,r11,r10 + abs.f r10,r4 + sub.mi r10,r10,1 + add.f r7,r6,32-5 + asl r4,r4,r7 + mov.mi r4,r10 + add.f r10,r6,23 + rsub r7,r6,9 + lsr r7,DBL1H,r7 + asl r10,DBL1H,r10 + or.pnz DBL0H,DBL0H,r7 + or.mi r4,r4,r10 + mov.mi r10,r7 + add.f DBL0L,r10,DBL0L + add.cs.f DBL0H,DBL0H,1 ; carry clear after this point + bxor.f 0,r4,31 + add.pnz.f DBL0L,DBL0L,1 + add.cs.f DBL0H,DBL0H,1 + jne_s [blink] + /* Calculation so far was not conclusive; calculate further rest. */ + mulu64 (r11,DBL1L) ; rest before considering r12 in r5 : -mlo + asr.f r12,r12,3 + asl r5,r5,25 ; s-51.7:25 + mov r11,mlo ; rest before considering r12 in r5 : -r11 + mulu64 (r12,r8) ; u-51.31:1 + and r9,DBL0L,1 ; tie-breaker: round to even + lsr r11,r11,7 ; u-51.30:2 + mov DBL1H,mlo ; u-51.31:1 + mulu64 (r12,DBL1L) ; u-51.62:2 + sub.mi r11,r11,DBL1L ; signed multiply adjust for r12*DBL1L + add_s DBL1H,DBL1H,r11 + sub DBL1H,DBL1H,r5 ; -rest msw + add_s DBL1H,DBL1H,mhi ; -rest msw + add.f 0,DBL1H,DBL1H ; can't ror.f by 32 :-( + tst_s DBL1H,DBL1H + cmp.eq mlo,r9 + add.cs.f DBL0L,DBL0L,1 + j_s.d [blink] + add.cs DBL0H,DBL0H,1 + +.Lret0: + /* return +- 0 */ + j_s.d [blink] + mov_s DBL0L,0 +.Linf: + mov_s DBL0H,r9 + mov_s DBL0L,0 + j_s.d [blink] + bxor.mi DBL0H,DBL0H,31 + ENDFUNC(__divdf3) diff --git a/libgcc/config/arc/ieee-754/arc600-dsp/divsf3.S b/libgcc/config/arc/ieee-754/arc600-dsp/divsf3.S new file mode 100644 index 00000000000..da25c711376 --- /dev/null +++ b/libgcc/config/arc/ieee-754/arc600-dsp/divsf3.S @@ -0,0 +1,274 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* + - calculate 15..18 bit inverse using a table of approximating polynoms. + precision is higher for polynoms used to evaluate input with larger + value. + - do one newton-raphson iteration step to double the precision, + then multiply this with the divisor + -> more time to decide if dividend is subnormal + - the worst error propagation is on the side of the value range + with the least initial defect, thus giving us about 30 bits precision. + */ +#include "../arc-ieee-754.h" +#define mlo acc2 +#define mhi acc1 +#define mul64(b,c) mullw 0,b,c` machlw 0,b,c +#define mulu64(b,c) mululw 0,b,c` machulw 0,b,c + +#if 0 /* DEBUG */ + .global __divsf3 + FUNC(__divsf3) + .balign 4 +__divsf3: + push_s blink + push_s r1 + bl.d __divsf3_c + push_s r0 + ld_s r1,[sp,4] + st_s r0,[sp,4] + bl.d __divsf3_asm + pop_s r0 + pop_s r1 + pop_s blink + cmp r0,r1 +#if 1 + bne abort + jeq_s [blink] + b abort +#else + bne abort + j_s [blink] +#endif + ENDFUNC(__divsf3) +#define __divsf3 __divsf3_asm +#endif /* DEBUG */ + + FUNC(__divsf3) + .balign 4 +.Ldivtab: + .long 0xfc0ffff0 + .long 0xf46ffefd + .long 0xed1ffd2a + .long 0xe627fa8e + .long 0xdf7ff73b + .long 0xd917f33b + .long 0xd2f7eea3 + .long 0xcd1fe986 + .long 0xc77fe3e7 + .long 0xc21fdddb + .long 0xbcefd760 + .long 0xb7f7d08c + .long 0xb32fc960 + .long 0xae97c1ea + .long 0xaa27ba26 + .long 0xa5e7b22e + .long 0xa1cfa9fe + .long 0x9ddfa1a0 + .long 0x9a0f990c + .long 0x9667905d + .long 0x92df878a + .long 0x8f6f7e84 + .long 0x8c27757e + .long 0x88f76c54 + .long 0x85df630c + .long 0x82e759c5 + .long 0x8007506d + .long 0x7d3f470a + .long 0x7a8f3da2 + .long 0x77ef341e + .long 0x756f2abe + .long 0x72f7212d + .long 0x709717ad + .long 0x6e4f0e44 + .long 0x6c1704d6 + .long 0x69e6fb44 + .long 0x67cef1d7 + .long 0x65c6e872 + .long 0x63cedf18 + .long 0x61e6d5cd + .long 0x6006cc6d + .long 0x5e36c323 + .long 0x5c76b9f3 + .long 0x5abeb0b7 + .long 0x5916a79b + .long 0x57769e77 + .long 0x55de954d + .long 0x54568c4e + .long 0x52d6834d + .long 0x51667a7f + .long 0x4ffe71b5 + .long 0x4e9e68f1 + .long 0x4d466035 + .long 0x4bf65784 + .long 0x4aae4ede + .long 0x496e4646 + .long 0x48363dbd + .long 0x47063547 + .long 0x45de2ce5 + .long 0x44be2498 + .long 0x43a61c64 + .long 0x4296144a + .long 0x41860c0e + .long 0x407e03ee +.L7f800000: + .long 0x7f800000 + .balign 4 + .global __divsf3_support +__divsf3_support: +.Linf_NaN: + bclr.f 0,r0,31 ; 0/0 -> NaN + xor_s r0,r0,r1 + bmsk r1,r0,30 + bic_s r0,r0,r1 + sub.eq r0,r0,1 + j_s.d [blink] + or r0,r0,r9 +.Lret0: + xor_s r0,r0,r1 + bmsk r1,r0,30 + j_s.d [blink] + bic_s r0,r0,r1 +/* N.B. the spacing between divtab and the sub3 to get its address must + be a multiple of 8. */ +__divsf3: + ld.as r9,[pcl,-9]; [pcl,(-((.-.L7f800000) >> 2))] ; 0x7f800000 + sub3 r3,pcl,37;(.-.Ldivtab) >> 3 + lsr r2,r1,17 + and.f r11,r1,r9 + bmsk r5,r2,5 + beq.d .Ldenorm_fp1 + asl r6,r1,8 + and.f r2,r0,r9 + ld.as r5,[r3,r5] + asl r4,r1,9 + bset r6,r6,31 + breq.d r11,r9,.Linf_nan_fp1 +.Lpast_denorm_fp1: + mululw 0,r5,r4 + machulw r8,r5,r4 + breq.d r2,r9,.Linf_nan_fp0 + asl r5,r5,13 + sub r7,r5,r8 + mululw 0,r7,r6 + machulw r8,r7,r6 + beq.d .Ldenorm_fp0 + asl r12,r0,8 + mulu64 (r8,r7) + bset r3,r12,31 +.Lpast_denorm_fp0: + cmp_s r3,r6 + lsr.cc r3,r3,1 + add_s r2,r2, /* wait for immediate */ \ + 0x3f000000 + sub r7,r7,mhi ; u1.31 inverse, about 30 bit + mulu64 (r3,r7) + sbc r2,r2,r11 + xor.f 0,r0,r1 + and r0,r2,r9 + bclr r3,r9,23 ; 0x7f000000 + brhs.d r2,r3,.Linf_denorm + bxor.mi r0,r0,31 +.Lpast_denorm: + add r3,mhi,0x22 ; round to nearest or higher + tst r3,0x3c ; check if rounding was unsafe + lsr r3,r3,6 + jne.d [blink] ; return if rounding was safe. + add_s r0,r0,r3 + /* work out exact rounding if we fall through here. */ + /* We know that the exact result cannot be represented in single + precision. Find the mid-point between the two nearest + representable values, multiply with the divisor, and check if + the result is larger than the dividend. */ + add_s r3,r3,r3 + sub_s r3,r3,1 + mulu64 (r3,r6) + asr.f 0,r0,1 ; for round-to-even in case this is a denorm + rsub r2,r9,25 + asl_s r12,r12,r2 + sub.f 0,r12,mlo + j_s.d [blink] + sub.mi r0,r0,1 +.Linf_nan_fp1: + lsr_s r0,r0,31 + bmsk.f 0,r1,22 + asl_s r0,r0,31 + bne_s 0f ; inf/inf -> nan + brne r2,r9,.Lsigned0 ; x/inf -> 0, but x/nan -> nan +0: j_s.d [blink] + mov r0,-1 +.Lsigned0: +.Linf_nan_fp0: + tst_s r1,r1 + j_s.d [blink] + bxor.mi r0,r0,31 + .balign 4 + .global __divsf3 +/* For denormal results, it is possible that an exact result needs + rounding, and thus the round-to-even rule has to come into play. */ +.Linf_denorm: + brlo r2,0xc0000000,.Linf +.Ldenorm: + asr_s r2,r2,23 + bic r0,r0,r9 + neg r9,r2 + brlo.d r9,25,.Lpast_denorm + lsr r3,mlo,r9 + /* Fall through: return +- 0 */ + j_s [blink] +.Linf: + j_s.d [blink] + or r0,r0,r9 + .balign 4 +.Ldenorm_fp1: + norm.f r12,r6 ; flag for x/0 -> Inf check + add r6,r6,r6 + rsub r5,r12,16 + ror r5,r1,r5 + bmsk r5,r5,5 + bic.ne.f 0, \ + 0x60000000,r0 ; large number / denorm -> Inf + ld.as r5,[r3,r5] + asl r6,r6,r12 + beq.d .Linf_NaN + and.f r2,r0,r9 + add r4,r6,r6 + asl_s r12,r12,23 + bne.d .Lpast_denorm_fp1 + add_s r2,r2,r12 +.Ldenorm_fp0: + mulu64 (r8,r7) + bclr r12,r12,31 + norm.f r3,r12 ; flag for 0/x -> 0 check + bic.ne.f 0,0x60000000,r1 ; denorm/large number -> 0 + beq_s .Lret0 + asl_s r12,r12,r3 + asl_s r3,r3,23 + add_s r12,r12,r12 + add r11,r11,r3 + b.d .Lpast_denorm_fp0 + mov_s r3,r12 + ENDFUNC(__divsf3) diff --git a/libgcc/config/arc/ieee-754/arc600-dsp/muldf3.S b/libgcc/config/arc/ieee-754/arc600-dsp/muldf3.S new file mode 100644 index 00000000000..88c541bf700 --- /dev/null +++ b/libgcc/config/arc/ieee-754/arc600-dsp/muldf3.S @@ -0,0 +1,231 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "../arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __muldf3 + .balign 4 +__muldf3: + push_s blink + push_s r2 + push_s r3 + push_s r0 + bl.d __muldf3_c + push_s r1 + ld_s r2,[sp,12] + ld_s r3,[sp,8] + st_s r0,[sp,12] + st_s r1,[sp,8] + pop_s r1 + bl.d __muldf3_asm + pop_s r0 + pop_s r3 + pop_s r2 + pop_s blink + cmp r0,r2 + cmp.eq r1,r3 + jeq_s [blink] + b abort +#define __muldf3 __muldf3_asm +#endif /* DEBUG */ + +__muldf3_support: /* This label makes debugger output saner. */ + .balign 4 + FUNC(__muldf3) +.Ldenorm_2: + breq.d DBL1L,0,.Lret0_2 ; 0 input -> 0 output + norm.f r12,DBL1L + mov.mi r12,21 + add.pl r12,r12,22 + neg r11,r12 + asl_s r12,r12,20 + lsr.f DBL1H,DBL1L,r11 + ror DBL1L,DBL1L,r11 + sub_s DBL0H,DBL0H,r12 + mov.eq DBL1H,DBL1L + sub_l DBL1L,DBL1L,DBL1H + /* Fall through. */ + .global __muldf3 + .balign 4 +__muldf3: + mululw 0,DBL0L,DBL1L + machulw r4,DBL0L,DBL1L + ld.as r9,[pcl,0x67] ; ((.L7ff00000-.+2)/4)] + bmsk r6,DBL0H,19 + bset r6,r6,20 + mov r8,acc2 + mululw 0,r4,1 + and r11,DBL0H,r9 + breq.d r11,0,.Ldenorm_dbl0 + and r12,DBL1H,r9 + breq.d r12,0,.Ldenorm_dbl1 + maclw 0,r6,DBL1L + machulw 0,r6,DBL1L + breq.d r11,r9,.Linf_nan + bmsk r10,DBL1H,19 + breq.d r12,r9,.Linf_nan + bset r10,r10,20 + maclw 0,r10,DBL0L + machulw r5,r10,DBL0L + add_s r12,r12,r11 ; add exponents + mov r4,acc2 + mululw 0,r5,1 + maclw 0,r6,r10 + machulw r7,r6,r10 ; fraction product in r7:acc2:r4:r8 + tst r8,r8 + bclr r8,r9,30 ; 0x3ff00000 + bset.ne r4,r4,0 ; put least significant word into sticky bit + bclr r6,r9,20 ; 0x7fe00000 + lsr.f r10,r7,9 + rsub.eq r8,r8,r9 ; 0x40000000 + sub r12,r12,r8 ; subtract bias + implicit 1 + brhs.d r12,r6,.Linf_denorm + rsub r10,r10,12 +.Lshift_frac: + neg r8,r10 + asl r6,r4,r10 + lsr DBL0L,r4,r8 + add.f 0,r6,r6 + btst.eq DBL0L,0 + cmp.eq r4,r4 ; round to nearest / round to even + asl r4,acc2,r10 + lsr r5,acc2,r8 + adc.f DBL0L,DBL0L,r4 + xor.f 0,DBL0H,DBL1H + asl r7,r7,r10 + add_s r12,r12,r5 + adc DBL0H,r12,r7 + j_s.d [blink] + bset.mi DBL0H,DBL0H,31 + +/* N.B. This is optimized for ARC700. + ARC600 has very different scheduling / instruction selection criteria. */ + +/* If one number is denormal, subtract some from the exponent of the other + one (if the other exponent is too small, return 0), and normalize the + denormal. Then re-run the computation. */ +.Lret0_2: + lsr_s DBL0H,DBL0H,31 + asl_s DBL0H,DBL0H,31 + j_s.d [blink] + mov_s DBL0L,0 + .balign 4 +.Ldenorm_dbl0: + mov_s r12,DBL0L + mov_s DBL0L,DBL1L + mov_s DBL1L,r12 + mov_s r12,DBL0H + mov_s DBL0H,DBL1H + mov_s DBL1H,r12 + and r11,DBL0H,r9 +.Ldenorm_dbl1: + brhs r11,r9,.Linf_nan + brhs 0x3ca00001,r11,.Lret0 + sub_s DBL0H,DBL0H,DBL1H + bmsk.f DBL1H,DBL1H,30 + add_s DBL0H,DBL0H,DBL1H + beq.d .Ldenorm_2 + norm r12,DBL1H + sub_s r12,r12,10 + asl r5,r12,20 + asl_s DBL1H,DBL1H,r12 + sub DBL0H,DBL0H,r5 + neg r5,r12 + lsr r6,DBL1L,r5 + asl_s DBL1L,DBL1L,r12 + b.d __muldf3 + add_s DBL1H,DBL1H,r6 + +.Lret0: xor_s DBL0H,DBL0H,DBL1H + bclr DBL1H,DBL0H,31 + xor_s DBL0H,DBL0H,DBL1H + j_s.d [blink] + mov_s DBL0L,0 + + .balign 4 +.Linf_nan: + bclr r12,DBL1H,31 + xor_s DBL1H,DBL1H,DBL0H + bclr_s DBL0H,DBL0H,31 + max r8,DBL0H,r12 ; either NaN -> NaN ; otherwise inf + or.f 0,DBL0H,DBL0L + mov_s DBL0L,0 + or.ne.f DBL1L,DBL1L,r12 + not_s DBL0H,DBL0L ; inf * 0 -> NaN + mov.ne DBL0H,r8 + tst_s DBL1H,DBL1H + j_s.d [blink] + bset.mi DBL0H,DBL0H,31 + +/* We have checked for infinity / NaN input before, and transformed + denormalized inputs into normalized inputs. Thus, the worst case + exponent overflows are: + 1 + 1 - 0x400 == 0xc02 : maximum underflow + 0x7fe + 0x7fe - 0x3ff == 0xbfd ; maximum overflow + N.B. 0x7e and 0x7f are also values for overflow. + + If (r12 <= -54), we have an underflow to zero. */ + .balign 4 +.Linf_denorm: + lsr r6,r12,28 + brlo.d r6,0xc,.Linf + asr r6,r12,20 + add.f r10,r10,r6 + brgt.d r10,0,.Lshift_frac + mov_s r12,0 + beq.d .Lround_frac + add r10,r10,32 +.Lshift32_frac: + tst r4,r4 + mov r4,acc2 + bset.ne r4,r4,1 + mululw 0,r7,1 + brge.d r10,1,.Lshift_frac + mov r7,0 + breq.d r10,0,.Lround_frac + add r10,r10,32 + brgt r10,21,.Lshift32_frac + b_s .Lret0 + +.Lround_frac: + add.f 0,r4,r4 + btst.eq acc2,0 + mov_s DBL0L,acc2 + mov_s DBL0H,r7 + adc.eq.f DBL0L,DBL0L,0 + j_s.d [blink] + adc.eq DBL0H,DBL0H,0 + +.Linf: mov_s DBL0L,0 + xor.f DBL1H,DBL1H,DBL0H + mov_s DBL0H,r9 + j_s.d [blink] + bset.mi DBL0H,DBL0H,31 + ENDFUNC(__muldf3) + + .balign 4 +.L7ff00000: + .long 0x7ff00000 diff --git a/libgcc/config/arc/ieee-754/arc600-dsp/mulsf3.S b/libgcc/config/arc/ieee-754/arc600-dsp/mulsf3.S new file mode 100644 index 00000000000..b58146f0271 --- /dev/null +++ b/libgcc/config/arc/ieee-754/arc600-dsp/mulsf3.S @@ -0,0 +1,176 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "../arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __mulsf3 + FUNC(__mulsf3) + .balign 4 +__mulsf3: + push_s blink + push_s r1 + bl.d __mulsf3_c + push_s r0 + ld_s r1,[sp,4] + st_s r0,[sp,4] + bl.d __mulsf3_asm + pop_s r0 + pop_s r1 + pop_s blink + cmp r0,r1 + jeq_s [blink] + and r12,r0,r1 + bic.f 0,0x7f800000,r12 + bne 0f + bmsk.f 0,r0,22 + bmsk.ne.f r1,r1,22 + jne_s [blink] ; both NaN -> OK +0: bl abort + ENDFUNC(__mulsf3) +#define __mulsf3 __mulsf3_asm +#endif /* DEBUG */ + + .balign 4 + .global __mulsf3 + FUNC(__mulsf3) +__mulsf3: + ld.as r9,[pcl,80]; [pcl,((.L7f800000-.+2)/4)] + bmsk r4,r1,22 + bset r2,r0,23 + asl_s r2,r2,8 + bset r3,r4,23 + and r11,r0,r9 + breq.d r11,0,.Ldenorm_dbl0 + and r12,r1,r9 + breq.d r12,0,.Ldenorm_dbl1 + xor_s r0,r0,r1 + mululw 0,r2,r3 + machulw r6,r2,r3 + breq.d r11,r9,.Linf_nan_dbl0 + ld.as r4,[pcl,69]; [pcl,((.L7fffffff-.+2)/4)] + breq.d r12,r9,.Linf_nan_dbl1 +.Lpast_denorm: + asl.f 0,r6,8 + mov r7,acc2 + add.pl r6,r6,r6 + bclr.pl r6,r6,23 + add.pl.f r7,r7,r7 + add.cs r6,r6,1 + lsr.f 0,r6,1 + add_s r12,r12,r11 + adc.f 0,r7,r4 + add_s r12,r12, \ + -0x3f800000 + adc.f r8,r6,r12 + tst.pl r8,r9 + bic r0,r0,r4 + min r3,r8,r9 + jpnz.d [blink] + add.pnz r0,r0,r3 +; infinity or denormal number + add.ne.f r3,r3,r3 + asr_s r3,r3,23+1 + bset r6,r6,23 + bpnz.d .Linfinity + sub_s r3,r3,1 + neg_s r2,r3 + brhi.d r2,24,.Lret_r0 ; right shift shift > 24 -> return +-0 + lsr r2,r6,r2 + asl r9,r6,r3 + lsr.f 0,r2,1 + tst r7,r7 + add_s r0,r0,r2 + bset.ne r9,r9,0 + adc.f 0,r9,r4 + j_s.d [blink] + add.cs r0,r0,1 +.Linfinity: + j_s.d [blink] + add_s r0,r0,r9 + +.Lret_r0: j_s [blink] + + .balign 4 +.Ldenorm_dbl0: + bclr_s r2,r2,31 + norm.f r4,r2 + add_s r2,r2,r2 + asl r2,r2,r4 + breq.d r12,r9,.Ldenorm_dbl0_inf_nan_dbl1 + asl r4,r4,23 + mululw 0,r2,r3 + machulw r6,r2,r3 + sub.ne.f r12,r12,r4 + ld.as r4,[pcl,28]; [pcl,((.L7fffffff-.+2)/4)] + bhi.d .Lpast_denorm + xor_s r0,r0,r1 + bmsk r1,r0,30 + j_s.d [blink] + bic_s r0,r0,r1 + + .balign 4 +.Ldenorm_dbl0_inf_nan_dbl1: + bmsk.f 0,r0,30 + mov.eq r1,-1 +.Linf_nan_dbl1: + xor_s r1,r1,r0 +.Linf_nan_dbl0: + bclr_s r1,r1,31 + j_s.d [blink] + xor_s r0,r0,r1 + + .balign 4 +.Ldenorm_dbl1: + breq.d r11,r9,.Linf_nan_dbl0_2 + norm.f r3,r4 + sub_s r3,r3,7 + asl r4,r4,r3 + mululw 0,r2,r4 + machulw r6,r2,r4 + sub_s r3,r3,1 + asl_s r3,r3,23 + sub.ne.f r11,r11,r3 + ld.as r4,[pcl,11]; [pcl,((.L7fffffff-.+2)/4)] + bhi.d .Lpast_denorm + bmsk r8,r0,30 + j_s.d [blink] + bic r0,r0,r8 + + .balign 4 +.Linf_nan_dbl0_2: + bclr_s r1,r1,31 + xor_s r0,r0,r1 + sub.eq r1,r1,1 ; inf/nan * 0 -> nan + bic.f 0,r9,r1 + j_s.d [blink] + or.eq r0,r0,r1 ; r1 nan -> result nan + + .balign 4 +.L7f800000: + .long 0x7f800000 +.L7fffffff: + .long 0x7fffffff + ENDFUNC(__mulsf3) diff --git a/libgcc/config/arc/ieee-754/arc600-mul64/divdf3.S b/libgcc/config/arc/ieee-754/arc600-mul64/divdf3.S new file mode 100644 index 00000000000..0584b53f77b --- /dev/null +++ b/libgcc/config/arc/ieee-754/arc600-mul64/divdf3.S @@ -0,0 +1,410 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* + to calculate a := b/x as b*y, with y := 1/x: + - x is in the range [1..2) + - calculate 15..18 bit inverse y0 using a table of approximating polynoms. + Precision is higher for polynoms used to evaluate input with larger + value. + - Do one newton-raphson iteration step to double the precision, + then multiply this with the divisor + -> more time to decide if dividend is subnormal + - the worst error propagation is on the side of the value range + with the least initial defect, thus giving us about 30 bits precision. + The truncation error for the either is less than 1 + x/2 ulp. + A 31 bit inverse can be simply calculated by using x with implicit 1 + and chaining the multiplies. For a 32 bit inverse, we multiply y0^2 + with the bare fraction part of x, then add in y0^2 for the implicit + 1 of x. + - If calculating a 31 bit inverse, the systematic error is less than + -1 ulp; likewise, for 32 bit, it is less than -2 ulp. + - If we calculate our seed with a 32 bit fraction, we can archive a + tentative result strictly better than -2 / +2.5 (1) ulp/128, i.e. we + only need to take the step to calculate the 2nd stage rest and + rounding adjust 1/32th of the time. However, if we use a 20 bit + fraction for the seed, the negative error can exceed -2 ulp/128, (2) + thus for a simple add / tst check, we need to do the 2nd stage + rest calculation/ rounding adjust 1/16th of the time. + (1): The inexactness of the 32 bit inverse contributes an error in the + range of (-1 .. +(1+x/2) ) ulp/128. Leaving out the low word of the + rest contributes an error < +1/x ulp/128 . In the interval [1,2), + x/2 + 1/x <= 1.5 . + (2): Unless proven otherwise. I have not actually looked for an + example where -2 ulp/128 is exceeded, and my calculations indicate + that the excess, if existent, is less than -1/512 ulp. + ??? The algorithm is still based on the ARC700 optimized code. + Maybe we could make better use of 64 bit multiply results and/or mmed . + */ +#include "../arc-ieee-754.h" + +/* N.B. fp-bit.c does double rounding on denormal numbers. */ +#if 0 /* DEBUG */ + .global __divdf3 + FUNC(__divdf3) + .balign 4 +__divdf3: + push_s blink + push_s r2 + push_s r3 + push_s r0 + bl.d __divdf3_c + push_s r1 + ld_s r2,[sp,12] + ld_s r3,[sp,8] + st_s r0,[sp,12] + st_s r1,[sp,8] + pop_s r1 + bl.d __divdf3_asm + pop_s r0 + pop_s r3 + pop_s r2 + pop_s blink + cmp r0,r2 + cmp.eq r1,r3 + jeq_s [blink] + and r12,DBL0H,DBL1H + bic.f 0,0x7ff80000,r12 ; both NaN -> OK + jeq_s [blink] + bl abort + ENDFUNC(__divdf3) +#define __divdf3 __divdf3_asm +#endif /* DEBUG */ + + FUNC(__divdf3) + .balign 4 +.L7ff00000: + .long 0x7ff00000 +.Ldivtab: + .long 0xfc0fffe1 + .long 0xf46ffdfb + .long 0xed1ffa54 + .long 0xe61ff515 + .long 0xdf7fee75 + .long 0xd91fe680 + .long 0xd2ffdd52 + .long 0xcd1fd30c + .long 0xc77fc7cd + .long 0xc21fbbb6 + .long 0xbcefaec0 + .long 0xb7efa100 + .long 0xb32f92bf + .long 0xae8f83b7 + .long 0xaa2f7467 + .long 0xa5ef6479 + .long 0xa1cf53fa + .long 0x9ddf433e + .long 0x9a0f3216 + .long 0x965f2091 + .long 0x92df0f11 + .long 0x8f6efd05 + .long 0x8c1eeacc + .long 0x88eed876 + .long 0x85dec615 + .long 0x82eeb3b9 + .long 0x800ea10b + .long 0x7d3e8e0f + .long 0x7a8e7b3f + .long 0x77ee6836 + .long 0x756e5576 + .long 0x72fe4293 + .long 0x709e2f93 + .long 0x6e4e1c7f + .long 0x6c0e095e + .long 0x69edf6c5 + .long 0x67cde3a5 + .long 0x65cdd125 + .long 0x63cdbe25 + .long 0x61ddab3f + .long 0x600d991f + .long 0x5e3d868c + .long 0x5c6d7384 + .long 0x5abd615f + .long 0x590d4ecd + .long 0x576d3c83 + .long 0x55dd2a89 + .long 0x545d18e9 + .long 0x52dd06e9 + .long 0x516cf54e + .long 0x4ffce356 + .long 0x4e9cd1ce + .long 0x4d3cbfec + .long 0x4becae86 + .long 0x4aac9da4 + .long 0x496c8c73 + .long 0x483c7bd3 + .long 0x470c6ae8 + .long 0x45dc59af + .long 0x44bc4915 + .long 0x43ac3924 + .long 0x428c27fb + .long 0x418c187a + .long 0x407c07bd + +__divdf3_support: /* This label makes debugger output saner. */ + .balign 4 +.Ldenorm_dbl1: + brge r6, \ + 0x43500000,.Linf_NaN ; large number / denorm -> Inf + bmsk.f r12,DBL1H,19 + mov.eq r12,DBL1L + mov.eq DBL1L,0 + sub.eq r7,r7,32 + norm.f r11,r12 ; flag for x/0 -> Inf check + beq_s .Linf_NaN + mov.mi r11,0 + add.pl r11,r11,1 + add_s r12,r12,r12 + asl r8,r12,r11 + rsub r12,r11,31 + lsr r12,DBL1L,r12 + tst_s DBL1H,DBL1H + or r8,r8,r12 + lsr r4,r8,26 + lsr DBL1H,r8,12 + ld.as r4,[r10,r4] + bxor.mi DBL1H,DBL1H,31 + sub r11,r11,11 + asl DBL1L,DBL1L,r11 + sub r11,r11,1 + mulu64 r4,r8 + sub r7,r7,r11 + b.d .Lpast_denorm_dbl1 + asl r7,r7,20 + + .balign 4 +.Ldenorm_dbl0: + bmsk.f r12,DBL0H,19 + ; wb stall + mov.eq r12,DBL0L + sub.eq r6,r6,32 + norm.f r11,r12 ; flag for 0/x -> 0 check + brge r7, \ + 0x43500000, .Lret0_2 ; denorm/large number -> 0 + beq_s .Lret0_2 + mov.mi r11,0 + add.pl r11,r11,1 + asl r12,r12,r11 + sub r6,r6,r11 + add.f 0,r6,31 + lsr r10,DBL0L,r6 + mov.mi r10,0 + add r6,r6,11+32 + neg.f r11,r6 + asl DBL0L,DBL0L,r11 + mov.pl DBL0L,0 + sub r6,r6,32-1 + b.d .Lpast_denorm_dbl0 + asl r6,r6,20 + +.Linf_NaN: + tst_s DBL0L,DBL0L ; 0/0 -> NaN + xor_s DBL1H,DBL1H,DBL0H + bclr.eq.f DBL0H,DBL0H,31 + bmsk DBL0H,DBL1H,30 + xor_s DBL0H,DBL0H,DBL1H + sub.eq DBL0H,DBL0H,1 + mov_s DBL0L,0 + j_s.d [blink] + or DBL0H,DBL0H,r9 + .balign 4 +.Lret0_2: + xor_s DBL1H,DBL1H,DBL0H + mov_s DBL0L,0 + bmsk DBL0H,DBL1H,30 + j_s.d [blink] + xor_s DBL0H,DBL0H,DBL1H + .balign 4 + .global __divdf3 +/* N.B. the spacing between divtab and the sub3 to get its address must + be a multiple of 8. */ +__divdf3: + asl r8,DBL1H,12 + lsr r4,r8,26 + sub3 r10,pcl,61; (.-.Ldivtab) >> 3 + ld.as r9,[pcl,-124]; [pcl,(-((.-.L7ff00000) >> 2))] ; 0x7ff00000 + ld.as r4,[r10,r4] + lsr r12,DBL1L,20 + and.f r7,DBL1H,r9 + or r8,r8,r12 + mulu64 r4,r8 + beq.d .Ldenorm_dbl1 +.Lpast_denorm_dbl1: + and.f r6,DBL0H,r9 + breq.d r7,r9,.Linf_nan_dbl1 + asl r4,r4,12 + sub r4,r4,mhi + mulu64 r4,r4 + beq.d .Ldenorm_dbl0 + lsr r8,r8,1 + breq.d r6,r9,.Linf_nan_dbl0 + asl r12,DBL0H,11 + lsr r10,DBL0L,21 +.Lpast_denorm_dbl0: + bset r8,r8,31 + mulu64 mhi,r8 + add_s r12,r12,r10 + bset r5,r12,31 + cmp r5,r8 + cmp.eq DBL0L,DBL1L + lsr.cc r5,r5,1 + sub r4,r4,mhi ; u1.31 inverse, about 30 bit + mulu64 r5,r4 ; result fraction highpart + lsr r8,r8,2 ; u3.29 + add r5,r6, /* wait for immediate */ \ + 0x3fe00000 + mov r11,mhi ; result fraction highpart + mulu64 r11,r8 ; u-28.31 + asl_s DBL1L,DBL1L,9 ; u-29.23:9 + sbc r6,r5,r7 + mov r12,mlo ; u-28.31 + mulu64 r11,DBL1L ; mhi: u-28.23:9 + add.cs DBL0L,DBL0L,DBL0L + asl_s DBL0L,DBL0L,6 ; u-26.25:7 + asl r10,r11,23 + sub_l DBL0L,DBL0L,r12 + lsr r7,r11,9 + sub r5,DBL0L,mhi ; rest msw ; u-26.31:0 + mul64 r5,r4 ; mhi: result fraction lowpart + xor.f 0,DBL0H,DBL1H + and DBL0H,r6,r9 + add_s DBL0H,DBL0H,r7 + bclr r12,r9,20 ; 0x7fe00000 + brhs.d r6,r12,.Linf_denorm + bxor.mi DBL0H,DBL0H,31 + add.f r12,mhi,0x11 + asr r9,r12,5 + sub.mi DBL0H,DBL0H,1 + add.f DBL0L,r9,r10 + tst r12,0x1c + jne.d [blink] + add.cs DBL0H,DBL0H,1 + /* work out exact rounding if we fall through here. */ + /* We know that the exact result cannot be represented in double + precision. Find the mid-point between the two nearest + representable values, multiply with the divisor, and check if + the result is larger than the dividend. Since we want to know + only the sign bit, it is sufficient to calculate only the + highpart of the lower 64 bits. */ + mulu64 r11,DBL1L ; rest before considering r12 in r5 : -mlo + sub.f DBL0L,DBL0L,1 + asl r12,r9,2 ; u-22.30:2 + sub.cs DBL0H,DBL0H,1 + sub.f r12,r12,2 + mov r10,mlo ; rest before considering r12 in r5 : -r10 + mulu64 r12,DBL1L ; mhi: u-51.32 + asl r5,r5,25 ; s-51.7:25 + lsr r10,r10,7 ; u-51.30:2 + mov r7,mhi ; u-51.32 + mulu64 r12,r8 ; mlo: u-51.31:1 + sub r5,r5,r10 + add.mi r5,r5,DBL1L ; signed multiply adjust for r12*DBL1L + bset r7,r7,0 ; make sure that the result is not zero, and that + sub r5,r5,r7 ; a highpart zero appears negative + sub.f r5,r5,mlo ; rest msw + add.pl.f DBL0L,DBL0L,1 + j_s.d [blink] + add.eq DBL0H,DBL0H,1 + +.Linf_nan_dbl1: ; 0/Inf -> NaN Inf/Inf -> NaN x/Inf-> 0 x/NaN -> NaN + or.f 0,r6,DBL0L + cmp.ne r6,r9 + not_s DBL0L,DBL1H + sub_s.ne DBL0L,DBL0L,DBL0L + tst_s DBL0H,DBL0H + add_s DBL0H,DBL1H,DBL0L + j_s.d [blink] + bxor.mi DBL0H,DBL0H,31 +.Linf_nan_dbl0: + tst_s DBL1H,DBL1H + j_s.d [blink] + bxor.mi DBL0H,DBL0H,31 + .balign 4 +.Linf_denorm: + lsr r12,r6,28 + brlo.d r12,0xc,.Linf +.Ldenorm: + asr r6,r6,20 + neg r9,r6 + mov_s DBL0H,0 + brhs.d r9,54,.Lret0 + bxor.mi DBL0H,DBL0H,31 + add r12,mhi,1 + and r12,r12,-4 + rsub r7,r6,5 + asr r10,r12,28 + bmsk r4,r12,27 + min r7,r7,31 + asr DBL0L,r4,r7 + add DBL1H,r11,r10 + abs.f r10,r4 + sub.mi r10,r10,1 + add.f r7,r6,32-5 + asl r4,r4,r7 + mov.mi r4,r10 + add.f r10,r6,23 + rsub r7,r6,9 + lsr r7,DBL1H,r7 + asl r10,DBL1H,r10 + or.pnz DBL0H,DBL0H,r7 + or.mi r4,r4,r10 + mov.mi r10,r7 + add.f DBL0L,r10,DBL0L + add.cs.f DBL0H,DBL0H,1 ; carry clear after this point + bxor.f 0,r4,31 + add.pnz.f DBL0L,DBL0L,1 + add.cs.f DBL0H,DBL0H,1 + jne_s [blink] + /* Calculation so far was not conclusive; calculate further rest. */ + mulu64 r11,DBL1L ; rest before considering r12 in r5 : -mlo + asr.f r12,r12,3 + asl r5,r5,25 ; s-51.7:25 + mov r11,mlo ; rest before considering r12 in r5 : -r11 + mulu64 r12,r8 ; u-51.31:1 + and r9,DBL0L,1 ; tie-breaker: round to even + lsr r11,r11,7 ; u-51.30:2 + mov DBL1H,mlo ; u-51.31:1 + mulu64 r12,DBL1L ; u-51.62:2 + sub.mi r11,r11,DBL1L ; signed multiply adjust for r12*DBL1L + add_s DBL1H,DBL1H,r11 + sub DBL1H,DBL1H,r5 ; -rest msw + add_s DBL1H,DBL1H,mhi ; -rest msw + add.f 0,DBL1H,DBL1H ; can't ror.f by 32 :-( + tst_s DBL1H,DBL1H + cmp.eq mlo,r9 + add.cs.f DBL0L,DBL0L,1 + j_s.d [blink] + add.cs DBL0H,DBL0H,1 + +.Lret0: + /* return +- 0 */ + j_s.d [blink] + mov_s DBL0L,0 +.Linf: + mov_s DBL0H,r9 + mov_s DBL0L,0 + j_s.d [blink] + bxor.mi DBL0H,DBL0H,31 + ENDFUNC(__divdf3) diff --git a/libgcc/config/arc/ieee-754/arc600-mul64/divsf3.S b/libgcc/config/arc/ieee-754/arc600-mul64/divsf3.S new file mode 100644 index 00000000000..a9934f0ad94 --- /dev/null +++ b/libgcc/config/arc/ieee-754/arc600-mul64/divsf3.S @@ -0,0 +1,274 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* + - calculate 15..18 bit inverse using a table of approximating polynoms. + precision is higher for polynoms used to evaluate input with larger + value. + - do one newton-raphson iteration step to double the precision, + then multiply this with the divisor + -> more time to decide if dividend is subnormal + - the worst error propagation is on the side of the value range + with the least initial defect, thus giving us about 30 bits precision. + */ +#include "../arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __divsf3 + FUNC(__divsf3) + .balign 4 +__divsf3: + push_s blink + push_s r1 + bl.d __divsf3_c + push_s r0 + ld_s r1,[sp,4] + st_s r0,[sp,4] + bl.d __divsf3_asm + pop_s r0 + pop_s r1 + pop_s blink + cmp r0,r1 +#if 1 + bne abort + jeq_s [blink] + b abort +#else + bne abort + j_s [blink] +#endif + ENDFUNC(__divsf3) +#define __divsf3 __divsf3_asm +#endif /* DEBUG */ + + FUNC(__divsf3) + .balign 4 +.Ldivtab: + .long 0xfc0ffff0 + .long 0xf46ffefd + .long 0xed1ffd2a + .long 0xe627fa8e + .long 0xdf7ff73b + .long 0xd917f33b + .long 0xd2f7eea3 + .long 0xcd1fe986 + .long 0xc77fe3e7 + .long 0xc21fdddb + .long 0xbcefd760 + .long 0xb7f7d08c + .long 0xb32fc960 + .long 0xae97c1ea + .long 0xaa27ba26 + .long 0xa5e7b22e + .long 0xa1cfa9fe + .long 0x9ddfa1a0 + .long 0x9a0f990c + .long 0x9667905d + .long 0x92df878a + .long 0x8f6f7e84 + .long 0x8c27757e + .long 0x88f76c54 + .long 0x85df630c + .long 0x82e759c5 + .long 0x8007506d + .long 0x7d3f470a + .long 0x7a8f3da2 + .long 0x77ef341e + .long 0x756f2abe + .long 0x72f7212d + .long 0x709717ad + .long 0x6e4f0e44 + .long 0x6c1704d6 + .long 0x69e6fb44 + .long 0x67cef1d7 + .long 0x65c6e872 + .long 0x63cedf18 + .long 0x61e6d5cd + .long 0x6006cc6d + .long 0x5e36c323 + .long 0x5c76b9f3 + .long 0x5abeb0b7 + .long 0x5916a79b + .long 0x57769e77 + .long 0x55de954d + .long 0x54568c4e + .long 0x52d6834d + .long 0x51667a7f + .long 0x4ffe71b5 + .long 0x4e9e68f1 + .long 0x4d466035 + .long 0x4bf65784 + .long 0x4aae4ede + .long 0x496e4646 + .long 0x48363dbd + .long 0x47063547 + .long 0x45de2ce5 + .long 0x44be2498 + .long 0x43a61c64 + .long 0x4296144a + .long 0x41860c0e + .long 0x407e03ee +.L7f800000: + .long 0x7f800000 + .balign 4 + .global __divsf3_support +__divsf3_support: +.Linf_NaN: + bclr.f 0,r0,31 ; 0/0 -> NaN + xor_s r0,r0,r1 + bmsk r1,r0,30 + bic_s r0,r0,r1 + sub.eq r0,r0,1 + j_s.d [blink] + or r0,r0,r9 +.Lret0: + xor_s r0,r0,r1 + bmsk r1,r0,30 + j_s.d [blink] + bic_s r0,r0,r1 +/* N.B. the spacing between divtab and the sub3 to get its address must + be a multiple of 8. */ +__divsf3: + lsr r2,r1,17 + sub3 r3,pcl,37 ; (.-.Ldivtab) >> 3 + bmsk_s r2,r2,5 + ld.as r5,[r3,r2] + asl r4,r1,9 + ld.as r9,[pcl,-13]; [pcl,(-((.-.L7f800000) >> 2))] ; 0x7f800000 + mulu64 r5,r4 + and.f r11,r1,r9 + asl r6,r1,8 + bset r6,r6,31 + beq.d .Ldenorm_fp1 + asl r5,r5,13 + breq.d r11,r9,.Linf_nan_fp1 + and.f r2,r0,r9 + sub r7,r5,mhi + mulu64 r7,r6 + beq.d .Ldenorm_fp0 + asl r12,r0,8 + breq.d r2,r9,.Linf_nan_fp0 + mulu64 mhi,r7 +.Lpast_denorm_fp1: + bset r3,r12,31 +.Lpast_denorm_fp0: + cmp_s r3,r6 + lsr.cc r3,r3,1 + add_s r2,r2, /* wait for immediate */ \ + 0x3f000000 + sub r7,r7,mhi ; u1.31 inverse, about 30 bit + mulu64 r3,r7 + sbc r2,r2,r11 + xor.f 0,r0,r1 + and r0,r2,r9 + bclr r3,r9,23 ; 0x7f000000 + brhs.d r2,r3,.Linf_denorm + bxor.mi r0,r0,31 +.Lpast_denorm: + add r3,mhi,0x22 ; round to nearest or higher + tst r3,0x3c ; check if rounding was unsafe + lsr r3,r3,6 + jne.d [blink] ; return if rounding was safe. + add_s r0,r0,r3 + /* work out exact rounding if we fall through here. */ + /* We know that the exact result cannot be represented in single + precision. Find the mid-point between the two nearest + representable values, multiply with the divisor, and check if + the result is larger than the dividend. */ + add_s r3,r3,r3 + sub_s r3,r3,1 + mulu64 r3,r6 + asr.f 0,r0,1 ; for round-to-even in case this is a denorm + rsub r2,r9,25 + asl_s r12,r12,r2 + sub.f 0,r12,mlo + j_s.d [blink] + sub.mi r0,r0,1 +.Linf_nan_fp1: + lsr_s r0,r0,31 + bmsk.f 0,r1,22 + asl_s r0,r0,31 + bne_s 0f ; inf/inf -> nan + brne r2,r9,.Lsigned0 ; x/inf -> 0, but x/nan -> nan +0: j_s.d [blink] + mov r0,-1 +.Lsigned0: +.Linf_nan_fp0: + tst_s r1,r1 + j_s.d [blink] + bxor.mi r0,r0,31 + .balign 4 + .global __divsf3 +/* For denormal results, it is possible that an exact result needs + rounding, and thus the round-to-even rule has to come into play. */ +.Linf_denorm: + brlo r2,0xc0000000,.Linf +.Ldenorm: + asr_s r2,r2,23 + bic r0,r0,r9 + neg r9,r2 + brlo.d r9,25,.Lpast_denorm + lsr r3,mlo,r9 + /* Fall through: return +- 0 */ + j_s [blink] +.Linf: + j_s.d [blink] + or r0,r0,r9 + .balign 4 +.Ldenorm_fp1: + bclr r6,r6,31 + norm.f r12,r6 ; flag for x/0 -> Inf check + add r6,r6,r6 + rsub r5,r12,16 + ror r5,r1,r5 + asl r6,r6,r12 + bmsk r5,r5,5 + ld.as r5,[r3,r5] + add r4,r6,r6 + ; load latency + mulu64 r5,r4 + bic.ne.f 0, \ + 0x60000000,r0 ; large number / denorm -> Inf + asl r5,r5,13 + sub r7,r5,mhi + beq.d .Linf_NaN + mulu64 r7,r6 + asl_s r12,r12,23 + and.f r2,r0,r9 + add_s r2,r2,r12 + asl r12,r0,8 + bne.d .Lpast_denorm_fp1 +.Ldenorm_fp0: mulu64 mhi,r7 + bclr r12,r12,31 + norm.f r3,r12 ; flag for 0/x -> 0 check + bic.ne.f 0,0x60000000,r1 ; denorm/large number -> 0 + beq_s .Lret0 + asl_s r12,r12,r3 + asl_s r3,r3,23 + add_s r12,r12,r12 + add r11,r11,r3 + b.d .Lpast_denorm_fp0 + mov_s r3,r12 + ENDFUNC(__divsf3) diff --git a/libgcc/config/arc/ieee-754/arc600-mul64/muldf3.S b/libgcc/config/arc/ieee-754/arc600-mul64/muldf3.S new file mode 100644 index 00000000000..1e18999e49a --- /dev/null +++ b/libgcc/config/arc/ieee-754/arc600-mul64/muldf3.S @@ -0,0 +1,234 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "../arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __muldf3 + .balign 4 +__muldf3: + push_s blink + push_s r2 + push_s r3 + push_s r0 + bl.d __muldf3_c + push_s r1 + ld_s r2,[sp,12] + ld_s r3,[sp,8] + st_s r0,[sp,12] + st_s r1,[sp,8] + pop_s r1 + bl.d __muldf3_asm + pop_s r0 + pop_s r3 + pop_s r2 + pop_s blink + cmp r0,r2 + cmp.eq r1,r3 + jeq_s [blink] + and r12,DBL0H,DBL1H + bic.f 0,0x7ff80000,r12 ; both NaN -> OK + jeq_s [blink] + b abort +#define __muldf3 __muldf3_asm +#endif /* DEBUG */ + +__muldf3_support: /* This label makes debugger output saner. */ + .balign 4 + FUNC(__muldf3) +.Ldenorm_2: + breq.d DBL1L,0,.Lret0_2 ; 0 input -> 0 output + norm.f r12,DBL1L + mov.mi r12,21 + add.pl r12,r12,22 + neg r11,r12 + asl_s r12,r12,20 + lsr.f DBL1H,DBL1L,r11 + ror DBL1L,DBL1L,r11 + sub_s DBL0H,DBL0H,r12 + mov.eq DBL1H,DBL1L + sub_l DBL1L,DBL1L,DBL1H + /* Fall through. */ + .global __muldf3 + .balign 4 +__muldf3: + mulu64 DBL0L,DBL1L + ld.as r9,[pcl,0x68] ; ((.L7ff00000-.+2)/4)] + bmsk r6,DBL0H,19 + bset r6,r6,20 + and r11,DBL0H,r9 + breq.d r11,0,.Ldenorm_dbl0 + and r12,DBL1H,r9 + breq.d r12,0,.Ldenorm_dbl1 + mov r8,mlo + mov r4,mhi + mulu64 r6,DBL1L + breq.d r11,r9,.Linf_nan + bmsk r10,DBL1H,19 + breq.d r12,r9,.Linf_nan + bset r10,r10,20 + add.f r4,r4,mlo + adc r5,mhi,0 + mulu64 r10,DBL0L + add_s r12,r12,r11 ; add exponents + add.f r4,r4,mlo + adc r5,r5,mhi + mulu64 r6,r10 + tst r8,r8 + bclr r8,r9,30 ; 0x3ff00000 + bset.ne r4,r4,0 ; put least significant word into sticky bit + bclr r6,r9,20 ; 0x7fe00000 + add.f r5,r5,mlo + adc r7,mhi,0 ; fraction product in r7:r5:r4 + lsr.f r10,r7,9 + rsub.eq r8,r8,r9 ; 0x40000000 + sub r12,r12,r8 ; subtract bias + implicit 1 + brhs.d r12,r6,.Linf_denorm + rsub r10,r10,12 +.Lshift_frac: + neg r8,r10 + asl r6,r4,r10 + lsr DBL0L,r4,r8 + add.f 0,r6,r6 + btst.eq DBL0L,0 + cmp.eq r4,r4 ; round to nearest / round to even + asl r4,r5,r10 + lsr r5,r5,r8 + adc.f DBL0L,DBL0L,r4 + xor.f 0,DBL0H,DBL1H + asl r7,r7,r10 + add_s r12,r12,r5 + adc DBL0H,r12,r7 + j_s.d [blink] + bset.mi DBL0H,DBL0H,31 + +/* N.B. This is optimized for ARC700. + ARC600 has very different scheduling / instruction selection criteria. */ + +/* If one number is denormal, subtract some from the exponent of the other + one (if the other exponent is too small, return 0), and normalize the + denormal. Then re-run the computation. */ +.Lret0_2: + lsr_s DBL0H,DBL0H,31 + asl_s DBL0H,DBL0H,31 + j_s.d [blink] + mov_s DBL0L,0 + .balign 4 +.Ldenorm_dbl0: + mov_s r12,DBL0L + mov_s DBL0L,DBL1L + mov_s DBL1L,r12 + mov_s r12,DBL0H + mov_s DBL0H,DBL1H + mov_s DBL1H,r12 + and r11,DBL0H,r9 +.Ldenorm_dbl1: + brhs r11,r9,.Linf_nan + brhs 0x3ca00001,r11,.Lret0 + sub_s DBL0H,DBL0H,DBL1H + bmsk.f DBL1H,DBL1H,30 + add_s DBL0H,DBL0H,DBL1H + beq.d .Ldenorm_2 + norm r12,DBL1H + sub_s r12,r12,10 + asl r5,r12,20 + asl_s DBL1H,DBL1H,r12 + sub DBL0H,DBL0H,r5 + neg r5,r12 + lsr r6,DBL1L,r5 + asl_s DBL1L,DBL1L,r12 + b.d __muldf3 + add_s DBL1H,DBL1H,r6 + +.Lret0: xor_s DBL0H,DBL0H,DBL1H + bclr DBL1H,DBL0H,31 + xor_s DBL0H,DBL0H,DBL1H + j_s.d [blink] + mov_s DBL0L,0 + + .balign 4 +.Linf_nan: + bclr r12,DBL1H,31 + xor_s DBL1H,DBL1H,DBL0H + bclr_s DBL0H,DBL0H,31 + max r8,DBL0H,r12 ; either NaN -> NaN ; otherwise inf + or.f 0,DBL0H,DBL0L + mov_s DBL0L,0 + or.ne.f DBL1L,DBL1L,r12 + not_s DBL0H,DBL0L ; inf * 0 -> NaN + mov.ne DBL0H,r8 + tst_s DBL1H,DBL1H + j_s.d [blink] + bset.mi DBL0H,DBL0H,31 + +/* We have checked for infinity / NaN input before, and transformed + denormalized inputs into normalized inputs. Thus, the worst case + exponent overflows are: + 1 + 1 - 0x400 == 0xc02 : maximum underflow + 0x7fe + 0x7fe - 0x3ff == 0xbfd ; maximum overflow + N.B. 0x7e and 0x7f are also values for overflow. + + If (r12 <= -54), we have an underflow to zero. */ + .balign 4 +.Linf_denorm: + lsr r6,r12,28 + brlo.d r6,0xc,.Linf + asr r6,r12,20 + add.f r10,r10,r6 + brgt.d r10,0,.Lshift_frac + mov_s r12,0 + beq.d .Lround_frac + add r10,r10,32 +.Lshift32_frac: + tst r4,r4 + mov r4,r5 + bset.ne r4,r4,1 + mov r5,r7 + brge.d r10,1,.Lshift_frac + mov r7,0 + breq.d r10,0,.Lround_frac + add r10,r10,32 + brgt r10,21,.Lshift32_frac + b_s .Lret0 + +.Lround_frac: + add.f 0,r4,r4 + btst.eq r5,0 + mov_s DBL0L,r5 + mov_s DBL0H,r7 + adc.eq.f DBL0L,DBL0L,0 + j_s.d [blink] + adc.eq DBL0H,DBL0H,0 + +.Linf: mov_s DBL0L,0 + xor.f DBL1H,DBL1H,DBL0H + mov_s DBL0H,r9 + j_s.d [blink] + bset.mi DBL0H,DBL0H,31 + ENDFUNC(__muldf3) + + .balign 4 +.L7ff00000: + .long 0x7ff00000 diff --git a/libgcc/config/arc/ieee-754/arc600-mul64/mulsf3.S b/libgcc/config/arc/ieee-754/arc600-mul64/mulsf3.S new file mode 100644 index 00000000000..619662491b2 --- /dev/null +++ b/libgcc/config/arc/ieee-754/arc600-mul64/mulsf3.S @@ -0,0 +1,180 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "../arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __mulsf3 + FUNC(__mulsf3) + .balign 4 +__mulsf3: + push_s blink + push_s r1 + bl.d __mulsf3_c + push_s r0 + ld_s r1,[sp,4] + st_s r0,[sp,4] + bl.d __mulsf3_asm + pop_s r0 + pop_s r1 + pop_s blink + cmp r0,r1 + jeq_s [blink] + and r12,r0,r1 + bic.f 0,0x7f800000,r12 + bne 0f + bmsk.f 0,r0,22 + bmsk.ne.f r1,r1,22 + jne_s [blink] ; both NaN -> OK +0: bl abort + ENDFUNC(__mulsf3) +#define __mulsf3 __mulsf3_asm +#endif /* DEBUG */ + + .balign 4 + .global __mulsf3 + FUNC(__mulsf3) +__mulsf3: + ld.as r9,[pcl,80]; [pcl,((.L7f800000-.+2)/4)] + bmsk r4,r1,22 + bset r2,r0,23 + asl_s r2,r2,8 + bset r3,r4,23 + mulu64 r2,r3 + and r11,r0,r9 + breq.d r11,0,.Ldenorm_dbl0 + and r12,r1,r9 + breq.d r12,0,.Ldenorm_dbl1 + xor_s r0,r0,r1 + breq.d r11,r9,.Linf_nan_dbl0 + ld.as r4,[pcl,70]; [pcl,((.L7fffffff-.+2)/4)] + breq.d r12,r9,.Linf_nan_dbl1 +.Lpast_denorm: + asl.f 0,mhi,8 + mov r6,mhi + mov r7,mlo + add.pl r6,r6,r6 + bclr.pl r6,r6,23 + add.pl.f r7,r7,r7 + add.cs r6,r6,1 + lsr.f 0,r6,1 + add_s r12,r12,r11 + adc.f 0,r7,r4 + add_s r12,r12, \ + -0x3f800000 + adc.f r8,r6,r12 + tst.pl r8,r9 + bic r0,r0,r4 + min r3,r8,r9 + jpnz.d [blink] + add.pnz r0,r0,r3 +; infinity or denormal number + add.ne.f r3,r3,r3 + asr_s r3,r3,23+1 + bset r6,r6,23 + bpnz.d .Linfinity + sub_s r3,r3,1 + neg_s r2,r3 + brhi.d r2,24,.Lret_r0 ; right shift shift > 24 -> return +-0 + lsr r2,r6,r2 + asl r9,r6,r3 + lsr.f 0,r2,1 + tst r7,r7 + add_s r0,r0,r2 + bset.ne r9,r9,0 + adc.f 0,r9,r4 + j_s.d [blink] + add.cs r0,r0,1 +.Linfinity: + j_s.d [blink] + add_s r0,r0,r9 + +.Lret_r0: j_s [blink] + + .balign 4 +.Ldenorm_dbl0: + bclr_s r2,r2,31 + norm.f r4,r2 + add_s r2,r2,r2 + asl r2,r2,r4 + mulu64 r2,r3 + breq.d r12,r9,.Ldenorm_dbl0_inf_nan_dbl1 + asl r4,r4,23 + sub.ne.f r12,r12,r4 + ld.as r4,[pcl,29]; [pcl,((.L7fffffff-.+2)/4)] + bhi.d .Lpast_denorm + xor_s r0,r0,r1 + bmsk r1,r0,30 + j_s.d [blink] + bic_s r0,r0,r1 + + .balign 4 +.Ldenorm_dbl0_inf_nan_dbl1: + bmsk.f 0,r0,30 + beq_s .Lretnan + xor_s r0,r0,r1 +.Linf_nan_dbl1: + xor_s r1,r1,r0 +.Linf_nan_dbl0: + bclr_s r1,r1,31 + cmp_s r1,r9 + jls.d [blink] + xor_s r0,r0,r1 +; r1 NaN -> result NaN +.Lretnan: + j_s.d [blink] + mov r0,-1 + + .balign 4 +.Ldenorm_dbl1: + breq.d r11,r9,.Linf_nan_dbl0_2 + norm.f r3,r4 + sub_s r3,r3,7 + asl r4,r4,r3 + mulu64 r2,r4 + sub_s r3,r3,1 + asl_s r3,r3,23 + sub.ne.f r11,r11,r3 + ld.as r4,[pcl,11]; [pcl,((.L7fffffff-.+2)/4)] + bhi.d .Lpast_denorm + bmsk r8,r0,30 + j_s.d [blink] + bic r0,r0,r8 + + .balign 4 +.Linf_nan_dbl0_2: + bclr_s r1,r1,31 + xor_s r0,r0,r1 + sub.eq r1,r1,1 ; inf/nan * 0 -> nan + bic.f 0,r9,r1 + j_s.d [blink] + or.eq r0,r0,r1 ; r1 nan -> result nan + + .balign 4 +.L7f800000: + .long 0x7f800000 +.L7fffffff: + .long 0x7fffffff + ENDFUNC(__mulsf3) diff --git a/libgcc/config/arc/ieee-754/arc600/divsf3.S b/libgcc/config/arc/ieee-754/arc600/divsf3.S new file mode 100644 index 00000000000..7fcbadbe086 --- /dev/null +++ b/libgcc/config/arc/ieee-754/arc600/divsf3.S @@ -0,0 +1,227 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "../arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __divsf3 + FUNC(__divsf3) + .balign 4 +__divsf3: + push_s blink + push_s r1 + bl.d __divsf3_c + push_s r0 + ld_s r1,[sp,4] + st_s r0,[sp,4] + bl.d __divsf3_asm + pop_s r0 + pop_s r1 + pop_s blink + cmp r0,r1 + jeq_s [blink] + and r12,r0,r1 + bic.f 0,0x7f800000,r12 ; both NaN -> OK + jeq_s [blink] + bl abort + ENDFUNC(__divsf3) +#define __divsf3 __divsf3_asm +#endif /* DEBUG */ + + .balign 4 +__divdf3_support: /* This label makes debugger output saner. */ + FUNC(__divsf3) +.Ldenorm_fp0: + norm.f r12,r2 ; flag for 0/x -> 0 check + bic.ne.f 0,0x60000000,r1 ; denorm/large number -> 0 + beq_s .Lret0_NaN + tst r1,r9 + add_s r2,r2,r2 + sub_s r12,r12,8 + asl_s r2,r2,r12 + asl_l r12,r12,23 + bne.d .Lpast_denorm_fp0 + add r5,r5,r12 +/* r0 is subnormal, r1 is subnormal or 0. */ + + .balign 4 +.Ldenorm_fp1: + norm.f r12,r3 ; flag for x/0 -> Inf check + bic.ne.f 0,0x60000000,r0 ; large number/denorm -> Inf + beq_s .Linf + add_s r3,r3,r3 + sub_s r12,r12,8 + asl_s r3,r3,r12 + asl_s r12,r12,23 + b.d .Lpast_denorm_fp1 + add r4,r4,r12 + +.Lret0_NaN: + bclr.f 0,r1,31 ; 0/0 -> NaN + bic r0,r10,r9 + j_s.d [blink] + sub.eq r0,r0,1 + + .balign 4 +.Linf_nan_fp0: + bic.f 0,r9,r1 ; fp1 Inf -> result NaN + bic r1,r5,r9 ; fp1 sign + sub.eq r1,r1,1 + j_s.d [blink] + xor_s r0,r0,r1 +.Linf_nan_fp1: + bic r0,r4,r9 ; fp0 sign + bmsk.f 0,r1,22 ; x/inf -> 0, x/nan -> nan + xor.eq r1,r1,r9 + j_s.d [blink] + xor_s r0,r0,r1 + + .global __divsf3 + .balign 4 + .long 0x7f800000 ; exponent mask +__divsf3: + ld r9,[pcl,-4] + bmsk r2,r0,22 + xor r4,r0,r2 + bmsk r3,r1,22 + xor r5,r1,r3 + and r11,r0,r9 + breq.d r11,0,.Ldenorm_fp0 + xor r10,r4,r5 + breq r11,r9,.Linf_nan_fp0 + bset_s r2,r2,23 + and r11,r1,r9 + breq r11,0,.Ldenorm_fp1 + breq r11,r9,.Linf_nan_fp1 +.Lpast_denorm_fp0: + bset_s r3,r3,23 +.Lpast_denorm_fp1: + cmp r2,r3 + asl_s r2,r2,6+1 + asl_s r3,r3,7 + add.lo r2,r2,r2 + bclr r8,r9,30 ; exponent bias + bclr.lo r8,r8,23 ; reduce exp by one if fraction is shifted + sub r4,r4,r5 + add r4,r4,r8 + xor.f 0,r10,r4 + bmi .Linf_denorm + and.f r12,r4,r9 + beq .Ldenorm + sub_s r2,r2,r3 ; discard implicit 1 + rsub r3,r3,1 ; prime r3 for two-insn divide-step use +.Ldiv_23bit: + .rep 6 + add1.f r2,r3,r2 + sub.cc r2,r2,r3 + .endr + breq r12,r9,.Linf + bmsk r0,r2,6 + xor_s r2,r2,r0 +.Ldiv_17bit: + .rep 7 + add1.f r2,r3,r2 + sub.cc r2,r2,r3 + .endr + asl_s r0,r0,7 + bmsk r1,r2,6 + xor_s r2,r2,r1 + or_s r0,r0,r1 +.Ldiv_10bit: + .rep 7 + add1.f r2,r3,r2 + sub.cc r2,r2,r3 + .endr + asl_s r0,r0,7 + bmsk r1,r2,6 + xor_s r2,r2,r1 + or_s r0,r0,r1 +.Ldiv_3bit: + .rep 3 + add1.f r2,r3,r2 + sub.cc r2,r2,r3 + .endr + asl_s r0,r0,3 +.Ldiv_0bit: + add1.f r1,r3,r2 + sub.cc r1,r1,r3 + bmsk_s r2,r2,2 + tst r1,-0x7e ; 0xffffff82, test for rest or odd + bmsk_s r1,r1,0 + add_s r0,r0,r2 ; assemble fraction + add_s r0,r0,r4 ; add in sign & exponent + j_s.d [blink] + add.ne r0,r0,r1 ; round to nearest / even + + .balign 4 +.Linf: + j_s.d [blink] + or r0,r10,r9 + +.Lret_r4: + j_s.d [blink] + mov_s r0,r4 + .balign 4 +.Linf_denorm: + add.f r12,r4,r4 + asr_l r12,r12,24 + bpl .Linf + max r12,r12,-24 +.Ldenorm: + rsub r3,r3,1 + add r1,pcl,68; .Ldenorm_tab-. + ldw.as r12,[r1,r12] + mov_s r0,0 + lsr_s r2,r2 + sub_s r1,r1,r12 + j_s.d [r1] + bic r4,r10,r9 + .short .Ldenorm_tab-.Lret_r4 + .short .Ldenorm_tab-.Ldiv_0bit + .short .Ldenorm_tab-.Ldiv_3bit-2*8 + .short .Ldenorm_tab-.Ldiv_3bit-1*8 + .short .Ldenorm_tab-.Ldiv_3bit + .short .Ldenorm_tab-.Ldiv_10bit-6*8 + .short .Ldenorm_tab-.Ldiv_10bit-5*8 + .short .Ldenorm_tab-.Ldiv_10bit-3*8 + .short .Ldenorm_tab-.Ldiv_10bit-3*8 + .short .Ldenorm_tab-.Ldiv_10bit-2*8 + .short .Ldenorm_tab-.Ldiv_10bit-1*8 + .short .Ldenorm_tab-.Ldiv_10bit + .short .Ldenorm_tab-.Ldiv_17bit-6*8 + .short .Ldenorm_tab-.Ldiv_17bit-5*8 + .short .Ldenorm_tab-.Ldiv_17bit-4*8 + .short .Ldenorm_tab-.Ldiv_17bit-3*8 + .short .Ldenorm_tab-.Ldiv_17bit-2*8 + .short .Ldenorm_tab-.Ldiv_17bit-1*8 + .short .Ldenorm_tab-.Ldiv_17bit + .short .Ldenorm_tab-.Ldiv_23bit-5*8 + .short .Ldenorm_tab-.Ldiv_23bit-4*8 + .short .Ldenorm_tab-.Ldiv_23bit-3*8 + .short .Ldenorm_tab-.Ldiv_23bit-2*8 + .short .Ldenorm_tab-.Ldiv_23bit-1*8 +.Ldenorm_tab: + .short .Ldenorm_tab-.Ldiv_23bit + ENDFUNC(__divsf3) diff --git a/libgcc/config/arc/ieee-754/arc600/mulsf3.S b/libgcc/config/arc/ieee-754/arc600/mulsf3.S new file mode 100644 index 00000000000..e3f0a3c12b6 --- /dev/null +++ b/libgcc/config/arc/ieee-754/arc600/mulsf3.S @@ -0,0 +1,179 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "../arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __mulsf3 + FUNC(__mulsf3) + .balign 4 +__mulsf3: + push_s blink + push_s r1 + bl.d __mulsf3_c + push_s r0 + ld_s r1,[sp,4] + st_s r0,[sp,4] + bl.d __mulsf3_asm + pop_s r0 + pop_s r1 + pop_s blink + cmp r0,r1 + jeq_s [blink] + and r12,r0,r1 + bic.f 0,0x7f800000,r12 + bne 0f + bmsk.f 0,r0,22 + bmsk.ne.f r1,r1,22 + jne_s [blink] ; both NaN -> OK +0: bl abort + ENDFUNC(__mulsf3) +#define __mulsf3 __mulsf3_asm +#endif /* DEBUG */ + + .balign 4 + .global __mulsf3 + FUNC(__mulsf3) +__mulsf3: + ld.as r9,[pcl,76]; [pcl,((.L7f800000-.+2)/4)] + bmsk r4,r1,22 + bset r3,r4,23 + bmsk r2,r0,22 + and r11,r0,r9 + breq.d r11,0,.Ldenorm_dbl0 + and r12,r1,r9 + xor_s r0,r0,r1 + breq.d r11,r9,.Linf_nan_dbl0 + bset_s r2,r2,23 + breq r12,0,.Ldenorm_dbl1 + breq r12,r9,.Linf_nan_dbl1 +.Lpast_denorm: + mov r6,0 + lsr.f r7,r2 +; We could so this a bit faster here with a 32 bit shift register and +; inserting the r2 factor / retrieving the low result a byte at a time, +; but that'd increase code size. + mov lp_count,24 + .balign 4 + lp 0f + add.cs r6,r6,r3 + lsr.f r6,r6 + rrc.f r7,r7 +0: + ld.as r4,[pcl,59]; [pcl,((.L7fffffff-.+2)/4)] + asl.f 0,r6,8 + add.pl r6,r6,r6 + bclr.pl r6,r6,23 + add.pl.f r7,r7,r7 + add.cs r6,r6,1 + lsr.f 0,r6,1 + add_s r12,r12,r11 + adc.f 0,r7,r4 + add_s r12,r12, \ + -0x3f800000 + adc.f r8,r6,r12 + tst.pl r8,r9 + bic r0,r0,r4 + min r3,r8,r9 + jpnz.d [blink] + add.pnz r0,r0,r3 +; infinity or denormal number + add.ne.f r3,r3,r3 + asr_s r3,r3,23+1 + bset r6,r6,23 + bpnz.d .Linfinity + sub_s r3,r3,1 + neg_s r2,r3 + brhi.d r2,24,.Lret_r0 ; right shift shift > 24 -> return +-0 + lsr r2,r6,r2 + asl r9,r6,r3 + lsr.f 0,r2,1 + tst r7,r7 + add_s r0,r0,r2 + bset.ne r9,r9,0 + adc.f 0,r9,r4 + j_s.d [blink] + add.cs r0,r0,1 +.Linfinity: + j_s.d [blink] + add_s r0,r0,r9 + +.Lret_r0: j_s [blink] + + .balign 4 +.Ldenorm_dbl0: + asl_s r2,r2,8 + norm.f r4,r2 + lsr_s r2,r2,7 + asl r2,r2,r4 + breq.d r12,r9,.Ldenorm_dbl0_inf_nan_dbl1 + asl r4,r4,23 + sub.ne.f r12,r12,r4 + bhi.d .Lpast_denorm + xor_s r0,r0,r1 + bmsk r1,r0,30 + j_s.d [blink] + bic_s r0,r0,r1 + + .balign 4 +.Ldenorm_dbl0_inf_nan_dbl1: + bmsk.f 0,r0,30 + beq_s .Lretnan + xor_s r0,r0,r1 +.Linf_nan_dbl1: + xor_s r1,r1,r0 + bclr_s r1,r1,31 + j_s.d [blink] + xor_s r0,r0,r1 +.Linf_nan_dbl0: + sub_s r2,r1,1 ; inf/nan * 0 -> nan; inf * nan -> nan (use |r2| >= inf) + bic.f 0,r9,r2 + xor_s r0,r0,r1 + bclr_s r1,r1,31 + xor_s r0,r0,r1 + jne_s [blink] +.Lretnan: + j_s.d [blink] + mov r0,-1 + .balign 4 +.Ldenorm_dbl1: + norm.f r3,r4 + sub_s r3,r3,7 + asl r4,r4,r3 + sub_s r3,r3,1 + asl_s r3,r3,23 + sub.ne.f r11,r11,r3 + bhi.d .Lpast_denorm + mov_s r3,r4 + bmsk r3,r0,30 + j_s.d [blink] + bic_s r0,r0,r3 + + .balign 4 +.L7f800000: + .long 0x7f800000 +.L7fffffff: + .long 0x7fffffff + ENDFUNC(__mulsf3) diff --git a/libgcc/config/arc/ieee-754/divdf3.S b/libgcc/config/arc/ieee-754/divdf3.S new file mode 100644 index 00000000000..783cee352b3 --- /dev/null +++ b/libgcc/config/arc/ieee-754/divdf3.S @@ -0,0 +1,416 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* + to calculate a := b/x as b*y, with y := 1/x: + - x is in the range [1..2) + - calculate 15..18 bit inverse y0 using a table of approximating polynoms. + Precision is higher for polynoms used to evaluate input with larger + value. + - Do one newton-raphson iteration step to double the precision, + then multiply this with the divisor + -> more time to decide if dividend is subnormal + - the worst error propagation is on the side of the value range + with the least initial defect, thus giving us about 30 bits precision. + The truncation error for the either is less than 1 + x/2 ulp. + A 31 bit inverse can be simply calculated by using x with implicit 1 + and chaining the multiplies. For a 32 bit inverse, we multiply y0^2 + with the bare fraction part of x, then add in y0^2 for the implicit + 1 of x. + - If calculating a 31 bit inverse, the systematic error is less than + -1 ulp; likewise, for 32 bit, it is less than -2 ulp. + - If we calculate our seed with a 32 bit fraction, we can archive a + tentative result strictly better than -2 / +2.5 (1) ulp/128, i.e. we + only need to take the step to calculate the 2nd stage rest and + rounding adjust 1/32th of the time. However, if we use a 20 bit + fraction for the seed, the negative error can exceed -2 ulp/128, (2) + thus for a simple add / tst check, we need to do the 2nd stage + rest calculation/ rounding adjust 1/16th of the time. + (1): The inexactness of the 32 bit inverse contributes an error in the + range of (-1 .. +(1+x/2) ) ulp/128. Leaving out the low word of the + rest contributes an error < +1/x ulp/128 . In the interval [1,2), + x/2 + 1/x <= 1.5 . + (2): Unless proven otherwise. I have not actually looked for an + example where -2 ulp/128 is exceeded, and my calculations indicate + that the excess, if existent, is less than -1/512 ulp. + */ +#include "arc-ieee-754.h" + +/* N.B. fp-bit.c does double rounding on denormal numbers. */ +#if 0 /* DEBUG */ + .global __divdf3 + FUNC(__divdf3) + .balign 4 +__divdf3: + push_s blink + push_s r2 + push_s r3 + push_s r0 + bl.d __divdf3_c + push_s r1 + ld_s r2,[sp,12] + ld_s r3,[sp,8] + st_s r0,[sp,12] + st_s r1,[sp,8] + pop_s r1 + bl.d __divdf3_asm + pop_s r0 + pop_s r3 + pop_s r2 + pop_s blink + cmp r0,r2 + cmp.eq r1,r3 + jeq_s [blink] + and r12,DBL0H,DBL1H + bic.f 0,0x7ff80000,r12 ; both NaN -> OK + jeq_s [blink] + bl abort + ENDFUNC(__divdf3) +#define __divdf3 __divdf3_asm +#endif /* DEBUG */ + + FUNC(__divdf3) +__divdf3_support: /* This label makes debugger output saner. */ + .balign 4 +.Ldenorm_dbl1: + brge r6, \ + 0x43500000,.Linf_NaN ; large number / denorm -> Inf + bmsk.f r12,DBL1H,19 + mov.eq r12,DBL1L + mov.eq DBL1L,0 + sub.eq r7,r7,32 + norm.f r11,r12 ; flag for x/0 -> Inf check + beq_s .Linf_NaN + mov.mi r11,0 + add.pl r11,r11,1 + add_s r12,r12,r12 + asl r8,r12,r11 + rsub r12,r11,31 + lsr r12,DBL1L,r12 + tst_s DBL1H,DBL1H + or r8,r8,r12 + lsr r4,r8,26 + lsr DBL1H,r8,12 + ld.as r4,[r10,r4] + bxor.mi DBL1H,DBL1H,31 + sub r11,r11,11 + asl DBL1L,DBL1L,r11 + sub r11,r11,1 + mpyhu r5,r4,r8 + sub r7,r7,r11 + asl r4,r4,12 + b.d .Lpast_denorm_dbl1 + asl r7,r7,20 + ; wb stall + + .balign 4 +.Ldenorm_dbl0: + bmsk.f r12,DBL0H,19 + ; wb stall + mov.eq r12,DBL0L + sub.eq r6,r6,32 + norm.f r11,r12 ; flag for 0/x -> 0 check + brge r7, \ + 0x43500000, .Lret0_NaN ; denorm/large number -> 0 + beq_s .Lret0_NaN + mov.mi r11,0 + add.pl r11,r11,1 + asl r12,r12,r11 + sub r6,r6,r11 + add.f 0,r6,31 + lsr r10,DBL0L,r6 + mov.mi r10,0 + add r6,r6,11+32 + neg.f r11,r6 + asl DBL0L,DBL0L,r11 + mov.pl DBL0L,0 + sub r6,r6,32-1 + b.d .Lpast_denorm_dbl0 + asl r6,r6,20 + +.Linf_NaN: + tst_s DBL0L,DBL0L ; 0/0 -> NaN + xor_s DBL1H,DBL1H,DBL0H + bclr.eq.f DBL0H,DBL0H,31 + bmsk DBL0H,DBL1H,30 + xor_s DBL0H,DBL0H,DBL1H + sub.eq DBL0H,DBL0H,1 + mov_s DBL0L,0 + j_s.d [blink] + or DBL0H,DBL0H,r9 + .balign 4 +.Lret0_NaN: + xor_s DBL1H,DBL1H,DBL0H + cmp_s r12,r9 + mov_s DBL0L,0 + bmsk DBL0H,DBL1H,30 + xor_s DBL0H,DBL0H,DBL1H + j_s.d [blink] + sub.hi DBL0H,DBL0H,1 +.Linf_nan_dbl1: ; Inf/Inf -> NaN x/Inf-> 0 x/NaN -> NaN + not_s DBL0L,DBL1H + cmp r6,r9 + sub_s.ne DBL0L,DBL0L,DBL0L + tst_s DBL0H,DBL0H + add_s DBL0H,DBL1H,DBL0L + j_s.d [blink] + bxor.mi DBL0H,DBL0H,31 +.Linf_nan_dbl0: + tst_s DBL1H,DBL1H + j_s.d [blink] + bxor.mi DBL0H,DBL0H,31 + .balign 4 + .global __divdf3 +/* N.B. the spacing between divtab and the add3 to get its address must + be a multiple of 8. */ +__divdf3: + asl r8,DBL1H,12 + lsr r12,DBL1L,20 + lsr r4,r8,26 + add3 r10,pcl,59 ; (.Ldivtab-.) >> 3 + ld.as r4,[r10,r4] + ld.as r9,[pcl,180]; [pcl,(-((.-.L7ff00000) >> 2))] ; 0x7ff00000 + or r8,r8,r12 + mpyhu r5,r4,r8 + and.f r7,DBL1H,r9 + asl r4,r4,12 ; having the asl here is a concession to the XMAC pipeline. + beq.d .Ldenorm_dbl1 + and r6,DBL0H,r9 +.Lpast_denorm_dbl1: ; wb stall + sub r4,r4,r5 + mpyhu r5,r4,r4 + breq.d r6,0,.Ldenorm_dbl0 + lsr r8,r8,1 + asl r12,DBL0H,11 + lsr r10,DBL0L,21 +.Lpast_denorm_dbl0: ; wb stall + bset r8,r8,31 + mpyhu r11,r5,r8 + add_s r12,r12,r10 + bset r5,r12,31 + cmp r5,r8 + cmp.eq DBL0L,DBL1L + ; wb stall + lsr.cc r5,r5,1 + sub r4,r4,r11 ; u1.31 inverse, about 30 bit + mpyhu r11,r5,r4 ; result fraction highpart + breq r7,r9,.Linf_nan_dbl1 + lsr r8,r8,2 ; u3.29 + add r5,r6, /* wait for immediate / XMAC wb stall */ \ + 0x3fe00000 + ; wb stall (not for XMAC) + breq r6,r9,.Linf_nan_dbl0 + mpyu r12,r11,r8 ; u-28.31 + asl_s DBL1L,DBL1L,9 ; u-29.23:9 + sbc r6,r5,r7 + ; resource conflict (not for XMAC) + mpyhu r5,r11,DBL1L ; u-28.23:9 + add.cs DBL0L,DBL0L,DBL0L + asl_s DBL0L,DBL0L,6 ; u-26.25:7 + asl r10,r11,23 + sub_l DBL0L,DBL0L,r12 + ; wb stall (before 'and' for XMAC) + lsr r7,r11,9 + sub r5,DBL0L,r5 ; rest msw ; u-26.31:0 + mpyh r12,r5,r4 ; result fraction lowpart + xor.f 0,DBL0H,DBL1H + and DBL0H,r6,r9 + add_s DBL0H,DBL0H,r7 ; (XMAC wb stall) + bxor.mi DBL0H,DBL0H,31 + brhs r6, /* wb stall / wait for immediate */ \ + 0x7fe00000,.Linf_denorm + add.f r12,r12,0x11 + asr r9,r12,5 + sub.mi DBL0H,DBL0H,1 + add.f DBL0L,r9,r10 + tst r12,0x1c + jne.d [blink] + add.cs DBL0H,DBL0H,1 + /* work out exact rounding if we fall through here. */ + /* We know that the exact result cannot be represented in double + precision. Find the mid-point between the two nearest + representable values, multiply with the divisor, and check if + the result is larger than the dividend. Since we want to know + only the sign bit, it is sufficient to calculate only the + highpart of the lower 64 bits. */ + sub.f DBL0L,DBL0L,1 + asl r12,r9,2 ; u-22.30:2 + mpyu r10,r11,DBL1L ; rest before considering r12 in r5 : -r10 + sub.cs DBL0H,DBL0H,1 + sub.f r12,r12,2 + ; resource conflict (not for XMAC) + mpyhu r7,r12,DBL1L ; u-51.32 + asl r5,r5,25 ; s-51.7:25 + lsr r10,r10,7 ; u-51.30:2 + ; resource conflict (not for XMAC) + ; resource conflict (not for XMAC) + mpyu r9,r12,r8 ; u-51.31:1 + sub r5,r5,r10 + add.mi r5,r5,DBL1L ; signed multiply adjust for r12*DBL1L + bset r7,r7,0 ; make sure that the result is not zero, and that + ; wb stall (one earlier for XMAC) + sub r5,r5,r7 ; a highpart zero appears negative + sub.f r5,r5,r9 ; rest msw + add.pl.f DBL0L,DBL0L,1 + j_s.d [blink] + add.eq DBL0H,DBL0H,1 + + .balign 4 +.Linf_denorm: + brlo r6,0xc0000000,.Linf +.Ldenorm: + asr r6,r6,20 + neg r9,r6 + mov_s DBL0H,0 + brhs.d r9,54,.Lret0 + bxor.mi DBL0H,DBL0H,31 + add_l r12,r12,1 + and r12,r12,-4 + rsub r7,r6,5 + asr r10,r12,28 + bmsk r4,r12,27 + asrs DBL0L,r4,r7 + add DBL1H,r11,r10 + add.f r7,r6,32-5 + abss r10,r4 + asl r4,r4,r7 + mov.mi r4,r10 + add.f r10,r6,23 + rsub r7,r6,9 + lsr r7,DBL1H,r7 + asl r10,DBL1H,r10 + or.pnz DBL0H,DBL0H,r7 + or.mi r4,r4,r10 + mov.mi r10,r7 + add.f DBL0L,r10,DBL0L + add.cs.f DBL0H,DBL0H,1 ; carry clear after this point + bxor.f 0,r4,31 + add.pnz.f DBL0L,DBL0L,1 + add.cs.f DBL0H,DBL0H,1 + jne_l [blink] + /* Calculation so far was not conclusive; calculate further rest. */ + mpyu r11,r11,DBL1L ; rest before considering r12 in r5 : -r11 + asr.f r12,r12,3 + asl r5,r5,25 ; s-51.7:25 + ; resource conflict (not for XMAC) + mpyu DBL1H,r12,r8 ; u-51.31:1 + and r9,DBL0L,1 ; tie-breaker: round to even + lsr r11,r11,7 ; u-51.30:2 + ; resource conflict (not for XMAC) + mpyhu r8,r12,DBL1L ; u-51.32 + sub.mi r11,r11,DBL1L ; signed multiply adjust for r12*DBL1L + add_s DBL1H,DBL1H,r11 + ; resource conflict (not for XMAC) + ; resource conflict (not for XMAC) + mpyu r12,r12,DBL1L ; u-83.30:2 + sub DBL1H,DBL1H,r5 ; -rest msw + add_s DBL1H,DBL1H,r8 ; -rest msw + add.f 0,DBL1H,DBL1H ; can't ror.f by 32 :-( + ; wb stall (XMAC: Before add.f) + tst_s DBL1H,DBL1H + cmp.eq r12,r9 + add.cs.f DBL0L,DBL0L,1 + j_s.d [blink] + add.cs DBL0H,DBL0H,1 + +.Lret0: + /* return +- 0 */ + j_s.d [blink] + mov_s DBL0L,0 +.Linf: + mov_s DBL0H,r9 + mov_s DBL0L,0 + j_s.d [blink] + bxor.mi DBL0H,DBL0H,31 + + .balign 4 +.Ldivtab: + .long 0xfc0fffe1 + .long 0xf46ffdfb + .long 0xed1ffa54 + .long 0xe61ff515 + .long 0xdf7fee75 + .long 0xd91fe680 + .long 0xd2ffdd52 + .long 0xcd1fd30c + .long 0xc77fc7cd + .long 0xc21fbbb6 + .long 0xbcefaec0 + .long 0xb7efa100 + .long 0xb32f92bf + .long 0xae8f83b7 + .long 0xaa2f7467 + .long 0xa5ef6479 + .long 0xa1cf53fa + .long 0x9ddf433e + .long 0x9a0f3216 + .long 0x965f2091 + .long 0x92df0f11 + .long 0x8f6efd05 + .long 0x8c1eeacc + .long 0x88eed876 + .long 0x85dec615 + .long 0x82eeb3b9 + .long 0x800ea10b + .long 0x7d3e8e0f + .long 0x7a8e7b3f + .long 0x77ee6836 + .long 0x756e5576 + .long 0x72fe4293 + .long 0x709e2f93 + .long 0x6e4e1c7f + .long 0x6c0e095e + .long 0x69edf6c5 + .long 0x67cde3a5 + .long 0x65cdd125 + .long 0x63cdbe25 + .long 0x61ddab3f + .long 0x600d991f + .long 0x5e3d868c + .long 0x5c6d7384 + .long 0x5abd615f + .long 0x590d4ecd + .long 0x576d3c83 + .long 0x55dd2a89 + .long 0x545d18e9 + .long 0x52dd06e9 + .long 0x516cf54e + .long 0x4ffce356 + .long 0x4e9cd1ce + .long 0x4d3cbfec + .long 0x4becae86 + .long 0x4aac9da4 + .long 0x496c8c73 + .long 0x483c7bd3 + .long 0x470c6ae8 + .long 0x45dc59af + .long 0x44bc4915 + .long 0x43ac3924 + .long 0x428c27fb + .long 0x418c187a + .long 0x407c07bd +.L7ff00000: + .long 0x7ff00000 + ENDFUNC(__divdf3) diff --git a/libgcc/config/arc/ieee-754/divsf3-stdmul.S b/libgcc/config/arc/ieee-754/divsf3-stdmul.S new file mode 100644 index 00000000000..b20f6c3889d --- /dev/null +++ b/libgcc/config/arc/ieee-754/divsf3-stdmul.S @@ -0,0 +1,281 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* + - calculate 15..18 bit inverse using a table of approximating polynoms. + precision is higher for polynoms used to evaluate input with larger + value. + - do one newton-raphson iteration step to double the precision, + then multiply this with the divisor + -> more time to decide if dividend is subnormal + - the worst error propagation is on the side of the value range + with the least initial defect, thus giving us about 30 bits precision. + */ +#include "arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __divsf3 + FUNC(__divsf3) + .balign 4 +__divsf3: + push_s blink + push_s r1 + bl.d __divsf3_c + push_s r0 + ld_s r1,[sp,4] + st_s r0,[sp,4] + bl.d __divsf3_asm + pop_s r0 + pop_s r1 + pop_s blink + cmp r0,r1 +#if 1 + bne abort + jeq_s [blink] + b abort +#else + bne abort + j_s [blink] +#endif + ENDFUNC(__divsf3) +#define __divsf3 __divsf3_asm +#endif /* DEBUG */ + + FUNC(__divsf3) + .balign 4 +.L7f800000: + .long 0x7f800000 +.Ldivtab: + .long 0xfc0ffff0 + .long 0xf46ffefd + .long 0xed1ffd2a + .long 0xe627fa8e + .long 0xdf7ff73b + .long 0xd917f33b + .long 0xd2f7eea3 + .long 0xcd1fe986 + .long 0xc77fe3e7 + .long 0xc21fdddb + .long 0xbcefd760 + .long 0xb7f7d08c + .long 0xb32fc960 + .long 0xae97c1ea + .long 0xaa27ba26 + .long 0xa5e7b22e + .long 0xa1cfa9fe + .long 0x9ddfa1a0 + .long 0x9a0f990c + .long 0x9667905d + .long 0x92df878a + .long 0x8f6f7e84 + .long 0x8c27757e + .long 0x88f76c54 + .long 0x85df630c + .long 0x82e759c5 + .long 0x8007506d + .long 0x7d3f470a + .long 0x7a8f3da2 + .long 0x77ef341e + .long 0x756f2abe + .long 0x72f7212d + .long 0x709717ad + .long 0x6e4f0e44 + .long 0x6c1704d6 + .long 0x69e6fb44 + .long 0x67cef1d7 + .long 0x65c6e872 + .long 0x63cedf18 + .long 0x61e6d5cd + .long 0x6006cc6d + .long 0x5e36c323 + .long 0x5c76b9f3 + .long 0x5abeb0b7 + .long 0x5916a79b + .long 0x57769e77 + .long 0x55de954d + .long 0x54568c4e + .long 0x52d6834d + .long 0x51667a7f + .long 0x4ffe71b5 + .long 0x4e9e68f1 + .long 0x4d466035 + .long 0x4bf65784 + .long 0x4aae4ede + .long 0x496e4646 + .long 0x48363dbd + .long 0x47063547 + .long 0x45de2ce5 + .long 0x44be2498 + .long 0x43a61c64 + .long 0x4296144a + .long 0x41860c0e + .long 0x407e03ee +__divsf3_support: /* This label makes debugger output saner. */ +.Ldenorm_fp1: + bclr r6,r6,31 + norm.f r12,r6 ; flag for x/0 -> Inf check + add r6,r6,r6 + rsub r5,r12,16 + ror r5,r1,r5 + asl r6,r6,r12 + bmsk r5,r5,5 + ld.as r5,[r3,r5] + add r4,r6,r6 + ; load latency + mpyhu r7,r5,r4 + bic.ne.f 0, \ + 0x60000000,r0 ; large number / denorm -> Inf + beq_s .Linf_NaN + asl r5,r5,13 + ; wb stall + ; slow track + sub r7,r5,r7 + mpyhu r8,r7,r6 + asl_s r12,r12,23 + and.f r2,r0,r9 + add r2,r2,r12 + asl r12,r0,8 + ; wb stall + bne.d .Lpast_denorm_fp1 +.Ldenorm_fp0: + mpyhu r8,r8,r7 + bclr r12,r12,31 + norm.f r3,r12 ; flag for 0/x -> 0 check + bic.ne.f 0,0x60000000,r1 ; denorm/large number -> 0 + beq_s .Lret0 + asl_s r12,r12,r3 + asl_s r3,r3,23 + add_s r12,r12,r12 + add r11,r11,r3 + b.d .Lpast_denorm_fp0 + mov_s r3,r12 + .balign 4 +.Linf_NaN: + bclr.f 0,r0,31 ; 0/0 -> NaN + xor_s r0,r0,r1 + bmsk r1,r0,30 + bic_s r0,r0,r1 + sub.eq r0,r0,1 + j_s.d [blink] + or r0,r0,r9 +.Lret0: + xor_s r0,r0,r1 + bmsk r1,r0,30 + j_s.d [blink] + bic_s r0,r0,r1 +.Linf_nan_fp1: + lsr_s r0,r0,31 + bmsk.f 0,r1,22 + asl_s r0,r0,31 + bne_s 0f ; inf/inf -> nan + brne r2,r9,.Lsigned0 ; x/inf -> 0, but x/nan -> nan +0: j_s.d [blink] + mov r0,-1 +.Lsigned0: +.Linf_nan_fp0: + tst_s r1,r1 + j_s.d [blink] + bxor.mi r0,r0,31 + .balign 4 + .global __divsf3 +/* N.B. the spacing between divtab and the sub3 to get its address must + be a multiple of 8. */ +__divsf3: + lsr r2,r1,17 + sub3 r3,pcl,55;(.-.Ldivtab) >> 3 + bmsk_s r2,r2,5 + ld.as r5,[r3,r2] + asl r4,r1,9 + ld.as r9,[pcl,-114]; [pcl,(-((.-.L7f800000) >> 2))] ; 0x7f800000 + mpyhu r7,r5,r4 + asl r6,r1,8 + and.f r11,r1,r9 + bset r6,r6,31 + asl r5,r5,13 + ; wb stall + beq .Ldenorm_fp1 + sub r7,r5,r7 + mpyhu r8,r7,r6 + breq.d r11,r9,.Linf_nan_fp1 + and.f r2,r0,r9 + beq.d .Ldenorm_fp0 + asl r12,r0,8 + ; wb stall + breq r2,r9,.Linf_nan_fp0 + mpyhu r8,r8,r7 +.Lpast_denorm_fp1: + bset r3,r12,31 +.Lpast_denorm_fp0: + cmp_s r3,r6 + lsr.cc r3,r3,1 + add_s r2,r2, /* wait for immediate */ \ + /* wb stall */ \ + 0x3f000000 + sub r7,r7,r8 ; u1.31 inverse, about 30 bit + mpyhu r3,r3,r7 + sbc r2,r2,r11 + xor.f 0,r0,r1 + and r0,r2,r9 + bxor.mi r0,r0,31 + brhs r2, /* wb stall / wait for immediate */ \ + 0x7f000000,.Linf_denorm +.Lpast_denorm: + add_s r3,r3,0x22 ; round to nearest or higher + tst r3,0x3c ; check if rounding was unsafe + lsr r3,r3,6 + jne.d [blink] ; return if rounding was safe. + add_s r0,r0,r3 + /* work out exact rounding if we fall through here. */ + /* We know that the exact result cannot be represented in single + precision. Find the mid-point between the two nearest + representable values, multiply with the divisor, and check if + the result is larger than the dividend. */ + add_s r3,r3,r3 + sub_s r3,r3,1 + mpyu r3,r3,r6 + asr.f 0,r0,1 ; for round-to-even in case this is a denorm + rsub r2,r9,25 + asl_s r12,r12,r2 + ; wb stall + ; slow track + sub.f 0,r12,r3 + j_s.d [blink] + sub.mi r0,r0,1 +/* For denormal results, it is possible that an exact result needs + rounding, and thus the round-to-even rule has to come into play. */ +.Linf_denorm: + brlo r2,0xc0000000,.Linf +.Ldenorm: + asr_s r2,r2,23 + bic r0,r0,r9 + neg r9,r2 + brlo.d r9,25,.Lpast_denorm + lsr r3,r3,r9 + /* Fall through: return +- 0 */ + j_s [blink] +.Linf: + j_s.d [blink] + or r0,r0,r9 + ENDFUNC(__divsf3) diff --git a/libgcc/config/arc/ieee-754/divsf3.S b/libgcc/config/arc/ieee-754/divsf3.S new file mode 100644 index 00000000000..d7cc2ee938d --- /dev/null +++ b/libgcc/config/arc/ieee-754/divsf3.S @@ -0,0 +1,221 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __divsf3 + FUNC(__divsf3) + .balign 4 +__divsf3: + push_s blink + push_s r1 + bl.d __divsf3_c + push_s r0 + ld_s r1,[sp,4] + st_s r0,[sp,4] + bl.d __divsf3_asm + pop_s r0 + pop_s r1 + pop_s blink + cmp r0,r1 +#if 1 + bne abort + jeq_s [blink] + b abort +#else + bne abort + j_s [blink] +#endif + ENDFUNC(__divsf3) +#define __divsf3 __divsf3_asm +#endif /* DEBUG */ + + .balign 4 +__divdf3_support: /* This label makes debugger output saner. */ + FUNC(__divsf3) +.Ldenorm_fp0: + norm.f r12,r2 ; flag for 0/x -> 0 check + bic.ne.f 0,0x60000000,r1 ; denorm/large number -> 0 + beq_s .Lret0_NaN + tst r1,r9 + add_s r2,r2,r2 + sub_s r12,r12,8 + asl_s r2,r2,r12 + asl_l r12,r12,23 + bne.d .Lpast_denorm_fp0 + add r5,r5,r12 +/* r0 is subnormal, r1 is subnormal or 0. */ + + .balign 4 +.Ldenorm_fp1: + norm.f r12,r3 ; flag for x/0 -> Inf check + bic.ne.f 0,0x60000000,r0 ; large number/denorm -> Inf + beq_s .Linf + add_s r3,r3,r3 + sub_s r12,r12,8 + asl_s r3,r3,r12 + asl_s r12,r12,23 + b.d .Lpast_denorm_fp1 + add r4,r4,r12 + +.Lret0_NaN: + bclr.f 0,r1,31 ; 0/0 -> NaN + bic r0,r10,r9 + j_s.d [blink] + sub.eq r0,r0,1 + + .global __divsf3 + .balign 4 + .long 0x7f800000 ; exponent mask +__divsf3: + ld r9,[pcl,-4] + bmsk r2,r0,22 + xor r4,r0,r2 + bmsk r3,r1,22 + xor r5,r1,r3 + and r11,r0,r9 + breq.d r11,0,.Ldenorm_fp0 + xor r10,r4,r5 + breq r11,r9,.Linf_nan_fp0 + bset_s r2,r2,23 + and r11,r1,r9 + breq r11,0,.Ldenorm_fp1 + breq r11,r9,.Linf_nan_fp1 +.Lpast_denorm_fp0: + bset_s r3,r3,23 +.Lpast_denorm_fp1: + cmp r2,r3 + asl_s r2,r2,6+1 + asl_s r3,r3,7 + add.lo r2,r2,r2 + bclr r8,r9,30 ; exponent bias + bclr.lo r8,r8,23 ; reduce exp by one if fraction is shifted + sub r4,r4,r5 + add r4,r4,r8 + xor.f 0,r10,r4 + bmi .Linf_denorm + and r12,r4,r9 + breq r12,0,.Ldenorm + sub_s r2,r2,r3 ; discard implicit 1 +.Ldiv_23bit: + .rep 6 + divaw r2,r2,r3 + .endr + breq r12,r9,.Linf + bmsk r0,r2,6 + xor_s r2,r2,r0 +.Ldiv_17bit: + .rep 7 + divaw r2,r2,r3 + .endr + asl_s r0,r0,7 + bmsk r1,r2,6 + xor_s r2,r2,r1 + or_s r0,r0,r1 +.Ldiv_10bit: + .rep 7 + divaw r2,r2,r3 + .endr + asl_s r0,r0,7 + bmsk r1,r2,6 + xor_s r2,r2,r1 + or_s r0,r0,r1 +.Ldiv_3bit: + .rep 3 + divaw r2,r2,r3 + .endr + asl_s r0,r0,3 +.Ldiv_0bit: + divaw r1,r2,r3 + bmsk_s r2,r2,2 + tst r1,-0x7e ; 0xffffff82, test for rest or odd + bmsk_s r1,r1,0 + add_s r0,r0,r2 ; assemble fraction + add_s r0,r0,r4 ; add in sign & exponent + j_s.d [blink] + add.ne r0,r0,r1 ; round to nearest / even + + .balign 4 +.Linf_nan_fp0: + bic.f 0,r9,r1 ; fp1 Inf -> result NaN + bic r1,r5,r9 ; fp1 sign + sub.eq r1,r1,1 + j_s.d [blink] + xor_s r0,r0,r1 +.Linf_nan_fp1: + bic r0,r4,r9 ; fp0 sign + bmsk.f 0,r1,22 ; x/inf -> 0, x/nan -> nan + xor.eq r1,r1,r9 + j_s.d [blink] + xor_s r0,r0,r1 +.Linf: + j_s.d [blink] + or r0,r10,r9 + +.Lret_r4: + j_s.d [blink] + mov_s r0,r4 + .balign 4 +.Linf_denorm: + add.f r12,r4,r4 + asr_l r12,r12,24 + bpl .Linf + max r12,r12,-24 +.Ldenorm: + add r1,pcl,42; .Ldenorm_tab-. + ldb_s r12,[r12,r1] + mov_s r0,0 + lsr_s r2,r2 + sub_s r1,r1,r12 + j_s.d [r1] + bic r4,r10,r9 + .byte .Ldenorm_tab-.Lret_r4 + .byte .Ldenorm_tab-.Ldiv_0bit + .byte .Ldenorm_tab-.Ldiv_3bit-8 + .byte .Ldenorm_tab-.Ldiv_3bit-4 + .byte .Ldenorm_tab-.Ldiv_3bit + .byte .Ldenorm_tab-.Ldiv_10bit-24 + .byte .Ldenorm_tab-.Ldiv_10bit-20 + .byte .Ldenorm_tab-.Ldiv_10bit-16 + .byte .Ldenorm_tab-.Ldiv_10bit-12 + .byte .Ldenorm_tab-.Ldiv_10bit-8 + .byte .Ldenorm_tab-.Ldiv_10bit-4 + .byte .Ldenorm_tab-.Ldiv_10bit + .byte .Ldenorm_tab-.Ldiv_17bit-24 + .byte .Ldenorm_tab-.Ldiv_17bit-20 + .byte .Ldenorm_tab-.Ldiv_17bit-16 + .byte .Ldenorm_tab-.Ldiv_17bit-12 + .byte .Ldenorm_tab-.Ldiv_17bit-8 + .byte .Ldenorm_tab-.Ldiv_17bit-4 + .byte .Ldenorm_tab-.Ldiv_17bit + .byte .Ldenorm_tab-.Ldiv_23bit-20 + .byte .Ldenorm_tab-.Ldiv_23bit-16 + .byte .Ldenorm_tab-.Ldiv_23bit-12 + .byte .Ldenorm_tab-.Ldiv_23bit-8 + .byte .Ldenorm_tab-.Ldiv_23bit-4 +.Ldenorm_tab: + .byte .Ldenorm_tab-.Ldiv_23bit + ENDFUNC(__divsf3) diff --git a/libgcc/config/arc/ieee-754/divtab-arc-df.c b/libgcc/config/arc/ieee-754/divtab-arc-df.c new file mode 100644 index 00000000000..b1574b9dc32 --- /dev/null +++ b/libgcc/config/arc/ieee-754/divtab-arc-df.c @@ -0,0 +1,161 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* We use a polynom similar to a Tchebycheff polynom to get an initial + seed, and then use a newton-raphson iteration step to get an + approximate result + If this result can't be rounded to the exact result with confidence, we + round to the value between the two closest representable values, and + test if the correctly rounded value is above or below this value. + + Because of the Newton-raphson iteration step, an error in the seed at X + is amplified by X. Therefore, we don't want a Tchebycheff polynom + or a polynom that is close to optimal according to the maximum norm + on the errro of the seed value; we want one that is close to optimal + according to the maximum norm on the error of the result, i.e. we + want the maxima of the polynom to increase linearily. + Given an interval [X0,X2) over which to approximate, + with X1 := (X0+X2)/2, D := X1-X0, F := 1/D, and S := D/X1 we have, + like for Tchebycheff polynoms: + P(0) := 1 + but then we have: + P(1) := X + S*D + P(2) := 2 * X^2 + S*D * X - D^2 + Then again: + P(n+1) := 2 * X * P(n) - D^2 * P (n-1) + */ + +static long double merr = 42.; + +double +err (long double a0, long double a1, long double x) +{ + long double y0 = a0 + (x-1)*a1; + + long double approx = 2. * y0 - y0 * x * y0; + long double true = 1./x; + long double err = approx - true; + + if (err <= -1./65536./16384.) + printf ("ERROR EXCEEDS 1 ULP %.15f %.15f %.15f\n", + (double)x, (double)approx, (double)true); + if (merr > err) + merr = err; + return err; +} + +int +main (void) +{ + long double T[5]; /* Taylor polynom */ + long double P[5][5]; + int i, j; + long double X0, X1, X2, S; + long double inc = 1./64; + long double D = inc*0.5; + long i0, i1, i2, io; + + memset (P, 0, sizeof (P)); + P[0][0] = 1.; + for (i = 1; i < 5; i++) + P[i][i] = 1 << i-1; + P[2][0] = -D*D; + for (X0 = 1.; X0 < 2.; X0 += inc) + { + X1 = X0 + inc * 0.5; + X2 = X0 + inc; + S = D / X1; + T[0] = 1./X1; + for (i = 1; i < 5; i++) + T[i] = T[i-1] * -T[0]; +#if 0 + printf ("T %1.8f %f %f %f %f\n", (double)T[0], (double)T[1], (double)T[2], +(double)T[3], (double)T[4]); +#endif + P[1][0] = S*D; + P[2][1] = S*D; + for (i = 3; i < 5; i++) + { + P[i][0] = -D*D*P[i-2][0]; + for (j = 1; j < i; j++) + P[i][j] = 2*P[i-1][j-1]-D*D*P[i-2][j]; + } +#if 0 + printf ("P3 %1.8f %f %f %f %f\n", (double)P[3][0], (double)P[3][1], (double)P[3][2], +(double)P[3][3], (double)P[3][4]); + printf ("P4 %1.8f %f %f %f %f\n", (double)P[4][0], (double)P[4][1], (double)P[4][2], +(double)P[4][3], (double)P[4][4]); +#endif + for (i = 4; i > 1; i--) + { + long double a = T[i]/P[i][i]; + + for (j = 0; j < i; j++) + T[j] -= a * P[i][j]; + } +#if 0 + printf ("A %1.8f %f %f\n", (double)T[0], (double)T[1], (double)T[2]); +#endif +#if 0 + i2 = T[2]*1024; + long double a = (T[2]-i/1024.)/P[2][2]; + for (j = 0; j < 2; j++) + T[j] -= a * P[2][j]; +#else + i2 = 0; +#endif + long double T0, Ti1; + for (i = 0, i0 = 0; i < 4; i++) + { + + i1 = T[1]*4096. + i0 / (long double)(1 << 20) - 0.5; + i1 = - (-i1 & 0x0fff); + Ti1 = ((unsigned)(-i1 << 20) | i0) /-(long double)(1LL<<32LL); + T0 = T[0] - (T[1]-Ti1)/P[1][1] * P[1][0] - (X1 - 1) * Ti1; + i0 = T0 * 1024 * 1024 + 0.5; + i0 &= 0xfffff; + } +#if 0 + printf ("A %1.8f %f %f\n", (double)T[0], (double)T[1], (double)T[2]); +#endif + io = (unsigned)(-i1 << 20) | i0; + long double A1 = (unsigned)io/-65536./65536.; + long double A0 = (unsigned)(io << 12)/65536./65536.; + long double Xm0 = 1./sqrt (-A1); + long double Xm1 = 0.5+0.5*-A0/A1; +#if 0 + printf ("%f %f %f %f\n", (double)A0, (double)A1, (double) Ti1, (double)X0); + printf ("%.12f %.12f %.12f\n", + err (A0, A1, X0), err (A0, A1, X1), err (A0, A1, X2)); + printf ("%.12f %.12f\n", (double)Xm0, (double)Xm1); + printf ("%.12f %.12f\n", err (A0, A1, Xm0), err (A0, A1, Xm1)); +#endif + printf ("\t.long 0x%x\n", io); + } +#if 0 + printf ("maximum error: %.15f %x %f\n", (double)merr, (unsigned)(long long)(-merr * 65536 * 65536), (double)log(-merr)/log(2)); +#endif + return 0; +} diff --git a/libgcc/config/arc/ieee-754/divtab-arc-sf.c b/libgcc/config/arc/ieee-754/divtab-arc-sf.c new file mode 100644 index 00000000000..d76e4996d21 --- /dev/null +++ b/libgcc/config/arc/ieee-754/divtab-arc-sf.c @@ -0,0 +1,127 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* We use a polynom similar to a Tchebycheff polynom to get an initial + seed, and then use a newton-raphson iteration step to get an + approximate result + If this result can't be rounded to the exact result with confidence, we + round to the value between the two closest representable values, and + test if the correctly rounded value is above or below this value. + + Because of the Newton-raphson iteration step, an error in the seed at X + is amplified by X. Therefore, we don't want a Tchebycheff polynom + or a polynom that is close to optimal according to the maximum norm + on the errro of the seed value; we want one that is close to optimal + according to the maximum norm on the error of the result, i.e. we + want the maxima of the polynom to increase linearily. + Given an interval [X0,X2) over which to approximate, + with X1 := (X0+X2)/2, D := X1-X0, F := 1/D, and S := D/X1 we have, + like for Tchebycheff polynoms: + P(0) := 1 + but then we have: + P(1) := X + S*D + P(2) := 2 * X^2 + S*D * X - D^2 + Then again: + P(n+1) := 2 * X * P(n) - D^2 * P (n-1) + */ + +int +main (void) +{ + long double T[5]; /* Taylor polynom */ + long double P[5][5]; + int i, j; + long double X0, X1, X2, S; + long double inc = 1./64; + long double D = inc*0.5; + long i0, i1, i2; + + memset (P, 0, sizeof (P)); + P[0][0] = 1.; + for (i = 1; i < 5; i++) + P[i][i] = 1 << i-1; + P[2][0] = -D*D; + for (X0 = 1.; X0 < 2.; X0 += inc) + { + X1 = X0 + inc * 0.5; + X2 = X1 + inc; + S = D / X1; + T[0] = 1./X1; + for (i = 1; i < 5; i++) + T[i] = T[i-1] * -T[0]; +#if 0 + printf ("T %1.8f %f %f %f %f\n", (double)T[0], (double)T[1], (double)T[2], +(double)T[3], (double)T[4]); +#endif + P[1][0] = S*D; + P[2][1] = S*D; + for (i = 3; i < 5; i++) + { + P[i][0] = -D*D*P[i-2][0]; + for (j = 1; j < i; j++) + P[i][j] = 2*P[i-1][j-1]-D*D*P[i-2][j]; + } +#if 0 + printf ("P3 %1.8f %f %f %f %f\n", (double)P[3][0], (double)P[3][1], (double)P[3][2], +(double)P[3][3], (double)P[3][4]); + printf ("P4 %1.8f %f %f %f %f\n", (double)P[4][0], (double)P[4][1], (double)P[4][2], +(double)P[4][3], (double)P[4][4]); +#endif + for (i = 4; i > 1; i--) + { + long double a = T[i]/P[i][i]; + + for (j = 0; j < i; j++) + T[j] -= a * P[i][j]; + } +#if 0 + printf ("A %1.8f %f %f\n", (double)T[0], (double)T[1], (double)T[2]); +#endif +#if 0 + i2 = T[2]*512; + long double a = (T[2]-i/512.)/P[2][2]; + for (j = 0; j < 2; j++) + T[j] -= a * P[2][j]; +#else + i2 = 0; +#endif + for (i = 0, i0 = 0; i < 4; i++) + { + long double T0, Ti1; + + i1 = T[1]*8192. + i0 / (long double)(1 << 19) - 0.5; + i1 = - (-i1 & 0x1fff); + Ti1 = ((unsigned)(-i1 << 19) | i0) /-(long double)(1LL<<32LL); + T0 = T[0] - (T[1]-Ti1)/P[1][1] * P[1][0] - (X1 - 1) * Ti1; + i0 = T0 * 512 * 1024 + 0.5; + i0 &= 0x7ffff; + } +#if 0 + printf ("A %1.8f %f %f\n", (double)T[0], (double)T[1], (double)T[2]); +#endif + printf ("\t.long 0x%x\n", (-i1 << 19) | i0); + } + return 0; +} diff --git a/libgcc/config/arc/ieee-754/eqdf2.S b/libgcc/config/arc/ieee-754/eqdf2.S new file mode 100644 index 00000000000..26f09682494 --- /dev/null +++ b/libgcc/config/arc/ieee-754/eqdf2.S @@ -0,0 +1,76 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" +/* inputs: DBL0, DBL1 + output: z flag + clobber: r12, flags + For NaNs, bit 19.. bit 30 of the high word must be set. */ +#if 0 /* DEBUG */ + .global __eqdf2 + .balign 4 + FUNC(__eqdf2) +__eqdf2: + st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4] + st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4] + st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1` + bl.d __eqdf2_c` push_s r0 + mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3 + ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]` + ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4] + bl.d __eqdf2_asm` ld.ab r10,[sp,4] + pop_s blink + breq.d r11,0,0f + ld.ab r11,[sp,4] + jne_s [blink] + bl abort +0: jeq_s [blink] + bl abort + ENDFUNC(__eqdf2) +#define __eqdf2 __eqdf2_asm +#endif /* DEBUG */ + .global __eqdf2 + .balign 4 + HIDDEN_FUNC(__eqdf2) + /* Good performance as long as the difference in high word is + well predictable (as seen from the branch predictor). */ +__eqdf2: + brne.d DBL0H,DBL1H,.Lhighdiff + bmsk r12,DBL0H,20 +#ifdef DPFP_COMPAT + or.f 0,DBL0L,DBL1L + bset.ne r12,r12,21 +#endif /* DPFP_COMPAT */ + add1.f r12,r12,DBL0H /* set c iff NaN; also, clear z if NaN. */ + j_s.d [blink] + cmp.cc DBL0L,DBL1L + .balign 4 +.Lhighdiff: + or r12,DBL0H,DBL1H + or.f 0,DBL0L,DBL1L + j_s.d [blink] + bmsk.eq.f r12,r12,30 + ENDFUNC(__eqdf2) +/* ??? could we do better by speeding up some 'common' case of inequality? */ diff --git a/libgcc/config/arc/ieee-754/eqsf2.S b/libgcc/config/arc/ieee-754/eqsf2.S new file mode 100644 index 00000000000..4390982bc83 --- /dev/null +++ b/libgcc/config/arc/ieee-754/eqsf2.S @@ -0,0 +1,69 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" +/* inputs: r0, r1 + output: z flag + clobber: r12, flags + For NaNs, bit 22 .. bit 30 must be set. */ +#if 0 /* DEBUG */ + .global __eqsf2 + .balign 4 + FUNC(__eqsf2) +__eqsf2: + st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4] + st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4] + st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1` + bl.d __eqsf2_c` push_s r0 + mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3 + ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]` + ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4] + bl.d __eqsf2_asm` ld.ab r10,[sp,4] + pop_s blink + breq.d r11,0,0f + ld.ab r11,[sp,4] + jne_s [blink] + bl abort +0: jeq_s [blink] + bl abort + ENDFUNC(__eqsf2) +#define __eqsf2 __eqsf2_asm +#endif /* DEBUG */ + /* Good performance as long as the binary difference is + well predictable (as seen from the branch predictor). */ + .global __eqsf2 + .balign 4 + HIDDEN_FUNC(__eqsf2) +__eqsf2: + breq r0, r1,.Lno_bdiff + or r12,r0,r1 + j_s.d [blink] + bmsk.f 0,r12,30 +.Lno_bdiff: + bmsk r12,r0,23 + add1.f r12,r12,r0 /* set c iff NaN; also, clear z if NaN. */ + j_s.d [blink] + cmp.cc r0,r1 + ENDFUNC(__eqsf2) diff --git a/libgcc/config/arc/ieee-754/extendsfdf2.S b/libgcc/config/arc/ieee-754/extendsfdf2.S new file mode 100644 index 00000000000..12e29449a96 --- /dev/null +++ b/libgcc/config/arc/ieee-754/extendsfdf2.S @@ -0,0 +1,122 @@ +/* Copyright (C) 2006, 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __extendsfdf2 + .balign 4 + FUNC(__extendsfdf2) +__extendsfdf2: + push_s blink + bl.d __extendsfdf2_c + push_s r0 + ld_s r2,[sp] + st_s r1,[sp] + push_s r0 + bl.d __extendsfdf2_asm + mov_s r0,r2 + pop_s r2 + pop_s r3 + pop_s blink + cmp r0,r2 + cmp.eq r1,r3 + jeq_s [blink] + bl abort + ENDFUNC(__extendsfdf2) +#define __extendsfdf2 __extendsfdf2_asm +#endif /* DEBUG */ +#if 0 /* ARC600 */ +__extendsfdf2: + lsr r2,r0,23 + tst r2,0xff + bic.ne.f r2,0xff + beq_s .Linf_nan_denorm_0 +.. +.Linf_nan_denorm: + bbit1 r0,30,.Linf_nan +#endif + .global __extendsfdf2 + .balign 4 + FUNC(__extendsfdf2) +__extendsfdf2: + add.f r1,r0,r0 + norm r3,r1 +#ifdef __LITTLE_ENDIAN__ + lsr_s DBL0H,r1,4 + brhs r3,7,.Linf_nan_denorm_0 + asl_s DBL0L,r0,29 + add_s DBL0H,DBL0H, \ + 0x38000000 +#else + lsr r2,r1,4 + brhs r3,7,.Linf_nan_denorm_0 + asl_s DBL0L,r1,28 + add DBL0H,r2, \ + 0x38000000 +#endif + j_s.d [blink] + bxor.cs DBL0H,DBL0H,31 + .balign 4 +.Linf_nan_denorm_0: +#ifdef __LITTLE_ENDIAN__ + mov_s DBL0H,r0 + jeq.d [blink] + mov.eq DBL0L,0 +#else + jeq_s [blink] +#endif + bmi .Linf_nan + asl_s r0,r0,r3 + rsub r3,r3,0x380+6 +#ifdef __LITTLE_ENDIAN__ + asl_s r3,r3,20 + lsr DBL0H,r0,9 + asl_s DBL0L,r0,23 + add_s DBL0H,DBL0H,r3 + j_s.d [blink] + bxor.cs DBL0H,DBL0H,31 +#else + asl DBL0L,r0,23 + lsr_s DBL0H,r0,9 + asl_s r3,r3,20 + bxor.cs DBL0H,DBL0H,31 + j_s.d [blink] + add_l DBL0H,DBL0H,r3 +#endif +.Linf_nan: +#ifdef __LITTLE_ENDIAN__ + lsr DBL0H,r0,3 + + or_s DBL0H,DBL0H,r0 + j_s.d [blink] + mov_l DBL0L,0 +#else + lsr r3,r0,3 + mov_s DBL0L,0 + j_s.d [blink] + or_l DBL0H,r0,r3 +#endif + ENDFUNC(__extendsfdf2) diff --git a/libgcc/config/arc/ieee-754/fixdfsi.S b/libgcc/config/arc/ieee-754/fixdfsi.S new file mode 100644 index 00000000000..f35d0b6eb06 --- /dev/null +++ b/libgcc/config/arc/ieee-754/fixdfsi.S @@ -0,0 +1,85 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" + +#if 0 /* DEBUG */ + FUNC(__fixdfsi) + .global __fixdfsi + .balign 4 +__fixdfsi: + push_s blink + push_s r0 + bl.d __fixdfsi_c + push_s r1 + mov_s r2,r0 + pop_s r1 + ld r0,[sp] + bl.d __fixdfsi_asm + st r2,[sp] + pop_s r1 + pop_s blink + cmp r0,r1 + jeq_s [blink] + bl abort + ENDFUNC(__fixdfsi) +#define __fixdfsi __fixdfsi_asm +#endif /* DEBUG */ + +/* If the fraction has to be shifted left by a positive non-zero amount, + we have to combine bits from DBL0L and DBL0H. If we shift right, + or shift by zero, we only want to have the bits from DBL0H in r0. */ + + .global __fixdfsi + FUNC(__fixdfsi) + .balign 4 +__fixdfsi: + bbit0 DBL0H,30,.Lret0or1 + asr r2,DBL0H,20 + bmsk_s DBL0H,DBL0H,19 + sub_s r2,r2,19; 0x3ff+20-0x400 + neg_s r3,r2 + asr.f 0,r3,11 + bset_s DBL0H,DBL0H,20 +#ifdef __LITTLE_ENDIAN__ + mov.cs DBL0L,DBL0H + asl DBL0H,DBL0H,r2 +#else + asl.cc DBL0H,DBL0H,r2 + lsr.cs DBL0H,DBL0H,r3 +#endif + lsr_s DBL0L,DBL0L,r3 + + add.cc r0,r0,r1 + j_s.d [blink] + neg.pl r0,r0 +.Lret0or1: + add.f r0,DBL0H,0x100000 + lsr_s r0,r0,30 + + bmsk_s r0,r0,0 + j_s.d [blink] + neg.mi r0,r0 + ENDFUNC(__fixdfsi) diff --git a/libgcc/config/arc/ieee-754/fixsfsi.S b/libgcc/config/arc/ieee-754/fixsfsi.S new file mode 100644 index 00000000000..045b99f1982 --- /dev/null +++ b/libgcc/config/arc/ieee-754/fixsfsi.S @@ -0,0 +1,71 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __fixsfsi + FUNC(__fixsfsi) + .balign 4 +__fixsfsi: + push_s blink + bl.d __fixsfsi_c + push_s r0 + ld_s r1,[sp] + st_s r0,[sp] + bl.d __fixsfsi_asm + mov_s r0,r1 + pop_s r1 + pop_s blink + cmp r0,r1 + jeq_s [blink] + bl abort + ENDFUNC(__fixsfsi) +#define __fixsfsi __fixsfsi_asm +#endif /* DEBUG */ + + .global __fixsfsi + FUNC(__fixsfsi) + .balign 4 +__fixsfsi: + bbit0 r0,30,.Lret0or1 + lsr r2,r0,23 + bmsk_s r0,r0,22 + bset_s r0,r0,23 + sub_s r2,r2,22;0x7f+23-0x80 + asl.f 0,r2,24 + neg r3,r2 + asl.mi r0,r0,r2 + lsr.pl r0,r0,r3 + j_s.d [blink] + neg.cs r0,r0 +.Lret0or1: + add.f r0,r0,0x800000 + lsr_s r0,r0,30 + + bmsk_s r0,r0,0 + j_s.d [blink] + neg.mi r0,r0 + ENDFUNC(__fixsfsi) diff --git a/libgcc/config/arc/ieee-754/fixunsdfsi.S b/libgcc/config/arc/ieee-754/fixunsdfsi.S new file mode 100644 index 00000000000..54116a5b94d --- /dev/null +++ b/libgcc/config/arc/ieee-754/fixunsdfsi.S @@ -0,0 +1,80 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" + +#if 0 /* DEBUG */ + FUNC(__fixunsdfsi) + .global __fixunsdfsi + .balign 4 +__fixunsdfsi: + push_s blink + push_s r0 + bl.d __fixunsdfsi_c + push_s r1 + mov_s r2,r0 + pop_s r1 + ld r0,[sp] + bl.d __fixunsdfsi_asm + st r2,[sp] + pop_s r1 + pop_s blink + cmp r0,r1 + jeq_s [blink] + bl abort + ENDFUNC(__fixunsdfsi) +#define __fixunsdfsi __fixunsdfsi_asm +#endif /* DEBUG */ + + .global __fixunsdfsi + FUNC(__fixunsdfsi) + .balign 4 +__fixunsdfsi: + bbit0 DBL0H,30,.Lret0or1 + lsr r2,DBL0H,20 + bmsk_s DBL0H,DBL0H,19 + sub_s r2,r2,19; 0x3ff+20-0x400 + neg_s r3,r2 + btst_s r3,10 + bset_s DBL0H,DBL0H,20 +#ifdef __LITTLE_ENDIAN__ + mov.ne DBL0L,DBL0H + asl DBL0H,DBL0H,r2 +#else + asl.eq DBL0H,DBL0H,r2 + lsr.ne DBL0H,DBL0H,r3 +#endif + lsr DBL0L,DBL0L,r3 + j_s.d [blink] + add.eq r0,r0,r1 +.Lret0: + j_s.d [blink] + mov_l r0,0 +.Lret0or1: + add_s DBL0H,DBL0H,0x100000 + lsr_s DBL0H,DBL0H,30 + j_s.d [blink] + bmsk_l r0,DBL0H,0 + ENDFUNC(__fixunsdfsi) diff --git a/libgcc/config/arc/ieee-754/floatsidf.S b/libgcc/config/arc/ieee-754/floatsidf.S new file mode 100644 index 00000000000..f7aa0324366 --- /dev/null +++ b/libgcc/config/arc/ieee-754/floatsidf.S @@ -0,0 +1,77 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __floatsidf + .balign 4 + FUNC(__floatsidf) +__floatsidf: + push_s blink + bl.d __floatsidf_c + push_s r0 + ld_s r2,[sp] + st_s r1,[sp] + push_s r0 + bl.d __floatsidf_asm + mov_s r0,r2 + pop_s r2 + pop_s r3 + pop_s blink + cmp r0,r2 + cmp.eq r1,r3 + jeq_s [blink] + bl abort + ENDFUNC(__floatsidf) +#define __floatsidf __floatsidf_asm +#endif /* DEBUG */ + + .global __floatsidf + .balign 4 + FUNC(__floatsidf) +__floatsidf: + abs.f r1,r0 + jeq_s [blink] + lsr r2,r1 + mov r12,-0x41d ; -(0x3ff+31-1) + norm r2,r2 + bclr.cs r12,r12,11 + rsub.f r3,r2,11 + add_s r12,r2,r12 + add_s r2,r2,21 +#ifdef __LITTLE_ENDIAN__ + asl DBL0L,r1,r2 + lsr_s DBL0H,r1,r3 +#else + lsr DBL0H,r1,r3 + asl_s DBL0L,r1,r2 +#endif + asl_s r12,r12,20 + mov.lo DBL0H,DBL0L + sub_s DBL0H,DBL0H,r12 + j_s.d [blink] + mov.ls DBL0L,0 + ENDFUNC(__floatsidf) diff --git a/libgcc/config/arc/ieee-754/floatsisf.S b/libgcc/config/arc/ieee-754/floatsisf.S new file mode 100644 index 00000000000..d5838b00d95 --- /dev/null +++ b/libgcc/config/arc/ieee-754/floatsisf.S @@ -0,0 +1,99 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __floatsisf + FUNC(__floatsisf) + .balign 4 +__floatsisf: + push_s blink + bl.d __floatsisf_c + push_s r0 + ld_s r1,[sp] + st_s r0,[sp] + bl.d __floatsisf_asm + mov_s r0,r1 + pop_s r1 + pop_s blink + cmp r0,r1 + jeq_s [blink] + bl abort + ENDFUNC(__floatsisf) + .global __floatunsisf + FUNC(__floatunsisf) + .balign 4 +__floatunsisf: + push_s blink + bl.d __floatunsisf_c + push_s r0 + ld_s r1,[sp] + st_s r0,[sp] + bl.d __floatunsisf_asm + mov_s r0,r1 + pop_s r1 + pop_s blink + cmp r0,r1 + jeq_s [blink] + bl abort + ENDFUNC(__floatunsisf) +#define __floatsisf __floatsisf_asm +#define __floatunsisf __floatunsisf_asm +#endif /* DEBUG */ + + .global __floatunsisf + .global __floatsisf + FUNC(__floatsisf) + FUNC(__floatunsisf) + .balign 4 +__floatunsisf: + lsr_s r2,r0 + mov_l r12,0x9d ; 0x7f + 31 - 1 + norm r2,r2 + brne_l r0,0,0f + j_s [blink] + .balign 4 +__floatsisf: + abs.f r0,r0 + jeq_s [blink] + lsr_s r2,r0 + mov_s r12,0x9d ; 0x7f + 31 - 1 + norm r2,r2 + bset.cs r12,r12,8 +0: rsub.f r3,r2,8 + bmsk r1,r0,r3 + ror r1,r1,r3 + lsr.pl r0,r0,r3 + neg_s r3,r3 + asl.mi r0,r0,r3 + sub_s r12,r12,r2 + asl_s r12,r12,23 + bxor.pl.f r1,r1,31 + add_s r0,r0,r12 + j_s.d [blink] + add.pnz r0,r0,1 + ENDFUNC(__floatunsisf) + ENDFUNC(__floatsisf) diff --git a/libgcc/config/arc/ieee-754/floatunsidf.S b/libgcc/config/arc/ieee-754/floatunsidf.S new file mode 100644 index 00000000000..c04b2461c3b --- /dev/null +++ b/libgcc/config/arc/ieee-754/floatunsidf.S @@ -0,0 +1,75 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __floatunsidf + .balign 4 + FUNC(__floatunsidf) +__floatunsidf: + push_s blink + bl.d __floatunsidf_c + push_s r0 + ld_s r2,[sp] + st_s r1,[sp] + push_s r0 + bl.d __floatunsidf_asm + mov_s r0,r2 + pop_s r2 + pop_s r3 + pop_s blink + cmp r0,r2 + cmp.eq r1,r3 + jeq_s [blink] + bl abort + ENDFUNC(__floatunsidf) +#define __floatunsidf __floatunsidf_asm +#endif /* DEBUG */ + + .global __floatunsidf + .balign 4 + FUNC(__floatunsidf) +__floatunsidf: + lsr_s r1,r0 + breq_s r0,0,.Lret0 + norm r2,r1 + mov r12,-0x41d ; -(0x3ff+31-1) + rsub.f r3,r2,11 + add_s r12,r2,r12 + add_s r2,r2,21 +#ifdef __LITTLE_ENDIAN__ + lsr DBL0H,r0,r3 + asl_s DBL0L,r0,r2 +#else + asl DBL0L,r0,r2 + lsr_s DBL0H,r0,r3 +#endif + asl_s r12,r12,20 + mov.lo DBL0H,DBL0L + sub_s DBL0H,DBL0H,r12 +.Lret0: j_s.d [blink] + mov.ls DBL0L,0 + ENDFUNC(__floatunsidf) diff --git a/libgcc/config/arc/ieee-754/gedf2.S b/libgcc/config/arc/ieee-754/gedf2.S new file mode 100644 index 00000000000..e0ea266104b --- /dev/null +++ b/libgcc/config/arc/ieee-754/gedf2.S @@ -0,0 +1,86 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" +/* inputs: DBL0, DBL1 + output: c flags to be used for 'hs' condition + clobber: r12, flags */ +/* For NaNs, bit 19.. bit 30 of the high word must be set. */ +#if 0 /* DEBUG */ + .global __gedf2 + .balign 4 + FUNC(__gedf2) +__gedf2: + st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4] + st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4] + st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1` + bl.d __gedf2_c` push_s r0 + mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3 + ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]` + ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4] + bl.d __gedf2_asm` ld.ab r10,[sp,4] + pop_s blink + brge.d r11,0,0f + ld.ab r11,[sp,4] + jlo [blink] + bl abort +0: jhs [blink] + bl abort + ENDFUNC(__gedf2) +#define __gedf2 __gedf2_asm +#endif /* DEBUG */ + .global __gedf2 + .balign 4 + HIDDEN_FUNC(__gedf2) +__gedf2: + or.f r12,DBL0H,DBL1H + bmi.d .Lneg + bmsk_s r12,r12,20 + add1.f 0,r12,DBL0H ; clear z; set c iff NaN + add1.cc.f r12,r12,DBL1H ; clear z; set c iff NaN + bbit1 DBL0H,31,.Lneg + cmp.cc DBL0H,DBL1H + j_s.d [blink] + cmp.eq DBL0L,DBL1L + .balign 4 +.Lneg: breq.d DBL1H,0,.L0 + add1.f 0,r12,DBL0H + add1.cc.f r12,r12,DBL1H + cmp.cc DBL1H,DBL0H + j_s.d [blink] + cmp.eq DBL1L,DBL0L + .balign 4 +.L0: + bxor.f 0,DBL0H,31 ; check for high word of -0. + beq_s .Lcheck_0 + cmp.cc DBL1H,DBL0H + j_s.d [blink] + cmp.eq DBL1L,DBL0L +.Lcheck_0: + ; high words suggest DBL0 may be -0, DBL1 +0; check low words. + cmp_s DBL1H,DBL0L + j_s.d [blink] + cmp.cc DBL1H,DBL1L + ENDFUNC(__gedf2) diff --git a/libgcc/config/arc/ieee-754/gesf2.S b/libgcc/config/arc/ieee-754/gesf2.S new file mode 100644 index 00000000000..857db58a237 --- /dev/null +++ b/libgcc/config/arc/ieee-754/gesf2.S @@ -0,0 +1,75 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" +/* inputs: r0, r1 + output: c flag to be used for 'hs' condition + clobber: r12,flags */ +/* For NaNs, bit 22.. bit 30 must be set. */ +#if 0 /* DEBUG */ + .global __gesf2 + .balign 4 + FUNC(__gesf2) +__gesf2: + st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4] + st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4] + st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1` + bl.d __gesf2_c` push_s r0 + mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3 + ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]` + ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4] + bl.d __gesf2_asm` ld.ab r10,[sp,4] + pop_s blink + brge.d r11,0,0f + ld.ab r11,[sp,4] + jlo [blink] + bl abort +0: jhs [blink] + bl abort + ENDFUNC(__gesf2) +#define __gesf2 __gesf2_asm +#endif /* DEBUG */ + .global __gesf2 + .balign 4 + HIDDEN_FUNC(__gesf2) +__gesf2: + or.f r12,r0,r1 + bmi.d .Lneg + bmsk_s r12,r12,23 + add1.f 0,r12,r0 ; check for NaN + add1.cc.f r12,r12,r1 + j_s.d [blink] + cmp.cc r0,r1 + .balign 4 +.Lneg: breq.d r1,0,.L0 + add1.f 0,r12,r0 ; check for NaN + add1.cc.f r12,r12,r1 + j_s.d [blink] + cmp.cc r1,r0 + .balign 4 +.L0: bxor.f 0,r0,31 ; check for -0 + j_s.d [blink] + cmp.hi r1,r0 + ENDFUNC(__gesf2) diff --git a/libgcc/config/arc/ieee-754/gtdf2.S b/libgcc/config/arc/ieee-754/gtdf2.S new file mode 100644 index 00000000000..b0abb95b84f --- /dev/null +++ b/libgcc/config/arc/ieee-754/gtdf2.S @@ -0,0 +1,86 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" +/* inputs: DBL0, DBL1 + output: c,z flags to be used for 'hi' condition + clobber: r12, flags */ +/* For NaNs, bit 19.. bit 30 of the high word must be set. */ +#if 0 /* DEBUG */ + .global __gtdf2 + .balign 4 + FUNC(__gtdf2) +__gtdf2: + st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4] + st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4] + st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1` + bl.d __gtdf2_c` push_s r0 + mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3 + ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]` + ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4] + bl.d __gtdf2_asm` ld.ab r10,[sp,4] + pop_s blink + brgt.d r11,0,0f + ld.ab r11,[sp,4] + jls [blink] + bl abort +0: jhi [blink] + bl abort + ENDFUNC(__gtdf2) +#define __gtdf2 __gtdf2_asm +#endif /* DEBUG */ + .global __gtdf2 + .balign 4 + HIDDEN_FUNC(__gtdf2) +__gtdf2: + or.f r12,DBL0H,DBL1H + bmi.d .Lneg + bmsk_s r12,r12,20 + add1.f 0,r12,DBL0H ; clear z; set c iff NaN + add1.cc.f r12,r12,DBL1H ; clear z; set c iff NaN + ; don't care: z may or may not be cleared if there is no NaN event + cmp.cc DBL0H,DBL1H + j_s.d [blink] + cmp.eq DBL0L,DBL1L + .balign 4 +.Lneg: breq.d DBL0H,0,.L0 + add1.f 0,r12,DBL1H + add1.cc.f r12,r12,DBL0H + cmp.cc DBL1H,DBL0H + j_s.d [blink] + cmp.eq DBL1L,DBL0L + .balign 4 +.L0: + bxor.f 0,DBL1H,31 + beq_s .Lcheck_0 + cmp.cc DBL1H,DBL0H + j_s.d [blink] + cmp.eq DBL1L,DBL0L + .balign 4 +.Lcheck_0: + ; high words suggest DBL0 may be +0, DBL1 -0; check low words. + j_s.d [blink] + or.f 0,DBL0L,DBL1L + ENDFUNC(__gtdf2) diff --git a/libgcc/config/arc/ieee-754/gtsf2.S b/libgcc/config/arc/ieee-754/gtsf2.S new file mode 100644 index 00000000000..b417fec8425 --- /dev/null +++ b/libgcc/config/arc/ieee-754/gtsf2.S @@ -0,0 +1,75 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" +/* inputs: r0, r1 + output: c, z flags to be used for 'hi' condition + clobber: r12,flags */ +/* For NaNs, bit 22.. bit 30 must be set. */ +#if 0 /* DEBUG */ + .global __gtsf2 + .balign 4 + FUNC(__gtsf2) +__gtsf2: + st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4] + st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4] + st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1` + bl.d __gtsf2_c` push_s r0 + mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3 + ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]` + ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4] + bl.d __gtsf2_asm` ld.ab r10,[sp,4] + pop_s blink + brgt.d r11,0,0f + ld.ab r11,[sp,4] + jls [blink] + bl abort +0: jhi [blink] + bl abort + ENDFUNC(__gtsf2) +#define __gtsf2 __gtsf2_asm +#endif /* DEBUG */ + .global __gtsf2 + .balign 4 + HIDDEN_FUNC(__gtsf2) +__gtsf2: + or.f r12,r0,r1 + bmi.d .Lneg + bmsk_s r12,r12,23 + add1.f 0,r12,r0 ; check for NaN + add1.cc.f r12,r12,r1 + j_s.d [blink] + cmp.cc r0,r1 + .balign 4 +.Lneg: breq.d r0,0,.L0 + add1.f 0,r12,r0 ; check for NaN + add1.cc.f r12,r12,r1 + j_s.d [blink] + cmp.cc r1,r0 + .balign 4 +.L0: bxor.f 0,r1,31 ; check for -0 + j_s.d [blink] + cmp.hi r1,r0 + ENDFUNC(__gtsf2) diff --git a/libgcc/config/arc/ieee-754/muldf3.S b/libgcc/config/arc/ieee-754/muldf3.S new file mode 100644 index 00000000000..59c2b07212b --- /dev/null +++ b/libgcc/config/arc/ieee-754/muldf3.S @@ -0,0 +1,235 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* XMAC schedule: directly back-to-back multiplies stall; the third + instruction after a multiply stalls unless it is also a multiply. */ +#include "arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __muldf3 + .balign 4 +__muldf3: + push_s blink + push_s r2 + push_s r3 + push_s r0 + bl.d __muldf3_c + push_s r1 + ld_s r2,[sp,12] + ld_s r3,[sp,8] + st_s r0,[sp,12] + st_s r1,[sp,8] + pop_s r1 + bl.d __muldf3_asm + pop_s r0 + pop_s r3 + pop_s r2 + pop_s blink + cmp r0,r2 + cmp.eq r1,r3 + jeq_s [blink] + b abort +#define __muldf3 __muldf3_asm +#endif /* DEBUG */ +/* N.B. This is optimized for ARC700. + ARC600 has very different scheduling / instruction selection criteria. */ +/* For the standard multiplier, instead of mpyu rx,DBL0L,DBL1L; tst rx,rx , + we can do: + sub rx,DBL0L,1; bic rx,DBL0L,rx; lsr rx,rx; norm rx,rx; asl.f 0,DBL1L,rx */ + +__muldf3_support: /* This label makes debugger output saner. */ +/* If one number is denormal, subtract some from the exponent of the other + one (if the other exponent is too small, return 0), and normalize the + denormal. Then re-run the computation. */ + .balign 4 + FUNC(__muldf3) +.Ldenorm_dbl0: + mov_s r12,DBL0L + mov_s DBL0L,DBL1L + mov_s DBL1L,r12 + mov_s r12,DBL0H + mov_s DBL0H,DBL1H + mov_s DBL1H,r12 + and r11,DBL0H,r9 +.Ldenorm_dbl1: + brhs r11,r9,.Linf_nan + brhs 0x3ca00001,r11,.Lret0 + sub_s DBL0H,DBL0H,DBL1H + bmsk_s DBL1H,DBL1H,30 + add_s DBL0H,DBL0H,DBL1H + breq_s DBL1H,0,.Ldenorm_2 + norm r12,DBL1H + + sub_s r12,r12,10 + asl r5,r12,20 + asl_s DBL1H,DBL1H,r12 + sub DBL0H,DBL0H,r5 + neg r5,r12 + lsr r6,DBL1L,r5 + asl_s DBL1L,DBL1L,r12 + b.d __muldf3 + add_s DBL1H,DBL1H,r6 + + .balign 4 +.Linf_nan: + bclr r12,DBL1H,31 + xor_s DBL1H,DBL1H,DBL0H + bclr_s DBL0H,DBL0H,31 + max r8,DBL0H,r12 ; either NaN -> NaN ; otherwise inf + or.f 0,DBL0H,DBL0L + mov_s DBL0L,0 + or.ne.f DBL1L,DBL1L,r12 + not_s DBL0H,DBL0L ; inf * 0 -> NaN + mov.ne DBL0H,r8 + tst_s DBL1H,DBL1H + j_s.d [blink] + bset.mi DBL0H,DBL0H,31 + +.Lret0: xor_s DBL0H,DBL0H,DBL1H + bclr DBL1H,DBL0H,31 + xor_s DBL0H,DBL0H,DBL1H + j_s.d [blink] + mov_l DBL0L,0 + + .balign 4 +.Ldenorm_2: + breq_s DBL1L,0,.Lret0 ; 0 input -> 0 output + norm.f r12,DBL1L + + mov.mi r12,21 + add.pl r12,r12,22 + neg r11,r12 + asl_s r12,r12,20 + lsr.f DBL1H,DBL1L,r11 + ror DBL1L,DBL1L,r11 + sub_s DBL0H,DBL0H,r12 + mov.eq DBL1H,DBL1L + sub_s DBL1L,DBL1L,DBL1H + /* Fall through. */ + .global __muldf3 + .balign 4 +__muldf3: + ld.as r9,[pcl,0x4b] ; ((.L7ff00000-.+2)/4)] + mpyhu r4,DBL0L,DBL1L + bmsk r6,DBL0H,19 + bset r6,r6,20 + mpyu r7,r6,DBL1L + and r11,DBL0H,r9 + breq r11,0,.Ldenorm_dbl0 + mpyhu r8,r6,DBL1L + bmsk r10,DBL1H,19 + bset r10,r10,20 + mpyhu r5,r10,DBL0L + add.f r4,r4,r7 + and r12,DBL1H,r9 + mpyhu r7,r6,r10 + breq r12,0,.Ldenorm_dbl1 + adc.f r5,r5,r8 + mpyu r8,r10,DBL0L + breq r11,r9,.Linf_nan + breq r12,r9,.Linf_nan + mpyu r6,r6,r10 + add.cs r7,r7,1 + add.f r4,r4,r8 + mpyu r10,DBL1L,DBL0L + bclr r8,r9,30 ; 0x3ff00000 + adc.f r5,r5,r6 + ; XMAC write-back stall / std. mult stall is one cycle later + bclr r6,r9,20 ; 0x7fe00000 + add.cs r7,r7,1 ; fraction product in r7:r5:r4 + tst r10,r10 + bset.ne r4,r4,0 ; put least significant word into sticky bit + lsr.f r10,r7,9 + add_l r12,r12,r11 ; add exponents + rsub.eq r8,r8,r9 ; 0x40000000 + sub r12,r12,r8 ; subtract bias + implicit 1 + brhs.d r12,r6,.Linf_denorm + rsub r10,r10,12 +.Lshift_frac: + neg r8,r10 + asl r6,r4,r10 + lsr DBL0L,r4,r8 + add.f 0,r6,r6 + btst.eq DBL0L,0 + cmp.eq r4,r4 ; round to nearest / round to even + asl r4,r5,r10 + lsr r5,r5,r8 + adc.f DBL0L,DBL0L,r4 + xor.f 0,DBL0H,DBL1H + asl r7,r7,r10 + add_s r12,r12,r5 + adc DBL0H,r12,r7 + j_s.d [blink] + bset.mi DBL0H,DBL0H,31 + +/* We have checked for infinity / NaN input before, and transformed + denormalized inputs into normalized inputs. Thus, the worst case + exponent overflows are: + 1 + 1 - 0x400 == 0xc02 : maximum underflow + 0x7fe + 0x7fe - 0x3ff == 0xbfd ; maximum overflow + N.B. 0x7e and 0x7f are also values for overflow. + + If (r12 <= -54), we have an underflow to zero. */ + .balign 4 +.Linf_denorm: + brlo r12,0xc0000000,.Linf + asr r6,r12,20 + mov_s r12,0 + add.f r10,r10,r6 + brgt r10,0,.Lshift_frac + beq_s .Lround_frac + add.f r10,r10,32 +.Lshift32_frac: + tst r4,r4 + mov r4,r5 + bset.ne r4,r4,1 + mov r5,r7 + mov r7,0 + brge r10,1,.Lshift_frac + breq r10,0,.Lround_frac + add.f r10,r10,32 + brgt r10,21,.Lshift32_frac + b_s .Lret0 + +.Lround_frac: + add.f 0,r4,r4 + btst.eq r5,0 + mov_s DBL0L,r5 + mov_s DBL0H,r7 + adc.eq.f DBL0L,DBL0L,0 + j_s.d [blink] + + adc.eq DBL0H,DBL0H,0 + +.Linf: xor.f DBL1H,DBL1H,DBL0H + mov_s DBL0L,0 + mov_s DBL0H,r9 + j_s.d [blink] + bset.mi DBL0H,DBL0H,31 + ENDFUNC(__muldf3) + + .balign 4 +.L7ff00000: + .long 0x7ff00000 diff --git a/libgcc/config/arc/ieee-754/mulsf3.S b/libgcc/config/arc/ieee-754/mulsf3.S new file mode 100644 index 00000000000..c931c3c947e --- /dev/null +++ b/libgcc/config/arc/ieee-754/mulsf3.S @@ -0,0 +1,180 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* XMAC schedule: directly back-to-back multiplies stall; the third + instruction after a multiply stalls unless it is also a multiply. */ +#include "arc-ieee-754.h" + +#if 0 /* DEBUG */ + .global __mulsf3 + FUNC(__mulsf3) + .balign 4 +__mulsf3: + push_s blink + push_s r1 + bl.d __mulsf3_c + push_s r0 + ld_s r1,[sp,4] + st_s r0,[sp,4] + bl.d __mulsf3_asm + pop_s r0 + pop_s r1 + pop_s blink + cmp r0,r1 + jeq_s [blink] + and r12,r0,r1 + bic.f 0,0x7f800000,r12 + bne 0f + bmsk.f 0,r0,22 + bmsk.ne.f r1,r1,22 + jne_s [blink] ; both NaN -> OK +0: bl abort + ENDFUNC(__mulsf3) +#define __mulsf3 __mulsf3_asm +#endif /* DEBUG */ + + .balign 4 + .global __mulsf3 + FUNC(__mulsf3) +__mulsf3: + ld.as r9,[pcl,79]; [pcl,((.L7f800000-.+2)/4)] + bmsk r4,r1,22 + bset r2,r0,23 + asl_s r2,r2,8 + bset r3,r4,23 + mpyhu r6,r2,r3 + and r11,r0,r9 + breq r11,0,.Ldenorm_dbl0 + mpyu r7,r2,r3 + breq r11,r9,.Linf_nan_dbl0 + and r12,r1,r9 + asl.f 0,r6,8 + breq r12,0,.Ldenorm_dbl1 +.Lpast_denorm: + xor_s r0,r0,r1 +.Lpast_denorm_dbl1: + add.pl r6,r6,r6 + bclr.pl r6,r6,23 + add.pl.f r7,r7,r7 + ld.as r4,[pcl,64]; [pcl,((.L7fffffff-.+2)/4)] + add.cs r6,r6,1 + lsr.f 0,r6,1 + breq r12,r9,.Linf_nan_dbl1 + add_s r12,r12,r11 + adc.f 0,r7,r4 + add_s r12,r12, \ + -0x3f800000 + adc.f r8,r6,r12 + bic r0,r0,r4 + tst.pl r8,r9 + min r3,r8,r9 + jpnz.d [blink] + add.pnz r0,r0,r3 +; infinity or denormal number + add.ne.f r3,r3,r3 + bpnz .Linfinity + asr_s r3,r3,23+1 + bset r6,r6,23 + sub_s r3,r3,1 + neg_s r2,r3 + brhi r2,24,.Lret_r0 ; right shift shift > 24 -> return +-0 + lsr r2,r6,r2 + asl r9,r6,r3 + lsr.f 0,r2,1 + tst r7,r7 + add_s r0,r0,r2 + bset.ne r9,r9,0 + adc.f 0,r9,r4 + j_s.d [blink] + add.cs r0,r0,1 +.Linfinity: + j_s.d [blink] + add_s r0,r0,r9 + +.Lret_r0: j_s [blink] + + .balign 4 +.Linf_nan_dbl0: + sub_s r2,r1,1 ; inf/nan * 0 -> nan; inf * nan -> nan (use |r2| >= inf) + bic.f 0,r9,r2 + xor_s r0,r0,r1 + bclr_s r1,r1,31 + xor_s r0,r0,r1 + jne_s [blink] +.Lretnan: + j_s.d [blink] + mov r0,-1 +.Ldenorm_dbl0_inf_nan_dbl1: + bmsk.f 0,r0,30 + beq_s .Lretnan + xor_s r0,r0,r1 +.Linf_nan_dbl1: + xor_s r1,r1,r0 + bclr_s r1,r1,31 + j_s.d [blink] + xor_s r0,r0,r1 + + .balign 4 +.Ldenorm_dbl0: + bclr_s r2,r2,31 + norm.f r4,r2 + and r12,r1,r9 + add_s r2,r2,r2 + asl r2,r2,r4 + asl r4,r4,23 + mpyhu r6,r2,r3 + breq r12,r9,.Ldenorm_dbl0_inf_nan_dbl1 + sub.ne.f r12,r12,r4 + mpyu r7,r2,r3 + bhi.d .Lpast_denorm + asl.f 0,r6,8 + xor_s r0,r0,r1 + bmsk r1,r0,30 + j_s.d [blink] + bic_l r0,r0,r1 + + .balign 4 +.Ldenorm_dbl1: + norm.f r3,r4 + xor_s r0,r0,r1 + sub_s r3,r3,7 + asl r4,r4,r3 + sub_s r3,r3,1 + asl_s r3,r3,23 + mpyhu r6,r2,r4 + sub.ne.f r11,r11,r3 + bmsk r8,r0,30 + mpyu r7,r2,r4 + bhi.d .Lpast_denorm_dbl1 + asl.f 0,r6,8 + j_s.d [blink] + bic r0,r0,r8 + + .balign 4 +.L7f800000: + .long 0x7f800000 +.L7fffffff: + .long 0x7fffffff + ENDFUNC(__mulsf3) diff --git a/libgcc/config/arc/ieee-754/orddf2.S b/libgcc/config/arc/ieee-754/orddf2.S new file mode 100644 index 00000000000..ac2793f6234 --- /dev/null +++ b/libgcc/config/arc/ieee-754/orddf2.S @@ -0,0 +1,63 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" +/* inputs: r0, r1 + output: c flag + clobber: r12, flags + For NaNs, bit 19 .. bit 30 must be set. */ +#if 0 /* DEBUG */ + .global __orddf2 + .balign 4 + FUNC(__orddf2) +__orddf2: + st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4] + st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4] + st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1` + bl.d __unorddf2_c` push_s r0 + mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3 + ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]` + ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4] + bl.d __orddf2_asm` ld.ab r10,[sp,4] + pop_s blink + brne.d r11,0,0f + ld.ab r11,[sp,4] + jcc [blink] + bl abort +0: jcs [blink] + bl abort + ENDFUNC(__orddf2) +#define __orddf2 __orddf2_asm +#endif /* DEBUG */ + .global __orddf2 + .balign 4 + HIDDEN_FUNC(__orddf2) +__orddf2: + bmsk r12,DBL0H,20 + add1.f r12,r12,DBL0H /* clear z; set c if NaN. */ + bmsk r12,DBL1H,20 + j_s.d [blink] + add1.cc.f r12,r12,DBL1H /* clear z; set c if NaN. */ + ENDFUNC(__orddf2) diff --git a/libgcc/config/arc/ieee-754/ordsf2.S b/libgcc/config/arc/ieee-754/ordsf2.S new file mode 100644 index 00000000000..8f1495156b6 --- /dev/null +++ b/libgcc/config/arc/ieee-754/ordsf2.S @@ -0,0 +1,63 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" +/* inputs: r0, r1 + output: c flag + clobber: r12, flags + For NaNs, bit 22 .. bit 30 must be set. */ +#if 0 /* DEBUG */ + .global __ordsf2 + .balign 4 + FUNC(__ordsf2) +__ordsf2: + st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4] + st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4] + st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1` + bl.d __unordsf2_c` push_s r0 + mov r11,r0` pop_s r0` pop_s r1` pop_s r2` pop_s r3 + ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]` + ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4] + bl.d __ordsf2_asm` ld.ab r10,[sp,4] + pop_s blink + brne.d r11,0,0f + ld.ab r11,[sp,4] + jcc [blink] + bl abort +0: jcs [blink] + bl abort + ENDFUNC(__ordsf2) +#define __ordsf2 __ordsf2_asm +#endif /* DEBUG */ + .global __ordsf2 + .balign 4 + HIDDEN_FUNC(__ordsf2) +__ordsf2: + bmsk r12,r0,23 + add1.f r12,r12,r0 /* clear z; set c if NaN. */ + bmsk r12,r1,23 + j_s.d [blink] + add1.cc.f r12,r12,r1 /* clear z; set c if NaN. */ + ENDFUNC(__ordsf2) diff --git a/libgcc/config/arc/ieee-754/truncdfsf2.S b/libgcc/config/arc/ieee-754/truncdfsf2.S new file mode 100644 index 00000000000..aafdf09445a --- /dev/null +++ b/libgcc/config/arc/ieee-754/truncdfsf2.S @@ -0,0 +1,134 @@ +/* Copyright (C) 2006, 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" + +#if 0 /* DEBUG */ + FUNC(__truncdfsf2) + .global __truncdfsf2 + .balign 4 +__truncdfsf2: + push_s blink + push_s r0 + bl.d __truncdfsf2_c + push_s r1 + mov_s r2,r0 + pop_s r1 + ld r0,[sp] + bl.d __truncdfsf2_asm + st r2,[sp] + pop_s r1 + pop_s blink + cmp r0,r1 + jeq_s [blink] + and r12,r0,r1 + bic.f 0,0x7f800000,r12 + bne 0f + bmsk.f 0,r0,22 + bmsk.ne.f r1,r1,22 + jne_s [blink] ; both NaN -> OK +0: bl abort + ENDFUNC(__truncdfsf2) +#define __truncdfsf2 __truncdfsf2_asm +#endif /* DEBUG */ + + .global __truncdfsf2 + .balign 4 + FUNC(__truncdfsf2) +__truncdfsf2: + lsr r2,DBL0H,20 + asl_s DBL0H,DBL0H,12 + sub r12,r2,0x380 + bclr.f r3,r12,11 + brhs r3,0xff,.Lill_exp + beq_l .Ldenorm0 + asl_s r12,r12,23 + tst DBL0L, \ + 0x2fffffff /* Check if msb guard bit wants rounding up. */ + lsr_s DBL0L,DBL0L,28 + lsr_s DBL0H,DBL0H,8 + add.ne DBL0L,DBL0L,1 + add_s DBL0H,DBL0H,DBL0L + lsr_s DBL0H,DBL0H + btst_s r2,11 + add_s r0,DBL0H,r12 + j_s.d [blink] + bxor.ne r0,r0,31 + .balign 4 +.Lill_exp: + bbit1 r2,10,.Linf_nan + bmsk_s r12,r12,9 + rsub.f r12,r12,8+0x400-32 ; Go from 9 to 1 guard bit in MSW. */ + bhs_s .Lzero + lsr r3,DBL0L,21 + rrc DBL0H,DBL0H ; insert leading 1 + asl.f 0,DBL0L,8 ; check lower 24 guard bits + add_s r3,DBL0H,r3 + add.pnz r3,r3,1 ; assemble fraction with compressed guard bits. + lsr r0,r3,r12 + neg_s r12,r12 + btst_s r0,1 + asl.eq.f r3,r3,r12 + add.ne r0,r0,1 + btst_s r2,11 + lsr_s r0,r0 + j_s.d [blink] + bxor.ne r0,r0,31 +.Lzero: + lsr_s r2,r2,11 + j_s.d [blink] + asl r0,r2,31 +.Ldenorm0: + asl_s r12,r12,20 + tst DBL0L, \ + 0x5fffffff /* Check if msb guard bit wants rounding up. */ + lsr_s DBL0L,DBL0L,29 + lsr_s DBL0H,DBL0H,9 + add.ne DBL0L,DBL0L,1 + bset_s DBL0H,DBL0H,23 + add_s DBL0H,DBL0H,DBL0L + lsr_s DBL0H,DBL0H + j_s.d [blink] + add_l r0,DBL0H,r12 + +/* We would generally say that NaNs must have a non-zero high fraction part, + but to allow hardware double precision floating point to interoperate + with single precision software floating point, we make an exception here. + The cost is to replace a tst_s DBL0H with an or.f DBL0L,DBL0L,DBL0H . + As we start out unaligned, and there is an odd number of other short insns, + we have a choice of letting this cost us a misalign penalty or + 4 more bytes (if we align the code). We choose the former here because + infinity / NaN is not expected to be prevalent in time-critical code. */ +.Linf_nan: + or.f DBL0L,DBL0L,DBL0H + mov_s r0,1 + add.ne r2,r2,1 + tst r2,0x7ff + asl.ne r0,r0,23 + btst_s r12,11 + neg r0,r0 + j_s.d [blink] + bxor.eq r0,r0,31 + ENDFUNC(__truncdfsf2) diff --git a/libgcc/config/arc/ieee-754/uneqdf2.S b/libgcc/config/arc/ieee-754/uneqdf2.S new file mode 100644 index 00000000000..b3d16d0c0a1 --- /dev/null +++ b/libgcc/config/arc/ieee-754/uneqdf2.S @@ -0,0 +1,73 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" +/* inputs: DBL0, DBL1 + output: z flag + clobber: r12, flags + For NaNs, bit 19.. bit 30 of the high word must be set. */ +#if 0 /* DEBUG */ + .global __uneqdf2 + .balign 4 + FUNC(__uneqdf2) +__uneqdf2: + st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4] + st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4] + st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1` + bl.d __eqdf2_c` push_s r0 + push_s r0` ld_s r0, [sp,4]` ld_s r1, [sp,8]` ld_s r2,[sp,12] + bl.d __unorddf2_c` ld_s r3,[sp,16] + ld.ab r11,[sp,4]` tst r0,r0` mov.ne r11,0 + pop_s r0` pop_s r1` pop_s r2` pop_s r3 + ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]` + ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4] + bl.d __uneqdf2_asm` ld.ab r10,[sp,4] + pop_s blink + breq.d r11,0,0f + ld.ab r11,[sp,4] + jne_s [blink] + bl abort +0: jeq_s [blink] + bl abort + ENDFUNC(__uneqdf2) +#define __uneqdf2 __uneqdf2_asm +#endif /* DEBUG */ + .global __uneqdf2 + .balign 4 + HIDDEN_FUNC(__uneqdf2) +__uneqdf2: + cmp_s DBL0H,DBL1H + cmp.eq DBL0L,DBL1L + jeq_s [blink] + or r12,DBL0H,DBL1H + or.f 0,DBL0L,DBL1L + bclr.eq.f r12,r12,31 + jeq_s [blink] + mov_s r12, \ + 0x7ff80000 + bic.f 0,r12,DBL0H + j_s.d [blink] + bic.ne.f r12,r12,DBL1H + ENDFUNC(__uneqdf2) diff --git a/libgcc/config/arc/ieee-754/uneqsf2.S b/libgcc/config/arc/ieee-754/uneqsf2.S new file mode 100644 index 00000000000..152c112dc4e --- /dev/null +++ b/libgcc/config/arc/ieee-754/uneqsf2.S @@ -0,0 +1,69 @@ +/* Copyright (C) 2008-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#include "arc-ieee-754.h" +/* inputs: r0, r1 + output: z flag + clobber: r12, flags + For NaNs, bit 22 .. bit 30 must be set. */ +#if 0 /* DEBUG */ + .global __uneqsf2 + .balign 4 + FUNC(__uneqsf2) +__uneqsf2: + st.a r11,[sp,-4]` push_s blink` st.a r10,[sp,-4]` st.a r9,[sp,-4] + st.a r8,[sp,-4]` st.a r7,[sp,-4]` st.a r6,[sp,-4]` st.a r5,[sp,-4] + st.a r4,[sp,-4]` push_s r3` push_s r2` push_s r1` + bl.d __eqsf2_c` push_s r0 + push_s r0` ld_s r0, [sp,4] + bl.d __unordsf2_c` ld_s r1,[sp,8] + ld.ab r11,[sp,4]` tst r0,r0` mov.ne r11,0 + pop_s r0` pop_s r1` pop_s r2` pop_s r3 + ld.ab r4,[sp,4]` ld.ab r5,[sp,4]` ld.ab r6,[sp,4]` + ld.ab r7,[sp,4]` ld.ab r8,[sp,4]` ld.ab r9,[sp,4] + bl.d __uneqsf2_asm` ld.ab r10,[sp,4] + pop_s blink + breq.d r11,0,0f + ld.ab r11,[sp,4] + jne_s [blink] + bl abort +0: jeq_s [blink] + bl abort + ENDFUNC(__uneqsf2) +#define __uneqsf2 __uneqsf2_asm +#endif /* DEBUG */ + .global __uneqsf2 + .balign 4 + HIDDEN_FUNC(__uneqsf2) +__uneqsf2: + mov_s r12, \ + 0x7fc00000 + bic.f 0,r12,r0 + bic.ne.f r12,r12,r1 + or r12,r0,r1 + bmsk.ne.f r12,r12,30 + j_s.d [blink] + cmp.ne r0,r1 + ENDFUNC(__uneqsf2) diff --git a/libgcc/config/arc/initfini.c b/libgcc/config/arc/initfini.c new file mode 100644 index 00000000000..46bd8b0f9f4 --- /dev/null +++ b/libgcc/config/arc/initfini.c @@ -0,0 +1,157 @@ +/* .init/.fini section handling + C++ global constructor/destructor handling. + This file is based on crtstuff.c, sol2-crti.asm, sol2-crtn.asm. + + Copyright (C) 1995, 1997, 1998, 2007-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* Declare a pointer to void function type. */ +typedef void (*func_ptr) (void); + +#ifdef CRT_INIT + +/* NOTE: In order to be able to support SVR4 shared libraries, we arrange + to have one set of symbols { __CTOR_LIST__, __DTOR_LIST__, __CTOR_END__, + __DTOR_END__ } per root executable and also one set of these symbols + per shared library. So in any given whole process image, we may have + multiple definitions of each of these symbols. In order to prevent + these definitions from conflicting with one another, and in order to + ensure that the proper lists are used for the initialization/finalization + of each individual shared library (respectively), we give these symbols + only internal (i.e. `static') linkage, and we also make it a point to + refer to only the __CTOR_END__ symbol in crtfini.o and the __DTOR_LIST__ + symbol in crtinit.o, where they are defined. */ + +static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors"))) + = { (func_ptr) (-1) }; + +static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors"))) + = { (func_ptr) (-1) }; + +/* Run all the global destructors on exit from the program. */ + +/* Some systems place the number of pointers in the first word of the + table. On SVR4 however, that word is -1. In all cases, the table is + null-terminated. On SVR4, we start from the beginning of the list and + invoke each per-compilation-unit destructor routine in order + until we find that null. + + Note that this function MUST be static. There will be one of these + functions in each root executable and one in each shared library, but + although they all have the same code, each one is unique in that it + refers to one particular associated `__DTOR_LIST__' which belongs to the + same particular root executable or shared library file. */ + +static void __do_global_dtors (void) +asm ("__do_global_dtors") __attribute__ ((section (".text"))); + +static void +__do_global_dtors (void) +{ + func_ptr *p; + for (p = __DTOR_LIST__ + 1; *p; p++) + (*p) (); +} + +/* .init section start. + This must appear at the start of the .init section. */ + +asm ("\n\ + .section .init\n\ + .global init\n\ + .word 0\n\ +init:\n\ + st blink,[sp,4]\n\ + st fp,[sp]\n\ + mov fp,sp\n\ + sub sp,sp,16\n\ +"); + +/* .fini section start. + This must appear at the start of the .init section. */ + +asm ("\n\ + .section .fini\n\ + .global fini\n\ + .word 0\n\ +fini:\n\ + st blink,[sp,4]\n\ + st fp,[sp]\n\ + mov fp,sp\n\ + sub sp,sp,16\n\ + bl.nd __do_global_dtors\n\ +"); + +#endif /* CRT_INIT */ + +#ifdef CRT_FINI + +/* Put a word containing zero at the end of each of our two lists of function + addresses. Note that the words defined here go into the .ctors and .dtors + sections of the crtend.o file, and since that file is always linked in + last, these words naturally end up at the very ends of the two lists + contained in these two sections. */ + +static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors"))) + = { (func_ptr) 0 }; + +static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors"))) + = { (func_ptr) 0 }; + +/* Run all global constructors for the program. + Note that they are run in reverse order. */ + +static void __do_global_ctors (void) +asm ("__do_global_ctors") __attribute__ ((section (".text"))); + +static void +__do_global_ctors (void) +{ + func_ptr *p; + for (p = __CTOR_END__ - 1; *p != (func_ptr) -1; p--) + (*p) (); +} + +/* .init section end. + This must live at the end of the .init section. */ + +asm ("\n\ + .section .init\n\ + bl.nd __do_global_ctors\n\ + ld blink,[fp,4]\n\ + j.d blink\n\ + ld.a fp,[sp,16]\n\ +"); + +/* .fini section end. + This must live at the end of the .fini section. */ + +asm ("\n\ + .section .fini\n\ + ld blink,[fp,4]\n\ + j.d blink\n\ + ld.a fp,[sp,16]\n\ +"); + +#endif /* CRT_FINI */ diff --git a/libgcc/config/arc/lib1funcs.S b/libgcc/config/arc/lib1funcs.S new file mode 100644 index 00000000000..d434ccb4edd --- /dev/null +++ b/libgcc/config/arc/lib1funcs.S @@ -0,0 +1,1418 @@ +; libgcc1 routines for Synopsys DesignWare ARC cpu. + +/* Copyright (C) 1995, 1997, 2007-2013 Free Software Foundation, Inc. + Contributor: Joern Rennecke <joern.rennecke@embecosm.com> + on behalf of Synopsys Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* As a special exception, if you link this library with other files, + some of which are compiled with GCC, to produce an executable, + this library does not by itself cause the resulting executable + to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. */ + + + /* ANSI concatenation macros. */ + + #define CONCAT1(a, b) CONCAT2(a, b) + #define CONCAT2(a, b) a ## b + + /* Use the right prefix for global labels. */ + + #define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) + +#ifndef WORKING_ASSEMBLER +#define abs_l abs +#define asl_l asl +#define mov_l mov +#endif + +#define FUNC(X) .type SYM(X),@function +#define HIDDEN_FUNC(X) FUNC(X)` .hidden X +#define ENDFUNC0(X) .Lfe_##X: .size X,.Lfe_##X-X +#define ENDFUNC(X) ENDFUNC0(X) + + + +#ifdef L_mulsi3 + .section .text + .align 4 + + .global SYM(__mulsi3) +SYM(__mulsi3): + +/* This the simple version. + + while (a) + { + if (a & 1) + r += b; + a >>= 1; + b <<= 1; + } +*/ + +#if defined (__ARC_MUL64__) + FUNC(__mulsi3) + mulu64 r0,r1 + j_s.d [blink] + mov_s r0,mlo + ENDFUNC(__mulsi3) +#elif defined (__ARC700__) + HIDDEN_FUNC(__mulsi3) + mpyu r0,r0,r1 + nop_s + j_s [blink] + ENDFUNC(__mulsi3) +#elif defined (__ARC_NORM__) + FUNC(__mulsi3) + norm.f r2,r0 + rsub lp_count,r2,31 + mov.mi lp_count,32 + mov_s r2,r0 + mov_s r0,0 + lpnz @.Lend ; loop is aligned + lsr.f r2,r2 + add.cs r0,r0,r1 + add_s r1,r1,r1 +.Lend: j_s [blink] + ENDFUNC(__mulsi3) +#elif !defined (__OPTIMIZE_SIZE__) && !defined(__ARC601__) + /* Up to 3.5 times faster than the simpler code below, but larger. */ + FUNC(__mulsi3) + ror.f r2,r0,4 + mov_s r0,0 + add3.mi r0,r0,r1 + asl.f r2,r2,2 + add2.cs r0,r0,r1 + jeq_s [blink] +.Loop: + add1.mi r0,r0,r1 + asl.f r2,r2,2 + add.cs r0,r0,r1 + asl_s r1,r1,4 + ror.f r2,r2,8 + add3.mi r0,r0,r1 + asl.f r2,r2,2 + bne.d .Loop + add2.cs r0,r0,r1 + j_s [blink] + ENDFUNC(__mulsi3) +#elif !defined (__OPTIMIZE_SIZE__) /* __ARC601__ */ + FUNC(__mulsi3) + lsr.f r2,r0 + mov_s r0,0 + mov_s r3,0 + add.cs r0,r0,r1 +.Loop: + lsr.f r2,r2 + add1.cs r0,r0,r1 + lsr.f r2,r2 + add2.cs r0,r0,r1 + lsr.f r2,r2 + add3.cs r0,r0,r1 + bne.d .Loop + add3 r1,r3,r1 + j_s [blink] + ENDFUNC(__mulsi3) +#else +/********************************************************/ + FUNC(__mulsi3) + mov_s r2,0 ; Accumulate result here. +.Lloop: + bbit0 r0,0,@.Ly + add_s r2,r2,r1 ; r += b +.Ly: + lsr_s r0,r0 ; a >>= 1 + asl_s r1,r1 ; b <<= 1 + brne_s r0,0,@.Lloop +.Ldone: + j_s.d [blink] + mov_s r0,r2 + ENDFUNC(__mulsi3) +/********************************************************/ +#endif + +#endif /* L_mulsi3 */ + +#ifdef L_umulsidi3 + .section .text + .align 4 + + .global SYM(__umulsidi3) +SYM(__umulsidi3): + HIDDEN_FUNC(__umulsidi3) +/* We need ARC700 /ARC_MUL64 definitions of __umulsidi3 / __umulsi3_highpart + in case some code has been compiled without multiply support enabled, + but linked with the multiply-support enabled libraries. + For ARC601 (i.e. without a barrel shifter), we also use umuldisi3 as our + umulsi3_highpart implementation; the use of the latter label doesn't + actually benefit ARC601 platforms, but is useful when ARC601 code is linked + against other libraries. */ +#if defined (__ARC700__) || defined (__ARC_MUL64__) || defined (__ARC601__) + .global SYM(__umulsi3_highpart) +SYM(__umulsi3_highpart): + HIDDEN_FUNC(__umulsi3_highpart) +#endif + +/* This the simple version. + + while (a) + { + if (a & 1) + r += b; + a >>= 1; + b <<= 1; + } +*/ +#include "ieee-754/arc-ieee-754.h" + +#ifdef __ARC700__ + mov_s r12,DBL0L + mpyu DBL0L,r12,DBL0H + j_s.d [blink] + mpyhu DBL0H,r12,DBL0H +#elif defined (__ARC_MUL64__) +/* Likewise for __ARC_MUL64__ */ + mulu64 r0,r1 + mov_s DBL0L,mlo + j_s.d [blink] + mov_s DBL0H,mhi +#else /* !__ARC700__ && !__ARC_MUL64__ */ +/* Although it might look tempting to extend this to handle muldi3, + using mulsi3 twice with 2.25 cycles per 32 bit add is faster + than one loop with 3 or four cycles per 32 bit add. */ + asl.f r12,0 ; Top part of b. + mov_s r2,0 ; Accumulate result here. + bbit1.d r0,0,@.Ladd + mov_s r3,0 +.Llooptst: + rlc r12,r12 + breq r0,0,@.Ldone ; while (a) +.Lloop: + asl.f r1,r1 ; b <<= 1 + bbit0.d r0,1,@.Llooptst + lsr r0,r0 ; a >>= 1 + rlc r12,r12 +.Ladd: + add.f r3,r3,r1 ; r += b + brne.d r0,0,@.Lloop ; while (a); + adc r2,r2,r12 +.Ldone: + mov_s DBL0L,r3 + j_s.d [blink] + mov DBL0H,r2 +#endif /* !__ARC700__*/ + ENDFUNC(__umulsidi3) +#if defined (__ARC700__) || defined (__ARC_MUL64__) || defined (__ARC601__) + ENDFUNC(__umulsi3_highpart) +#endif +#endif /* L_umulsidi3 */ + +#ifdef L_umulsi3_highpart +#include "ieee-754/arc-ieee-754.h" +/* For use without a barrel shifter, and for ARC700 / ARC_MUL64, the + mulsidi3 algorithms above look better, so for these, there is an + extra label up there. */ +#if !defined (__ARC700__) && !defined (__ARC_MUL64__) && !defined (__ARC601__) + .global SYM(__umulsi3_highpart) +SYM(__umulsi3_highpart): + HIDDEN_FUNC(__umulsi3_highpart) + mov_s r2,0 + mov_s r3,32 +.Loop: + lsr.f r0,r0 + add.cs.f r2,r2,r1 + sub_s r3,r3,1 + brne.d r0,0,.Loop + rrc r2,r2 + j_s.d [blink] +/* Make the result register peephole-compatible with mulsidi3. */ + lsr DBL0H,r2,r3 + ENDFUNC(__umulsi3_highpart) +#endif /* !__ARC700__ && !__ARC601__ */ +#endif /* L_umulsi3_highpart */ + +#ifdef L_divmod_tools + +; Utilities used by all routines. + + .section .text + +/* +unsigned long +udivmodsi4(int modwanted, unsigned long num, unsigned long den) +{ + unsigned long bit = 1; + unsigned long res = 0; + + while (den < num && bit && !(den & (1L<<31))) + { + den <<=1; + bit <<=1; + } + while (bit) + { + if (num >= den) + { + num -= den; + res |= bit; + } + bit >>=1; + den >>=1; + } + if (modwanted) return num; + return res; +} +*/ + +; inputs: r0 = numerator, r1 = denominator +; outputs: r0 = quotient, r1 = remainder, r2/r3 trashed + + .balign 4 + .global SYM(__udivmodsi4) + FUNC(__udivmodsi4) +SYM(__udivmodsi4): + +#if defined (__ARC700__) +/* Normalize divisor and divident, and then use the appropriate number of + divaw (the number of result bits, or one more) to produce the result. + There are some special conditions that need to be tested: + - We can only directly normalize unsigned numbers that fit in 31 bit. For + the divisor, we test early on that it is not 'negative'. + - divaw can't corrrectly process a divident that is larger than the divisor. + We handle this be checking that the divident prior to normalization is + not larger than the normalized divisor. As we then already know then + that the divisor fits 31 bit, this check also makes sure that the + divident fits. + - ordinary normalization of the divident could make it larger than the + normalized divisor, which again would be unsuitable for divaw. + Thus, we want to shift left the divident by one less, except that we + want to leave it alone if it is already 31 bit. To this end, we + double the input to norm with adds. + - If the divident has less bits than the divisor, that would leave us + with a negative number of divaw to execute. Although we could use a + conditional loop to avoid excess divaw, and then the quotient could + be extracted correctly as there'd be more than enough zero bits, the + remainder would be shifted left too far, requiring a conditional shift + right. The cost of that shift and the possible mispredict on the + conditional loop cost as much as putting in an early check for a zero + result. */ + bmsk r3,r0,29 + brne.d r3,r0,.Large_dividend + norm.f r2,r1 + brlo r0,r1,.Lret0 + norm r3,r0 + asl_s r1,r1,r2 + sub_s r3,r3,1 + asl_l r0,r0,r3 ; not short to keep loop aligned + sub lp_count,r2,r3 + lp .Ldiv_end + divaw r0,r0,r1 +.Ldiv_end:sub_s r3,r2,1 + lsr r1,r0,r2 + j_s.d [blink] + bmsk r0,r0,r3 + + .balign 4 +.Large_dividend: + bmi .Ltrivial + asl_s r1,r1,r2 + mov_s r3,0 + sub1.f r4,r0,r1 + mov.lo r4,r0 + mov.hs r3,2 + cmp r4,r1 + sub.hs r4,r4,r1 + add.hs r3,r3,1 + mov.f lp_count,r2 + lpne .Ldiv_end2 + divaw r4,r4,r1 +.Ldiv_end2:asl r0,r3,r2 + lsr r1,r4,r2 + sub_s r2,r2,1 + bmsk r4,r4,r2 + j_s.d [blink] + or.ne r0,r0,r4 + +.Lret0: + mov_s r1,r0 + j_s.d [blink] + mov_l r0,0 + .balign 4 +.Ltrivial: + sub.f r1,r0,r1 + mov.c r1,r0 + mov_s r0,1 + j_s.d [blink] + mov.c r0,0 +#elif !defined (__OPTIMIZE_SIZE__) +#ifdef __ARC_NORM__ + lsr_s r2,r0 + brhs.d r1,r2,.Lret0_3 + norm r2,r2 + norm r3,r1 + sub_s r3,r3,r2 + asl_s r1,r1,r3 + sub1.f 0,r0,r1 + lsr.cs r1,r1,1 + sbc r2,r3,0 + sub1 r0,r0,r1 + cmp_s r0,r1 + mov.f lp_count,r2 +#else /* ! __ARC_NORM__ */ + lsr_s r2,r0 + brhs.d r1,r2,.Lret0_3 + mov lp_count,32 +.Lloop1: + asl_s r1,r1 ; den <<= 1 + brls.d r1,r2,@.Lloop1 + sub lp_count,lp_count,1 + sub_s r0,r0,r1 + lsr_s r1,r1 + cmp_s r0,r1 + xor.f r2,lp_count,31 + mov_s lp_count,r2 +#endif /* !__ARC_NORM__ */ + sub.cc r0,r0,r1 + mov_s r3,3 + sbc r3,r3,0 +#ifndef __ARC601__ + asl_s r3,r3,r2 + rsub r1,r1,1 + lpne @.Lloop2_end + add1.f r0,r1,r0 + sub.cc r0,r0,r1 +.Lloop2_end: + lsr r1,r0,r2 +#else + rsub r1,r1,1 + lpne @.Lloop2_end + asl_s r3,r3 + add1.f r0,r1,r0 + sub.cc r0,r0,r1 +.Lloop2_end: + lsr_s r1,r0 + lsr.f lp_count,r2 + mov.cc r1,r0 + lpnz 1f + lsr_s r1,r1 + lsr_s r1,r1 +1: +#endif + bmsk r0,r0,r2 + bclr r0,r0,r2 + j_s.d [blink] + or_s r0,r0,r3 +.Lret0_3: +#if 0 /* Slightly shorter, but slower. */ + lp .Loop3_end + brhi.d r1,r0,.Loop3_end + sub_s r0,r0,r1 +.Loop3_end + add_s r1,r1,r0 + j_s.d [blink] + rsub r0,lp_count,32-1 +#else + mov_s r4,r1 + sub.f r1,r0,r1 + sbc r0,r0,r0 + sub.cc.f r1,r1,r4 + sbc r0,r0,0 + sub.cc.f r1,r1,r4 + sbc r0,r0,-3 + j_s.d [blink] + add.cs r1,r1,r4 +#endif +#else /* Arctangent-A5 */ + breq_s r1,0,@.Ldivmodend + mov_s r2,1 ; bit = 1 + mov_s r3,0 ; res = 0 +.Lloop1: + brhs r1,r0,@.Lloop2 + bbit1 r1,31,@.Lloop2 + asl_s r1,r1 ; den <<= 1 + b.d @.Lloop1 + asl_s r2,r2 ; bit <<= 1 +.Lloop2: + brlo r0,r1,@.Lshiftdown + sub_s r0,r0,r1 ; num -= den + or_s r3,r3,r2 ; res |= bit +.Lshiftdown: + lsr_s r2,r2 ; bit >>= 1 + lsr_s r1,r1 ; den >>= 1 + brne_s r2,0,@.Lloop2 +.Ldivmodend: + mov_s r1,r0 ; r1 = mod + j.d [blink] + mov_s r0,r3 ; r0 = res +/******************************************************/ +#endif + ENDFUNC(__udivmodsi4) + +#endif + +#ifdef L_udivsi3 + .section .text + .align 4 + + .global SYM(__udivsi3) + FUNC(__udivsi3) +SYM(__udivsi3): + b @SYM(__udivmodsi4) + ENDFUNC(__udivsi3) +#if 0 /* interferes with linux loader */ + .section .__arc_profile_forward, "a" + .long SYM(__udivsi3) + .long SYM(__udivmodsi4) + .long 65536 +#endif + +#endif /* L_udivsi3 */ + +#ifdef L_divsi3 + .section .text + .align 4 + + .global SYM(__divsi3) + FUNC(__divsi3) + +#ifndef __ARC700__ +SYM(__divsi3): + /* A5 / ARC60? */ + mov r7,blink + xor r6,r0,r1 + abs_s r0,r0 + bl.d @SYM(__udivmodsi4) + abs_s r1,r1 + tst r6,r6 + j.d [r7] + neg.mi r0,r0 +#else /* !ifndef __ARC700__ */ + ;; We can use the abs, norm, divaw and mpy instructions for ARC700 +#define MULDIV +#ifdef MULDIV +/* This table has been generated by divtab-arc700.c. */ +/* 1/512 .. 1/256, normalized. There is a leading 1 in bit 31. + For powers of two, we list unnormalized numbers instead. The values + for powers of 2 are loaded, but not used. The value for 1 is actually + the first instruction after .Lmuldiv. */ + .balign 4 +.Ldivtab: + + .long 0x1000000 + .long 0x80808081 + .long 0x81020409 + .long 0x81848DA9 + .long 0x82082083 + .long 0x828CBFBF + .long 0x83126E98 + .long 0x83993053 + .long 0x84210843 + .long 0x84A9F9C9 + .long 0x85340854 + .long 0x85BF3762 + .long 0x864B8A7E + .long 0x86D90545 + .long 0x8767AB60 + .long 0x87F78088 + .long 0x88888889 + .long 0x891AC73B + .long 0x89AE408A + .long 0x8A42F871 + .long 0x8AD8F2FC + .long 0x8B70344B + .long 0x8C08C08D + .long 0x8CA29C05 + .long 0x8D3DCB09 + .long 0x8DDA5203 + .long 0x8E78356E + .long 0x8F1779DA + .long 0x8FB823EF + .long 0x905A3864 + .long 0x90FDBC0A + .long 0x91A2B3C5 + .long 0x92492493 + .long 0x92F11385 + .long 0x939A85C5 + .long 0x94458095 + .long 0x94F20950 + .long 0x95A02569 + .long 0x964FDA6D + .long 0x97012E03 + .long 0x97B425EE + .long 0x9868C80A + .long 0x991F1A52 + .long 0x99D722DB + .long 0x9A90E7DA + .long 0x9B4C6F9F + .long 0x9C09C09D + .long 0x9CC8E161 + .long 0x9D89D89E + .long 0x9E4CAD24 + .long 0x9F1165E8 + .long 0x9FD809FE + .long 0xA0A0A0A1 + .long 0xA16B312F + .long 0xA237C32C + .long 0xA3065E40 + .long 0xA3D70A3E + .long 0xA4A9CF1E + .long 0xA57EB503 + .long 0xA655C43A + .long 0xA72F053A + .long 0xA80A80A9 + .long 0xA8E83F58 + .long 0xA9C84A48 + .long 0xAAAAAAAB + .long 0xAB8F69E3 + .long 0xAC769185 + .long 0xAD602B59 + .long 0xAE4C415D + .long 0xAF3ADDC7 + .long 0xB02C0B03 + .long 0xB11FD3B9 + .long 0xB21642C9 + .long 0xB30F6353 + .long 0xB40B40B5 + .long 0xB509E68B + .long 0xB60B60B7 + .long 0xB70FBB5B + .long 0xB81702E1 + .long 0xB92143FB + .long 0xBA2E8BA3 + .long 0xBB3EE722 + .long 0xBC52640C + .long 0xBD691048 + .long 0xBE82FA0C + .long 0xBFA02FE9 + .long 0xC0C0C0C1 + .long 0xC1E4BBD6 + .long 0xC30C30C4 + .long 0xC4372F86 + .long 0xC565C87C + .long 0xC6980C6A + .long 0xC7CE0C7D + .long 0xC907DA4F + .long 0xCA4587E7 + .long 0xCB8727C1 + .long 0xCCCCCCCD + .long 0xCE168A78 + .long 0xCF6474A9 + .long 0xD0B69FCC + .long 0xD20D20D3 + .long 0xD3680D37 + .long 0xD4C77B04 + .long 0xD62B80D7 + .long 0xD79435E6 + .long 0xD901B204 + .long 0xDA740DA8 + .long 0xDBEB61EF + .long 0xDD67C8A7 + .long 0xDEE95C4D + .long 0xE070381D + .long 0xE1FC780F + .long 0xE38E38E4 + .long 0xE525982B + .long 0xE6C2B449 + .long 0xE865AC7C + .long 0xEA0EA0EB + .long 0xEBBDB2A6 + .long 0xED7303B6 + .long 0xEF2EB720 + .long 0xF0F0F0F1 + .long 0xF2B9D649 + .long 0xF4898D60 + .long 0xF6603D99 + .long 0xF83E0F84 + .long 0xFA232CF3 + .long 0xFC0FC0FD + .long 0xFE03F810 + .long 0x2000000 + .long 0x81020409 + .long 0x82082083 + .long 0x83126E98 + .long 0x84210843 + .long 0x85340854 + .long 0x864B8A7E + .long 0x8767AB60 + .long 0x88888889 + .long 0x89AE408A + .long 0x8AD8F2FC + .long 0x8C08C08D + .long 0x8D3DCB09 + .long 0x8E78356E + .long 0x8FB823EF + .long 0x90FDBC0A + .long 0x92492493 + .long 0x939A85C5 + .long 0x94F20950 + .long 0x964FDA6D + .long 0x97B425EE + .long 0x991F1A52 + .long 0x9A90E7DA + .long 0x9C09C09D + .long 0x9D89D89E + .long 0x9F1165E8 + .long 0xA0A0A0A1 + .long 0xA237C32C + .long 0xA3D70A3E + .long 0xA57EB503 + .long 0xA72F053A + .long 0xA8E83F58 + .long 0xAAAAAAAB + .long 0xAC769185 + .long 0xAE4C415D + .long 0xB02C0B03 + .long 0xB21642C9 + .long 0xB40B40B5 + .long 0xB60B60B7 + .long 0xB81702E1 + .long 0xBA2E8BA3 + .long 0xBC52640C + .long 0xBE82FA0C + .long 0xC0C0C0C1 + .long 0xC30C30C4 + .long 0xC565C87C + .long 0xC7CE0C7D + .long 0xCA4587E7 + .long 0xCCCCCCCD + .long 0xCF6474A9 + .long 0xD20D20D3 + .long 0xD4C77B04 + .long 0xD79435E6 + .long 0xDA740DA8 + .long 0xDD67C8A7 + .long 0xE070381D + .long 0xE38E38E4 + .long 0xE6C2B449 + .long 0xEA0EA0EB + .long 0xED7303B6 + .long 0xF0F0F0F1 + .long 0xF4898D60 + .long 0xF83E0F84 + .long 0xFC0FC0FD + .long 0x4000000 + .long 0x82082083 + .long 0x84210843 + .long 0x864B8A7E + .long 0x88888889 + .long 0x8AD8F2FC + .long 0x8D3DCB09 + .long 0x8FB823EF + .long 0x92492493 + .long 0x94F20950 + .long 0x97B425EE + .long 0x9A90E7DA + .long 0x9D89D89E + .long 0xA0A0A0A1 + .long 0xA3D70A3E + .long 0xA72F053A + .long 0xAAAAAAAB + .long 0xAE4C415D + .long 0xB21642C9 + .long 0xB60B60B7 + .long 0xBA2E8BA3 + .long 0xBE82FA0C + .long 0xC30C30C4 + .long 0xC7CE0C7D + .long 0xCCCCCCCD + .long 0xD20D20D3 + .long 0xD79435E6 + .long 0xDD67C8A7 + .long 0xE38E38E4 + .long 0xEA0EA0EB + .long 0xF0F0F0F1 + .long 0xF83E0F84 + .long 0x8000000 + .long 0x84210843 + .long 0x88888889 + .long 0x8D3DCB09 + .long 0x92492493 + .long 0x97B425EE + .long 0x9D89D89E + .long 0xA3D70A3E + .long 0xAAAAAAAB + .long 0xB21642C9 + .long 0xBA2E8BA3 + .long 0xC30C30C4 + .long 0xCCCCCCCD + .long 0xD79435E6 + .long 0xE38E38E4 + .long 0xF0F0F0F1 + .long 0x10000000 + .long 0x88888889 + .long 0x92492493 + .long 0x9D89D89E + .long 0xAAAAAAAB + .long 0xBA2E8BA3 + .long 0xCCCCCCCD + .long 0xE38E38E4 + .long 0x20000000 + .long 0x92492493 + .long 0xAAAAAAAB + .long 0xCCCCCCCD + .long 0x40000000 + .long 0xAAAAAAAB + .long 0x80000000 +__muldiv: + neg r4,r2 + ld.as r5,[pcl,r4] + abs_s r12,r0 + bic.f 0,r2,r4 + mpyhu.ne r12,r12,r5 + norm r3,r2 + xor.f 0,r0,r1 + ; write port allocation stall + rsub r3,r3,30 + lsr r0,r12,r3 + j_s.d [blink] + neg.mi r0,r0 + + .balign 4 +SYM(__divsi3): + norm r3,r1 + abs_s r2,r1 + brhs r3,23,__muldiv + norm r4,r0 + abs_l r12,r0 + brhs r4,r3,.Lonebit + asl_s r2,r2,r3 + asl r12,r12,r4 + sub lp_count,r3,r4 + sub.f r12,r12,r2 + brge.d r12,r2,.Lsbit + sub r4,r3,r4 + add.lo r12,r12,r2 + lp .Ldivend +.Ldivstart:divaw r12,r12,r2 +.Ldivend:xor_s r1,r1,r0 + sub r0,r4,1 + bmsk r0,r12,r0 + bset.hs r0,r0,r4 + tst_s r1,r1 + j_s.d [blink] + neg.mi r0,r0 +.Lonebit: + xor_s r1,r1,r0 + asr_s r1,r1,31 + sub1.f 0,r12,r2 ; special case: -2**(n+1) / 2**n + or r0,r1,1 + add.eq r0,r0,r0 + cmp_s r12,r2 + j_s.d [blink] + mov.lo r0,0 +.Lsbit: + ; Need to handle special cases involving negative powers of two: + ; r12,r2 are normalized dividend / divisor; + ; divide anything by 0x80000000, or divide 0x80000000 by 0x40000000 + add_s r12,r12,r2 + xor_s r1,r1,r0 + rsub r4,r4,-1 + ror r0,r12,r4 + tst_s r2,r2 + bmsk r0,r0,r3 + add.pl r0,r0,r0 + tst_s r1,r1 + j_s.d [blink] + neg.mi r0,r0 +#else /* !MULDIV */ +/* This version requires that divaw works with a divisor of 0x80000000U */ + abs_s r2,r1 + norm r4,r0 + neg_s r3,r2 + norm r3,r3 + abs_s r12,r0 + brhs r4,r3,.Lonebit + asl_s r2,r2,r3 + asl r12,r12,r4 + sub lp_count,r3,r4 + cmp_s r12,r2 + sub.hs r12,r12,r2 + lp .Ldivend +.Ldivstart:divaw r12,r12,r2 +.Ldivend:xor_s r1,r1,r0 + sub_s r0,r3,1 + bmsk r0,r12,r0 + bset.hs r0,r0,r3 + tst_s r1,r1 + j_s.d [blink] + negmi r0,r0 +.Lonebit: + xor_s r1,r1,r0 + asr_s r1,r1,31 + cmp_s r12,r2 + mov_s r0,0 + j_s.d [blink] + orhs r0,r1,1 +#endif /* MULDIV */ + +#endif /* ifndef __ARC700__ */ + ENDFUNC(__divsi3) + + +#endif /* L_divsi3 */ + +#ifdef L_umodsi3 + .section .text + .align 4 + + .global SYM(__umodsi3) + FUNC(__umodsi3) +SYM(__umodsi3): + mov r7,blink + bl.nd @SYM(__udivmodsi4) + j.d [r7] + mov r0,r1 + ENDFUNC(__umodsi3) +#if 0 /* interferes with linux loader */ + .section .__arc_profile_forward, "a" + .long SYM(__umodsi3) + .long SYM(__udivmodsi4) + .long 65536 +#endif + +#endif /* L_umodsi3 */ + +#ifdef L_modsi3 + .section .text + .align 4 + + .global SYM (__modsi3) + FUNC(__modsi3) +SYM(__modsi3): +#ifndef __ARC700__ + /* A5 / ARC60? */ + mov_s r12,blink + mov_s r6,r0 + abs_s r0,r0 + bl.d @SYM(__udivmodsi4) + abs_s r1,r1 + tst r6,r6 + neg_s r0,r1 + j_s.d [r12] + mov.pl r0,r1 +#else /* __ARC700__ */ + abs_s r2,r1 + norm.f r4,r0 + neg r5,r2 + norm r3,r5 + abs_l r12,r0 + brhs r4,r3,.Lonebit + asl_s r2,r2,r3 + asl r12,r12,r4 + sub lp_count,r3,r4 + cmp_s r12,r2 + sub.hs r12,r12,r2 + tst_s r0,r0 + lp .Ldivend +.Ldivstart:divaw r12,r12,r2 +.Ldivend: + lsr r0,r12,r3 + j_s.d [blink] + neg.mi r0,r0 + .balign 4 +.Lonebit:neg.pl r5,r5 + cmp_s r12,r2 + j_s.d [blink] + sub.hs r0,r0,r5 +#endif /* __ARC700__ */ + ENDFUNC(__modsi3) + +#endif /* L_modsi3 */ + +#ifdef L_clzsi2 + .section .text + .align 4 + .global SYM (__clzsi2) +SYM(__clzsi2): +#ifdef __ARC_NORM__ + HIDDEN_FUNC(__clzsi2) + norm.f r0,r0 + mov.n r0,0 + j_s.d [blink] + add.pl r0,r0,1 + ENDFUNC(__clzsi2) +#elif defined (__ARC601__) + FUNC(__clzsi2) + mov lp_count,10 + mov_l r1,0 + bset r2,r1,29 + lp .Loop_end + brhs r0,r2,.Loop_end + add3 r0,r1,r0 +.Loop_end: + asl.f 0,r0 + sub2 r0,lp_count,lp_count + sub.cs.f r0,r0,1 + add r0,r0,31 + j_s.d [blink] + add.pl r0,r0,1 + ENDFUNC(__clzsi2) +#else + FUNC(__clzsi2) + asl.f 0,r0,2 + mov r1,-1 +.Lcheck: + bbit1.d r0,31,.Ldone + asl.pl r0,r0,3 + bcs.d .Ldone_1 + add_s r1,r1,3 + bpnz.d .Lcheck + asl.f 0,r0,2 + mov_s r0,32 + j_s.d [blink] + mov.ne r0,r1 +.Ldone: + j_s.d [blink] + add_s r0,r1,1 +.Ldone_1: + j_s.d [blink] + sub_s r0,r1,1 + ENDFUNC(__clzsi2) +#endif +#endif /* L_clzsi2 */ + .section .text + + +;;; MILLICODE THUNK LIB ;*************** + +;;; .macro push_regs from, to, offset +;;; st_s "\from", [sp, \offset] +;;; .if \to-\from +;;; push_regs "(\from+1)", \to, "(\offset+4)" +;;; .endif +;;; .endm +;;; push_regs 13, 18, 0 +;;; + +;;;; .macro sum from, to, three +;;;; .long \from +;;;; .long \three +;;;; .local regno +;;;; .set regno, \from+1 +;;;; .set shift, 32 +;;;; .set shift, shift - 1 +;;;; # st_s %shift @3 lsl #shift +;;;; .if \to-\from +;;;; sum "(\from+1)", \to, "(\three)" +;;;; .endif +;;;; .endm +;;;; +;;;; SUM 0,5, 9 +;;;; +; .altmacro +;; .macro push_regs from=0, to=3, offset +;; st_s r\from, [sp, \offset] +;; .if \to-\from +;; push_regs "\from+1 ",\to,"(\offset+4)" +;; .endif +;; .endm +;; +;; .macro expand_to_push from=13, to +;; ; .section .text +;; ; .align 4 +;; ; .global st_ +;; ; .type foo, +;; st_13_to_25: +;; ; push_regs \from, \to, 0 +;; push_regs 0,3 ; +;; .endm +;; +;; expand_to_push 13,18 +;; +;#endif + +#ifdef L_millicodethunk_st + .section .text + .align 4 + .global SYM(__st_r13_to_r15) + .global SYM(__st_r13_to_r16) + .global SYM(__st_r13_to_r17) + .global SYM(__st_r13_to_r18) + .global SYM(__st_r13_to_r19) + .global SYM(__st_r13_to_r20) + .global SYM(__st_r13_to_r21) + .global SYM(__st_r13_to_r22) + .global SYM(__st_r13_to_r23) + .global SYM(__st_r13_to_r24) + .global SYM(__st_r13_to_r25) + HIDDEN_FUNC(__st_r13_to_r15) + HIDDEN_FUNC(__st_r13_to_r16) + HIDDEN_FUNC(__st_r13_to_r17) + HIDDEN_FUNC(__st_r13_to_r18) + HIDDEN_FUNC(__st_r13_to_r19) + HIDDEN_FUNC(__st_r13_to_r20) + HIDDEN_FUNC(__st_r13_to_r21) + HIDDEN_FUNC(__st_r13_to_r22) + HIDDEN_FUNC(__st_r13_to_r23) + HIDDEN_FUNC(__st_r13_to_r24) + HIDDEN_FUNC(__st_r13_to_r25) + .align 4 +SYM(__st_r13_to_r25): + st r25, [sp,48] +SYM(__st_r13_to_r24): + st r24, [sp,44] +SYM(__st_r13_to_r23): + st r23, [sp,40] +SYM(__st_r13_to_r22): + st r22, [sp,36] +SYM(__st_r13_to_r21): + st r21, [sp,32] +SYM(__st_r13_to_r20): + st r20, [sp,28] +SYM(__st_r13_to_r19): + st r19, [sp,24] +SYM(__st_r13_to_r18): + st r18, [sp,20] +SYM(__st_r13_to_r17): + st r17, [sp,16] +SYM(__st_r13_to_r16): + st r16, [sp,12] +SYM(__st_r13_to_r15): +#ifdef __ARC700__ + st r15, [sp,8] ; minimum function size to avoid stall: 6 bytes. +#else + st_s r15, [sp,8] +#endif + st_s r14, [sp,4] + j_s.d [%blink] + st_s r13, [sp,0] + ENDFUNC(__st_r13_to_r15) + ENDFUNC(__st_r13_to_r16) + ENDFUNC(__st_r13_to_r17) + ENDFUNC(__st_r13_to_r18) + ENDFUNC(__st_r13_to_r19) + ENDFUNC(__st_r13_to_r20) + ENDFUNC(__st_r13_to_r21) + ENDFUNC(__st_r13_to_r22) + ENDFUNC(__st_r13_to_r23) + ENDFUNC(__st_r13_to_r24) + ENDFUNC(__st_r13_to_r25) +#endif /* L_millicodethunk_st */ + + +#ifdef L_millicodethunk_ld + .section .text + .align 4 +; ================================== +; the loads + + .global SYM(__ld_r13_to_r15) + .global SYM(__ld_r13_to_r16) + .global SYM(__ld_r13_to_r17) + .global SYM(__ld_r13_to_r18) + .global SYM(__ld_r13_to_r19) + .global SYM(__ld_r13_to_r20) + .global SYM(__ld_r13_to_r21) + .global SYM(__ld_r13_to_r22) + .global SYM(__ld_r13_to_r23) + .global SYM(__ld_r13_to_r24) + .global SYM(__ld_r13_to_r25) + HIDDEN_FUNC(__ld_r13_to_r15) + HIDDEN_FUNC(__ld_r13_to_r16) + HIDDEN_FUNC(__ld_r13_to_r17) + HIDDEN_FUNC(__ld_r13_to_r18) + HIDDEN_FUNC(__ld_r13_to_r19) + HIDDEN_FUNC(__ld_r13_to_r20) + HIDDEN_FUNC(__ld_r13_to_r21) + HIDDEN_FUNC(__ld_r13_to_r22) + HIDDEN_FUNC(__ld_r13_to_r23) + HIDDEN_FUNC(__ld_r13_to_r24) + HIDDEN_FUNC(__ld_r13_to_r25) +SYM(__ld_r13_to_r25): + ld r25, [sp,48] +SYM(__ld_r13_to_r24): + ld r24, [sp,44] +SYM(__ld_r13_to_r23): + ld r23, [sp,40] +SYM(__ld_r13_to_r22): + ld r22, [sp,36] +SYM(__ld_r13_to_r21): + ld r21, [sp,32] +SYM(__ld_r13_to_r20): + ld r20, [sp,28] +SYM(__ld_r13_to_r19): + ld r19, [sp,24] +SYM(__ld_r13_to_r18): + ld r18, [sp,20] +SYM(__ld_r13_to_r17): + ld r17, [sp,16] +SYM(__ld_r13_to_r16): + ld r16, [sp,12] +SYM(__ld_r13_to_r15): +#ifdef __ARC700__ + ld r15, [sp,8] ; minimum function size to avoid stall: 6 bytes. +#else + ld_s r15, [sp,8] +#endif + ld_s r14, [sp,4] + j_s.d [%blink] + ld_s r13, [sp,0] + ENDFUNC(__ld_r13_to_r15) + ENDFUNC(__ld_r13_to_r16) + ENDFUNC(__ld_r13_to_r17) + ENDFUNC(__ld_r13_to_r18) + ENDFUNC(__ld_r13_to_r19) + ENDFUNC(__ld_r13_to_r20) + ENDFUNC(__ld_r13_to_r21) + ENDFUNC(__ld_r13_to_r22) + ENDFUNC(__ld_r13_to_r23) + ENDFUNC(__ld_r13_to_r24) + ENDFUNC(__ld_r13_to_r25) + +#endif /* L_millicodethunk_ld */ +#ifdef L_millicodethunk_ret + .global SYM(__ld_r13_to_r14_ret) + .global SYM(__ld_r13_to_r15_ret) + .global SYM(__ld_r13_to_r16_ret) + .global SYM(__ld_r13_to_r17_ret) + .global SYM(__ld_r13_to_r18_ret) + .global SYM(__ld_r13_to_r19_ret) + .global SYM(__ld_r13_to_r20_ret) + .global SYM(__ld_r13_to_r21_ret) + .global SYM(__ld_r13_to_r22_ret) + .global SYM(__ld_r13_to_r23_ret) + .global SYM(__ld_r13_to_r24_ret) + .global SYM(__ld_r13_to_r25_ret) + HIDDEN_FUNC(__ld_r13_to_r14_ret) + HIDDEN_FUNC(__ld_r13_to_r15_ret) + HIDDEN_FUNC(__ld_r13_to_r16_ret) + HIDDEN_FUNC(__ld_r13_to_r17_ret) + HIDDEN_FUNC(__ld_r13_to_r18_ret) + HIDDEN_FUNC(__ld_r13_to_r19_ret) + HIDDEN_FUNC(__ld_r13_to_r20_ret) + HIDDEN_FUNC(__ld_r13_to_r21_ret) + HIDDEN_FUNC(__ld_r13_to_r22_ret) + HIDDEN_FUNC(__ld_r13_to_r23_ret) + HIDDEN_FUNC(__ld_r13_to_r24_ret) + HIDDEN_FUNC(__ld_r13_to_r25_ret) + .section .text + .align 4 +SYM(__ld_r13_to_r25_ret): + ld r25, [sp,48] +SYM(__ld_r13_to_r24_ret): + ld r24, [sp,44] +SYM(__ld_r13_to_r23_ret): + ld r23, [sp,40] +SYM(__ld_r13_to_r22_ret): + ld r22, [sp,36] +SYM(__ld_r13_to_r21_ret): + ld r21, [sp,32] +SYM(__ld_r13_to_r20_ret): + ld r20, [sp,28] +SYM(__ld_r13_to_r19_ret): + ld r19, [sp,24] +SYM(__ld_r13_to_r18_ret): + ld r18, [sp,20] +SYM(__ld_r13_to_r17_ret): + ld r17, [sp,16] +SYM(__ld_r13_to_r16_ret): + ld r16, [sp,12] +SYM(__ld_r13_to_r15_ret): + ld r15, [sp,8] +SYM(__ld_r13_to_r14_ret): + ld blink,[sp,r12] + ld_s r14, [sp,4] + ld.ab r13, [sp,r12] + j_s.d [%blink] + add_s sp,sp,4 + ENDFUNC(__ld_r13_to_r14_ret) + ENDFUNC(__ld_r13_to_r15_ret) + ENDFUNC(__ld_r13_to_r16_ret) + ENDFUNC(__ld_r13_to_r17_ret) + ENDFUNC(__ld_r13_to_r18_ret) + ENDFUNC(__ld_r13_to_r19_ret) + ENDFUNC(__ld_r13_to_r20_ret) + ENDFUNC(__ld_r13_to_r21_ret) + ENDFUNC(__ld_r13_to_r22_ret) + ENDFUNC(__ld_r13_to_r23_ret) + ENDFUNC(__ld_r13_to_r24_ret) + ENDFUNC(__ld_r13_to_r25_ret) + +#endif /* L_millicodethunk_ret */ + +#ifdef L_adddf3 +#ifdef __ARC_NORM__ +#include "ieee-754/adddf3.S" +#endif +#endif + +#ifdef L_muldf3 +#ifdef __ARC700__ +#include "ieee-754/muldf3.S" +#elif defined (__ARC_NORM__) && defined(__ARC_MUL64__) +#include "ieee-754/arc600-mul64/muldf3.S" +#elif defined (__ARC_NORM__) && defined(__ARC_MUL32BY16__) +#include "ieee-754/arc600-dsp/muldf3.S" +#endif +#endif + +#ifdef L_addsf3 +#ifdef __ARC_NORM__ +#include "ieee-754/addsf3.S" +#endif +#endif + +#ifdef L_mulsf3 +#ifdef __ARC700__ +#include "ieee-754/mulsf3.S" +#elif defined (__ARC_NORM__) && defined(__ARC_MUL64__) +#include "ieee-754/arc600-mul64/mulsf3.S" +#elif defined (__ARC_NORM__) && defined(__ARC_MUL32BY16__) +#include "ieee-754/arc600-dsp/mulsf3.S" +#elif defined (__ARC_NORM__) +#include "ieee-754/arc600/mulsf3.S" +#endif +#endif + +#ifdef L_divdf3 +#ifdef __ARC700__ +#include "ieee-754/divdf3.S" +#elif defined (__ARC_NORM__) && defined(__ARC_MUL64__) +#include "ieee-754/arc600-mul64/divdf3.S" +#elif defined (__ARC_NORM__) && defined(__ARC_MUL32BY16__) +#include "ieee-754/arc600-dsp/divdf3.S" +#endif +#endif + +#ifdef L_divsf3 +#ifdef __ARC700__ +#include "ieee-754/divsf3-stdmul.S" +#elif defined (__ARC_NORM__) && defined(__ARC_MUL64__) +#include "ieee-754/arc600-mul64/divsf3.S" +#elif defined (__ARC_NORM__) && defined(__ARC_MUL32BY16__) +#include "ieee-754/arc600-dsp/divsf3.S" +#elif defined (__ARC_NORM__) +#include "ieee-754/arc600/divsf3.S" +#endif +#endif + +#ifdef L_extendsfdf2 +#ifdef __ARC_NORM__ +#include "ieee-754/extendsfdf2.S" +#endif +#endif + +#ifdef L_truncdfsf2 +#ifdef __ARC_NORM__ +#include "ieee-754/truncdfsf2.S" +#endif +#endif + +#ifdef L_floatsidf +#ifdef __ARC_NORM__ +#include "ieee-754/floatsidf.S" +#endif +#endif + +#ifdef L_floatsisf +#ifdef __ARC_NORM__ +#include "ieee-754/floatsisf.S" +#endif +#endif + +#ifdef L_floatunsidf +#ifdef __ARC_NORM__ +#include "ieee-754/floatunsidf.S" +#endif +#endif + +#ifdef L_fixdfsi +#ifdef __ARC_NORM__ +#include "ieee-754/fixdfsi.S" +#endif +#endif + +#ifdef L_fixsfsi +#ifdef __ARC_NORM__ +#include "ieee-754/fixsfsi.S" +#endif +#endif + +#ifdef L_fixunsdfsi +#ifdef __ARC_NORM__ +#include "ieee-754/fixunsdfsi.S" +#endif +#endif + +#ifdef L_eqdf2 +#ifdef __ARC_NORM__ +#include "ieee-754/eqdf2.S" +#endif +#endif + +#ifdef L_eqsf2 +#ifdef __ARC_NORM__ +#include "ieee-754/eqsf2.S" +#endif +#endif + +#ifdef L_gtdf2 +#ifdef __ARC_NORM__ +#include "ieee-754/gtdf2.S" +#endif +#endif + +#ifdef L_gtsf2 +#ifdef __ARC_NORM__ +#include "ieee-754/gtsf2.S" +#endif +#endif + +#ifdef L_gedf2 +#ifdef __ARC_NORM__ +#include "ieee-754/gedf2.S" +#endif +#endif + +#ifdef L_gesf2 +#ifdef __ARC_NORM__ +#include "ieee-754/gesf2.S" +#endif +#endif + +#ifdef L_uneqdf2 +#ifdef __ARC_NORM__ +#include "ieee-754/uneqdf2.S" +#endif +#endif + +#ifdef L_uneqsf2 +#ifdef __ARC_NORM__ +#include "ieee-754/uneqsf2.S" +#endif +#endif + +#ifdef L_orddf2 +#ifdef __ARC_NORM__ +#include "ieee-754/orddf2.S" +#endif +#endif + +#ifdef L_ordsf2 +#ifdef __ARC_NORM__ +#include "ieee-754/ordsf2.S" +#endif +#endif diff --git a/libgcc/config/arc/libgcc-excl.ver b/libgcc/config/arc/libgcc-excl.ver new file mode 100644 index 00000000000..57c96e1e765 --- /dev/null +++ b/libgcc/config/arc/libgcc-excl.ver @@ -0,0 +1,43 @@ +# Exclude libgcc.so symbols for the Synopsys DesignWare ARC CPU. + +# Copyright (C) 2007-2013 Free Software Foundation, Inc. +# Contributor: Joern Rennecke <joern.rennecke@embecosm.com> +# on behalf of Synopsys Inc. + +# This file is part of GCC. + +# GCC is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3, or (at your option) any later +# version. + +# GCC is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. + +# Under Section 7 of GPL version 3, you are granted additional +# permissions described in the GCC Runtime Library Exception, version +# 3.1, as published by the Free Software Foundation. + +# You should have received a copy of the GNU General Public License and +# a copy of the GCC Runtime Library Exception along with this program; +# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +# <http://www.gnu.org/licenses/>. */ + +# Exclude various symbols which should not be visible in libgcc.so for ARC. +# Floating point comparisons use a special lightweight ABI which is not +# compatible with calls via a plt. Moreover, the code is so compact that +# it is better to include a separate copy in each dso. +%exclude { + __eqsf2 + __eqdf2 + __gtsf2 + __gtdf2 + __gesf2 + __gedf2 + __uneqsf2 + __uneqdf2 + __ordsf2 + __orddf2 +} diff --git a/libgcc/config/arc/t-arc b/libgcc/config/arc/t-arc new file mode 100644 index 00000000000..6edf10ee3ec --- /dev/null +++ b/libgcc/config/arc/t-arc @@ -0,0 +1,100 @@ +# GCC Makefile fragment for Synopsys DesignWare ARC + +# Copyright (C) 2007-2013 Free Software Foundation, Inc. +# Contributor: Joern Rennecke <joern.rennecke@embecosm.com> +# on behalf of Synopsys Inc. + +# This file is part of GCC. + +# GCC is free software; you can redistribute it and/or modify it under the +# terms of the GNU General Public License as published by the Free Software +# Foundation; either version 3, or (at your option) any later version. + +# GCC is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +# details. + +# You should have received a copy of the GNU General Public License along +# with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +CROSS_LIBGCC1 = libgcc1-asm.a +LIB1ASMSRC = arc/lib1funcs.S +LIB1ASMFUNCS = _mulsi3 _umulsidi3 _umulsi3_highpart \ + _udivsi3 _divsi3 _umodsi3 _modsi3 \ + _divmod_tools _clzsi2 \ + _millicodethunk_st _millicodethunk_ld _millicodethunk_ret \ + _adddf3 _muldf3 _addsf3 _mulsf3 _divsf3 _divdf3 _truncdfsf2 _extendsfdf2 \ + _eqdf2 _eqsf2 _gedf2 _gesf2 _gtdf2 _gtsf2 _uneqdf2 _uneqsf2 _ordsf2 _orddf2 \ + _fixdfsi _fixsfsi _floatsidf _floatsisf _fixunsdfsi _floatunsidf + +#LIBGCC2_CFLAGS = -g1 -O2 $(LIBGCC2_INCLUDES) $(GCC_CFLAGS) + +# For floating-point emulation, we mostly use hand-coded assembly. +# We use fp-bit.c for debugging purposes, and some parts of it +# as a fallback for hardware configurations for which the hand-coded +# assembly support is incomplete, i.e., where there is no NORM and/or no +# supported multiply instruction. Using floating point on such a +# configuration is generally inadvisable, but we got to provide support +# somehow so that we can run the testsuites. +# fp-hack.h / dp-hack.h take care of slecting the parts that are needed, +# and (for debugging) of renaming functions so that they can be +# used in an asm wrapper. + +LIB2ADD = fp-bit.c dp-bit.c + +dp-bit.c: $(srcdir)/fp-bit.c + echo '#ifndef __big_endian__' > dp-bit.c + echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c + echo '#endif' >> dp-bit.c + echo '#include "fp-bit.h"' >> dp-bit.c + echo '#include "config/arc/dp-hack.h"' >> dp-bit.c + grep -v 'include.*fp-bit.h' $(srcdir)/fp-bit.c >> dp-bit.c + +fp-bit.c: $(srcdir)/fp-bit.c + echo '#define FLOAT' > fp-bit.c + echo '#ifndef __big_endian__' >> fp-bit.c + echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c + echo '#endif' >> fp-bit.c + echo '#include "config/arc/fp-hack.h"' >> fp-bit.c + cat $(srcdir)/fp-bit.c >> fp-bit.c + +# .init/.fini section routines + +crtg.o: $(srcdir)/config/arc/crtg.S + $(crt_compile) -c -x assembler-with-cpp $< + +crtgend.o: $(srcdir)/config/arc/crtgend.S + $(crt_compile) -c -x assembler-with-cpp $< + +mcount.o: $(srcdir)/config/arc/gmon/mcount.c + $(gcc_compile) -isystem $(srcdir)/config/arc/gmon -c $< \ + -fcall-saved-r0 -fcall-saved-r1 -fcall-saved-r2 -fcall-saved-r3 \ + -fcall-saved-r4 -fcall-saved-r5 -fcall-saved-r6 -fcall-saved-r7 \ + -fomit-frame-pointer + +gmon.o: $(srcdir)/config/arc/gmon/gmon.c + $(gcc_compile) -isystem $(srcdir)/config/arc/gmon -mno-sdata -c $< \ + -fno-strict-aliasing \ + -Wno-extra # suppress inane warning about missing initializer. + # Adding initializers for the remaining elements of gmonparam would + # make the code more brittle. + +prof-freq-stub.o: $(srcdir)/config/arc/gmon/prof-freq-stub.S + $(gcc_compile) -isystem $(srcdir)/config/arc/gmon -c $< + +prof-freq.o: $(srcdir)/config/arc/gmon/prof-freq.c + $(gcc_compile) -isystem $(srcdir)/config/arc/gmon -c $< + +dcache_linesz.o: $(srcdir)/config/arc/gmon/dcache_linesz.S + $(gcc_compile) -isystem $(srcdir)/config/arc/gmon -c $< + +profil.o: $(srcdir)/config/arc/gmon/profil.S + $(gcc_compile) -isystem $(srcdir)/config/arc/gmon -c $< + +profil-uclibc.o: $(srcdir)/config/arc/gmon/profil-uclibc.c + $(gcc_compile) -isystem $(srcdir)/config/arc/gmon -c $< + +libgmon.a: mcount.o gmon.o dcache_linesz.o $(PROFILE_OSDEP) + $(AR_CREATE_FOR_TARGET) $@ $^ diff --git a/libgcc/config/arc/t-arc-newlib b/libgcc/config/arc/t-arc-newlib new file mode 100644 index 00000000000..c9b994657a6 --- /dev/null +++ b/libgcc/config/arc/t-arc-newlib @@ -0,0 +1,22 @@ +# GCC Makefile fragment for the Synopsys DesignWare ARC CPU with newlib. + +# Copyright (C) 2007-2013 Free Software Foundation, Inc. +# Contributor: Joern Rennecke <joern.rennecke@embecosm.com> +# on behalf of Synopsys Inc. + +# This file is part of GCC. + +# GCC is free software; you can redistribute it and/or modify it under the +# terms of the GNU General Public License as published by the Free Software +# Foundation; either version 3, or (at your option) any later version. + +# GCC is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more +# details. + +# You should have received a copy of the GNU General Public License along +# with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +PROFILE_OSDEP = prof-freq-stub.o profil.o diff --git a/libgcc/config/arc/t-arc700-uClibc b/libgcc/config/arc/t-arc700-uClibc new file mode 100644 index 00000000000..ebaba498e96 --- /dev/null +++ b/libgcc/config/arc/t-arc700-uClibc @@ -0,0 +1,40 @@ +# GCC Makefile fragment for the Synopsys DesignWare ARC700 CPU with uClibc. + +# Copyright (C) 2007-2013 Free Software Foundation, Inc. +# Contributor: Joern Rennecke <joern.rennecke@embecosm.com> +# on behalf of Synopsys Inc. + +# This file is part of GCC. + +# GCC is free software; you can redistribute it and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 3, or (at your option) any later +# version. + +# GCC is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. + +# Under Section 7 of GPL version 3, you are granted additional +# permissions described in the GCC Runtime Library Exception, version +# 3.1, as published by the Free Software Foundation. + +# You should have received a copy of the GNU General Public License and +# a copy of the GCC Runtime Library Exception along with this program; +# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +# <http://www.gnu.org/licenses/>. */ + +CRTSTUFF_T_CFLAGS += -mno-sdata + +# Compile crtbeginS.o and crtendS.o with pic. +CRTSTUFF_T_CFLAGS_S = $(CRTSTUFF_T_CFLAGS) -mA7 -fPIC + +# Compile libgcc2.a with pic. +TARGET_LIBGCC2_CFLAGS = -mA7 -fPIC + +PROFILE_OSDEP = prof-freq.o + +# Override t-slibgcc-elf-ver to hide some lib1func +# routines which should not be called via PLT. +SHLIB_MAPFILES = libgcc-std.ver $(srcdir)/config/arc/libgcc-excl.ver diff --git a/libgcc/config/arm/t-vxworks b/libgcc/config/arm/t-vxworks deleted file mode 100644 index 9db1f1602bc..00000000000 --- a/libgcc/config/arm/t-vxworks +++ /dev/null @@ -1 +0,0 @@ -LIB1ASMFUNCS += _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func _call_via_rX _interwork_call_via_rX _clzsi2 _clzdi2 _ctzsi2 diff --git a/libgcc/config/cris/arit.c b/libgcc/config/cris/arit.c index b64d7c95245..00ffa07a5a0 100644 --- a/libgcc/config/cris/arit.c +++ b/libgcc/config/cris/arit.c @@ -38,6 +38,14 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define LZ(v) __builtin_clz (v) #endif +/* In (at least) the 4.7 series, GCC doesn't automatically choose the + most optimal strategy, possibly related to insufficient modelling of + delay-slot costs. */ +#if defined (__CRIS_arch_version) && __CRIS_arch_version >= 10 +#define SIGNMULT(s, a) ((s) * (a)) /* Cheap multiplication, better than branch. */ +#else +#define SIGNMULT(s, a) ((s) < 0 ? -(a) : (a)) /* Branches are still better. */ +#endif #if defined (L_udivsi3) || defined (L_divsi3) || defined (L_umodsi3) \ || defined (L_modsi3) @@ -198,6 +206,7 @@ __Div (long a, long b) { long extra = 0; long sign = (b < 0) ? -1 : 1; + long res; /* We need to handle a == -2147483648 as expected and must while doing that avoid producing a sequence like "abs (a) < 0" as GCC @@ -213,15 +222,14 @@ __Div (long a, long b) if ((a & 0x7fffffff) == 0) { /* We're at 0x80000000. Tread carefully. */ - a -= b * sign; + a -= SIGNMULT (sign, b); extra = sign; } a = -a; } - /* We knowingly penalize pre-v10 models by multiplication with the - sign. */ - return sign * do_31div (a, __builtin_labs (b)).quot + extra; + res = do_31div (a, __builtin_labs (b)).quot; + return SIGNMULT (sign, res) + extra; } #endif /* L_divsi3 */ @@ -273,6 +281,7 @@ long __Mod (long a, long b) { long sign = 1; + long res; /* We need to handle a == -2147483648 as expected and must while doing that avoid producing a sequence like "abs (a) < 0" as GCC @@ -290,7 +299,8 @@ __Mod (long a, long b) a = -a; } - return sign * do_31div (a, __builtin_labs (b)).rem; + res = do_31div (a, __builtin_labs (b)).rem; + return SIGNMULT (sign, res); } #endif /* L_modsi3 */ #endif /* L_udivsi3 || L_divsi3 || L_umodsi3 || L_modsi3 */ diff --git a/libgcc/config/cris/mulsi3.S b/libgcc/config/cris/mulsi3.S index 8ff76e51e58..734e162b4cb 100644 --- a/libgcc/config/cris/mulsi3.S +++ b/libgcc/config/cris/mulsi3.S @@ -113,16 +113,22 @@ ___Mul: ret nop #else - move.d $r10,$r12 +;; See if we can avoid multiplying some of the parts, knowing +;; they're zero. + move.d $r11,$r9 - bound.d $r12,$r9 + bound.d $r10,$r9 cmpu.w 65535,$r9 bls L(L3) - move.d $r12,$r13 + move.d $r10,$r12 - movu.w $r11,$r9 +;; Nope, have to do all the parts of a 32-bit multiplication. +;; See head comment in optabs.c:expand_doubleword_mult. + + move.d $r10,$r13 + movu.w $r11,$r9 ; ab*cd = (a*d + b*c)<<16 + b*d lslq 16,$r13 - mstep $r9,$r13 + mstep $r9,$r13 ; d*b mstep $r9,$r13 mstep $r9,$r13 mstep $r9,$r13 @@ -140,7 +146,7 @@ ___Mul: mstep $r9,$r13 clear.w $r10 test.d $r10 - mstep $r9,$r10 + mstep $r9,$r10 ; d*a mstep $r9,$r10 mstep $r9,$r10 mstep $r9,$r10 @@ -157,10 +163,9 @@ ___Mul: mstep $r9,$r10 mstep $r9,$r10 movu.w $r12,$r12 - move.d $r11,$r9 - clear.w $r9 - test.d $r9 - mstep $r12,$r9 + clear.w $r11 + move.d $r11,$r9 ; Doubles as a "test.d" preparing for the mstep. + mstep $r12,$r9 ; b*c mstep $r12,$r9 mstep $r12,$r9 mstep $r12,$r9 @@ -182,17 +187,24 @@ ___Mul: add.d $r13,$r10 L(L3): - move.d $r9,$r10 +;; Form the maximum in $r10, by knowing the minimum, $r9. +;; (We don't know which one of $r10 or $r11 it is.) +;; Check if the largest operand is still just 16 bits. + + xor $r9,$r10 xor $r11,$r10 - xor $r12,$r10 cmpu.w 65535,$r10 bls L(L5) movu.w $r9,$r13 - movu.w $r13,$r13 +;; We have ab*cd = (a*c)<<32 + (a*d + b*c)<<16 + b*d, but c==0 +;; so we only need (a*d)<<16 + b*d with d = $r13, ab = $r10. +;; We drop the upper part of (a*d)<<16 as we're only doing a +;; 32-bit-result multiplication. + move.d $r10,$r9 lslq 16,$r9 - mstep $r13,$r9 + mstep $r13,$r9 ; b*d mstep $r13,$r9 mstep $r13,$r9 mstep $r13,$r9 @@ -210,7 +222,7 @@ L(L3): mstep $r13,$r9 clear.w $r10 test.d $r10 - mstep $r13,$r10 + mstep $r13,$r10 ; a*d mstep $r13,$r10 mstep $r13,$r10 mstep $r13,$r10 @@ -231,25 +243,27 @@ L(L3): add.d $r9,$r10 L(L5): - movu.w $r9,$r9 +;; We have ab*cd = (a*c)<<32 + (a*d + b*c)<<16 + b*d, but a and c==0 +;; so b*d (with b=$r13, a=$r10) it is. + lslq 16,$r10 - mstep $r9,$r10 - mstep $r9,$r10 - mstep $r9,$r10 - mstep $r9,$r10 - mstep $r9,$r10 - mstep $r9,$r10 - mstep $r9,$r10 - mstep $r9,$r10 - mstep $r9,$r10 - mstep $r9,$r10 - mstep $r9,$r10 - mstep $r9,$r10 - mstep $r9,$r10 - mstep $r9,$r10 - mstep $r9,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 ret - mstep $r9,$r10 + mstep $r13,$r10 #endif L(Lfe1): .size ___Mul,L(Lfe1)-___Mul diff --git a/libgcc/config/cris/sfp-machine.h b/libgcc/config/cris/sfp-machine.h new file mode 100644 index 00000000000..484693ea60a --- /dev/null +++ b/libgcc/config/cris/sfp-machine.h @@ -0,0 +1,78 @@ +/* Soft-FP definitions for CRIS. + Copyright (C) 2013 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +#define _FP_W_TYPE_SIZE 32 +#define _FP_W_TYPE unsigned long +#define _FP_WS_TYPE signed long +#define _FP_I_TYPE long + +/* The type of the result of a floating point comparison. This must + match `__libgcc_cmp_return__' in GCC for the target. */ +typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); +#define CMPtype __gcc_CMPtype + +/* FIXME: none of the *MEAT* macros have actually been benchmarked to be + better than any other choice for any CRIS variant. */ + +#define _FP_MUL_MEAT_S(R,X,Y) \ + _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_D(R,X,Y) \ + _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) + +#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_loop(S,R,X,Y) +#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) + +#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) +#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1 +#define _FP_NANSIGN_S 0 +#define _FP_NANSIGN_D 0 +#define _FP_QNANNEGATEDP 0 +#define _FP_KEEPNANFRACP 1 + +/* Someone please check this. */ +#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ + do { \ + if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \ + && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \ + { \ + R##_s = Y##_s; \ + _FP_FRAC_COPY_##wc(R,Y); \ + } \ + else \ + { \ + R##_s = X##_s; \ + _FP_FRAC_COPY_##wc(R,X); \ + } \ + R##_c = FP_CLS_NAN; \ + } while (0) + +#define __LITTLE_ENDIAN 1234 +#define __BIG_ENDIAN 4321 + +# define __BYTE_ORDER __LITTLE_ENDIAN + +/* Define ALIASNAME as a strong alias for NAME. */ +# define strong_alias(name, aliasname) _strong_alias(name, aliasname) +# define _strong_alias(name, aliasname) \ + extern __typeof (name) aliasname __attribute__ ((alias (#name))); diff --git a/libgcc/config/cris/t-elfmulti b/libgcc/config/cris/t-elfmulti index b180521039e..308ef5105a9 100644 --- a/libgcc/config/cris/t-elfmulti +++ b/libgcc/config/cris/t-elfmulti @@ -1,3 +1,3 @@ -LIB2ADD_ST = $(srcdir)/config/cris/mulsi3.S +LIB2ADD_ST = $(srcdir)/config/cris/mulsi3.S $(srcdir)/config/cris/umulsidi3.S CRTSTUFF_T_CFLAGS = -moverride-best-lib-options diff --git a/libgcc/config/cris/umulsidi3.S b/libgcc/config/cris/umulsidi3.S new file mode 100644 index 00000000000..eba98a12228 --- /dev/null +++ b/libgcc/config/cris/umulsidi3.S @@ -0,0 +1,289 @@ +;; Copyright (C) 2001, 2004, 2013 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it under +;; the terms of the GNU General Public License as published by the Free +;; Software Foundation; either version 3, or (at your option) any later +;; version. +;; +;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY +;; WARRANTY; without even the implied warranty of MERCHANTABILITY or +;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +;; for more details. +;; +;; Under Section 7 of GPL version 3, you are granted additional +;; permissions described in the GCC Runtime Library Exception, version +;; 3.1, as published by the Free Software Foundation. +;; +;; You should have received a copy of the GNU General Public License and +;; a copy of the GCC Runtime Library Exception along with this program; +;; see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +;; <http://www.gnu.org/licenses/>. +;; +;; This code is derived from mulsi3.S, observing that the mstep*16-based +;; multiplications there, from which it is formed, are actually +;; zero-extending; in gcc-speak "umulhisi3". The difference to *this* +;; function is just a missing top mstep*16 sequence and shifts and 64-bit +;; additions for the high part. Compared to an implementation based on +;; calling __Mul four times (see default implementation of umul_ppmm in +;; longlong.h), this will complete in a time between a fourth and a third +;; of that, assuming the value-based optimizations don't strike. If they +;; all strike there (very often) but none here, we still win, though by a +;; lesser margin, due to lesser total overhead. + +#define L(x) .x +#define CONCAT1(a, b) CONCAT2(a, b) +#define CONCAT2(a, b) a ## b + +#ifdef __USER_LABEL_PREFIX__ +# define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) +#else +# define SYM(x) x +#endif + + .global SYM(__umulsidi3) + .type SYM(__umulsidi3),@function +SYM(__umulsidi3): +#if defined (__CRIS_arch_version) && __CRIS_arch_version >= 10 +;; Can't have the mulu.d last on a cache-line, due to a hardware bug. See +;; the documentation for -mmul-bug-workaround. +;; Not worthwhile to conditionalize here. + .p2alignw 2,0x050f + mulu.d $r11,$r10 + ret + move $mof,$r11 +#else + move.d $r11,$r9 + bound.d $r10,$r9 + cmpu.w 65535,$r9 + bls L(L3) + move.d $r10,$r12 + + move.d $r10,$r13 + movu.w $r11,$r9 ; ab*cd = (a*c)<<32 (a*d + b*c)<<16 + b*d + +;; We're called for floating point numbers very often with the "low" 16 +;; bits zero, so it's worthwhile to optimize for that. + + beq L(L6) ; d == 0? + lslq 16,$r13 + + beq L(L7) ; b == 0? + clear.w $r10 + + mstep $r9,$r13 ; d*b + mstep $r9,$r13 + mstep $r9,$r13 + mstep $r9,$r13 + mstep $r9,$r13 + mstep $r9,$r13 + mstep $r9,$r13 + mstep $r9,$r13 + mstep $r9,$r13 + mstep $r9,$r13 + mstep $r9,$r13 + mstep $r9,$r13 + mstep $r9,$r13 + mstep $r9,$r13 + mstep $r9,$r13 + mstep $r9,$r13 + +L(L7): + test.d $r10 + mstep $r9,$r10 ; d*a + mstep $r9,$r10 + mstep $r9,$r10 + mstep $r9,$r10 + mstep $r9,$r10 + mstep $r9,$r10 + mstep $r9,$r10 + mstep $r9,$r10 + mstep $r9,$r10 + mstep $r9,$r10 + mstep $r9,$r10 + mstep $r9,$r10 + mstep $r9,$r10 + mstep $r9,$r10 + mstep $r9,$r10 + mstep $r9,$r10 + +;; d*a in $r10, d*b in $r13, ab in $r12 and cd in $r11 +;; $r9 = d, need to do b*c and a*c; we can drop d. +;; so $r9 is up for use and we can shift down $r11 as the mstep +;; source for the next mstep-part. + +L(L8): + lsrq 16,$r11 + move.d $r12,$r9 + lslq 16,$r9 + beq L(L9) ; b == 0? + mstep $r11,$r9 + + mstep $r11,$r9 ; b*c + mstep $r11,$r9 + mstep $r11,$r9 + mstep $r11,$r9 + mstep $r11,$r9 + mstep $r11,$r9 + mstep $r11,$r9 + mstep $r11,$r9 + mstep $r11,$r9 + mstep $r11,$r9 + mstep $r11,$r9 + mstep $r11,$r9 + mstep $r11,$r9 + mstep $r11,$r9 + mstep $r11,$r9 +L(L9): + +;; d*a in $r10, d*b in $r13, c*b in $r9, ab in $r12 and c in $r11, +;; need to do a*c. We want that to end up in $r11, so we shift up $r11 to +;; now use as the destination operand. We'd need a test insn to update N +;; to do it the other way round. + + lsrq 16,$r12 + lslq 16,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + mstep $r12,$r11 + +;; d*a in $r10, d*b in $r13, c*b in $r9, a*c in $r11 ($r12 free). +;; Need (a*d + b*c)<<16 + b*d into $r10 and +;; a*c + (a*d + b*c)>>16 plus carry from the additions into $r11. + + add.d $r9,$r10 ; (a*d + b*c) - may produce a carry. + scs $r12 ; The carry corresponds to bit 16 of $r11. + lslq 16,$r12 + add.d $r12,$r11 ; $r11 = a*c + carry from (a*d + b*c). + +#if defined (__CRIS_arch_version) && __CRIS_arch_version >= 8 + swapw $r10 + addu.w $r10,$r11 ; $r11 = a*c + (a*d + b*c) >> 16 including carry. + clear.w $r10 ; $r10 = (a*d + b*c) << 16 +#else + move.d $r10,$r9 + lsrq 16,$r9 + add.d $r9,$r11 ; $r11 = a*c + (a*d + b*c) >> 16 including carry. + lslq 16,$r10 ; $r10 = (a*d + b*c) << 16 +#endif + add.d $r13,$r10 ; $r10 = (a*d + b*c) << 16 + b*d - may produce a carry. + scs $r9 + ret + add.d $r9,$r11 ; Last carry added to the high-order 32 bits. + +L(L6): + clear.d $r13 + ba L(L8) + clear.d $r10 + +L(L11): + clear.d $r10 + ret + clear.d $r11 + +L(L3): +;; Form the maximum in $r10, by knowing the minimum, $r9. +;; (We don't know which one of $r10 or $r11 it is.) +;; Check if the largest operand is still just 16 bits. + + xor $r9,$r10 + xor $r11,$r10 + cmpu.w 65535,$r10 + bls L(L5) + movu.w $r9,$r13 + +;; We have ab*cd = (a*c)<<32 + (a*d + b*c)<<16 + b*d, but c==0 +;; so we only need (a*d)<<16 + b*d with d = $r13, ab = $r10. +;; Remember that the upper part of (a*d)<<16 goes into the lower part +;; of $r11 and there may be a carry from adding the low 32 parts. + beq L(L11) ; d == 0? + move.d $r10,$r9 + + lslq 16,$r9 + beq L(L10) ; b == 0? + clear.w $r10 + + mstep $r13,$r9 ; b*d + mstep $r13,$r9 + mstep $r13,$r9 + mstep $r13,$r9 + mstep $r13,$r9 + mstep $r13,$r9 + mstep $r13,$r9 + mstep $r13,$r9 + mstep $r13,$r9 + mstep $r13,$r9 + mstep $r13,$r9 + mstep $r13,$r9 + mstep $r13,$r9 + mstep $r13,$r9 + mstep $r13,$r9 + mstep $r13,$r9 +L(L10): + test.d $r10 + mstep $r13,$r10 ; a*d + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + move.d $r10,$r11 + lsrq 16,$r11 + lslq 16,$r10 + add.d $r9,$r10 + scs $r12 + ret + add.d $r12,$r11 + +L(L5): +;; We have ab*cd = (a*c)<<32 + (a*d + b*c)<<16 + b*d, but a and c==0 +;; so b*d (with min=b=$r13, max=d=$r10) it is. As it won't overflow the +;; 32-bit part, just set $r11 to 0. + + lslq 16,$r10 + clear.d $r11 + + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + mstep $r13,$r10 + ret + mstep $r13,$r10 +#endif +L(Lfe1): + .size SYM(__umulsidi3),L(Lfe1)-SYM(__umulsidi3) diff --git a/libgcc/config/i386/32/sfp-machine.h b/libgcc/config/i386/32/sfp-machine.h index 143296d69ff..b9eb16633eb 100644 --- a/libgcc/config/i386/32/sfp-machine.h +++ b/libgcc/config/i386/32/sfp-machine.h @@ -65,9 +65,15 @@ "g" ((USItype) (y0))) +#define _FP_MUL_MEAT_S(R,X,Y) \ + _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_D(R,X,Y) \ + _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) #define _FP_MUL_MEAT_Q(R,X,Y) \ _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) +#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_loop(S,R,X,Y) +#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y) #define _FP_NANFRAC_S _FP_QNANBIT_S diff --git a/libgcc/config/i386/crtfastmath.c b/libgcc/config/i386/crtfastmath.c index 991f531fe7d..5a267c3b1a5 100644 --- a/libgcc/config/i386/crtfastmath.c +++ b/libgcc/config/i386/crtfastmath.c @@ -21,6 +21,7 @@ * <http://www.gnu.org/licenses/>. */ +#ifndef _SOFT_FLOAT #define MXCSR_DAZ (1 << 6) /* Enable denormals are zero mode */ #define MXCSR_FTZ (1 << 15) /* Enable flush to zero mode */ @@ -134,3 +135,4 @@ set_fast_math (void) __builtin_ia32_ldmxcsr (mxcsr); #endif } +#endif diff --git a/libgcc/config/i386/crtprec.c b/libgcc/config/i386/crtprec.c index f0c1fbe7228..f8f9962b13b 100644 --- a/libgcc/config/i386/crtprec.c +++ b/libgcc/config/i386/crtprec.c @@ -21,6 +21,7 @@ * <http://www.gnu.org/licenses/>. */ +#ifndef _SOFT_FLOAT #if __PREC == 32 #define X87CW (0 << 8) /* Single precision (24 bits) */ #elif __PREC == 64 @@ -45,3 +46,4 @@ set_precision (void) asm volatile ("fldcw\t%0" : : "m" (cwd)); } +#endif diff --git a/libgcc/config/i386/cygming-crtbegin.c b/libgcc/config/i386/cygming-crtbegin.c index c34178787c8..53909d2dc14 100644 --- a/libgcc/config/i386/cygming-crtbegin.c +++ b/libgcc/config/i386/cygming-crtbegin.c @@ -91,6 +91,9 @@ static EH_FRAME_SECTION_CONST char __EH_FRAME_BEGIN__[] = { }; static struct object obj; + +/* Handle of libgcc's DLL reference. */ +HANDLE hmod_libgcc; #endif #if TARGET_USE_JCR_SECTION @@ -115,9 +118,14 @@ __gcc_register_frame (void) void (*register_frame_fn) (const void *, struct object *); HANDLE h = GetModuleHandle (LIBGCC_SONAME); + if (h) - register_frame_fn = (void (*) (const void *, struct object *)) - GetProcAddress (h, "__register_frame_info"); + { + /* Increasing the load-count of LIBGCC_SONAME DLL. */ + hmod_libgcc = LoadLibrary (LIBGCC_SONAME); + register_frame_fn = (void (*) (const void *, struct object *)) + GetProcAddress (h, "__register_frame_info"); + } else register_frame_fn = __register_frame_info; if (register_frame_fn) @@ -154,5 +162,7 @@ __gcc_deregister_frame (void) deregister_frame_fn = __deregister_frame_info; if (deregister_frame_fn) deregister_frame_fn (__EH_FRAME_BEGIN__); + if (hmod_libgcc) + FreeLibrary (hmod_libgcc); #endif } diff --git a/libgcc/config/i386/sfp-exceptions.c b/libgcc/config/i386/sfp-exceptions.c index fbaaab22f50..3504c4aedd1 100644 --- a/libgcc/config/i386/sfp-exceptions.c +++ b/libgcc/config/i386/sfp-exceptions.c @@ -48,20 +48,32 @@ __sfp_handle_exceptions (int _fex) { float f = 0.0f; #ifdef __x86_64__ + volatile float r __attribute__ ((unused)); asm volatile ("%vdivss\t{%0, %d0|%d0, %0}" : "+x" (f)); + r = f; /* Needed to trigger exception. */ #else asm volatile ("fdiv\t{%y0, %0|%0, %y0}" : "+t" (f)); - asm volatile ("fwait"); + /* No need for fwait, exception is triggered by emitted fstp. */ #endif } + if (_fex & FP_EX_DENORM) + { + struct fenv temp; + asm volatile ("fnstenv\t%0" : "=m" (temp)); + temp.__status_word |= FP_EX_DENORM; + asm volatile ("fldenv\t%0" : : "m" (temp)); + asm volatile ("fwait"); + } if (_fex & FP_EX_DIVZERO) { float f = 1.0f, g = 0.0f; #ifdef __x86_64__ + volatile float r __attribute__ ((unused)); asm volatile ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g)); + r = f; /* Needed to trigger exception. */ #else asm volatile ("fdivs\t%1" : "+t" (f) : "m" (g)); - asm volatile ("fwait"); + /* No need for fwait, exception is triggered by emitted fstp. */ #endif } if (_fex & FP_EX_OVERFLOW) @@ -82,11 +94,15 @@ __sfp_handle_exceptions (int _fex) } if (_fex & FP_EX_INEXACT) { - struct fenv temp; - asm volatile ("fnstenv\t%0" : "=m" (temp)); - temp.__status_word |= FP_EX_INEXACT; - asm volatile ("fldenv\t%0" : : "m" (temp)); - asm volatile ("fwait"); + float f = 1.0f, g = 3.0f; +#ifdef __x86_64__ + volatile float r __attribute__ ((unused)); + asm volatile ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g)); + r = f; /* Needed to trigger exception. */ +#else + asm volatile ("fdivs\t%1" : "+t" (f) : "m" (g)); + /* No need for fwait, exception is triggered by emitted fstp. */ +#endif } }; #endif diff --git a/libgcc/config/nds32/crtzero.S b/libgcc/config/nds32/crtzero.S new file mode 100644 index 00000000000..65098698dba --- /dev/null +++ b/libgcc/config/nds32/crtzero.S @@ -0,0 +1,103 @@ +/* The startup code sample of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +!!============================================================================== +!! +!! crtzero.S +!! +!! This is JUST A SAMPLE of nds32 startup code !! +!! You can refer this content and implement +!! the actual one in newlib/mculib. +!! +!!============================================================================== + +!!------------------------------------------------------------------------------ +!! Jump to start up code +!!------------------------------------------------------------------------------ + .section .nds32_init, "ax" + j _start + +!!------------------------------------------------------------------------------ +!! Startup code implementation +!!------------------------------------------------------------------------------ + .section .text + .global _start + .weak _SDA_BASE_ + .weak _FP_BASE_ + .align 2 + .func _start + .type _start, @function +_start: +.L_fp_gp_lp_init: + la $fp, _FP_BASE_ ! init $fp + la $gp, _SDA_BASE_ ! init $gp for small data access + movi $lp, 0 ! init $lp + +.L_stack_init: + la $sp, _stack ! init $sp + movi $r0, -8 ! align $sp to 8-byte (use 0xfffffff8) + and $sp, $sp, $r0 ! align $sp to 8-byte (filter out lower 3-bit) + +.L_bss_init: + ! clear BSS, this process can be 4 time faster if data is 4 byte aligned + ! if so, use swi.p instead of sbi.p + ! the related stuff are defined in linker script + la $r0, _edata ! get the starting addr of bss + la $r2, _end ! get ending addr of bss + beq $r0, $r2, .L_call_main ! if no bss just do nothing + movi $r1, 0 ! should be cleared to 0 +.L_clear_bss: + sbi.p $r1, [$r0], 1 ! Set 0 to bss + bne $r0, $r2, .L_clear_bss ! Still bytes left to set + +!.L_stack_heap_check: +! la $r0, _end ! init heap_end +! s.w $r0, heap_end ! save it + + +!.L_init_argc_argv: +! ! argc/argv initialization if necessary; default implementation is in crt1.o +! la $r9, _arg_init ! load address of _arg_init? +! beqz $r9, .L4 ! has _arg_init? no, go check main() +! addi $sp, $sp, -512 ! allocate space for command line + arguments +! move $r6, $sp ! r6 = buffer addr of cmd line +! move $r0, $r6 ! r0 = buffer addr of cmd line +! syscall 6002 ! get cmd line +! move $r0, $r6 ! r0 = buffer addr of cmd line +! addi $r1, $r6, 256 ! r1 = argv +! jral $r9 ! init argc/argv +! addi $r1, $r6, 256 ! r1 = argv + +.L_call_main: + ! call main() if main() is provided + la $r15, main ! load address of main + jral $r15 ! call main + +.L_terminate_program: + syscall 0x1 ! use syscall 0x1 to terminate program + .size _start, .-_start + .end + +!! ------------------------------------------------------------------------ diff --git a/libgcc/config/nds32/initfini.c b/libgcc/config/nds32/initfini.c new file mode 100644 index 00000000000..7235148c5e3 --- /dev/null +++ b/libgcc/config/nds32/initfini.c @@ -0,0 +1,159 @@ +/* .init/.fini section handling + C++ global constructor/destructor + handling of Andes NDS32 cpu for GNU compiler. + This file is based on crtstuff.c, sol2-crti.asm, sol2-crtn.asm. + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +/* Declare a pointer to void function type. */ +typedef void (*func_ptr) (void); + +#ifdef CRT_BEGIN + +/* NOTE: In order to be able to support SVR4 shared libraries, we arrange + to have one set of symbols { __CTOR_LIST__, __DTOR_LIST__, __CTOR_END__, + __DTOR_END__ } per root executable and also one set of these symbols + per shared library. So in any given whole process image, we may have + multiple definitions of each of these symbols. In order to prevent + these definitions from conflicting with one another, and in order to + ensure that the proper lists are used for the initialization/finalization + of each individual shared library (respectively), we give these symbols + only internal (i.e. `static') linkage, and we also make it a point to + refer to only the __CTOR_END__ symbol in crtfini.o and the __DTOR_LIST__ + symbol in crtinit.o, where they are defined. */ + +static func_ptr __CTOR_LIST__[1] __attribute__ ((section (".ctors"))) + = { (func_ptr) (-1) }; + +static func_ptr __DTOR_LIST__[1] __attribute__ ((section (".dtors"))) + = { (func_ptr) (-1) }; + +/* Run all the global destructors on exit from the program. */ + +/* Some systems place the number of pointers in the first word of the + table. On SVR4 however, that word is -1. In all cases, the table is + null-terminated. On SVR4, we start from the beginning of the list and + invoke each per-compilation-unit destructor routine in order + until we find that null. + + Note that this function MUST be static. There will be one of these + functions in each root executable and one in each shared library, but + although they all have the same code, each one is unique in that it + refers to one particular associated `__DTOR_LIST__' which belongs to the + same particular root executable or shared library file. */ + +static void __do_global_dtors (void) +asm ("__do_global_dtors") __attribute__ ((section (".text"))); + +static void +__do_global_dtors (void) +{ + func_ptr *p; + for (p = __DTOR_LIST__ + 1; *p; p++) + (*p) (); +} + +/* .init section start. + This must appear at the start of the .init section. */ + +asm ("\n\ + .section .init\n\ + .global _init\n\ + .type _init, @function\n\ +_init:\n\ + ! 1. store $fp\n\ + ! 2. adjust $fp by $sp\n\ + ! 3. adjust $sp\n\ +"); + +/* .fini section start. + This must appear at the start of the .fini section. */ + +asm ("\n\ + .section .fini\n\ + .global _fini\n\ + .type _fini, @function\n\ +_fini:\n\ + ! 1. store $fp\n\ + ! 2. adjust $fp by $sp\n\ + ! 3. adjust $sp\n\ + ! 4. call __do_global_dtors\n\ + j __do_global_dtors\n\ +"); + +#endif /* CRT_BEGIN */ + +#ifdef CRT_END + +/* Define __dso_handle which would be needed for C++ library. + Since our elf-toolchain only builds programs with static link, + we can directly define 'void *__dso_handle = 0'. */ +void *__dso_handle = 0; + +/* Put a word containing zero at the end of each of our two lists of function + addresses. Note that the words defined here go into the .ctors and .dtors + sections of the crtend.o file, and since that file is always linked in + last, these words naturally end up at the very ends of the two lists + contained in these two sections. */ + +static func_ptr __CTOR_END__[1] __attribute__ ((section (".ctors"))) + = { (func_ptr) 0 }; + +static func_ptr __DTOR_END__[1] __attribute__ ((section (".dtors"))) + = { (func_ptr) 0 }; + +/* Run all global constructors for the program. + Note that they are run in reverse order. */ + +static void __do_global_ctors (void) +asm ("__do_global_ctors") __attribute__ ((section (".text"))); + +static void +__do_global_ctors (void) +{ + func_ptr *p; + for (p = __CTOR_END__ - 1; *p != (func_ptr) -1; p--) + (*p) (); +} + +/* .init section end. + This must live at the end of the .init section. */ + +asm ("\n\ + .section .init\n\ + ! 1. call __do_global_ctors\n\ + ! 2. adjust back $sp\n\ + ! 3. restore $fp\n\ + j __do_global_ctors\n\ +"); + +/* .fini section end. + This must live at the end of the .fini section. */ + +asm ("\n\ + .section .fini\n\ + ! 1. adjust back $sp\n\ + ! 2. restore $fp\n\ +"); + +#endif /* CRT_END */ diff --git a/libgcc/config/nds32/isr-library/adj_intr_lvl.inc b/libgcc/config/nds32/isr-library/adj_intr_lvl.inc new file mode 100644 index 00000000000..6c0c8aaebad --- /dev/null +++ b/libgcc/config/nds32/isr-library/adj_intr_lvl.inc @@ -0,0 +1,38 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro ADJ_INTR_LVL +#if defined(NDS32_NESTED) /* Nested handler. */ + mfsr $r3, $PSW + addi $r3, $r3, #-0x1 + mtsr $r3, $PSW +#elif defined(NDS32_NESTED_READY) /* Nested ready handler. */ + /* Save ipc and ipsw and lower INT level. */ + mfsr $r3, $PSW + addi $r3, $r3, #-0x2 + mtsr $r3, $PSW +#else /* Not nested handler. */ +#endif +.endm diff --git a/libgcc/config/nds32/isr-library/excp_isr.S b/libgcc/config/nds32/isr-library/excp_isr.S new file mode 100644 index 00000000000..a68a8ec3313 --- /dev/null +++ b/libgcc/config/nds32/isr-library/excp_isr.S @@ -0,0 +1,132 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#include "save_mac_regs.inc" +#include "save_fpu_regs.inc" +#include "save_fpu_regs_00.inc" +#include "save_fpu_regs_01.inc" +#include "save_fpu_regs_02.inc" +#include "save_fpu_regs_03.inc" +#include "save_all.inc" +#include "save_partial.inc" +#include "adj_intr_lvl.inc" +#include "restore_mac_regs.inc" +#include "restore_fpu_regs_00.inc" +#include "restore_fpu_regs_01.inc" +#include "restore_fpu_regs_02.inc" +#include "restore_fpu_regs_03.inc" +#include "restore_fpu_regs.inc" +#include "restore_all.inc" +#include "restore_partial.inc" + .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ + .align 1 +/* + First Level Handlers + 1. First Level Handlers are invokded in vector section via jump instruction + with specific names for different configurations. + 2. Naming Format: _nds32_e_SR_NT for exception handlers. + _nds32_i_SR_NT for interrupt handlers. + 2.1 All upper case letters are replaced with specific lower case letters encodings. + 2.2 SR: Saved Registers + sa: Save All regs (context) + ps: Partial Save (all caller-saved regs) + 2.3 NT: Nested Type + ns: nested + nn: not nested + nr: nested ready +*/ + +/* + This is original 16-byte vector size version. +*/ +#ifdef NDS32_SAVE_ALL_REGS +#if defined(NDS32_NESTED) + .globl _nds32_e_sa_ns + .type _nds32_e_sa_ns, @function +_nds32_e_sa_ns: +#elif defined(NDS32_NESTED_READY) + .globl _nds32_e_sa_nr + .type _nds32_e_sa_nr, @function +_nds32_e_sa_nr: +#else /* Not nested handler. */ + .globl _nds32_e_sa_nn + .type _nds32_e_sa_nn, @function +_nds32_e_sa_nn: +#endif /* endif for Nest Type */ +#else /* not NDS32_SAVE_ALL_REGS */ +#if defined(NDS32_NESTED) + .globl _nds32_e_ps_ns + .type _nds32_e_ps_ns, @function +_nds32_e_ps_ns: +#elif defined(NDS32_NESTED_READY) + .globl _nds32_e_ps_nr + .type _nds32_e_ps_nr, @function +_nds32_e_ps_nr: +#else /* Not nested handler. */ + .globl _nds32_e_ps_nn + .type _nds32_e_ps_nn, @function +_nds32_e_ps_nn: +#endif /* endif for Nest Type */ +#endif /* not NDS32_SAVE_ALL_REGS */ + +/* + This is 16-byte vector size version. + The vector id was restored into $r0 in vector by compiler. +*/ +#ifdef NDS32_SAVE_ALL_REGS + SAVE_ALL +#else + SAVE_PARTIAL +#endif + /* Prepare to call 2nd level handler. */ + la $r2, _nds32_jmptbl_00 + lw $r2, [$r2 + $r0 << #2] + ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */ + jral $r2 + /* Restore used registers. */ +#ifdef NDS32_SAVE_ALL_REGS + RESTORE_ALL +#else + RESTORE_PARTIAL +#endif + iret + +#ifdef NDS32_SAVE_ALL_REGS +#if defined(NDS32_NESTED) + .size _nds32_e_sa_ns, .-_nds32_e_sa_ns +#elif defined(NDS32_NESTED_READY) + .size _nds32_e_sa_nr, .-_nds32_e_sa_nr +#else /* Not nested handler. */ + .size _nds32_e_sa_nn, .-_nds32_e_sa_nn +#endif /* endif for Nest Type */ +#else /* not NDS32_SAVE_ALL_REGS */ +#if defined(NDS32_NESTED) + .size _nds32_e_ps_ns, .-_nds32_e_ps_ns +#elif defined(NDS32_NESTED_READY) + .size _nds32_e_ps_nr, .-_nds32_e_ps_nr +#else /* Not nested handler. */ + .size _nds32_e_ps_nn, .-_nds32_e_ps_nn +#endif /* endif for Nest Type */ +#endif /* not NDS32_SAVE_ALL_REGS */ diff --git a/libgcc/config/nds32/isr-library/excp_isr_4b.S b/libgcc/config/nds32/isr-library/excp_isr_4b.S new file mode 100644 index 00000000000..e37c2f62dd2 --- /dev/null +++ b/libgcc/config/nds32/isr-library/excp_isr_4b.S @@ -0,0 +1,133 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#include "save_mac_regs.inc" +#include "save_fpu_regs.inc" +#include "save_fpu_regs_00.inc" +#include "save_fpu_regs_01.inc" +#include "save_fpu_regs_02.inc" +#include "save_fpu_regs_03.inc" +#include "save_all.inc" +#include "save_partial.inc" +#include "adj_intr_lvl.inc" +#include "restore_mac_regs.inc" +#include "restore_fpu_regs_00.inc" +#include "restore_fpu_regs_01.inc" +#include "restore_fpu_regs_02.inc" +#include "restore_fpu_regs_03.inc" +#include "restore_fpu_regs.inc" +#include "restore_all.inc" +#include "restore_partial.inc" + .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ + .align 1 +/* + First Level Handlers + 1. First Level Handlers are invokded in vector section via jump instruction + with specific names for different configurations. + 2. Naming Format: _nds32_e_SR_NT for exception handlers. + _nds32_i_SR_NT for interrupt handlers. + 2.1 All upper case letters are replaced with specific lower case letters encodings. + 2.2 SR: Saved Registers + sa: Save All regs (context) + ps: Partial Save (all caller-saved regs) + 2.3 NT: Nested Type + ns: nested + nn: not nested + nr: nested ready +*/ + +/* + This is 4-byte vector size version. + The "_4b" postfix was added for 4-byte version symbol. +*/ +#ifdef NDS32_SAVE_ALL_REGS +#if defined(NDS32_NESTED) + .globl _nds32_e_sa_ns_4b + .type _nds32_e_sa_ns_4b, @function +_nds32_e_sa_ns_4b: +#elif defined(NDS32_NESTED_READY) + .globl _nds32_e_sa_nr_4b + .type _nds32_e_sa_nr_4b, @function +_nds32_e_sa_nr_4b: +#else /* Not nested handler. */ + .globl _nds32_e_sa_nn_4b + .type _nds32_e_sa_nn_4b, @function +_nds32_e_sa_nn_4b: +#endif /* endif for Nest Type */ +#else /* not NDS32_SAVE_ALL_REGS */ +#if defined(NDS32_NESTED) + .globl _nds32_e_ps_ns_4b + .type _nds32_e_ps_ns_4b, @function +_nds32_e_ps_ns_4b: +#elif defined(NDS32_NESTED_READY) + .globl _nds32_e_ps_nr_4b + .type _nds32_e_ps_nr_4b, @function +_nds32_e_ps_nr_4b: +#else /* Not nested handler. */ + .globl _nds32_e_ps_nn_4b + .type _nds32_e_ps_nn_4b, @function +_nds32_e_ps_nn_4b: +#endif /* endif for Nest Type */ +#endif /* not NDS32_SAVE_ALL_REGS */ + +/* + This is 4-byte vector size version. + The vector id was restored into $lp in vector by compiler. +*/ +#ifdef NDS32_SAVE_ALL_REGS + SAVE_ALL_4B +#else + SAVE_PARTIAL_4B +#endif + /* Prepare to call 2nd level handler. */ + la $r2, _nds32_jmptbl_00 + lw $r2, [$r2 + $r0 << #2] + ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */ + jral $r2 + /* Restore used registers. */ +#ifdef NDS32_SAVE_ALL_REGS + RESTORE_ALL +#else + RESTORE_PARTIAL +#endif + iret + +#ifdef NDS32_SAVE_ALL_REGS +#if defined(NDS32_NESTED) + .size _nds32_e_sa_ns_4b, .-_nds32_e_sa_ns_4b +#elif defined(NDS32_NESTED_READY) + .size _nds32_e_sa_nr_4b, .-_nds32_e_sa_nr_4b +#else /* Not nested handler. */ + .size _nds32_e_sa_nn_4b, .-_nds32_e_sa_nn_4b +#endif /* endif for Nest Type */ +#else /* not NDS32_SAVE_ALL_REGS */ +#if defined(NDS32_NESTED) + .size _nds32_e_ps_ns_4b, .-_nds32_e_ps_ns_4b +#elif defined(NDS32_NESTED_READY) + .size _nds32_e_ps_nr_4b, .-_nds32_e_ps_nr_4b +#else /* Not nested handler. */ + .size _nds32_e_ps_nn_4b, .-_nds32_e_ps_nn_4b +#endif /* endif for Nest Type */ +#endif /* not NDS32_SAVE_ALL_REGS */ diff --git a/libgcc/config/nds32/isr-library/intr_isr.S b/libgcc/config/nds32/isr-library/intr_isr.S new file mode 100644 index 00000000000..4d9537474b9 --- /dev/null +++ b/libgcc/config/nds32/isr-library/intr_isr.S @@ -0,0 +1,132 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#include "save_mac_regs.inc" +#include "save_fpu_regs.inc" +#include "save_fpu_regs_00.inc" +#include "save_fpu_regs_01.inc" +#include "save_fpu_regs_02.inc" +#include "save_fpu_regs_03.inc" +#include "save_all.inc" +#include "save_partial.inc" +#include "adj_intr_lvl.inc" +#include "restore_mac_regs.inc" +#include "restore_fpu_regs_00.inc" +#include "restore_fpu_regs_01.inc" +#include "restore_fpu_regs_02.inc" +#include "restore_fpu_regs_03.inc" +#include "restore_fpu_regs.inc" +#include "restore_all.inc" +#include "restore_partial.inc" + .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ + .align 1 +/* + First Level Handlers + 1. First Level Handlers are invokded in vector section via jump instruction + with specific names for different configurations. + 2. Naming Format: _nds32_e_SR_NT for exception handlers. + _nds32_i_SR_NT for interrupt handlers. + 2.1 All upper case letters are replaced with specific lower case letters encodings. + 2.2 SR: Saved Registers + sa: Save All regs (context) + ps: Partial Save (all caller-saved regs) + 2.3 NT: Nested Type + ns: nested + nn: not nested + nr: nested ready +*/ + +/* + This is original 16-byte vector size version. +*/ +#ifdef NDS32_SAVE_ALL_REGS +#if defined(NDS32_NESTED) + .globl _nds32_i_sa_ns + .type _nds32_i_sa_ns, @function +_nds32_i_sa_ns: +#elif defined(NDS32_NESTED_READY) + .globl _nds32_i_sa_nr + .type _nds32_i_sa_nr, @function +_nds32_i_sa_nr: +#else /* Not nested handler. */ + .globl _nds32_i_sa_nn + .type _nds32_i_sa_nn, @function +_nds32_i_sa_nn: +#endif /* endif for Nest Type */ +#else /* not NDS32_SAVE_ALL_REGS */ +#if defined(NDS32_NESTED) + .globl _nds32_i_ps_ns + .type _nds32_i_ps_ns, @function +_nds32_i_ps_ns: +#elif defined(NDS32_NESTED_READY) + .globl _nds32_i_ps_nr + .type _nds32_i_ps_nr, @function +_nds32_i_ps_nr: +#else /* Not nested handler. */ + .globl _nds32_i_ps_nn + .type _nds32_i_ps_nn, @function +_nds32_i_ps_nn: +#endif /* endif for Nest Type */ +#endif /* not NDS32_SAVE_ALL_REGS */ + +/* + This is 16-byte vector size version. + The vector id was restored into $r0 in vector by compiler. +*/ +#ifdef NDS32_SAVE_ALL_REGS + SAVE_ALL +#else + SAVE_PARTIAL +#endif + /* Prepare to call 2nd level handler. */ + la $r2, _nds32_jmptbl_09 /* For zero-based vcetor id. */ + lw $r2, [$r2 + $r0 << #2] + ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */ + jral $r2 + /* Restore used registers. */ +#ifdef NDS32_SAVE_ALL_REGS + RESTORE_ALL +#else + RESTORE_PARTIAL +#endif + iret + +#ifdef NDS32_SAVE_ALL_REGS +#if defined(NDS32_NESTED) + .size _nds32_i_sa_ns, .-_nds32_i_sa_ns +#elif defined(NDS32_NESTED_READY) + .size _nds32_i_sa_nr, .-_nds32_i_sa_nr +#else /* Not nested handler. */ + .size _nds32_i_sa_nn, .-_nds32_i_sa_nn +#endif /* endif for Nest Type */ +#else /* not NDS32_SAVE_ALL_REGS */ +#if defined(NDS32_NESTED) + .size _nds32_i_ps_ns, .-_nds32_i_ps_ns +#elif defined(NDS32_NESTED_READY) + .size _nds32_i_ps_nr, .-_nds32_i_ps_nr +#else /* Not nested handler. */ + .size _nds32_i_ps_nn, .-_nds32_i_ps_nn +#endif /* endif for Nest Type */ +#endif /* not NDS32_SAVE_ALL_REGS */ diff --git a/libgcc/config/nds32/isr-library/intr_isr_4b.S b/libgcc/config/nds32/isr-library/intr_isr_4b.S new file mode 100644 index 00000000000..21e60e72ed7 --- /dev/null +++ b/libgcc/config/nds32/isr-library/intr_isr_4b.S @@ -0,0 +1,134 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +#include "save_mac_regs.inc" +#include "save_fpu_regs.inc" +#include "save_fpu_regs_00.inc" +#include "save_fpu_regs_01.inc" +#include "save_fpu_regs_02.inc" +#include "save_fpu_regs_03.inc" +#include "save_all.inc" +#include "save_partial.inc" +#include "adj_intr_lvl.inc" +#include "restore_mac_regs.inc" +#include "restore_fpu_regs_00.inc" +#include "restore_fpu_regs_01.inc" +#include "restore_fpu_regs_02.inc" +#include "restore_fpu_regs_03.inc" +#include "restore_fpu_regs.inc" +#include "restore_all.inc" +#include "restore_partial.inc" + .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ + .align 1 +/* + First Level Handlers + 1. First Level Handlers are invokded in vector section via jump instruction + with specific names for different configurations. + 2. Naming Format: _nds32_e_SR_NT for exception handlers. + _nds32_i_SR_NT for interrupt handlers. + 2.1 All upper case letters are replaced with specific lower case letters encodings. + 2.2 SR: Saved Registers + sa: Save All regs (context) + ps: Partial Save (all caller-saved regs) + 2.3 NT: Nested Type + ns: nested + nn: not nested + nr: nested ready +*/ + +/* + This is 4-byte vector size version. + The "_4b" postfix was added for 4-byte version symbol. +*/ +#ifdef NDS32_SAVE_ALL_REGS +#if defined(NDS32_NESTED) + .globl _nds32_i_sa_ns_4b + .type _nds32_i_sa_ns_4b, @function +_nds32_i_sa_ns_4b: +#elif defined(NDS32_NESTED_READY) + .globl _nds32_i_sa_nr_4b + .type _nds32_i_sa_nr_4b, @function +_nds32_i_sa_nr_4b: +#else /* Not nested handler. */ + .globl _nds32_i_sa_nn_4b + .type _nds32_i_sa_nn_4b, @function +_nds32_i_sa_nn_4b: +#endif /* endif for Nest Type */ +#else /* not NDS32_SAVE_ALL_REGS */ +#if defined(NDS32_NESTED) + .globl _nds32_i_ps_ns_4b + .type _nds32_i_ps_ns_4b, @function +_nds32_i_ps_ns_4b: +#elif defined(NDS32_NESTED_READY) + .globl _nds32_i_ps_nr_4b + .type _nds32_i_ps_nr_4b, @function +_nds32_i_ps_nr_4b: +#else /* Not nested handler. */ + .globl _nds32_i_ps_nn_4b + .type _nds32_i_ps_nn_4b, @function +_nds32_i_ps_nn_4b: +#endif /* endif for Nest Type */ +#endif /* not NDS32_SAVE_ALL_REGS */ + +/* + This is 4-byte vector size version. + The vector id was restored into $lp in vector by compiler. +*/ +#ifdef NDS32_SAVE_ALL_REGS + SAVE_ALL_4B +#else + SAVE_PARTIAL_4B +#endif + /* Prepare to call 2nd level handler. */ + la $r2, _nds32_jmptbl_00 + lw $r2, [$r2 + $r0 << #2] + addi $r0, $r0, #-9 /* Make interrput vector id zero-based. */ + ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */ + jral $r2 + /* Restore used registers. */ +#ifdef NDS32_SAVE_ALL_REGS + RESTORE_ALL +#else + RESTORE_PARTIAL +#endif + iret + +#ifdef NDS32_SAVE_ALL_REGS +#if defined(NDS32_NESTED) + .size _nds32_i_sa_ns_4b, .-_nds32_i_sa_ns_4b +#elif defined(NDS32_NESTED_READY) + .size _nds32_i_sa_nr_4b, .-_nds32_i_sa_nr_4b +#else /* Not nested handler. */ + .size _nds32_i_sa_nn_4b, .-_nds32_i_sa_nn_4b +#endif /* endif for Nest Type */ +#else /* not NDS32_SAVE_ALL_REGS */ +#if defined(NDS32_NESTED) + .size _nds32_i_ps_ns_4b, .-_nds32_i_ps_ns_4b +#elif defined(NDS32_NESTED_READY) + .size _nds32_i_ps_nr_4b, .-_nds32_i_ps_nr_4b +#else /* Not nested handler. */ + .size _nds32_i_ps_nn_4b, .-_nds32_i_ps_nn_4b +#endif /* endif for Nest Type */ +#endif /* not NDS32_SAVE_ALL_REGS */ diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid00.S b/libgcc/config/nds32/isr-library/jmptbl_vid00.S new file mode 100644 index 00000000000..f0ed85a8275 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid00.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.00, "a" + .align 2 + .weak _nds32_jmptbl_00 + .type _nds32_jmptbl_00, @object +_nds32_jmptbl_00: + .word 0 + .size _nds32_jmptbl_00, .-_nds32_jmptbl_00 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid01.S b/libgcc/config/nds32/isr-library/jmptbl_vid01.S new file mode 100644 index 00000000000..4c6b9c1d73d --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid01.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.01, "a" + .align 2 + .weak _nds32_jmptbl_01 + .type _nds32_jmptbl_01, @object +_nds32_jmptbl_01: + .word 0 + .size _nds32_jmptbl_01, .-_nds32_jmptbl_01 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid02.S b/libgcc/config/nds32/isr-library/jmptbl_vid02.S new file mode 100644 index 00000000000..83ba980ad36 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid02.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.02, "a" + .align 2 + .weak _nds32_jmptbl_02 + .type _nds32_jmptbl_02, @object +_nds32_jmptbl_02: + .word 0 + .size _nds32_jmptbl_02, .-_nds32_jmptbl_02 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid03.S b/libgcc/config/nds32/isr-library/jmptbl_vid03.S new file mode 100644 index 00000000000..47f11a4b86a --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid03.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.03, "a" + .align 2 + .weak _nds32_jmptbl_03 + .type _nds32_jmptbl_03, @object +_nds32_jmptbl_03: + .word 0 + .size _nds32_jmptbl_03, .-_nds32_jmptbl_03 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid04.S b/libgcc/config/nds32/isr-library/jmptbl_vid04.S new file mode 100644 index 00000000000..e3e7fb8c1da --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid04.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.04, "a" + .align 2 + .weak _nds32_jmptbl_04 + .type _nds32_jmptbl_04, @object +_nds32_jmptbl_04: + .word 0 + .size _nds32_jmptbl_04, .-_nds32_jmptbl_04 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid05.S b/libgcc/config/nds32/isr-library/jmptbl_vid05.S new file mode 100644 index 00000000000..32fa7eafd7b --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid05.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.05, "a" + .align 2 + .weak _nds32_jmptbl_05 + .type _nds32_jmptbl_05, @object +_nds32_jmptbl_05: + .word 0 + .size _nds32_jmptbl_05, .-_nds32_jmptbl_05 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid06.S b/libgcc/config/nds32/isr-library/jmptbl_vid06.S new file mode 100644 index 00000000000..df2d83acaa3 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid06.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.06, "a" + .align 2 + .weak _nds32_jmptbl_06 + .type _nds32_jmptbl_06, @object +_nds32_jmptbl_06: + .word 0 + .size _nds32_jmptbl_06, .-_nds32_jmptbl_06 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid07.S b/libgcc/config/nds32/isr-library/jmptbl_vid07.S new file mode 100644 index 00000000000..0070f7f5ae8 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid07.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.07, "a" + .align 2 + .weak _nds32_jmptbl_07 + .type _nds32_jmptbl_07, @object +_nds32_jmptbl_07: + .word 0 + .size _nds32_jmptbl_07, .-_nds32_jmptbl_07 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid08.S b/libgcc/config/nds32/isr-library/jmptbl_vid08.S new file mode 100644 index 00000000000..0b19e60b9df --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid08.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.08, "a" + .align 2 + .weak _nds32_jmptbl_08 + .type _nds32_jmptbl_08, @object +_nds32_jmptbl_08: + .word 0 + .size _nds32_jmptbl_08, .-_nds32_jmptbl_08 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid09.S b/libgcc/config/nds32/isr-library/jmptbl_vid09.S new file mode 100644 index 00000000000..b0e216b7520 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid09.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.09, "a" + .align 2 + .weak _nds32_jmptbl_09 + .type _nds32_jmptbl_09, @object +_nds32_jmptbl_09: + .word 0 + .size _nds32_jmptbl_09, .-_nds32_jmptbl_09 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid10.S b/libgcc/config/nds32/isr-library/jmptbl_vid10.S new file mode 100644 index 00000000000..bd378ed5f7a --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid10.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.10, "a" + .align 2 + .weak _nds32_jmptbl_10 + .type _nds32_jmptbl_10, @object +_nds32_jmptbl_10: + .word 0 + .size _nds32_jmptbl_10, .-_nds32_jmptbl_10 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid11.S b/libgcc/config/nds32/isr-library/jmptbl_vid11.S new file mode 100644 index 00000000000..9648ef347f0 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid11.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.11, "a" + .align 2 + .weak _nds32_jmptbl_11 + .type _nds32_jmptbl_11, @object +_nds32_jmptbl_11: + .word 0 + .size _nds32_jmptbl_11, .-_nds32_jmptbl_11 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid12.S b/libgcc/config/nds32/isr-library/jmptbl_vid12.S new file mode 100644 index 00000000000..0ab14e2249c --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid12.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.12, "a" + .align 2 + .weak _nds32_jmptbl_12 + .type _nds32_jmptbl_12, @object +_nds32_jmptbl_12: + .word 0 + .size _nds32_jmptbl_12, .-_nds32_jmptbl_12 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid13.S b/libgcc/config/nds32/isr-library/jmptbl_vid13.S new file mode 100644 index 00000000000..31664689df4 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid13.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.13, "a" + .align 2 + .weak _nds32_jmptbl_13 + .type _nds32_jmptbl_13, @object +_nds32_jmptbl_13: + .word 0 + .size _nds32_jmptbl_13, .-_nds32_jmptbl_13 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid14.S b/libgcc/config/nds32/isr-library/jmptbl_vid14.S new file mode 100644 index 00000000000..cb8d129d81f --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid14.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.14, "a" + .align 2 + .weak _nds32_jmptbl_14 + .type _nds32_jmptbl_14, @object +_nds32_jmptbl_14: + .word 0 + .size _nds32_jmptbl_14, .-_nds32_jmptbl_14 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid15.S b/libgcc/config/nds32/isr-library/jmptbl_vid15.S new file mode 100644 index 00000000000..bac9bc98407 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid15.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.15, "a" + .align 2 + .weak _nds32_jmptbl_15 + .type _nds32_jmptbl_15, @object +_nds32_jmptbl_15: + .word 0 + .size _nds32_jmptbl_15, .-_nds32_jmptbl_15 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid16.S b/libgcc/config/nds32/isr-library/jmptbl_vid16.S new file mode 100644 index 00000000000..9066f81cfde --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid16.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.16, "a" + .align 2 + .weak _nds32_jmptbl_16 + .type _nds32_jmptbl_16, @object +_nds32_jmptbl_16: + .word 0 + .size _nds32_jmptbl_16, .-_nds32_jmptbl_16 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid17.S b/libgcc/config/nds32/isr-library/jmptbl_vid17.S new file mode 100644 index 00000000000..60a8ba9ac4d --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid17.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.17, "a" + .align 2 + .weak _nds32_jmptbl_17 + .type _nds32_jmptbl_17, @object +_nds32_jmptbl_17: + .word 0 + .size _nds32_jmptbl_17, .-_nds32_jmptbl_17 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid18.S b/libgcc/config/nds32/isr-library/jmptbl_vid18.S new file mode 100644 index 00000000000..a926fecc0b6 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid18.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.18, "a" + .align 2 + .weak _nds32_jmptbl_18 + .type _nds32_jmptbl_18, @object +_nds32_jmptbl_18: + .word 0 + .size _nds32_jmptbl_18, .-_nds32_jmptbl_18 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid19.S b/libgcc/config/nds32/isr-library/jmptbl_vid19.S new file mode 100644 index 00000000000..064ace009bb --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid19.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.19, "a" + .align 2 + .weak _nds32_jmptbl_19 + .type _nds32_jmptbl_19, @object +_nds32_jmptbl_19: + .word 0 + .size _nds32_jmptbl_19, .-_nds32_jmptbl_19 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid20.S b/libgcc/config/nds32/isr-library/jmptbl_vid20.S new file mode 100644 index 00000000000..e75bc71fbb6 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid20.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.20, "a" + .align 2 + .weak _nds32_jmptbl_20 + .type _nds32_jmptbl_20, @object +_nds32_jmptbl_20: + .word 0 + .size _nds32_jmptbl_20, .-_nds32_jmptbl_20 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid21.S b/libgcc/config/nds32/isr-library/jmptbl_vid21.S new file mode 100644 index 00000000000..0c3d2b871c7 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid21.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.21, "a" + .align 2 + .weak _nds32_jmptbl_21 + .type _nds32_jmptbl_21, @object +_nds32_jmptbl_21: + .word 0 + .size _nds32_jmptbl_21, .-_nds32_jmptbl_21 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid22.S b/libgcc/config/nds32/isr-library/jmptbl_vid22.S new file mode 100644 index 00000000000..415bf9f75e8 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid22.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.22, "a" + .align 2 + .weak _nds32_jmptbl_22 + .type _nds32_jmptbl_22, @object +_nds32_jmptbl_22: + .word 0 + .size _nds32_jmptbl_22, .-_nds32_jmptbl_22 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid23.S b/libgcc/config/nds32/isr-library/jmptbl_vid23.S new file mode 100644 index 00000000000..1efe31099c2 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid23.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.23, "a" + .align 2 + .weak _nds32_jmptbl_23 + .type _nds32_jmptbl_23, @object +_nds32_jmptbl_23: + .word 0 + .size _nds32_jmptbl_23, .-_nds32_jmptbl_23 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid24.S b/libgcc/config/nds32/isr-library/jmptbl_vid24.S new file mode 100644 index 00000000000..bb27eaa0812 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid24.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.24, "a" + .align 2 + .weak _nds32_jmptbl_24 + .type _nds32_jmptbl_24, @object +_nds32_jmptbl_24: + .word 0 + .size _nds32_jmptbl_24, .-_nds32_jmptbl_24 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid25.S b/libgcc/config/nds32/isr-library/jmptbl_vid25.S new file mode 100644 index 00000000000..ca64f8c8bad --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid25.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.25, "a" + .align 2 + .weak _nds32_jmptbl_25 + .type _nds32_jmptbl_25, @object +_nds32_jmptbl_25: + .word 0 + .size _nds32_jmptbl_25, .-_nds32_jmptbl_25 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid26.S b/libgcc/config/nds32/isr-library/jmptbl_vid26.S new file mode 100644 index 00000000000..95feab094fd --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid26.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.26, "a" + .align 2 + .weak _nds32_jmptbl_26 + .type _nds32_jmptbl_26, @object +_nds32_jmptbl_26: + .word 0 + .size _nds32_jmptbl_26, .-_nds32_jmptbl_26 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid27.S b/libgcc/config/nds32/isr-library/jmptbl_vid27.S new file mode 100644 index 00000000000..2bb9eabe6a4 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid27.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.27, "a" + .align 2 + .weak _nds32_jmptbl_27 + .type _nds32_jmptbl_27, @object +_nds32_jmptbl_27: + .word 0 + .size _nds32_jmptbl_27, .-_nds32_jmptbl_27 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid28.S b/libgcc/config/nds32/isr-library/jmptbl_vid28.S new file mode 100644 index 00000000000..57772ba494d --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid28.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.28, "a" + .align 2 + .weak _nds32_jmptbl_28 + .type _nds32_jmptbl_28, @object +_nds32_jmptbl_28: + .word 0 + .size _nds32_jmptbl_28, .-_nds32_jmptbl_28 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid29.S b/libgcc/config/nds32/isr-library/jmptbl_vid29.S new file mode 100644 index 00000000000..c69d7398eb1 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid29.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.29, "a" + .align 2 + .weak _nds32_jmptbl_29 + .type _nds32_jmptbl_29, @object +_nds32_jmptbl_29: + .word 0 + .size _nds32_jmptbl_29, .-_nds32_jmptbl_29 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid30.S b/libgcc/config/nds32/isr-library/jmptbl_vid30.S new file mode 100644 index 00000000000..f739c5821d7 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid30.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.30, "a" + .align 2 + .weak _nds32_jmptbl_30 + .type _nds32_jmptbl_30, @object +_nds32_jmptbl_30: + .word 0 + .size _nds32_jmptbl_30, .-_nds32_jmptbl_30 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid31.S b/libgcc/config/nds32/isr-library/jmptbl_vid31.S new file mode 100644 index 00000000000..4997f4e9cc8 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid31.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.31, "a" + .align 2 + .weak _nds32_jmptbl_31 + .type _nds32_jmptbl_31, @object +_nds32_jmptbl_31: + .word 0 + .size _nds32_jmptbl_31, .-_nds32_jmptbl_31 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid32.S b/libgcc/config/nds32/isr-library/jmptbl_vid32.S new file mode 100644 index 00000000000..1cde3fab097 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid32.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.32, "a" + .align 2 + .weak _nds32_jmptbl_32 + .type _nds32_jmptbl_32, @object +_nds32_jmptbl_32: + .word 0 + .size _nds32_jmptbl_32, .-_nds32_jmptbl_32 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid33.S b/libgcc/config/nds32/isr-library/jmptbl_vid33.S new file mode 100644 index 00000000000..84edda36751 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid33.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.33, "a" + .align 2 + .weak _nds32_jmptbl_33 + .type _nds32_jmptbl_33, @object +_nds32_jmptbl_33: + .word 0 + .size _nds32_jmptbl_33, .-_nds32_jmptbl_33 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid34.S b/libgcc/config/nds32/isr-library/jmptbl_vid34.S new file mode 100644 index 00000000000..82dc9f1dc24 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid34.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.34, "a" + .align 2 + .weak _nds32_jmptbl_34 + .type _nds32_jmptbl_34, @object +_nds32_jmptbl_34: + .word 0 + .size _nds32_jmptbl_34, .-_nds32_jmptbl_34 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid35.S b/libgcc/config/nds32/isr-library/jmptbl_vid35.S new file mode 100644 index 00000000000..c99fc6cd996 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid35.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.35, "a" + .align 2 + .weak _nds32_jmptbl_35 + .type _nds32_jmptbl_35, @object +_nds32_jmptbl_35: + .word 0 + .size _nds32_jmptbl_35, .-_nds32_jmptbl_35 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid36.S b/libgcc/config/nds32/isr-library/jmptbl_vid36.S new file mode 100644 index 00000000000..9154d713c40 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid36.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.36, "a" + .align 2 + .weak _nds32_jmptbl_36 + .type _nds32_jmptbl_36, @object +_nds32_jmptbl_36: + .word 0 + .size _nds32_jmptbl_36, .-_nds32_jmptbl_36 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid37.S b/libgcc/config/nds32/isr-library/jmptbl_vid37.S new file mode 100644 index 00000000000..1f3acfd2c49 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid37.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.37, "a" + .align 2 + .weak _nds32_jmptbl_37 + .type _nds32_jmptbl_37, @object +_nds32_jmptbl_37: + .word 0 + .size _nds32_jmptbl_37, .-_nds32_jmptbl_37 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid38.S b/libgcc/config/nds32/isr-library/jmptbl_vid38.S new file mode 100644 index 00000000000..0ff99b02235 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid38.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.38, "a" + .align 2 + .weak _nds32_jmptbl_38 + .type _nds32_jmptbl_38, @object +_nds32_jmptbl_38: + .word 0 + .size _nds32_jmptbl_38, .-_nds32_jmptbl_38 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid39.S b/libgcc/config/nds32/isr-library/jmptbl_vid39.S new file mode 100644 index 00000000000..3fe74367c46 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid39.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.39, "a" + .align 2 + .weak _nds32_jmptbl_39 + .type _nds32_jmptbl_39, @object +_nds32_jmptbl_39: + .word 0 + .size _nds32_jmptbl_39, .-_nds32_jmptbl_39 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid40.S b/libgcc/config/nds32/isr-library/jmptbl_vid40.S new file mode 100644 index 00000000000..fcd05dc627d --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid40.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.40, "a" + .align 2 + .weak _nds32_jmptbl_40 + .type _nds32_jmptbl_40, @object +_nds32_jmptbl_40: + .word 0 + .size _nds32_jmptbl_40, .-_nds32_jmptbl_40 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid41.S b/libgcc/config/nds32/isr-library/jmptbl_vid41.S new file mode 100644 index 00000000000..0ec546a7f5b --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid41.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.41, "a" + .align 2 + .weak _nds32_jmptbl_41 + .type _nds32_jmptbl_41, @object +_nds32_jmptbl_41: + .word 0 + .size _nds32_jmptbl_41, .-_nds32_jmptbl_41 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid42.S b/libgcc/config/nds32/isr-library/jmptbl_vid42.S new file mode 100644 index 00000000000..761ef769089 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid42.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.42, "a" + .align 2 + .weak _nds32_jmptbl_42 + .type _nds32_jmptbl_42, @object +_nds32_jmptbl_42: + .word 0 + .size _nds32_jmptbl_42, .-_nds32_jmptbl_42 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid43.S b/libgcc/config/nds32/isr-library/jmptbl_vid43.S new file mode 100644 index 00000000000..0b2fc0eeedd --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid43.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.43, "a" + .align 2 + .weak _nds32_jmptbl_43 + .type _nds32_jmptbl_43, @object +_nds32_jmptbl_43: + .word 0 + .size _nds32_jmptbl_43, .-_nds32_jmptbl_43 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid44.S b/libgcc/config/nds32/isr-library/jmptbl_vid44.S new file mode 100644 index 00000000000..0fc7e7e1662 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid44.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.44, "a" + .align 2 + .weak _nds32_jmptbl_44 + .type _nds32_jmptbl_44, @object +_nds32_jmptbl_44: + .word 0 + .size _nds32_jmptbl_44, .-_nds32_jmptbl_44 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid45.S b/libgcc/config/nds32/isr-library/jmptbl_vid45.S new file mode 100644 index 00000000000..725d14483bf --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid45.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.45, "a" + .align 2 + .weak _nds32_jmptbl_45 + .type _nds32_jmptbl_45, @object +_nds32_jmptbl_45: + .word 0 + .size _nds32_jmptbl_45, .-_nds32_jmptbl_45 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid46.S b/libgcc/config/nds32/isr-library/jmptbl_vid46.S new file mode 100644 index 00000000000..6b4253ada9d --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid46.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.46, "a" + .align 2 + .weak _nds32_jmptbl_46 + .type _nds32_jmptbl_46, @object +_nds32_jmptbl_46: + .word 0 + .size _nds32_jmptbl_46, .-_nds32_jmptbl_46 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid47.S b/libgcc/config/nds32/isr-library/jmptbl_vid47.S new file mode 100644 index 00000000000..460e8509bcc --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid47.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.47, "a" + .align 2 + .weak _nds32_jmptbl_47 + .type _nds32_jmptbl_47, @object +_nds32_jmptbl_47: + .word 0 + .size _nds32_jmptbl_47, .-_nds32_jmptbl_47 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid48.S b/libgcc/config/nds32/isr-library/jmptbl_vid48.S new file mode 100644 index 00000000000..d481e50e290 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid48.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.48, "a" + .align 2 + .weak _nds32_jmptbl_48 + .type _nds32_jmptbl_48, @object +_nds32_jmptbl_48: + .word 0 + .size _nds32_jmptbl_48, .-_nds32_jmptbl_48 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid49.S b/libgcc/config/nds32/isr-library/jmptbl_vid49.S new file mode 100644 index 00000000000..4cea0b7e434 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid49.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.49, "a" + .align 2 + .weak _nds32_jmptbl_49 + .type _nds32_jmptbl_49, @object +_nds32_jmptbl_49: + .word 0 + .size _nds32_jmptbl_49, .-_nds32_jmptbl_49 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid50.S b/libgcc/config/nds32/isr-library/jmptbl_vid50.S new file mode 100644 index 00000000000..dd15a384570 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid50.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.50, "a" + .align 2 + .weak _nds32_jmptbl_50 + .type _nds32_jmptbl_50, @object +_nds32_jmptbl_50: + .word 0 + .size _nds32_jmptbl_50, .-_nds32_jmptbl_50 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid51.S b/libgcc/config/nds32/isr-library/jmptbl_vid51.S new file mode 100644 index 00000000000..02cf8dfb2f5 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid51.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.51, "a" + .align 2 + .weak _nds32_jmptbl_51 + .type _nds32_jmptbl_51, @object +_nds32_jmptbl_51: + .word 0 + .size _nds32_jmptbl_51, .-_nds32_jmptbl_51 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid52.S b/libgcc/config/nds32/isr-library/jmptbl_vid52.S new file mode 100644 index 00000000000..5bc784611dd --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid52.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.52, "a" + .align 2 + .weak _nds32_jmptbl_52 + .type _nds32_jmptbl_52, @object +_nds32_jmptbl_52: + .word 0 + .size _nds32_jmptbl_52, .-_nds32_jmptbl_52 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid53.S b/libgcc/config/nds32/isr-library/jmptbl_vid53.S new file mode 100644 index 00000000000..94f0dabcb44 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid53.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.53, "a" + .align 2 + .weak _nds32_jmptbl_53 + .type _nds32_jmptbl_53, @object +_nds32_jmptbl_53: + .word 0 + .size _nds32_jmptbl_53, .-_nds32_jmptbl_53 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid54.S b/libgcc/config/nds32/isr-library/jmptbl_vid54.S new file mode 100644 index 00000000000..f13d6895bed --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid54.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.54, "a" + .align 2 + .weak _nds32_jmptbl_54 + .type _nds32_jmptbl_54, @object +_nds32_jmptbl_54: + .word 0 + .size _nds32_jmptbl_54, .-_nds32_jmptbl_54 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid55.S b/libgcc/config/nds32/isr-library/jmptbl_vid55.S new file mode 100644 index 00000000000..521af640669 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid55.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.55, "a" + .align 2 + .weak _nds32_jmptbl_55 + .type _nds32_jmptbl_55, @object +_nds32_jmptbl_55: + .word 0 + .size _nds32_jmptbl_55, .-_nds32_jmptbl_55 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid56.S b/libgcc/config/nds32/isr-library/jmptbl_vid56.S new file mode 100644 index 00000000000..2c01ed2c341 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid56.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.56, "a" + .align 2 + .weak _nds32_jmptbl_56 + .type _nds32_jmptbl_56, @object +_nds32_jmptbl_56: + .word 0 + .size _nds32_jmptbl_56, .-_nds32_jmptbl_56 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid57.S b/libgcc/config/nds32/isr-library/jmptbl_vid57.S new file mode 100644 index 00000000000..58d4c1d72b0 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid57.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.57, "a" + .align 2 + .weak _nds32_jmptbl_57 + .type _nds32_jmptbl_57, @object +_nds32_jmptbl_57: + .word 0 + .size _nds32_jmptbl_57, .-_nds32_jmptbl_57 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid58.S b/libgcc/config/nds32/isr-library/jmptbl_vid58.S new file mode 100644 index 00000000000..ceb7711c3cf --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid58.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.58, "a" + .align 2 + .weak _nds32_jmptbl_58 + .type _nds32_jmptbl_58, @object +_nds32_jmptbl_58: + .word 0 + .size _nds32_jmptbl_58, .-_nds32_jmptbl_58 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid59.S b/libgcc/config/nds32/isr-library/jmptbl_vid59.S new file mode 100644 index 00000000000..527a1f52be6 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid59.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.59, "a" + .align 2 + .weak _nds32_jmptbl_59 + .type _nds32_jmptbl_59, @object +_nds32_jmptbl_59: + .word 0 + .size _nds32_jmptbl_59, .-_nds32_jmptbl_59 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid60.S b/libgcc/config/nds32/isr-library/jmptbl_vid60.S new file mode 100644 index 00000000000..eedd8b88807 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid60.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.60, "a" + .align 2 + .weak _nds32_jmptbl_60 + .type _nds32_jmptbl_60, @object +_nds32_jmptbl_60: + .word 0 + .size _nds32_jmptbl_60, .-_nds32_jmptbl_60 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid61.S b/libgcc/config/nds32/isr-library/jmptbl_vid61.S new file mode 100644 index 00000000000..e9813128491 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid61.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.61, "a" + .align 2 + .weak _nds32_jmptbl_61 + .type _nds32_jmptbl_61, @object +_nds32_jmptbl_61: + .word 0 + .size _nds32_jmptbl_61, .-_nds32_jmptbl_61 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid62.S b/libgcc/config/nds32/isr-library/jmptbl_vid62.S new file mode 100644 index 00000000000..ef66f2b7e07 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid62.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.62, "a" + .align 2 + .weak _nds32_jmptbl_62 + .type _nds32_jmptbl_62, @object +_nds32_jmptbl_62: + .word 0 + .size _nds32_jmptbl_62, .-_nds32_jmptbl_62 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid63.S b/libgcc/config/nds32/isr-library/jmptbl_vid63.S new file mode 100644 index 00000000000..95e38ba5eb1 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid63.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.63, "a" + .align 2 + .weak _nds32_jmptbl_63 + .type _nds32_jmptbl_63, @object +_nds32_jmptbl_63: + .word 0 + .size _nds32_jmptbl_63, .-_nds32_jmptbl_63 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid64.S b/libgcc/config/nds32/isr-library/jmptbl_vid64.S new file mode 100644 index 00000000000..f27b6df9439 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid64.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.64, "a" + .align 2 + .weak _nds32_jmptbl_64 + .type _nds32_jmptbl_64, @object +_nds32_jmptbl_64: + .word 0 + .size _nds32_jmptbl_64, .-_nds32_jmptbl_64 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid65.S b/libgcc/config/nds32/isr-library/jmptbl_vid65.S new file mode 100644 index 00000000000..69d83c67467 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid65.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.65, "a" + .align 2 + .weak _nds32_jmptbl_65 + .type _nds32_jmptbl_65, @object +_nds32_jmptbl_65: + .word 0 + .size _nds32_jmptbl_65, .-_nds32_jmptbl_65 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid66.S b/libgcc/config/nds32/isr-library/jmptbl_vid66.S new file mode 100644 index 00000000000..3474d05a5d9 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid66.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.66, "a" + .align 2 + .weak _nds32_jmptbl_66 + .type _nds32_jmptbl_66, @object +_nds32_jmptbl_66: + .word 0 + .size _nds32_jmptbl_66, .-_nds32_jmptbl_66 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid67.S b/libgcc/config/nds32/isr-library/jmptbl_vid67.S new file mode 100644 index 00000000000..8bbb5163f69 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid67.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.67, "a" + .align 2 + .weak _nds32_jmptbl_67 + .type _nds32_jmptbl_67, @object +_nds32_jmptbl_67: + .word 0 + .size _nds32_jmptbl_67, .-_nds32_jmptbl_67 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid68.S b/libgcc/config/nds32/isr-library/jmptbl_vid68.S new file mode 100644 index 00000000000..fc875055818 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid68.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.68, "a" + .align 2 + .weak _nds32_jmptbl_68 + .type _nds32_jmptbl_68, @object +_nds32_jmptbl_68: + .word 0 + .size _nds32_jmptbl_68, .-_nds32_jmptbl_68 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid69.S b/libgcc/config/nds32/isr-library/jmptbl_vid69.S new file mode 100644 index 00000000000..78847706f51 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid69.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.69, "a" + .align 2 + .weak _nds32_jmptbl_69 + .type _nds32_jmptbl_69, @object +_nds32_jmptbl_69: + .word 0 + .size _nds32_jmptbl_69, .-_nds32_jmptbl_69 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid70.S b/libgcc/config/nds32/isr-library/jmptbl_vid70.S new file mode 100644 index 00000000000..0f41e21d4db --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid70.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.70, "a" + .align 2 + .weak _nds32_jmptbl_70 + .type _nds32_jmptbl_70, @object +_nds32_jmptbl_70: + .word 0 + .size _nds32_jmptbl_70, .-_nds32_jmptbl_70 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid71.S b/libgcc/config/nds32/isr-library/jmptbl_vid71.S new file mode 100644 index 00000000000..5aab1252e1b --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid71.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.71, "a" + .align 2 + .weak _nds32_jmptbl_71 + .type _nds32_jmptbl_71, @object +_nds32_jmptbl_71: + .word 0 + .size _nds32_jmptbl_71, .-_nds32_jmptbl_71 diff --git a/libgcc/config/nds32/isr-library/jmptbl_vid72.S b/libgcc/config/nds32/isr-library/jmptbl_vid72.S new file mode 100644 index 00000000000..6d40bfffb75 --- /dev/null +++ b/libgcc/config/nds32/isr-library/jmptbl_vid72.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_jmptbl.72, "a" + .align 2 + .weak _nds32_jmptbl_72 + .type _nds32_jmptbl_72, @object +_nds32_jmptbl_72: + .word 0 + .size _nds32_jmptbl_72, .-_nds32_jmptbl_72 diff --git a/libgcc/config/nds32/isr-library/nmih.S b/libgcc/config/nds32/isr-library/nmih.S new file mode 100644 index 00000000000..083ec98023c --- /dev/null +++ b/libgcc/config/nds32/isr-library/nmih.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_nmih, "a" + .align 2 + .weak _nds32_nmih + .type _nds32_nmih, @object +_nds32_nmih: + .word 0 + .size _nds32_nmih, .-_nds32_nmih diff --git a/libgcc/config/nds32/isr-library/reset.S b/libgcc/config/nds32/isr-library/reset.S new file mode 100644 index 00000000000..3f539de48ea --- /dev/null +++ b/libgcc/config/nds32/isr-library/reset.S @@ -0,0 +1,130 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ + .align 1 + .weak _SDA_BASE_ /* For reset handler only. */ + .weak _FP_BASE_ /* For reset handler only. */ + .weak _nds32_init_mem /* User defined memory initialization function. */ + .globl _start + .globl _nds32_reset + .type _nds32_reset, @function +_nds32_reset: +_start: +#ifdef NDS32_EXT_EX9 + .no_ex9_begin +#endif + /* Handle NMI and warm boot if any of them exists. */ + beqz $sp, 1f /* Reset, NMI or warm boot? */ + /* Either NMI or warm boot; save all regs. */ + + /* Preserve registers for context-switching. */ +#ifdef __NDS32_REDUCED_REGS__ + /* For 16-reg mode. */ + smw.adm $r0, [$sp], $r10, #0x0 + smw.adm $r15, [$sp], $r15, #0xf +#else + /* For 32-reg mode. */ + smw.adm $r0, [$sp], $r27, #0xf +#endif +#ifdef NDS32_EXT_IFC + mfusr $r1, $IFC_LP + smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep + stack 8-byte alignment. */ +#endif + + la $gp, _SDA_BASE_ /* Init GP for small data access. */ + move $r0, $sp /* Init parameter. */ + mfsr $r1, $ITYPE /* Check ITYPE for NMI or warm boot. */ + andi $r1, $r1, #0xf + addi $r1, $r1, #-1 + beqz $r1, 2f /* Warm boot if true. */ + l.w $r15, _nds32_nmih /* Load NMI handler. */ + j 3f +2: + l.w $r15, _nds32_wrh /* Load warm boot handler. */ +3: + beqz $r15, 1f /* If no handler, do cold boot. */ + jral $r15 /* Call handler. */ + bnez $r0, 1f /* If fail to resume, do cold boot. */ + + /* Restore registers for context-switching. */ +#ifdef NDS32_EXT_IFC + lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep + stack 8-byte alignment. */ + mtusr $r1, $IFC_LP +#endif +#ifdef __NDS32_REDUCED_REGS__ + /* For 16-reg mode. */ + lmw.bim $r15, [$sp], $r15, #0xf + lmw.bim $r0, [$sp], $r10, #0x0 +#else + /* For 32-reg mode. */ + lmw.bim $r0, [$sp], $r27, #0xf +#endif + iret /* Resume operation. */ + + +1: /* Cold boot. */ + /* Set IVB.ESZ = 1 (vector table entry size = 16 bytes) */ + mfsr $r0, $IVB + li $r1, #0xffff3fff + and $r0, $r0, $r1 + ori $r0, $r0, #0x4000 + mtsr $r0, $IVB + dsb + + la $gp, _SDA_BASE_ /* Init $gp. */ + la $fp, _FP_BASE_ /* Init $fp. */ + la $sp, _stack /* Init $sp. */ +#ifdef NDS32_EXT_EX9 +/* + * Initialize the table base of EX9 instruction + * ex9 generation needs to disable before the ITB is set + */ + mfsr $r0, $MSC_CFG /* Check if HW support of EX9. */ + srli $r0, $r0, 24 + andi $r0, $r0, 0x1 + beqz $r0, 4f /* Zero means HW does not support EX9. */ + la $r0, _ITB_BASE_ /* Init $ITB. */ + mtusr $r0, $ITB + .no_ex9_end +4: +#endif + la $r15, _nds32_init_mem /* Call DRAM init. _nds32_init_mem + may written by C language. */ + beqz $r15, 6f + jral $r15 +6: + l.w $r15, _nds32_jmptbl_00 /* Load reset handler. */ + jral $r15 +/* Reset handler() should never return in a RTOS or non-OS system. + In case it does return, an exception will be generated. + This exception will be caught either by default break handler or by EDM. + Default break handle may just do an infinite loop. + EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */ +5: + break #0x7fff + .size _nds32_reset, .-_nds32_reset diff --git a/libgcc/config/nds32/isr-library/reset_4b.S b/libgcc/config/nds32/isr-library/reset_4b.S new file mode 100644 index 00000000000..23b821a1aaf --- /dev/null +++ b/libgcc/config/nds32/isr-library/reset_4b.S @@ -0,0 +1,131 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ + .align 1 + .weak _SDA_BASE_ /* For reset handler only. */ + .weak _FP_BASE_ /* For reset handler only. */ + .weak _nds32_init_mem /* User defined memory initialization function. */ + .globl _start + .globl _nds32_reset_4b + .type _nds32_reset_4b, @function +_nds32_reset_4b: +_start: +#ifdef NDS32_EXT_EX9 + .no_ex9_begin +#endif + /* Handle NMI and warm boot if any of them exists. */ + beqz $sp, 1f /* Reset, NMI or warm boot? */ + /* Either NMI or warm boot; save all regs. */ + + /* Preserve registers for context-switching. */ +#ifdef __NDS32_REDUCED_REGS__ + /* For 16-reg mode. */ + smw.adm $r0, [$sp], $r10, #0x0 + smw.adm $r15, [$sp], $r15, #0xf +#else + /* For 32-reg mode. */ + smw.adm $r0, [$sp], $r27, #0xf +#endif +#ifdef NDS32_EXT_IFC + mfusr $r1, $IFC_LP + smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep + stack 8-byte alignment. */ +#endif + + la $gp, _SDA_BASE_ /* Init GP for small data access. */ + move $r0, $sp /* Init parameter. */ + mfsr $r1, $ITYPE /* Check ITYPE for NMI or warm boot. */ + andi $r1, $r1, #0xf + addi $r1, $r1, #-1 + beqz $r1, 2f /* Warm boot if true. */ + l.w $r15, _nds32_nmih /* Load NMI handler. */ + j 3f +2: + l.w $r15, _nds32_wrh /* Load warm boot handler. */ +3: + beqz $r15, 1f /* If no handler, do cold boot. */ + jral $r15 /* Call handler. */ + bnez $r0, 1f /* If fail to resume, do cold boot. */ + + /* Restore registers for context-switching. */ +#ifdef NDS32_EXT_IFC + lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep + stack 8-byte alignment. */ + mtusr $r1, $IFC_LP +#endif +#ifdef __NDS32_REDUCED_REGS__ + /* For 16-reg mode. */ + lmw.bim $r15, [$sp], $r15, #0xf + lmw.bim $r0, [$sp], $r10, #0x0 +#else + /* For 32-reg mode. */ + lmw.bim $r0, [$sp], $r27, #0xf +#endif + iret /* Resume operation. */ + + +1: /* Cold boot. */ + /* With vector ID feature, set default vector size to 4B. */ + /* Set IVB.ESZ = 0 (vector table entry size = 4 bytes) */ + mfsr $r0, $IVB + li $r1, #0xc000 + or $r0, $r0, $r1 + xor $r0, $r0, $r1 + mtsr $r0, $IVB + dsb + + la $gp, _SDA_BASE_ /* Init $gp. */ + la $fp, _FP_BASE_ /* Init $fp. */ + la $sp, _stack /* Init $sp. */ +#ifdef NDS32_EXT_EX9 +/* + * Initialize the table base of EX9 instruction + * ex9 generation needs to disable before the ITB is set + */ + mfsr $r0, $MSC_CFG /* Check if HW support of EX9. */ + srli $r0, $r0, 24 + andi $r0, $r0, 0x1 + beqz $r0, 4f /* Zero means HW does not support EX9. */ + la $r0, _ITB_BASE_ /* Init $ITB. */ + mtusr $r0, $ITB + .no_ex9_end +4: +#endif + la $r15, _nds32_init_mem /* Call DRAM init. _nds32_init_mem + may written by C language. */ + beqz $r15, 6f + jral $r15 +6: + l.w $r15, _nds32_jmptbl_00 /* Load reset handler. */ + jral $r15 +/* Reset handler() should never return in a RTOS or non-OS system. + In case it does return, an exception will be generated. + This exception will be caught either by default break handler or by EDM. + Default break handle may just do an infinite loop. + EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */ +5: + break #0x7fff + .size _nds32_reset_4b, .-_nds32_reset_4b diff --git a/libgcc/config/nds32/isr-library/restore_all.inc b/libgcc/config/nds32/isr-library/restore_all.inc new file mode 100644 index 00000000000..a0799540358 --- /dev/null +++ b/libgcc/config/nds32/isr-library/restore_all.inc @@ -0,0 +1,45 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro RESTORE_ALL + setgie.d + dsb + lmw.bim $r1, [$sp], $r2, #0x0 /* Restore IPC, IPSW. */ + mtsr $r1, $IPC + mtsr $r2, $IPSW + RESTORE_FPU_REGS + RESTORE_MAC_REGS +#ifdef NDS32_EXT_IFC + lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep + stack 8-byte alignment. */ + mtusr $r1, $IFC_LP +#endif +#ifdef __NDS32_REDUCED_REGS__ + lmw.bim $r0, [$sp], $r10, #0x0 /* Restore all regs. */ + lmw.bim $r15, [$sp], $r15, #0xf +#else /* not __NDS32_REDUCED_REGS__ */ + lmw.bim $r0, [$sp], $r27, #0xf /* Restore all regs. */ +#endif +.endm diff --git a/libgcc/config/nds32/isr-library/restore_fpu_regs.inc b/libgcc/config/nds32/isr-library/restore_fpu_regs.inc new file mode 100644 index 00000000000..23a86c424a9 --- /dev/null +++ b/libgcc/config/nds32/isr-library/restore_fpu_regs.inc @@ -0,0 +1,36 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro RESTORE_FPU_REGS +#if defined(NDS32_EXT_FPU_CONFIG_0) + RESTORE_FPU_REGS_00 +#elif defined(NDS32_EXT_FPU_CONFIG_1) + RESTORE_FPU_REGS_01 +#elif defined(NDS32_EXT_FPU_CONFIG_2) + RESTORE_FPU_REGS_02 +#elif defined(NDS32_EXT_FPU_CONFIG_3) + RESTORE_FPU_REGS_03 +#endif +.endm diff --git a/libgcc/config/nds32/isr-library/restore_fpu_regs_00.inc b/libgcc/config/nds32/isr-library/restore_fpu_regs_00.inc new file mode 100644 index 00000000000..a90a368fecf --- /dev/null +++ b/libgcc/config/nds32/isr-library/restore_fpu_regs_00.inc @@ -0,0 +1,31 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro RESTORE_FPU_REGS_00 + fldi.bi $fd0, [$sp], #8 + fldi.bi $fd1, [$sp], #8 + fldi.bi $fd2, [$sp], #8 + fldi.bi $fd3, [$sp], #8 +.endm diff --git a/libgcc/config/nds32/isr-library/restore_fpu_regs_01.inc b/libgcc/config/nds32/isr-library/restore_fpu_regs_01.inc new file mode 100644 index 00000000000..615e4530924 --- /dev/null +++ b/libgcc/config/nds32/isr-library/restore_fpu_regs_01.inc @@ -0,0 +1,35 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro RESTORE_FPU_REGS_01 + fldi.bi $fd0, [$sp], #8 + fldi.bi $fd1, [$sp], #8 + fldi.bi $fd2, [$sp], #8 + fldi.bi $fd3, [$sp], #8 + fldi.bi $fd4, [$sp], #8 + fldi.bi $fd5, [$sp], #8 + fldi.bi $fd6, [$sp], #8 + fldi.bi $fd7, [$sp], #8 +.endm diff --git a/libgcc/config/nds32/isr-library/restore_fpu_regs_02.inc b/libgcc/config/nds32/isr-library/restore_fpu_regs_02.inc new file mode 100644 index 00000000000..cfeed32451d --- /dev/null +++ b/libgcc/config/nds32/isr-library/restore_fpu_regs_02.inc @@ -0,0 +1,43 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro RESTORE_FPU_REGS_02 + fldi.bi $fd0, [$sp], 8 + fldi.bi $fd1, [$sp], 8 + fldi.bi $fd2, [$sp], 8 + fldi.bi $fd3, [$sp], 8 + fldi.bi $fd4, [$sp], 8 + fldi.bi $fd5, [$sp], 8 + fldi.bi $fd6, [$sp], 8 + fldi.bi $fd7, [$sp], 8 + fldi.bi $fd8, [$sp], 8 + fldi.bi $fd9, [$sp], 8 + fldi.bi $fd10, [$sp], 8 + fldi.bi $fd11, [$sp], 8 + fldi.bi $fd12, [$sp], 8 + fldi.bi $fd13, [$sp], 8 + fldi.bi $fd14, [$sp], 8 + fldi.bi $fd15, [$sp], 8 +.endm diff --git a/libgcc/config/nds32/isr-library/restore_fpu_regs_03.inc b/libgcc/config/nds32/isr-library/restore_fpu_regs_03.inc new file mode 100644 index 00000000000..61391c91259 --- /dev/null +++ b/libgcc/config/nds32/isr-library/restore_fpu_regs_03.inc @@ -0,0 +1,59 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro RESTORE_FPU_REGS_03 + fldi.bi $fd0, [$sp], #8 + fldi.bi $fd1, [$sp], #8 + fldi.bi $fd2, [$sp], #8 + fldi.bi $fd3, [$sp], #8 + fldi.bi $fd4, [$sp], #8 + fldi.bi $fd5, [$sp], #8 + fldi.bi $fd6, [$sp], #8 + fldi.bi $fd7, [$sp], #8 + fldi.bi $fd8, [$sp], #8 + fldi.bi $fd9, [$sp], #8 + fldi.bi $fd10, [$sp], #8 + fldi.bi $fd11, [$sp], #8 + fldi.bi $fd12, [$sp], #8 + fldi.bi $fd13, [$sp], #8 + fldi.bi $fd14, [$sp], #8 + fldi.bi $fd15, [$sp], #8 + fldi.bi $fd16, [$sp], #8 + fldi.bi $fd17, [$sp], #8 + fldi.bi $fd18, [$sp], #8 + fldi.bi $fd19, [$sp], #8 + fldi.bi $fd20, [$sp], #8 + fldi.bi $fd21, [$sp], #8 + fldi.bi $fd22, [$sp], #8 + fldi.bi $fd23, [$sp], #8 + fldi.bi $fd24, [$sp], #8 + fldi.bi $fd25, [$sp], #8 + fldi.bi $fd26, [$sp], #8 + fldi.bi $fd27, [$sp], #8 + fldi.bi $fd28, [$sp], #8 + fldi.bi $fd29, [$sp], #8 + fldi.bi $fd30, [$sp], #8 + fldi.bi $fd31, [$sp], #8 +.endm diff --git a/libgcc/config/nds32/isr-library/restore_mac_regs.inc b/libgcc/config/nds32/isr-library/restore_mac_regs.inc new file mode 100644 index 00000000000..770817dd817 --- /dev/null +++ b/libgcc/config/nds32/isr-library/restore_mac_regs.inc @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro RESTORE_MAC_REGS +#ifdef NDS32_DX_REGS + lmw.bim $r1, [$sp], $r4, #0x0 + mtusr $r1, $d0.lo + mtusr $r2, $d0.hi + mtusr $r3, $d1.lo + mtusr $r4, $d1.hi +#endif +.endm diff --git a/libgcc/config/nds32/isr-library/restore_partial.inc b/libgcc/config/nds32/isr-library/restore_partial.inc new file mode 100644 index 00000000000..eeb815f93d6 --- /dev/null +++ b/libgcc/config/nds32/isr-library/restore_partial.inc @@ -0,0 +1,47 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro RESTORE_PARTIAL +#if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY) + setgie.d + dsb + lmw.bim $r1, [$sp], $r2, #0x0 /* Restore IPC, IPSW. */ + mtsr $r1, $IPC /* Set IPC. */ + mtsr $r2, $IPSW /* Set IPSW. */ +#endif + RESTORE_FPU_REGS + RESTORE_MAC_REGS +#ifdef NDS32_EXT_IFC + lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep + stack 8-byte alignment. */ + mtusr $r1, $IFC_LP +#endif + lmw.bim $r0, [$sp], $r5, #0x0 /* Restore all regs. */ +#ifdef __NDS32_REDUCED_REGS__ + lmw.bim $r15, [$sp], $r15, #0x2 +#else + lmw.bim $r15, [$sp], $r27, #0x2 /* Restore all regs. */ +#endif +.endm diff --git a/libgcc/config/nds32/isr-library/save_all.inc b/libgcc/config/nds32/isr-library/save_all.inc new file mode 100644 index 00000000000..2ac053d71f8 --- /dev/null +++ b/libgcc/config/nds32/isr-library/save_all.inc @@ -0,0 +1,67 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro SAVE_ALL_4B +#ifdef __NDS32_REDUCED_REGS__ + smw.adm $r15, [$sp], $r15, #0xf + smw.adm $r0, [$sp], $r10, #0x0 +#else /* not __NDS32_REDUCED_REGS__ */ + smw.adm $r0, [$sp], $r27, #0xf +#endif /* not __NDS32_REDUCED_REGS__ */ +#ifdef NDS32_EXT_IFC + mfusr $r1, $IFC_LP + smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep + stack 8-byte alignment. */ +#endif + SAVE_MAC_REGS + SAVE_FPU_REGS + mfsr $r1, $IPC /* Get IPC. */ + mfsr $r2, $IPSW /* Get IPSW. */ + smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */ + move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */ + mfsr $r0, $ITYPE /* Get VID to $r0. */ + srli $r0, $r0, #5 +#ifdef __NDS32_ISA_V2__ + andi $r0, $r0, #127 +#else + fexti33 $r0, #6 +#endif +.endm + +.macro SAVE_ALL +/* SAVE_REG_TBL code has been moved to + vector table generated by compiler. */ +#ifdef NDS32_EXT_IFC + mfusr $r1, $IFC_LP + smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep + stack 8-byte alignment. */ +#endif + SAVE_MAC_REGS + SAVE_FPU_REGS + mfsr $r1, $IPC /* Get IPC. */ + mfsr $r2, $IPSW /* Get IPSW. */ + smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */ + move $r1, $sp /* $r1 is ptr to NDS32_CONTEXT. */ +.endm diff --git a/libgcc/config/nds32/isr-library/save_fpu_regs.inc b/libgcc/config/nds32/isr-library/save_fpu_regs.inc new file mode 100644 index 00000000000..be3a504e440 --- /dev/null +++ b/libgcc/config/nds32/isr-library/save_fpu_regs.inc @@ -0,0 +1,36 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro SAVE_FPU_REGS +#if defined(NDS32_EXT_FPU_CONFIG_0) + SAVE_FPU_REGS_00 +#elif defined(NDS32_EXT_FPU_CONFIG_1) + SAVE_FPU_REGS_01 +#elif defined(NDS32_EXT_FPU_CONFIG_2) + SAVE_FPU_REGS_02 +#elif defined(NDS32_EXT_FPU_CONFIG_3) + SAVE_FPU_REGS_03 +#endif +.endm diff --git a/libgcc/config/nds32/isr-library/save_fpu_regs_00.inc b/libgcc/config/nds32/isr-library/save_fpu_regs_00.inc new file mode 100644 index 00000000000..2514f59b90e --- /dev/null +++ b/libgcc/config/nds32/isr-library/save_fpu_regs_00.inc @@ -0,0 +1,33 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro SAVE_FPU_REGS_00 + addi $sp, $sp, #-8 + fsdi.bi $fd3, [$sp], #-8 + fsdi.bi $fd2, [$sp], #-8 + fsdi.bi $fd1, [$sp], #-8 + fsdi.bi $fd0, [$sp], #-8 + addi $sp, $sp, #8 +.endm diff --git a/libgcc/config/nds32/isr-library/save_fpu_regs_01.inc b/libgcc/config/nds32/isr-library/save_fpu_regs_01.inc new file mode 100644 index 00000000000..1d605f2acdd --- /dev/null +++ b/libgcc/config/nds32/isr-library/save_fpu_regs_01.inc @@ -0,0 +1,37 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro SAVE_FPU_REGS_01 + addi $sp, $sp, #-8 + fsdi.bi $fd7, [$sp], #-8 + fsdi.bi $fd6, [$sp], #-8 + fsdi.bi $fd5, [$sp], #-8 + fsdi.bi $fd4, [$sp], #-8 + fsdi.bi $fd3, [$sp], #-8 + fsdi.bi $fd2, [$sp], #-8 + fsdi.bi $fd1, [$sp], #-8 + fsdi.bi $fd0, [$sp], #-8 + addi $sp, $sp, #8 +.endm diff --git a/libgcc/config/nds32/isr-library/save_fpu_regs_02.inc b/libgcc/config/nds32/isr-library/save_fpu_regs_02.inc new file mode 100644 index 00000000000..30cb833ad0f --- /dev/null +++ b/libgcc/config/nds32/isr-library/save_fpu_regs_02.inc @@ -0,0 +1,45 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro SAVE_FPU_REGS_02 + addi $sp, $sp, #-8 + fsdi.bi $fd15, [$sp], #-8 + fsdi.bi $fd14, [$sp], #-8 + fsdi.bi $fd13, [$sp], #-8 + fsdi.bi $fd12, [$sp], #-8 + fsdi.bi $fd11, [$sp], #-8 + fsdi.bi $fd10, [$sp], #-8 + fsdi.bi $fd9, [$sp], #-8 + fsdi.bi $fd8, [$sp], #-8 + fsdi.bi $fd7, [$sp], #-8 + fsdi.bi $fd6, [$sp], #-8 + fsdi.bi $fd5, [$sp], #-8 + fsdi.bi $fd4, [$sp], #-8 + fsdi.bi $fd3, [$sp], #-8 + fsdi.bi $fd2, [$sp], #-8 + fsdi.bi $fd1, [$sp], #-8 + fsdi.bi $fd0, [$sp], #-8 + addi $sp, $sp, #8 +.endm diff --git a/libgcc/config/nds32/isr-library/save_fpu_regs_03.inc b/libgcc/config/nds32/isr-library/save_fpu_regs_03.inc new file mode 100644 index 00000000000..693e051a847 --- /dev/null +++ b/libgcc/config/nds32/isr-library/save_fpu_regs_03.inc @@ -0,0 +1,61 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro SAVE_FPU_REGS_03 + addi $sp, $sp, #-8 + fsdi.bi $fd31, [$sp], #-8 + fsdi.bi $fd30, [$sp], #-8 + fsdi.bi $fd29, [$sp], #-8 + fsdi.bi $fd28, [$sp], #-8 + fsdi.bi $fd27, [$sp], #-8 + fsdi.bi $fd26, [$sp], #-8 + fsdi.bi $fd25, [$sp], #-8 + fsdi.bi $fd24, [$sp], #-8 + fsdi.bi $fd23, [$sp], #-8 + fsdi.bi $fd22, [$sp], #-8 + fsdi.bi $fd21, [$sp], #-8 + fsdi.bi $fd20, [$sp], #-8 + fsdi.bi $fd19, [$sp], #-8 + fsdi.bi $fd18, [$sp], #-8 + fsdi.bi $fd17, [$sp], #-8 + fsdi.bi $fd16, [$sp], #-8 + fsdi.bi $fd15, [$sp], #-8 + fsdi.bi $fd14, [$sp], #-8 + fsdi.bi $fd13, [$sp], #-8 + fsdi.bi $fd12, [$sp], #-8 + fsdi.bi $fd11, [$sp], #-8 + fsdi.bi $fd10, [$sp], #-8 + fsdi.bi $fd9, [$sp], #-8 + fsdi.bi $fd8, [$sp], #-8 + fsdi.bi $fd7, [$sp], #-8 + fsdi.bi $fd6, [$sp], #-8 + fsdi.bi $fd5, [$sp], #-8 + fsdi.bi $fd4, [$sp], #-8 + fsdi.bi $fd3, [$sp], #-8 + fsdi.bi $fd2, [$sp], #-8 + fsdi.bi $fd1, [$sp], #-8 + fsdi.bi $fd0, [$sp], #-8 + addi $sp, $sp, #8 +.endm diff --git a/libgcc/config/nds32/isr-library/save_mac_regs.inc b/libgcc/config/nds32/isr-library/save_mac_regs.inc new file mode 100644 index 00000000000..14c1851736f --- /dev/null +++ b/libgcc/config/nds32/isr-library/save_mac_regs.inc @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro SAVE_MAC_REGS +#ifdef NDS32_DX_REGS + mfusr $r1, $d0.lo + mfusr $r2, $d0.hi + mfusr $r3, $d1.lo + mfusr $r4, $d1.hi + smw.adm $r1, [$sp], $r4, #0x0 +#endif +.endm diff --git a/libgcc/config/nds32/isr-library/save_partial.inc b/libgcc/config/nds32/isr-library/save_partial.inc new file mode 100644 index 00000000000..61df3966d1e --- /dev/null +++ b/libgcc/config/nds32/isr-library/save_partial.inc @@ -0,0 +1,69 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +.macro SAVE_PARTIAL_4B +#ifdef __NDS32_REDUCED_REGS__ + smw.adm $r15, [$sp], $r15, #0x2 +#else /* not __NDS32_REDUCED_REGS__ */ + smw.adm $r15, [$sp], $r27, #0x2 +#endif /* not __NDS32_REDUCED_REGS__ */ + smw.adm $r0, [$sp], $r5, #0x0 +#ifdef NDS32_EXT_IFC + mfusr $r1, $IFC_LP + smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep + stack 8-byte alignment. */ +#endif + SAVE_MAC_REGS + SAVE_FPU_REGS +#if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY) + mfsr $r1, $IPC /* Get IPC. */ + mfsr $r2, $IPSW /* Get IPSW. */ + smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */ +#endif + mfsr $r0, $ITYPE /* Get VID to $r0. */ + srli $r0, $r0, #5 +#ifdef __NDS32_ISA_V2__ + andi $r0, $r0, #127 +#else + fexti33 $r0, #6 +#endif +.endm + +.macro SAVE_PARTIAL +/* SAVE_CALLER_REGS code has been moved to + vector table generated by compiler. */ +#ifdef NDS32_EXT_IFC + mfusr $r1, $IFC_LP + smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep + stack 8-byte alignment. */ +#endif + SAVE_MAC_REGS + SAVE_FPU_REGS +#if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY) + mfsr $r1, $IPC /* Get IPC. */ + mfsr $r2, $IPSW /* Get IPSW. */ + smw.adm $r1, [$sp], $r2, #0x0 /* Push IPC, IPSW. */ +#endif +.endm diff --git a/libgcc/config/nds32/isr-library/vec_vid00.S b/libgcc/config/nds32/isr-library/vec_vid00.S new file mode 100644 index 00000000000..cef2df23b21 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid00.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.00, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_00 + .type _nds32_vector_00, @function +_nds32_vector_00: +1: + j 1b + .size _nds32_vector_00, .-_nds32_vector_00 diff --git a/libgcc/config/nds32/isr-library/vec_vid00_4b.S b/libgcc/config/nds32/isr-library/vec_vid00_4b.S new file mode 100644 index 00000000000..957ac485e2a --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid00_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.00, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_00_4b + .type _nds32_vector_00_4b, @function +_nds32_vector_00_4b: +1: + j 1b + .size _nds32_vector_00_4b, .-_nds32_vector_00_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid01.S b/libgcc/config/nds32/isr-library/vec_vid01.S new file mode 100644 index 00000000000..319d64bcd20 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid01.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.01, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_01 + .type _nds32_vector_01, @function +_nds32_vector_01: +1: + j 1b + .size _nds32_vector_01, .-_nds32_vector_01 diff --git a/libgcc/config/nds32/isr-library/vec_vid01_4b.S b/libgcc/config/nds32/isr-library/vec_vid01_4b.S new file mode 100644 index 00000000000..ad52fcb9cc1 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid01_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.01, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_01_4b + .type _nds32_vector_01_4b, @function +_nds32_vector_01_4b: +1: + j 1b + .size _nds32_vector_01_4b, .-_nds32_vector_01_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid02.S b/libgcc/config/nds32/isr-library/vec_vid02.S new file mode 100644 index 00000000000..4c98c5cebb5 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid02.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.02, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_02 + .type _nds32_vector_02, @function +_nds32_vector_02: +1: + j 1b + .size _nds32_vector_02, .-_nds32_vector_02 diff --git a/libgcc/config/nds32/isr-library/vec_vid02_4b.S b/libgcc/config/nds32/isr-library/vec_vid02_4b.S new file mode 100644 index 00000000000..790356bc655 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid02_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.02, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_02_4b + .type _nds32_vector_02_4b, @function +_nds32_vector_02_4b: +1: + j 1b + .size _nds32_vector_02_4b, .-_nds32_vector_02_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid03.S b/libgcc/config/nds32/isr-library/vec_vid03.S new file mode 100644 index 00000000000..7cca9aa7544 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid03.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.03, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_03 + .type _nds32_vector_03, @function +_nds32_vector_03: +1: + j 1b + .size _nds32_vector_03, .-_nds32_vector_03 diff --git a/libgcc/config/nds32/isr-library/vec_vid03_4b.S b/libgcc/config/nds32/isr-library/vec_vid03_4b.S new file mode 100644 index 00000000000..be756bf3d1d --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid03_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.03, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_03_4b + .type _nds32_vector_03_4b, @function +_nds32_vector_03_4b: +1: + j 1b + .size _nds32_vector_03_4b, .-_nds32_vector_03_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid04.S b/libgcc/config/nds32/isr-library/vec_vid04.S new file mode 100644 index 00000000000..ec9ea16cc91 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid04.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.04, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_04 + .type _nds32_vector_04, @function +_nds32_vector_04: +1: + j 1b + .size _nds32_vector_04, .-_nds32_vector_04 diff --git a/libgcc/config/nds32/isr-library/vec_vid04_4b.S b/libgcc/config/nds32/isr-library/vec_vid04_4b.S new file mode 100644 index 00000000000..6883718814e --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid04_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.04, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_04_4b + .type _nds32_vector_04_4b, @function +_nds32_vector_04_4b: +1: + j 1b + .size _nds32_vector_04_4b, .-_nds32_vector_04_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid05.S b/libgcc/config/nds32/isr-library/vec_vid05.S new file mode 100644 index 00000000000..38aa4d99d52 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid05.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.05, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_05 + .type _nds32_vector_05, @function +_nds32_vector_05: +1: + j 1b + .size _nds32_vector_05, .-_nds32_vector_05 diff --git a/libgcc/config/nds32/isr-library/vec_vid05_4b.S b/libgcc/config/nds32/isr-library/vec_vid05_4b.S new file mode 100644 index 00000000000..914287f69d4 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid05_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.05, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_05_4b + .type _nds32_vector_05_4b, @function +_nds32_vector_05_4b: +1: + j 1b + .size _nds32_vector_05_4b, .-_nds32_vector_05_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid06.S b/libgcc/config/nds32/isr-library/vec_vid06.S new file mode 100644 index 00000000000..8b1bcfb7ee8 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid06.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.06, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_06 + .type _nds32_vector_06, @function +_nds32_vector_06: +1: + j 1b + .size _nds32_vector_06, .-_nds32_vector_06 diff --git a/libgcc/config/nds32/isr-library/vec_vid06_4b.S b/libgcc/config/nds32/isr-library/vec_vid06_4b.S new file mode 100644 index 00000000000..c0bd26e2e6e --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid06_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.06, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_06_4b + .type _nds32_vector_06_4b, @function +_nds32_vector_06_4b: +1: + j 1b + .size _nds32_vector_06_4b, .-_nds32_vector_06_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid07.S b/libgcc/config/nds32/isr-library/vec_vid07.S new file mode 100644 index 00000000000..b708ada47e9 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid07.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.07, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_07 + .type _nds32_vector_07, @function +_nds32_vector_07: +1: + j 1b + .size _nds32_vector_07, .-_nds32_vector_07 diff --git a/libgcc/config/nds32/isr-library/vec_vid07_4b.S b/libgcc/config/nds32/isr-library/vec_vid07_4b.S new file mode 100644 index 00000000000..3532551ab5e --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid07_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.07, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_07_4b + .type _nds32_vector_07_4b, @function +_nds32_vector_07_4b: +1: + j 1b + .size _nds32_vector_07_4b, .-_nds32_vector_07_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid08.S b/libgcc/config/nds32/isr-library/vec_vid08.S new file mode 100644 index 00000000000..3afb6e6cb1d --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid08.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.08, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_08 + .type _nds32_vector_08, @function +_nds32_vector_08: +1: + j 1b + .size _nds32_vector_08, .-_nds32_vector_08 diff --git a/libgcc/config/nds32/isr-library/vec_vid08_4b.S b/libgcc/config/nds32/isr-library/vec_vid08_4b.S new file mode 100644 index 00000000000..0493fefde64 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid08_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.08, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_08_4b + .type _nds32_vector_08_4b, @function +_nds32_vector_08_4b: +1: + j 1b + .size _nds32_vector_08_4b, .-_nds32_vector_08_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid09.S b/libgcc/config/nds32/isr-library/vec_vid09.S new file mode 100644 index 00000000000..35747ec212d --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid09.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.09, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_09 + .type _nds32_vector_09, @function +_nds32_vector_09: +1: + j 1b + .size _nds32_vector_09, .-_nds32_vector_09 diff --git a/libgcc/config/nds32/isr-library/vec_vid09_4b.S b/libgcc/config/nds32/isr-library/vec_vid09_4b.S new file mode 100644 index 00000000000..d44f9b22ac0 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid09_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.09, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_09_4b + .type _nds32_vector_09_4b, @function +_nds32_vector_09_4b: +1: + j 1b + .size _nds32_vector_09_4b, .-_nds32_vector_09_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid10.S b/libgcc/config/nds32/isr-library/vec_vid10.S new file mode 100644 index 00000000000..71ab8ac056b --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid10.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.10, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_10 + .type _nds32_vector_10, @function +_nds32_vector_10: +1: + j 1b + .size _nds32_vector_10, .-_nds32_vector_10 diff --git a/libgcc/config/nds32/isr-library/vec_vid10_4b.S b/libgcc/config/nds32/isr-library/vec_vid10_4b.S new file mode 100644 index 00000000000..49fd669f10d --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid10_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.10, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_10_4b + .type _nds32_vector_10_4b, @function +_nds32_vector_10_4b: +1: + j 1b + .size _nds32_vector_10_4b, .-_nds32_vector_10_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid11.S b/libgcc/config/nds32/isr-library/vec_vid11.S new file mode 100644 index 00000000000..732559d17e2 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid11.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.11, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_11 + .type _nds32_vector_11, @function +_nds32_vector_11: +1: + j 1b + .size _nds32_vector_11, .-_nds32_vector_11 diff --git a/libgcc/config/nds32/isr-library/vec_vid11_4b.S b/libgcc/config/nds32/isr-library/vec_vid11_4b.S new file mode 100644 index 00000000000..e878e36c947 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid11_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.11, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_11_4b + .type _nds32_vector_11_4b, @function +_nds32_vector_11_4b: +1: + j 1b + .size _nds32_vector_11_4b, .-_nds32_vector_11_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid12.S b/libgcc/config/nds32/isr-library/vec_vid12.S new file mode 100644 index 00000000000..5d78fbb2e68 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid12.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.12, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_12 + .type _nds32_vector_12, @function +_nds32_vector_12: +1: + j 1b + .size _nds32_vector_12, .-_nds32_vector_12 diff --git a/libgcc/config/nds32/isr-library/vec_vid12_4b.S b/libgcc/config/nds32/isr-library/vec_vid12_4b.S new file mode 100644 index 00000000000..a03e8d89b6d --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid12_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.12, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_12_4b + .type _nds32_vector_12_4b, @function +_nds32_vector_12_4b: +1: + j 1b + .size _nds32_vector_12_4b, .-_nds32_vector_12_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid13.S b/libgcc/config/nds32/isr-library/vec_vid13.S new file mode 100644 index 00000000000..3df6a1e4299 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid13.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.13, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_13 + .type _nds32_vector_13, @function +_nds32_vector_13: +1: + j 1b + .size _nds32_vector_13, .-_nds32_vector_13 diff --git a/libgcc/config/nds32/isr-library/vec_vid13_4b.S b/libgcc/config/nds32/isr-library/vec_vid13_4b.S new file mode 100644 index 00000000000..2117edb43ce --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid13_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.13, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_13_4b + .type _nds32_vector_13_4b, @function +_nds32_vector_13_4b: +1: + j 1b + .size _nds32_vector_13_4b, .-_nds32_vector_13_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid14.S b/libgcc/config/nds32/isr-library/vec_vid14.S new file mode 100644 index 00000000000..8a554bebad9 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid14.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.14, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_14 + .type _nds32_vector_14, @function +_nds32_vector_14: +1: + j 1b + .size _nds32_vector_14, .-_nds32_vector_14 diff --git a/libgcc/config/nds32/isr-library/vec_vid14_4b.S b/libgcc/config/nds32/isr-library/vec_vid14_4b.S new file mode 100644 index 00000000000..1c5bf2dbdaa --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid14_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.14, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_14_4b + .type _nds32_vector_14_4b, @function +_nds32_vector_14_4b: +1: + j 1b + .size _nds32_vector_14_4b, .-_nds32_vector_14_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid15.S b/libgcc/config/nds32/isr-library/vec_vid15.S new file mode 100644 index 00000000000..1d49d62f42f --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid15.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.15, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_15 + .type _nds32_vector_15, @function +_nds32_vector_15: +1: + j 1b + .size _nds32_vector_15, .-_nds32_vector_15 diff --git a/libgcc/config/nds32/isr-library/vec_vid15_4b.S b/libgcc/config/nds32/isr-library/vec_vid15_4b.S new file mode 100644 index 00000000000..ffa8ea9aec8 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid15_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.15, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_15_4b + .type _nds32_vector_15_4b, @function +_nds32_vector_15_4b: +1: + j 1b + .size _nds32_vector_15_4b, .-_nds32_vector_15_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid16.S b/libgcc/config/nds32/isr-library/vec_vid16.S new file mode 100644 index 00000000000..70d6ab36592 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid16.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.16, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_16 + .type _nds32_vector_16, @function +_nds32_vector_16: +1: + j 1b + .size _nds32_vector_16, .-_nds32_vector_16 diff --git a/libgcc/config/nds32/isr-library/vec_vid16_4b.S b/libgcc/config/nds32/isr-library/vec_vid16_4b.S new file mode 100644 index 00000000000..133fe6a2123 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid16_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.16, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_16_4b + .type _nds32_vector_16_4b, @function +_nds32_vector_16_4b: +1: + j 1b + .size _nds32_vector_16_4b, .-_nds32_vector_16_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid17.S b/libgcc/config/nds32/isr-library/vec_vid17.S new file mode 100644 index 00000000000..8eb871eb7f5 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid17.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.17, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_17 + .type _nds32_vector_17, @function +_nds32_vector_17: +1: + j 1b + .size _nds32_vector_17, .-_nds32_vector_17 diff --git a/libgcc/config/nds32/isr-library/vec_vid17_4b.S b/libgcc/config/nds32/isr-library/vec_vid17_4b.S new file mode 100644 index 00000000000..e10e7d65963 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid17_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.17, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_17_4b + .type _nds32_vector_17_4b, @function +_nds32_vector_17_4b: +1: + j 1b + .size _nds32_vector_17_4b, .-_nds32_vector_17_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid18.S b/libgcc/config/nds32/isr-library/vec_vid18.S new file mode 100644 index 00000000000..3699454153e --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid18.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.18, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_18 + .type _nds32_vector_18, @function +_nds32_vector_18: +1: + j 1b + .size _nds32_vector_18, .-_nds32_vector_18 diff --git a/libgcc/config/nds32/isr-library/vec_vid18_4b.S b/libgcc/config/nds32/isr-library/vec_vid18_4b.S new file mode 100644 index 00000000000..e52910210a8 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid18_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.18, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_18_4b + .type _nds32_vector_18_4b, @function +_nds32_vector_18_4b: +1: + j 1b + .size _nds32_vector_18_4b, .-_nds32_vector_18_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid19.S b/libgcc/config/nds32/isr-library/vec_vid19.S new file mode 100644 index 00000000000..b572bf9516a --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid19.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.19, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_19 + .type _nds32_vector_19, @function +_nds32_vector_19: +1: + j 1b + .size _nds32_vector_19, .-_nds32_vector_19 diff --git a/libgcc/config/nds32/isr-library/vec_vid19_4b.S b/libgcc/config/nds32/isr-library/vec_vid19_4b.S new file mode 100644 index 00000000000..49462674f2a --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid19_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.19, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_19_4b + .type _nds32_vector_19_4b, @function +_nds32_vector_19_4b: +1: + j 1b + .size _nds32_vector_19_4b, .-_nds32_vector_19_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid20.S b/libgcc/config/nds32/isr-library/vec_vid20.S new file mode 100644 index 00000000000..c8fa4194cfc --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid20.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.20, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_20 + .type _nds32_vector_20, @function +_nds32_vector_20: +1: + j 1b + .size _nds32_vector_20, .-_nds32_vector_20 diff --git a/libgcc/config/nds32/isr-library/vec_vid20_4b.S b/libgcc/config/nds32/isr-library/vec_vid20_4b.S new file mode 100644 index 00000000000..95ab9170308 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid20_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.20, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_20_4b + .type _nds32_vector_20_4b, @function +_nds32_vector_20_4b: +1: + j 1b + .size _nds32_vector_20_4b, .-_nds32_vector_20_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid21.S b/libgcc/config/nds32/isr-library/vec_vid21.S new file mode 100644 index 00000000000..8fc8cc706b7 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid21.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.21, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_21 + .type _nds32_vector_21, @function +_nds32_vector_21: +1: + j 1b + .size _nds32_vector_21, .-_nds32_vector_21 diff --git a/libgcc/config/nds32/isr-library/vec_vid21_4b.S b/libgcc/config/nds32/isr-library/vec_vid21_4b.S new file mode 100644 index 00000000000..33956bbbc33 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid21_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.21, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_21_4b + .type _nds32_vector_21_4b, @function +_nds32_vector_21_4b: +1: + j 1b + .size _nds32_vector_21_4b, .-_nds32_vector_21_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid22.S b/libgcc/config/nds32/isr-library/vec_vid22.S new file mode 100644 index 00000000000..8e71ecb856a --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid22.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.22, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_22 + .type _nds32_vector_22, @function +_nds32_vector_22: +1: + j 1b + .size _nds32_vector_22, .-_nds32_vector_22 diff --git a/libgcc/config/nds32/isr-library/vec_vid22_4b.S b/libgcc/config/nds32/isr-library/vec_vid22_4b.S new file mode 100644 index 00000000000..5ecd38261e7 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid22_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.22, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_22_4b + .type _nds32_vector_22_4b, @function +_nds32_vector_22_4b: +1: + j 1b + .size _nds32_vector_22_4b, .-_nds32_vector_22_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid23.S b/libgcc/config/nds32/isr-library/vec_vid23.S new file mode 100644 index 00000000000..c9f2ae3bfb9 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid23.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.23, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_23 + .type _nds32_vector_23, @function +_nds32_vector_23: +1: + j 1b + .size _nds32_vector_23, .-_nds32_vector_23 diff --git a/libgcc/config/nds32/isr-library/vec_vid23_4b.S b/libgcc/config/nds32/isr-library/vec_vid23_4b.S new file mode 100644 index 00000000000..eb7ea1f15ee --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid23_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.23, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_23_4b + .type _nds32_vector_23_4b, @function +_nds32_vector_23_4b: +1: + j 1b + .size _nds32_vector_23_4b, .-_nds32_vector_23_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid24.S b/libgcc/config/nds32/isr-library/vec_vid24.S new file mode 100644 index 00000000000..dc16e56267d --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid24.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.24, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_24 + .type _nds32_vector_24, @function +_nds32_vector_24: +1: + j 1b + .size _nds32_vector_24, .-_nds32_vector_24 diff --git a/libgcc/config/nds32/isr-library/vec_vid24_4b.S b/libgcc/config/nds32/isr-library/vec_vid24_4b.S new file mode 100644 index 00000000000..023cee9e83a --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid24_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.24, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_24_4b + .type _nds32_vector_24_4b, @function +_nds32_vector_24_4b: +1: + j 1b + .size _nds32_vector_24_4b, .-_nds32_vector_24_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid25.S b/libgcc/config/nds32/isr-library/vec_vid25.S new file mode 100644 index 00000000000..cc0c0623150 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid25.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.25, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_25 + .type _nds32_vector_25, @function +_nds32_vector_25: +1: + j 1b + .size _nds32_vector_25, .-_nds32_vector_25 diff --git a/libgcc/config/nds32/isr-library/vec_vid25_4b.S b/libgcc/config/nds32/isr-library/vec_vid25_4b.S new file mode 100644 index 00000000000..f9c747829c2 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid25_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.25, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_25_4b + .type _nds32_vector_25_4b, @function +_nds32_vector_25_4b: +1: + j 1b + .size _nds32_vector_25_4b, .-_nds32_vector_25_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid26.S b/libgcc/config/nds32/isr-library/vec_vid26.S new file mode 100644 index 00000000000..8afb5f78850 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid26.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.26, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_26 + .type _nds32_vector_26, @function +_nds32_vector_26: +1: + j 1b + .size _nds32_vector_26, .-_nds32_vector_26 diff --git a/libgcc/config/nds32/isr-library/vec_vid26_4b.S b/libgcc/config/nds32/isr-library/vec_vid26_4b.S new file mode 100644 index 00000000000..51aea6c5ffb --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid26_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.26, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_26_4b + .type _nds32_vector_26_4b, @function +_nds32_vector_26_4b: +1: + j 1b + .size _nds32_vector_26_4b, .-_nds32_vector_26_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid27.S b/libgcc/config/nds32/isr-library/vec_vid27.S new file mode 100644 index 00000000000..5babf0761c5 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid27.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.27, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_27 + .type _nds32_vector_27, @function +_nds32_vector_27: +1: + j 1b + .size _nds32_vector_27, .-_nds32_vector_27 diff --git a/libgcc/config/nds32/isr-library/vec_vid27_4b.S b/libgcc/config/nds32/isr-library/vec_vid27_4b.S new file mode 100644 index 00000000000..7a6e8705f0f --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid27_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.27, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_27_4b + .type _nds32_vector_27_4b, @function +_nds32_vector_27_4b: +1: + j 1b + .size _nds32_vector_27_4b, .-_nds32_vector_27_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid28.S b/libgcc/config/nds32/isr-library/vec_vid28.S new file mode 100644 index 00000000000..3600b9c1738 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid28.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.28, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_28 + .type _nds32_vector_28, @function +_nds32_vector_28: +1: + j 1b + .size _nds32_vector_28, .-_nds32_vector_28 diff --git a/libgcc/config/nds32/isr-library/vec_vid28_4b.S b/libgcc/config/nds32/isr-library/vec_vid28_4b.S new file mode 100644 index 00000000000..5c752956269 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid28_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.28, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_28_4b + .type _nds32_vector_28_4b, @function +_nds32_vector_28_4b: +1: + j 1b + .size _nds32_vector_28_4b, .-_nds32_vector_28_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid29.S b/libgcc/config/nds32/isr-library/vec_vid29.S new file mode 100644 index 00000000000..02f8e9ceb62 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid29.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.29, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_29 + .type _nds32_vector_29, @function +_nds32_vector_29: +1: + j 1b + .size _nds32_vector_29, .-_nds32_vector_29 diff --git a/libgcc/config/nds32/isr-library/vec_vid29_4b.S b/libgcc/config/nds32/isr-library/vec_vid29_4b.S new file mode 100644 index 00000000000..48412f0c6b9 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid29_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.29, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_29_4b + .type _nds32_vector_29_4b, @function +_nds32_vector_29_4b: +1: + j 1b + .size _nds32_vector_29_4b, .-_nds32_vector_29_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid30.S b/libgcc/config/nds32/isr-library/vec_vid30.S new file mode 100644 index 00000000000..e08d7e8be0f --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid30.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.30, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_30 + .type _nds32_vector_30, @function +_nds32_vector_30: +1: + j 1b + .size _nds32_vector_30, .-_nds32_vector_30 diff --git a/libgcc/config/nds32/isr-library/vec_vid30_4b.S b/libgcc/config/nds32/isr-library/vec_vid30_4b.S new file mode 100644 index 00000000000..36265727377 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid30_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.30, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_30_4b + .type _nds32_vector_30_4b, @function +_nds32_vector_30_4b: +1: + j 1b + .size _nds32_vector_30_4b, .-_nds32_vector_30_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid31.S b/libgcc/config/nds32/isr-library/vec_vid31.S new file mode 100644 index 00000000000..b6aba1d2c40 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid31.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.31, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_31 + .type _nds32_vector_31, @function +_nds32_vector_31: +1: + j 1b + .size _nds32_vector_31, .-_nds32_vector_31 diff --git a/libgcc/config/nds32/isr-library/vec_vid31_4b.S b/libgcc/config/nds32/isr-library/vec_vid31_4b.S new file mode 100644 index 00000000000..460bf5266da --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid31_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.31, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_31_4b + .type _nds32_vector_31_4b, @function +_nds32_vector_31_4b: +1: + j 1b + .size _nds32_vector_31_4b, .-_nds32_vector_31_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid32.S b/libgcc/config/nds32/isr-library/vec_vid32.S new file mode 100644 index 00000000000..278e191b43e --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid32.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.32, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_32 + .type _nds32_vector_32, @function +_nds32_vector_32: +1: + j 1b + .size _nds32_vector_32, .-_nds32_vector_32 diff --git a/libgcc/config/nds32/isr-library/vec_vid32_4b.S b/libgcc/config/nds32/isr-library/vec_vid32_4b.S new file mode 100644 index 00000000000..d3b74f8129c --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid32_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.32, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_32_4b + .type _nds32_vector_32_4b, @function +_nds32_vector_32_4b: +1: + j 1b + .size _nds32_vector_32_4b, .-_nds32_vector_32_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid33.S b/libgcc/config/nds32/isr-library/vec_vid33.S new file mode 100644 index 00000000000..320289db05e --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid33.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.33, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_33 + .type _nds32_vector_33, @function +_nds32_vector_33: +1: + j 1b + .size _nds32_vector_33, .-_nds32_vector_33 diff --git a/libgcc/config/nds32/isr-library/vec_vid33_4b.S b/libgcc/config/nds32/isr-library/vec_vid33_4b.S new file mode 100644 index 00000000000..fd3c997697e --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid33_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.33, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_33_4b + .type _nds32_vector_33_4b, @function +_nds32_vector_33_4b: +1: + j 1b + .size _nds32_vector_33_4b, .-_nds32_vector_33_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid34.S b/libgcc/config/nds32/isr-library/vec_vid34.S new file mode 100644 index 00000000000..b9a99893386 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid34.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.34, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_34 + .type _nds32_vector_34, @function +_nds32_vector_34: +1: + j 1b + .size _nds32_vector_34, .-_nds32_vector_34 diff --git a/libgcc/config/nds32/isr-library/vec_vid34_4b.S b/libgcc/config/nds32/isr-library/vec_vid34_4b.S new file mode 100644 index 00000000000..0b726f6790c --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid34_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.34, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_34_4b + .type _nds32_vector_34_4b, @function +_nds32_vector_34_4b: +1: + j 1b + .size _nds32_vector_34_4b, .-_nds32_vector_34_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid35.S b/libgcc/config/nds32/isr-library/vec_vid35.S new file mode 100644 index 00000000000..e53017d88da --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid35.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.35, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_35 + .type _nds32_vector_35, @function +_nds32_vector_35: +1: + j 1b + .size _nds32_vector_35, .-_nds32_vector_35 diff --git a/libgcc/config/nds32/isr-library/vec_vid35_4b.S b/libgcc/config/nds32/isr-library/vec_vid35_4b.S new file mode 100644 index 00000000000..7ac998faa6d --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid35_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.35, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_35_4b + .type _nds32_vector_35_4b, @function +_nds32_vector_35_4b: +1: + j 1b + .size _nds32_vector_35_4b, .-_nds32_vector_35_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid36.S b/libgcc/config/nds32/isr-library/vec_vid36.S new file mode 100644 index 00000000000..2d3779c9ef5 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid36.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.36, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_36 + .type _nds32_vector_36, @function +_nds32_vector_36: +1: + j 1b + .size _nds32_vector_36, .-_nds32_vector_36 diff --git a/libgcc/config/nds32/isr-library/vec_vid36_4b.S b/libgcc/config/nds32/isr-library/vec_vid36_4b.S new file mode 100644 index 00000000000..54230ac22b7 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid36_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.36, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_36_4b + .type _nds32_vector_36_4b, @function +_nds32_vector_36_4b: +1: + j 1b + .size _nds32_vector_36_4b, .-_nds32_vector_36_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid37.S b/libgcc/config/nds32/isr-library/vec_vid37.S new file mode 100644 index 00000000000..1b4066f99d3 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid37.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.37, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_37 + .type _nds32_vector_37, @function +_nds32_vector_37: +1: + j 1b + .size _nds32_vector_37, .-_nds32_vector_37 diff --git a/libgcc/config/nds32/isr-library/vec_vid37_4b.S b/libgcc/config/nds32/isr-library/vec_vid37_4b.S new file mode 100644 index 00000000000..f3a50b2f60e --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid37_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.37, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_37_4b + .type _nds32_vector_37_4b, @function +_nds32_vector_37_4b: +1: + j 1b + .size _nds32_vector_37_4b, .-_nds32_vector_37_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid38.S b/libgcc/config/nds32/isr-library/vec_vid38.S new file mode 100644 index 00000000000..d626d3c3703 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid38.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.38, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_38 + .type _nds32_vector_38, @function +_nds32_vector_38: +1: + j 1b + .size _nds32_vector_38, .-_nds32_vector_38 diff --git a/libgcc/config/nds32/isr-library/vec_vid38_4b.S b/libgcc/config/nds32/isr-library/vec_vid38_4b.S new file mode 100644 index 00000000000..677145fea4d --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid38_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.38, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_38_4b + .type _nds32_vector_38_4b, @function +_nds32_vector_38_4b: +1: + j 1b + .size _nds32_vector_38_4b, .-_nds32_vector_38_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid39.S b/libgcc/config/nds32/isr-library/vec_vid39.S new file mode 100644 index 00000000000..bbb376378e0 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid39.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.39, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_39 + .type _nds32_vector_39, @function +_nds32_vector_39: +1: + j 1b + .size _nds32_vector_39, .-_nds32_vector_39 diff --git a/libgcc/config/nds32/isr-library/vec_vid39_4b.S b/libgcc/config/nds32/isr-library/vec_vid39_4b.S new file mode 100644 index 00000000000..b5cd07e6a6d --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid39_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.39, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_39_4b + .type _nds32_vector_39_4b, @function +_nds32_vector_39_4b: +1: + j 1b + .size _nds32_vector_39_4b, .-_nds32_vector_39_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid40.S b/libgcc/config/nds32/isr-library/vec_vid40.S new file mode 100644 index 00000000000..48c2eea7537 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid40.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.40, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_40 + .type _nds32_vector_40, @function +_nds32_vector_40: +1: + j 1b + .size _nds32_vector_40, .-_nds32_vector_40 diff --git a/libgcc/config/nds32/isr-library/vec_vid40_4b.S b/libgcc/config/nds32/isr-library/vec_vid40_4b.S new file mode 100644 index 00000000000..201988c43db --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid40_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.40, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_40_4b + .type _nds32_vector_40_4b, @function +_nds32_vector_40_4b: +1: + j 1b + .size _nds32_vector_40_4b, .-_nds32_vector_40_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid41.S b/libgcc/config/nds32/isr-library/vec_vid41.S new file mode 100644 index 00000000000..7be5dfdf55d --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid41.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.41, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_41 + .type _nds32_vector_41, @function +_nds32_vector_41: +1: + j 1b + .size _nds32_vector_41, .-_nds32_vector_41 diff --git a/libgcc/config/nds32/isr-library/vec_vid41_4b.S b/libgcc/config/nds32/isr-library/vec_vid41_4b.S new file mode 100644 index 00000000000..1b8b57132ea --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid41_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.41, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_41_4b + .type _nds32_vector_41_4b, @function +_nds32_vector_41_4b: +1: + j 1b + .size _nds32_vector_41_4b, .-_nds32_vector_41_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid42.S b/libgcc/config/nds32/isr-library/vec_vid42.S new file mode 100644 index 00000000000..f16127ba843 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid42.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.42, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_42 + .type _nds32_vector_42, @function +_nds32_vector_42: +1: + j 1b + .size _nds32_vector_42, .-_nds32_vector_42 diff --git a/libgcc/config/nds32/isr-library/vec_vid42_4b.S b/libgcc/config/nds32/isr-library/vec_vid42_4b.S new file mode 100644 index 00000000000..9bf7a5dff32 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid42_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.42, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_42_4b + .type _nds32_vector_42_4b, @function +_nds32_vector_42_4b: +1: + j 1b + .size _nds32_vector_42_4b, .-_nds32_vector_42_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid43.S b/libgcc/config/nds32/isr-library/vec_vid43.S new file mode 100644 index 00000000000..eecfa98e5c2 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid43.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.43, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_43 + .type _nds32_vector_43, @function +_nds32_vector_43: +1: + j 1b + .size _nds32_vector_43, .-_nds32_vector_43 diff --git a/libgcc/config/nds32/isr-library/vec_vid43_4b.S b/libgcc/config/nds32/isr-library/vec_vid43_4b.S new file mode 100644 index 00000000000..0c9e5a44ffb --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid43_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.43, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_43_4b + .type _nds32_vector_43_4b, @function +_nds32_vector_43_4b: +1: + j 1b + .size _nds32_vector_43_4b, .-_nds32_vector_43_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid44.S b/libgcc/config/nds32/isr-library/vec_vid44.S new file mode 100644 index 00000000000..47e24a41831 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid44.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.44, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_44 + .type _nds32_vector_44, @function +_nds32_vector_44: +1: + j 1b + .size _nds32_vector_44, .-_nds32_vector_44 diff --git a/libgcc/config/nds32/isr-library/vec_vid44_4b.S b/libgcc/config/nds32/isr-library/vec_vid44_4b.S new file mode 100644 index 00000000000..43aa995b1e5 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid44_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.44, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_44_4b + .type _nds32_vector_44_4b, @function +_nds32_vector_44_4b: +1: + j 1b + .size _nds32_vector_44_4b, .-_nds32_vector_44_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid45.S b/libgcc/config/nds32/isr-library/vec_vid45.S new file mode 100644 index 00000000000..711aba55969 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid45.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.45, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_45 + .type _nds32_vector_45, @function +_nds32_vector_45: +1: + j 1b + .size _nds32_vector_45, .-_nds32_vector_45 diff --git a/libgcc/config/nds32/isr-library/vec_vid45_4b.S b/libgcc/config/nds32/isr-library/vec_vid45_4b.S new file mode 100644 index 00000000000..96b505ead26 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid45_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.45, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_45_4b + .type _nds32_vector_45_4b, @function +_nds32_vector_45_4b: +1: + j 1b + .size _nds32_vector_45_4b, .-_nds32_vector_45_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid46.S b/libgcc/config/nds32/isr-library/vec_vid46.S new file mode 100644 index 00000000000..0c86a8c4eb4 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid46.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.46, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_46 + .type _nds32_vector_46, @function +_nds32_vector_46: +1: + j 1b + .size _nds32_vector_46, .-_nds32_vector_46 diff --git a/libgcc/config/nds32/isr-library/vec_vid46_4b.S b/libgcc/config/nds32/isr-library/vec_vid46_4b.S new file mode 100644 index 00000000000..1e3dee61f5c --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid46_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.46, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_46_4b + .type _nds32_vector_46_4b, @function +_nds32_vector_46_4b: +1: + j 1b + .size _nds32_vector_46_4b, .-_nds32_vector_46_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid47.S b/libgcc/config/nds32/isr-library/vec_vid47.S new file mode 100644 index 00000000000..72954018559 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid47.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.47, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_47 + .type _nds32_vector_47, @function +_nds32_vector_47: +1: + j 1b + .size _nds32_vector_47, .-_nds32_vector_47 diff --git a/libgcc/config/nds32/isr-library/vec_vid47_4b.S b/libgcc/config/nds32/isr-library/vec_vid47_4b.S new file mode 100644 index 00000000000..e8556c21fbc --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid47_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.47, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_47_4b + .type _nds32_vector_47_4b, @function +_nds32_vector_47_4b: +1: + j 1b + .size _nds32_vector_47_4b, .-_nds32_vector_47_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid48.S b/libgcc/config/nds32/isr-library/vec_vid48.S new file mode 100644 index 00000000000..92c583aecb4 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid48.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.48, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_48 + .type _nds32_vector_48, @function +_nds32_vector_48: +1: + j 1b + .size _nds32_vector_48, .-_nds32_vector_48 diff --git a/libgcc/config/nds32/isr-library/vec_vid48_4b.S b/libgcc/config/nds32/isr-library/vec_vid48_4b.S new file mode 100644 index 00000000000..c998a55f90f --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid48_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.48, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_48_4b + .type _nds32_vector_48_4b, @function +_nds32_vector_48_4b: +1: + j 1b + .size _nds32_vector_48_4b, .-_nds32_vector_48_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid49.S b/libgcc/config/nds32/isr-library/vec_vid49.S new file mode 100644 index 00000000000..c1b1677d032 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid49.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.49, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_49 + .type _nds32_vector_49, @function +_nds32_vector_49: +1: + j 1b + .size _nds32_vector_49, .-_nds32_vector_49 diff --git a/libgcc/config/nds32/isr-library/vec_vid49_4b.S b/libgcc/config/nds32/isr-library/vec_vid49_4b.S new file mode 100644 index 00000000000..0c18eee1761 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid49_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.49, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_49_4b + .type _nds32_vector_49_4b, @function +_nds32_vector_49_4b: +1: + j 1b + .size _nds32_vector_49_4b, .-_nds32_vector_49_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid50.S b/libgcc/config/nds32/isr-library/vec_vid50.S new file mode 100644 index 00000000000..910ad028436 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid50.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.50, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_50 + .type _nds32_vector_50, @function +_nds32_vector_50: +1: + j 1b + .size _nds32_vector_50, .-_nds32_vector_50 diff --git a/libgcc/config/nds32/isr-library/vec_vid50_4b.S b/libgcc/config/nds32/isr-library/vec_vid50_4b.S new file mode 100644 index 00000000000..1ec0b700244 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid50_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.50, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_50_4b + .type _nds32_vector_50_4b, @function +_nds32_vector_50_4b: +1: + j 1b + .size _nds32_vector_50_4b, .-_nds32_vector_50_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid51.S b/libgcc/config/nds32/isr-library/vec_vid51.S new file mode 100644 index 00000000000..2053ebccf3a --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid51.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.51, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_51 + .type _nds32_vector_51, @function +_nds32_vector_51: +1: + j 1b + .size _nds32_vector_51, .-_nds32_vector_51 diff --git a/libgcc/config/nds32/isr-library/vec_vid51_4b.S b/libgcc/config/nds32/isr-library/vec_vid51_4b.S new file mode 100644 index 00000000000..38c02107ce5 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid51_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.51, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_51_4b + .type _nds32_vector_51_4b, @function +_nds32_vector_51_4b: +1: + j 1b + .size _nds32_vector_51_4b, .-_nds32_vector_51_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid52.S b/libgcc/config/nds32/isr-library/vec_vid52.S new file mode 100644 index 00000000000..6eaac798038 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid52.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.52, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_52 + .type _nds32_vector_52, @function +_nds32_vector_52: +1: + j 1b + .size _nds32_vector_52, .-_nds32_vector_52 diff --git a/libgcc/config/nds32/isr-library/vec_vid52_4b.S b/libgcc/config/nds32/isr-library/vec_vid52_4b.S new file mode 100644 index 00000000000..de8a9283042 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid52_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.52, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_52_4b + .type _nds32_vector_52_4b, @function +_nds32_vector_52_4b: +1: + j 1b + .size _nds32_vector_52_4b, .-_nds32_vector_52_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid53.S b/libgcc/config/nds32/isr-library/vec_vid53.S new file mode 100644 index 00000000000..8ac761394b1 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid53.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.53, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_53 + .type _nds32_vector_53, @function +_nds32_vector_53: +1: + j 1b + .size _nds32_vector_53, .-_nds32_vector_53 diff --git a/libgcc/config/nds32/isr-library/vec_vid53_4b.S b/libgcc/config/nds32/isr-library/vec_vid53_4b.S new file mode 100644 index 00000000000..564346c2347 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid53_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.53, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_53_4b + .type _nds32_vector_53_4b, @function +_nds32_vector_53_4b: +1: + j 1b + .size _nds32_vector_53_4b, .-_nds32_vector_53_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid54.S b/libgcc/config/nds32/isr-library/vec_vid54.S new file mode 100644 index 00000000000..ef222ada15d --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid54.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.54, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_54 + .type _nds32_vector_54, @function +_nds32_vector_54: +1: + j 1b + .size _nds32_vector_54, .-_nds32_vector_54 diff --git a/libgcc/config/nds32/isr-library/vec_vid54_4b.S b/libgcc/config/nds32/isr-library/vec_vid54_4b.S new file mode 100644 index 00000000000..104b7e7958e --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid54_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.54, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_54_4b + .type _nds32_vector_54_4b, @function +_nds32_vector_54_4b: +1: + j 1b + .size _nds32_vector_54_4b, .-_nds32_vector_54_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid55.S b/libgcc/config/nds32/isr-library/vec_vid55.S new file mode 100644 index 00000000000..c061e69f1b9 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid55.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.55, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_55 + .type _nds32_vector_55, @function +_nds32_vector_55: +1: + j 1b + .size _nds32_vector_55, .-_nds32_vector_55 diff --git a/libgcc/config/nds32/isr-library/vec_vid55_4b.S b/libgcc/config/nds32/isr-library/vec_vid55_4b.S new file mode 100644 index 00000000000..15fced687f2 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid55_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.55, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_55_4b + .type _nds32_vector_55_4b, @function +_nds32_vector_55_4b: +1: + j 1b + .size _nds32_vector_55_4b, .-_nds32_vector_55_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid56.S b/libgcc/config/nds32/isr-library/vec_vid56.S new file mode 100644 index 00000000000..d7c305a8754 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid56.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.56, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_56 + .type _nds32_vector_56, @function +_nds32_vector_56: +1: + j 1b + .size _nds32_vector_56, .-_nds32_vector_56 diff --git a/libgcc/config/nds32/isr-library/vec_vid56_4b.S b/libgcc/config/nds32/isr-library/vec_vid56_4b.S new file mode 100644 index 00000000000..e8b975c8f41 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid56_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.56, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_56_4b + .type _nds32_vector_56_4b, @function +_nds32_vector_56_4b: +1: + j 1b + .size _nds32_vector_56_4b, .-_nds32_vector_56_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid57.S b/libgcc/config/nds32/isr-library/vec_vid57.S new file mode 100644 index 00000000000..b701bbab67f --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid57.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.57, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_57 + .type _nds32_vector_57, @function +_nds32_vector_57: +1: + j 1b + .size _nds32_vector_57, .-_nds32_vector_57 diff --git a/libgcc/config/nds32/isr-library/vec_vid57_4b.S b/libgcc/config/nds32/isr-library/vec_vid57_4b.S new file mode 100644 index 00000000000..ef29203f607 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid57_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.57, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_57_4b + .type _nds32_vector_57_4b, @function +_nds32_vector_57_4b: +1: + j 1b + .size _nds32_vector_57_4b, .-_nds32_vector_57_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid58.S b/libgcc/config/nds32/isr-library/vec_vid58.S new file mode 100644 index 00000000000..211b27dae59 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid58.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.58, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_58 + .type _nds32_vector_58, @function +_nds32_vector_58: +1: + j 1b + .size _nds32_vector_58, .-_nds32_vector_58 diff --git a/libgcc/config/nds32/isr-library/vec_vid58_4b.S b/libgcc/config/nds32/isr-library/vec_vid58_4b.S new file mode 100644 index 00000000000..9eaefca6c49 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid58_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.58, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_58_4b + .type _nds32_vector_58_4b, @function +_nds32_vector_58_4b: +1: + j 1b + .size _nds32_vector_58_4b, .-_nds32_vector_58_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid59.S b/libgcc/config/nds32/isr-library/vec_vid59.S new file mode 100644 index 00000000000..227edf2e097 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid59.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.59, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_59 + .type _nds32_vector_59, @function +_nds32_vector_59: +1: + j 1b + .size _nds32_vector_59, .-_nds32_vector_59 diff --git a/libgcc/config/nds32/isr-library/vec_vid59_4b.S b/libgcc/config/nds32/isr-library/vec_vid59_4b.S new file mode 100644 index 00000000000..30fccab1ca3 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid59_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.59, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_59_4b + .type _nds32_vector_59_4b, @function +_nds32_vector_59_4b: +1: + j 1b + .size _nds32_vector_59_4b, .-_nds32_vector_59_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid60.S b/libgcc/config/nds32/isr-library/vec_vid60.S new file mode 100644 index 00000000000..68889685825 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid60.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.60, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_60 + .type _nds32_vector_60, @function +_nds32_vector_60: +1: + j 1b + .size _nds32_vector_60, .-_nds32_vector_60 diff --git a/libgcc/config/nds32/isr-library/vec_vid60_4b.S b/libgcc/config/nds32/isr-library/vec_vid60_4b.S new file mode 100644 index 00000000000..26d94ac5f96 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid60_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.60, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_60_4b + .type _nds32_vector_60_4b, @function +_nds32_vector_60_4b: +1: + j 1b + .size _nds32_vector_60_4b, .-_nds32_vector_60_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid61.S b/libgcc/config/nds32/isr-library/vec_vid61.S new file mode 100644 index 00000000000..b3111e75c35 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid61.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.61, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_61 + .type _nds32_vector_61, @function +_nds32_vector_61: +1: + j 1b + .size _nds32_vector_61, .-_nds32_vector_61 diff --git a/libgcc/config/nds32/isr-library/vec_vid61_4b.S b/libgcc/config/nds32/isr-library/vec_vid61_4b.S new file mode 100644 index 00000000000..845125cf3ec --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid61_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.61, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_61_4b + .type _nds32_vector_61_4b, @function +_nds32_vector_61_4b: +1: + j 1b + .size _nds32_vector_61_4b, .-_nds32_vector_61_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid62.S b/libgcc/config/nds32/isr-library/vec_vid62.S new file mode 100644 index 00000000000..d6342381b22 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid62.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.62, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_62 + .type _nds32_vector_62, @function +_nds32_vector_62: +1: + j 1b + .size _nds32_vector_62, .-_nds32_vector_62 diff --git a/libgcc/config/nds32/isr-library/vec_vid62_4b.S b/libgcc/config/nds32/isr-library/vec_vid62_4b.S new file mode 100644 index 00000000000..d4c4413dd73 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid62_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.62, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_62_4b + .type _nds32_vector_62_4b, @function +_nds32_vector_62_4b: +1: + j 1b + .size _nds32_vector_62_4b, .-_nds32_vector_62_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid63.S b/libgcc/config/nds32/isr-library/vec_vid63.S new file mode 100644 index 00000000000..8d2770c3f21 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid63.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.63, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_63 + .type _nds32_vector_63, @function +_nds32_vector_63: +1: + j 1b + .size _nds32_vector_63, .-_nds32_vector_63 diff --git a/libgcc/config/nds32/isr-library/vec_vid63_4b.S b/libgcc/config/nds32/isr-library/vec_vid63_4b.S new file mode 100644 index 00000000000..6403a7b6ed7 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid63_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.63, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_63_4b + .type _nds32_vector_63_4b, @function +_nds32_vector_63_4b: +1: + j 1b + .size _nds32_vector_63_4b, .-_nds32_vector_63_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid64.S b/libgcc/config/nds32/isr-library/vec_vid64.S new file mode 100644 index 00000000000..269bdf92f75 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid64.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.64, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_64 + .type _nds32_vector_64, @function +_nds32_vector_64: +1: + j 1b + .size _nds32_vector_64, .-_nds32_vector_64 diff --git a/libgcc/config/nds32/isr-library/vec_vid64_4b.S b/libgcc/config/nds32/isr-library/vec_vid64_4b.S new file mode 100644 index 00000000000..64691899043 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid64_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.64, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_64_4b + .type _nds32_vector_64_4b, @function +_nds32_vector_64_4b: +1: + j 1b + .size _nds32_vector_64_4b, .-_nds32_vector_64_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid65.S b/libgcc/config/nds32/isr-library/vec_vid65.S new file mode 100644 index 00000000000..4fbf3e43b8c --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid65.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.65, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_65 + .type _nds32_vector_65, @function +_nds32_vector_65: +1: + j 1b + .size _nds32_vector_65, .-_nds32_vector_65 diff --git a/libgcc/config/nds32/isr-library/vec_vid65_4b.S b/libgcc/config/nds32/isr-library/vec_vid65_4b.S new file mode 100644 index 00000000000..25f0a8773f7 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid65_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.65, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_65_4b + .type _nds32_vector_65_4b, @function +_nds32_vector_65_4b: +1: + j 1b + .size _nds32_vector_65_4b, .-_nds32_vector_65_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid66.S b/libgcc/config/nds32/isr-library/vec_vid66.S new file mode 100644 index 00000000000..ad8d6d2a475 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid66.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.66, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_66 + .type _nds32_vector_66, @function +_nds32_vector_66: +1: + j 1b + .size _nds32_vector_66, .-_nds32_vector_66 diff --git a/libgcc/config/nds32/isr-library/vec_vid66_4b.S b/libgcc/config/nds32/isr-library/vec_vid66_4b.S new file mode 100644 index 00000000000..d283d4337cf --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid66_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.66, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_66_4b + .type _nds32_vector_66_4b, @function +_nds32_vector_66_4b: +1: + j 1b + .size _nds32_vector_66_4b, .-_nds32_vector_66_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid67.S b/libgcc/config/nds32/isr-library/vec_vid67.S new file mode 100644 index 00000000000..f3a97a6db7e --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid67.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.67, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_67 + .type _nds32_vector_67, @function +_nds32_vector_67: +1: + j 1b + .size _nds32_vector_67, .-_nds32_vector_67 diff --git a/libgcc/config/nds32/isr-library/vec_vid67_4b.S b/libgcc/config/nds32/isr-library/vec_vid67_4b.S new file mode 100644 index 00000000000..fb8283dcf9f --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid67_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.67, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_67_4b + .type _nds32_vector_67_4b, @function +_nds32_vector_67_4b: +1: + j 1b + .size _nds32_vector_67_4b, .-_nds32_vector_67_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid68.S b/libgcc/config/nds32/isr-library/vec_vid68.S new file mode 100644 index 00000000000..815f4368633 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid68.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.68, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_68 + .type _nds32_vector_68, @function +_nds32_vector_68: +1: + j 1b + .size _nds32_vector_68, .-_nds32_vector_68 diff --git a/libgcc/config/nds32/isr-library/vec_vid68_4b.S b/libgcc/config/nds32/isr-library/vec_vid68_4b.S new file mode 100644 index 00000000000..94959a8cd1d --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid68_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.68, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_68_4b + .type _nds32_vector_68_4b, @function +_nds32_vector_68_4b: +1: + j 1b + .size _nds32_vector_68_4b, .-_nds32_vector_68_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid69.S b/libgcc/config/nds32/isr-library/vec_vid69.S new file mode 100644 index 00000000000..cd1d17c605d --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid69.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.69, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_69 + .type _nds32_vector_69, @function +_nds32_vector_69: +1: + j 1b + .size _nds32_vector_69, .-_nds32_vector_69 diff --git a/libgcc/config/nds32/isr-library/vec_vid69_4b.S b/libgcc/config/nds32/isr-library/vec_vid69_4b.S new file mode 100644 index 00000000000..df0f7d36842 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid69_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.69, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_69_4b + .type _nds32_vector_69_4b, @function +_nds32_vector_69_4b: +1: + j 1b + .size _nds32_vector_69_4b, .-_nds32_vector_69_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid70.S b/libgcc/config/nds32/isr-library/vec_vid70.S new file mode 100644 index 00000000000..4a2edce903b --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid70.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.70, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_70 + .type _nds32_vector_70, @function +_nds32_vector_70: +1: + j 1b + .size _nds32_vector_70, .-_nds32_vector_70 diff --git a/libgcc/config/nds32/isr-library/vec_vid70_4b.S b/libgcc/config/nds32/isr-library/vec_vid70_4b.S new file mode 100644 index 00000000000..cb12f9f3fd2 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid70_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.70, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_70_4b + .type _nds32_vector_70_4b, @function +_nds32_vector_70_4b: +1: + j 1b + .size _nds32_vector_70_4b, .-_nds32_vector_70_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid71.S b/libgcc/config/nds32/isr-library/vec_vid71.S new file mode 100644 index 00000000000..9ae82659ce5 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid71.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.71, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_71 + .type _nds32_vector_71, @function +_nds32_vector_71: +1: + j 1b + .size _nds32_vector_71, .-_nds32_vector_71 diff --git a/libgcc/config/nds32/isr-library/vec_vid71_4b.S b/libgcc/config/nds32/isr-library/vec_vid71_4b.S new file mode 100644 index 00000000000..4f640b9b340 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid71_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.71, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_71_4b + .type _nds32_vector_71_4b, @function +_nds32_vector_71_4b: +1: + j 1b + .size _nds32_vector_71_4b, .-_nds32_vector_71_4b diff --git a/libgcc/config/nds32/isr-library/vec_vid72.S b/libgcc/config/nds32/isr-library/vec_vid72.S new file mode 100644 index 00000000000..ab07fdb0dd3 --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid72.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.72, "ax" + .vec_size 16 + .align 4 + .weak _nds32_vector_72 + .type _nds32_vector_72, @function +_nds32_vector_72: +1: + j 1b + .size _nds32_vector_72, .-_nds32_vector_72 diff --git a/libgcc/config/nds32/isr-library/vec_vid72_4b.S b/libgcc/config/nds32/isr-library/vec_vid72_4b.S new file mode 100644 index 00000000000..d3864e1024c --- /dev/null +++ b/libgcc/config/nds32/isr-library/vec_vid72_4b.S @@ -0,0 +1,34 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_vector.72, "ax" + .vec_size 4 + .align 2 + .weak _nds32_vector_72_4b + .type _nds32_vector_72_4b, @function +_nds32_vector_72_4b: +1: + j 1b + .size _nds32_vector_72_4b, .-_nds32_vector_72_4b diff --git a/libgcc/config/nds32/isr-library/wrh.S b/libgcc/config/nds32/isr-library/wrh.S new file mode 100644 index 00000000000..fe964a51578 --- /dev/null +++ b/libgcc/config/nds32/isr-library/wrh.S @@ -0,0 +1,32 @@ +/* c-isr library stuff of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .nds32_wrh, "a" + .align 2 + .weak _nds32_wrh + .type _nds32_wrh, @object +_nds32_wrh: + .word 0 + .size _nds32_wrh, .-_nds32_wrh diff --git a/libgcc/config/nds32/lib1asmsrc-mculib.S b/libgcc/config/nds32/lib1asmsrc-mculib.S new file mode 100644 index 00000000000..25295b6a9f2 --- /dev/null +++ b/libgcc/config/nds32/lib1asmsrc-mculib.S @@ -0,0 +1,5213 @@ +/* mculib libgcc routines of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .mdebug.abi_nds32 + .previous + + +/* ------------------------------------------- */ +/* FPBIT floating point operations for libgcc */ +/* ------------------------------------------- */ + +#ifdef L_addsub_sf + + .text + .align 2 + .global __subsf3 + .type __subsf3, @function +__subsf3: + push $lp + pushm $r6, $r9 + + move $r2, #0x80000000 + xor $r1, $r1, $r2 + + j .Lsfpadd + + .global __addsf3 + .type __addsf3, @function +__addsf3: + push $lp + pushm $r6, $r9 +.Lsfpadd: + srli $r5, $r0, #23 + andi $r5, $r5, #0xff + srli $r7, $r1, #23 + andi $r7, $r7, #0xff + move $r3, #0x80000000 + slli $r4, $r0, #8 + or $r4, $r4, $r3 + slli $r6, $r1, #8 + or $r6, $r6, $r3 + + addi $r9, $r5, #-1 + slti $r15, $r9, #0xfe + beqzs8 .LEspecA + +.LElab1: + addi $r9, $r7, #-1 + slti $r15, $r9, #0xfe + beqzs8 .LEspecB + +.LElab2: + sub $r8, $r5, $r7 + sltsi $r15, $r8, #0 + bnezs8 .Li1 + sltsi $r15, $r8, #0x20 + bnezs8 .Li2 + move $r6, #2 + j .Le1 +.Li2: + move $r2, $r6 + srl $r6, $r6, $r8 + sll $r9, $r6, $r8 + beq $r9, $r2, .Le1 + ori $r6, $r6, #2 + j .Le1 +.Li1: + move $r5, $r7 + subri $r8, $r8, #0 + sltsi $r15, $r8, #0x20 + bnezs8 .Li4 + move $r4, #2 + j .Le1 +.Li4: + move $r2, $r4 + srl $r4, $r4, $r8 + sll $r9, $r4, $r8 + beq $r9, $r2, .Le1 + ori $r4, $r4, #2 + +.Le1: + and $r8, $r0, $r3 + xor $r9, $r8, $r1 + sltsi $r15, $r9, #0 + bnezs8 .LEsub1 + + #ADD($r4, $r6) + add $r4, $r4, $r6 + slt $r15, $r4, $r6 + beqzs8 .LEres + andi $r9, $r4, #1 + beqz $r9, .Li7 + ori $r4, $r4, #2 +.Li7: + srli $r4, $r4, #1 + addi $r5, $r5, #1 + subri $r15, $r5, #0xff + bnezs8 .LEres + move $r4, #0 + j .LEres + +.LEsub1: + #SUB($r4, $r6) + move $r15, $r4 + sub $r4, $r4, $r6 + slt $r15, $r15, $r4 + beqzs8 .Li9 + subri $r4, $r4, #0 + xor $r8, $r8, $r3 + j .Le9 +.Li9: + beqz $r4, .LEzer +.Le9: +#ifdef __NDS32_PERF_EXT__ + clz $r2, $r4 +#else + pushm $r0, $r1 + pushm $r3, $r5 + move $r0, $r4 + bal __clzsi2 + move $r2, $r0 + popm $r3, $r5 + popm $r0, $r1 +#endif + sub $r5, $r5, $r2 + sll $r4, $r4, $r2 + +.LEres: + blez $r5, .LEund + +.LElab12: + #ADD($r4, $0x80) + move $r15, #0x80 + add $r4, $r4, $r15 + slt $r15, $r4, $r15 + + #ADDC($r5, $0x0) + add $r5, $r5, $r15 + srli $r9, $r4, #8 + andi $r9, $r9, #1 + sub $r4, $r4, $r9 + slli $r4, $r4, #1 + srli $r4, $r4, #9 + slli $r9, $r5, #23 + or $r4, $r4, $r9 + or $r0, $r4, $r8 + +.LE999: + popm $r6, $r9 + pop $lp + ret5 $lp + +.LEund: + subri $r2, $r5, #1 + slti $r15, $r2, #0x20 + beqzs8 .LEzer + move $r9, #0x80000000 + or $r4, $r4, $r9 + subri $r9, $r2, #0x20 + sll $r5, $r4, $r9 + srl $r4, $r4, $r2 + beqz $r5, .Li10 + ori $r4, $r4, #1 +.Li10: + move $r5, #0 + addi $r9, $r4, #0x80 + sltsi $r15, $r9, #0 + beqzs8 .LElab12 + move $r5, #1 + j .LElab12 + +.LEspecA: + bnez $r5, .Li12 + add $r4, $r4, $r4 + beqz $r4, .Li13 +#ifdef __NDS32_PERF_EXT__ + clz $r8, $r4 +#else + pushm $r0, $r5 + move $r0, $r4 + bal __clzsi2 + move $r8, $r0 + popm $r0, $r5 +#endif + sub $r5, $r5, $r8 + sll $r4, $r4, $r8 + j .LElab1 +.Li13: + subri $r15, $r7, #0xff + beqzs8 .LEspecB + move $r9, #0x80000000 + bne $r1, $r9, .LEretB +.Li12: + add $r9, $r4, $r4 + bnez $r9, .LEnan + subri $r15, $r7, #0xff + bnezs8 .LEretA + xor $r9, $r0, $r1 + sltsi $r15, $r9, #0 + bnezs8 .LEnan + j .LEretB + +.LEspecB: + bnez $r7, .Li15 + add $r6, $r6, $r6 + beqz $r6, .LEretA +#ifdef __NDS32_PERF_EXT__ + clz $r8, $r6 +#else + pushm $r0, $r5 + move $r0, $r6 + bal __clzsi2 + move $r8, $r0 + popm $r0, $r5 +#endif + sub $r7, $r7, $r8 + sll $r6, $r6, $r8 + j .LElab2 +.Li15: + add $r9, $r6, $r6 + bnez $r9, .LEnan + +.LEretB: + move $r0, $r1 + j .LE999 + +.LEretA: + j .LE999 + +.LEzer: + move $r0, #0 + j .LE999 + +.LEnan: + move $r0, #0xffc00000 + j .LE999 + .size __subsf3, .-__subsf3 + .size __addsf3, .-__addsf3 +#endif /* L_addsub_sf */ + + + +#ifdef L_sf_to_si + + .text + .align 2 + .global __fixsfsi + .type __fixsfsi, @function +__fixsfsi: + push $lp + + slli $r1, $r0, #8 + move $r3, #0x80000000 + or $r1, $r1, $r3 + srli $r3, $r0, #23 + andi $r3, $r3, #0xff + subri $r2, $r3, #0x9e + blez $r2, .LJspec + sltsi $r15, $r2, #0x20 + bnezs8 .Li42 + move $r0, #0 + j .LJ999 +.Li42: + srl $r1, $r1, $r2 + sltsi $r15, $r0, #0 + beqzs8 .Li43 + subri $r1, $r1, #0 +.Li43: + move $r0, $r1 + +.LJ999: + pop $lp + ret5 $lp + +.LJspec: + move $r3, #0x7f800000 + slt $r15, $r3, $r0 + beqzs8 .Li44 + move $r0, #0x80000000 + j .LJ999 +.Li44: + move $r0, #0x7fffffff + j .LJ999 + .size __fixsfsi, .-__fixsfsi +#endif /* L_sf_to_si */ + + + +#ifdef L_divsi3 + + .text + .align 2 + .globl __divsi3 + .type __divsi3, @function +__divsi3: + ! --------------------------------------------------------------------- + ! neg = 0; + ! if (a < 0) + ! { a = -a; + ! neg = !neg; + ! } + ! --------------------------------------------------------------------- + sltsi $r5, $r0, 0 ! $r5 <- neg = (a < 0) ? 1 : 0 + subri $r4, $r0, 0 ! $r4 <- a = -a + cmovn $r0, $r4, $r5 ! $r0 <- a = neg ? -a : a +.L2: + ! --------------------------------------------------------------------- + ! if (b < 0) + ! --------------------------------------------------------------------- + bgez $r1, .L3 ! if b >= 0, skip + ! --------------------------------------------------------------------- + ! { b=-b; + ! neg=!neg; + ! } + ! --------------------------------------------------------------------- + subri $r1, $r1, 0 ! $r1 <- b = -b + subri $r5, $r5, 1 ! $r5 <- neg = !neg +.L3: + ! --------------------------------------------------------------------- + !!res = udivmodsi4 (a, b, 1); + ! res = 0; + ! if (den != 0) + ! --------------------------------------------------------------------- + movi $r2, 0 ! $r2 <- res = 0 + beqz $r1, .L1 ! if den == 0, skip + ! --------------------------------------------------------------------- + ! bit = 1; + ! --------------------------------------------------------------------- + movi $r4, 1 ! $r4 <- bit = 1 +#ifndef __OPTIMIZE_SIZE__ +.L6: +#endif + ! --------------------------------------------------------------------- + ! while (den < num && bit && !(den & (1L << 31))) + ! --------------------------------------------------------------------- + slt $ta, $r1, $r0 ! $ta <- den < num ? + beqz $ta, .L5 ! if no, skip + ! --------------------------------------------------------------------- + ! { den << = 1; + ! bit << = 1; + ! } + ! --------------------------------------------------------------------- +#if defined (__OPTIMIZE_SIZE__) && !defined (__NDS32_ISA_V3M__) + clz $r3, $r1 ! $r3 <- leading zero count for den + clz $ta, $r0 ! $ta <- leading zero count for num + sub $r3, $r3, $ta ! $r3 <- number of bits to shift + sll $r1, $r1, $r3 ! $r1 <- den + sll $r4, $r4, $r3 ! $r2 <- bit +#else + slli $r1, $r1, 1 ! $r1 <- den << = 1 + slli $r4, $r4, 1 ! $r4 <- bit << = 1 + b .L6 ! continue loop +#endif +.L5: + ! --------------------------------------------------------------------- + ! while (bit) + ! { if (num >= den) + ! --------------------------------------------------------------------- + slt $ta, $r0, $r1 ! $ta <- num < den ? + bnez $ta, .L9 ! if yes, skip + ! --------------------------------------------------------------------- + ! { num -= den; + ! res |= bit; + ! } + ! --------------------------------------------------------------------- + sub $r0, $r0, $r1 ! $r0 <- num -= den + or $r2, $r2, $r4 ! $r2 <- res |= bit +.L9: + ! --------------------------------------------------------------------- + ! bit >> = 1; + ! den >> = 1; + ! } + !!if (modwanted) + !! return num; + !!return res; + ! --------------------------------------------------------------------- + srli $r4, $r4, 1 ! $r4 <- bit >> = 1 + srli $r1, $r1, 1 ! $r1 <- den >> = 1 + bnez $r4, .L5 ! if bit != 0, continue loop +.L1: + ! --------------------------------------------------------------------- + ! if (neg) + ! res = -res; + ! return res; + ! --------------------------------------------------------------------- + subri $r0, $r2, 0 ! $r0 <- -res + cmovz $r0, $r2, $r5 ! $r0 <- neg ? -res : res + ! --------------------------------------------------------------------- + ret + .size __divsi3, .-__divsi3 +#endif /* L_divsi3 */ + + + +#ifdef L_divdi3 + + !-------------------------------------- + #ifdef __big_endian__ + #define V1H $r0 + #define V1L $r1 + #define V2H $r2 + #define V2L $r3 + #else + #define V1H $r1 + #define V1L $r0 + #define V2H $r3 + #define V2L $r2 + #endif + !-------------------------------------- + .text + .align 2 + .globl __divdi3 + .type __divdi3, @function +__divdi3: + ! prologue +#ifdef __NDS32_ISA_V3M__ + push25 $r10, 0 +#else + smw.adm $r6, [$sp], $r10, 2 +#endif + ! end of prologue + move $r8, V1L + move $r9, V1H + move $r6, V2L + move $r7, V2H + movi $r10, 0 + bgez V1H, .L80 + bal __negdi2 + move $r8, V1L + move $r9, V1H + movi $r10, -1 +.L80: + bgez $r7, .L81 + move V1L, $r6 + move V1H, $r7 + bal __negdi2 + move $r6, V1L + move $r7, V1H + nor $r10, $r10, $r10 +.L81: + move V2L, $r6 + move V2H, $r7 + move V1L, $r8 + move V1H, $r9 + movi $r4, 0 + bal __udivmoddi4 + beqz $r10, .L82 + bal __negdi2 +.L82: + ! epilogue +#ifdef __NDS32_ISA_V3M__ + pop25 $r10, 0 +#else + lmw.bim $r6, [$sp], $r10, 2 + ret +#endif + .size __divdi3, .-__divdi3 +#endif /* L_divdi3 */ + + + +#ifdef L_modsi3 + + .text + .align 2 + .globl __modsi3 + .type __modsi3, @function +__modsi3: + ! --------------------------------------------------------------------- + ! neg=0; + ! if (a<0) + ! { a=-a; + ! neg=1; + ! } + ! --------------------------------------------------------------------- + sltsi $r5, $r0, 0 ! $r5 <- neg < 0 ? 1 : 0 + subri $r4, $r0, 0 ! $r4 <- -a + cmovn $r0, $r4, $r5 ! $r0 <- |a| + ! --------------------------------------------------------------------- + ! if (b < 0) +#ifndef __NDS32_PERF_EXT__ + ! --------------------------------------------------------------------- + bgez $r1, .L3 ! if b >= 0, skip + ! --------------------------------------------------------------------- + ! b = -b; + ! --------------------------------------------------------------------- + subri $r1, $r1, 0 ! $r1 <- |b| +.L3: + ! --------------------------------------------------------------------- + !!res = udivmodsi4 (a, b, 1); + ! if (den != 0) + ! --------------------------------------------------------------------- +#else /* __NDS32_PERF_EXT__ */ + ! b = -b; + !!res = udivmodsi4 (a, b, 1); + ! if (den != 0) + ! --------------------------------------------------------------------- + abs $r1, $r1 ! $r1 <- |b| +#endif /* __NDS32_PERF_EXT__ */ + beqz $r1, .L1 ! if den == 0, skip + ! --------------------------------------------------------------------- + ! { bit = 1; + ! res = 0; + ! --------------------------------------------------------------------- + movi $r4, 1 ! $r4 <- bit = 1 +#ifndef __OPTIMIZE_SIZE__ +.L6: +#endif + ! --------------------------------------------------------------------- + ! while (den < num&&bit && !(den & (1L << 31))) + ! --------------------------------------------------------------------- + slt $ta, $r1, $r0 ! $ta <- den < num ? + beqz $ta, .L5 ! if no, skip + ! --------------------------------------------------------------------- + ! { den << = 1; + ! bit << = 1; + ! } + ! --------------------------------------------------------------------- +#if defined (__OPTIMIZE_SIZE__) && ! defined (__NDS32_ISA_V3M__) + clz $r3, $r1 ! $r3 <- leading zero count for den + clz $ta, $r0 ! $ta <- leading zero count for num + sub $r3, $r3, $ta ! $r3 <- number of bits to shift + sll $r1, $r1, $r3 ! $r1 <- den + sll $r4, $r4, $r3 ! $r2 <- bit +#else + slli $r1, $r1, 1 ! $r1 <- den << = 1 + slli $r4, $r4, 1 ! $r4 <- bit << = 1 + b .L6 ! continue loop +#endif +.L5: + ! --------------------------------------------------------------------- + ! while (bit) + ! { if (num >= den) + ! { num -= den; + ! res |= bit; + ! } + ! bit >> = 1; + ! den >> = 1; + ! } + ! } + !!if (modwanted) + !! return num; + !!return res; + ! --------------------------------------------------------------------- + sub $r2, $r0, $r1 ! $r2 <- num - den + slt $ta, $r0, $r1 ! $ta <- num < den ? + srli $r4, $r4, 1 ! $r4 <- bit >> = 1 + cmovz $r0, $r2, $ta ! $r0 <- num = (num < den) ? num : num - den + srli $r1, $r1, 1 ! $r1 <- den >> = 1 + bnez $r4, .L5 ! if bit != 0, continue loop +.L1: + ! --------------------------------------------------------------------- + ! if (neg) + ! res = -res; + ! return res; + ! --------------------------------------------------------------------- + subri $r3, $r0, 0 ! $r3 <- -res + cmovn $r0, $r3, $r5 ! $r0 <- neg ? -res : res + ! --------------------------------------------------------------------- + ret + .size __modsi3, .-__modsi3 +#endif /* L_modsi3 */ + + + +#ifdef L_moddi3 + + !-------------------------------------- + #ifdef __big_endian__ + #define V1H $r0 + #define V1L $r1 + #define V2H $r2 + #define V2L $r3 + #else + #define V1H $r1 + #define V1L $r0 + #define V2H $r3 + #define V2L $r2 + #endif + !-------------------------------------- + .text + .align 2 + .globl __moddi3 + .type __moddi3, @function +__moddi3: + ! ===================================================================== + ! stack allocation: + ! sp+32 +-----------------------+ + ! | $lp | + ! sp+28 +-----------------------+ + ! | $r6 - $r10 | + ! sp+8 +-----------------------+ + ! | | + ! sp+4 +-----------------------+ + ! | | + ! sp +-----------------------+ + ! ===================================================================== + ! prologue +#ifdef __NDS32_ISA_V3M__ + push25 $r10, 8 +#else + smw.adm $r6, [$sp], $r10, 2 + addi $sp, $sp, -8 +#endif + ! end of prologue + !------------------------------------------ + ! __moddi3 (DWtype u, DWtype v) + ! { + ! word_type c = 0; + ! DWunion uu = {.ll = u}; + ! DWunion vv = {.ll = v}; + ! DWtype w; + ! if (uu.s.high < 0) + ! c = ~c, + ! uu.ll = -uu.ll; + !--------------------------------------------- + move $r8, V1L + move $r9, V1H + move $r6, V2L + move $r7, V2H + movi $r10, 0 ! r10 = c = 0 + bgez V1H, .L80 ! if u > 0 , go L80 + bal __negdi2 + move $r8, V1L + move $r9, V1H + movi $r10, -1 ! r10 = c = ~c + !------------------------------------------------ + ! if (vv.s.high < 0) + ! vv.ll = -vv.ll; + !---------------------------------------------- +.L80: + bgez $r7, .L81 ! if v > 0 , go L81 + move V1L, $r6 + move V1H, $r7 + bal __negdi2 + move $r6, V1L + move $r7, V1H + !------------------------------------------ + ! (void) __udivmoddi4 (uu.ll, vv.ll, &w); + ! if (c) + ! w = -w; + ! return w; + !----------------------------------------- +.L81: + move V2L, $r6 + move V2H, $r7 + move V1L, $r8 + move V1H, $r9 + addi $r4, $sp, 0 + bal __udivmoddi4 + lwi $r0, [$sp+(0)] ! le: sp + 0 is low, be: sp + 0 is high + lwi $r1, [$sp+(4)] ! le: sp + 4 is low, be: sp + 4 is high + beqz $r10, .L82 + bal __negdi2 +.L82: + ! epilogue +#ifdef __NDS32_ISA_V3M__ + pop25 $r10, 8 +#else + addi $sp, $sp, 8 + lmw.bim $r6, [$sp], $r10, 2 + ret +#endif + .size __moddi3, .-__moddi3 +#endif /* L_moddi3 */ + + + +#ifdef L_mulsi3 + + .text + .align 2 + .globl __mulsi3 + .type __mulsi3, @function +__mulsi3: + ! --------------------------------------------------------------------- + ! r = 0; + ! while (a) + ! $r0: r + ! $r1: b + ! $r2: a + ! --------------------------------------------------------------------- + beqz $r0, .L7 ! if a == 0, done + move $r2, $r0 ! $r2 <- a + movi $r0, 0 ! $r0 <- r <- 0 +.L8: + ! --------------------------------------------------------------------- + ! { if (a & 1) + ! r += b; + ! a >> = 1; + ! b << = 1; + ! } + ! $r0: r + ! $r1: b + ! $r2: a + ! $r3: scratch + ! $r4: scratch + ! --------------------------------------------------------------------- + andi $r3, $r2, 1 ! $r3 <- a & 1 + add $r4, $r0, $r1 ! $r4 <- r += b + cmovn $r0, $r4, $r3 ! $r0 <- r + srli $r2, $r2, 1 ! $r2 <- a >> = 1 + slli $r1, $r1, 1 ! $r1 <- b << = 1 + bnez $r2, .L8 ! if a != 0, continue loop +.L7: + ! --------------------------------------------------------------------- + ! $r0: return code + ! --------------------------------------------------------------------- + ret + .size __mulsi3, .-__mulsi3 +#endif /* L_mulsi3 */ + + + +#ifdef L_udivsi3 + + .text + .align 2 + .globl __udivsi3 + .type __udivsi3, @function +__udivsi3: + ! --------------------------------------------------------------------- + !!res=udivmodsi4(a,b,0); + ! res=0; + ! if (den!=0) + ! --------------------------------------------------------------------- + movi $r2, 0 ! $r2 <- res=0 + beqz $r1, .L1 ! if den==0, skip + ! --------------------------------------------------------------------- + ! { bit=1; + ! --------------------------------------------------------------------- + movi $r4, 1 ! $r4 <- bit=1 +#ifndef __OPTIMIZE_SIZE__ +.L6: +#endif + ! --------------------------------------------------------------------- + ! while (den<num + ! --------------------------------------------------------------------- + slt $ta, $r1, $r0 ! $ta <- den<num? + beqz $ta, .L5 ! if no, skip + ! --------------------------------------------------------------------- + ! &&bit&&!(den&(1L<<31))) + ! --------------------------------------------------------------------- + bltz $r1, .L5 ! if den<0, skip + ! --------------------------------------------------------------------- + ! { den<<=1; + ! bit<<=1; + ! } + ! --------------------------------------------------------------------- +#if defined (__OPTIMIZE_SIZE__) && ! defined (__NDS32_ISA_V3M__) + clz $r3, $r1 ! $r3 <- leading zero count for den + clz $ta, $r0 ! $ta <- leading zero count for num + sub $r3, $r3, $ta ! $r3 <- number of bits to shift + sll $r1, $r1, $r3 ! $r1 <- den + sll $r2, $r2, $r3 ! $r2 <- bit +#else + slli $r1, $r1, 1 ! $r1 <- den<<=1 + slli $r4, $r4, 1 ! $r4 <- bit<<=1 + b .L6 ! continue loop +#endif +.L5: + ! --------------------------------------------------------------------- + ! while (bit) + ! { if (num>=den) + ! --------------------------------------------------------------------- + slt $ta, $r0, $r1 ! $ta <- num<den? + bnez $ta, .L9 ! if yes, skip + ! --------------------------------------------------------------------- + ! { num-=den; + ! res|=bit; + ! } + ! --------------------------------------------------------------------- + sub $r0, $r0, $r1 ! $r0 <- num-=den + or $r2, $r2, $r4 ! $r2 <- res|=bit +.L9: + ! --------------------------------------------------------------------- + ! bit>>=1; + ! den>>=1; + ! } + ! } + !!if (modwanted) + !! return num; + !!return res; + ! --------------------------------------------------------------------- + srli $r4, $r4, 1 ! $r4 <- bit>>=1 + srli $r1, $r1, 1 ! $r1 <- den>>=1 + bnez $r4, .L5 ! if bit!=0, continue loop +.L1: + ! --------------------------------------------------------------------- + ! return res; + ! --------------------------------------------------------------------- + move $r0, $r2 ! $r0 <- return value + ! --------------------------------------------------------------------- + ! --------------------------------------------------------------------- + ret + .size __udivsi3, .-__udivsi3 +#endif /* L_udivsi3 */ + + + +#ifdef L_udivdi3 + + !-------------------------------------- + #ifdef __big_endian__ + #define V1H $r0 + #define V1L $r1 + #define V2H $r2 + #define V2L $r3 + #else + #define V1H $r1 + #define V1L $r0 + #define V2H $r3 + #define V2L $r2 + #endif + !-------------------------------------- + + .text + .align 2 + .globl __udivdi3 + .type __udivdi3, @function +__udivdi3: + ! prologue +#ifdef __NDS32_ISA_V3M__ + push25 $r8, 0 +#else + smw.adm $r6, [$sp], $r8, 2 +#endif + ! end of prologue + movi $r4, 0 + bal __udivmoddi4 + ! epilogue +#ifdef __NDS32_ISA_V3M__ + pop25 $r8, 0 +#else + lmw.bim $r6, [$sp], $r8, 2 + ret +#endif + .size __udivdi3, .-__udivdi3 +#endif /* L_udivdi3 */ + + + +#ifdef L_udivmoddi4 + + .text + .align 2 + .globl fudiv_qrnnd + .type fudiv_qrnnd, @function + #ifdef __big_endian__ + #define P1H $r0 + #define P1L $r1 + #define P2H $r2 + #define P2L $r3 + #define W6H $r4 + #define W6L $r5 + #define OFFSET_L 4 + #define OFFSET_H 0 + #else + #define P1H $r1 + #define P1L $r0 + #define P2H $r3 + #define P2L $r2 + #define W6H $r5 + #define W6L $r4 + #define OFFSET_L 0 + #define OFFSET_H 4 + #endif +fudiv_qrnnd: + !------------------------------------------------------ + ! function: fudiv_qrnnd(quotient, remainder, high_numerator, low_numerator, denominator) + ! divides a UDWtype, composed by the UWtype integers,HIGH_NUMERATOR (from $r4) + ! and LOW_NUMERATOR(from $r5) by DENOMINATOR(from $r6), and places the quotient + ! in $r7 and the remainder in $r8. + !------------------------------------------------------ + ! in reg:$r4(n1), $r5(n0), $r6(d0) + ! __d1 = ((USItype) (d) >> ((4 * 8) / 2)); + ! __d0 = ((USItype) (d) & (((USItype) 1 << ((4 * 8) / 2)) - 1)); + ! __r1 = (n1) % __d1; + ! __q1 = (n1) / __d1; + ! __m = (USItype) __q1 * __d0; + ! __r1 = __r1 * ((USItype) 1 << ((4 * 8) / 2)) | ((USItype) (n0) >> ((4 * 8) / 2)); + ! if (__r1 < __m) + ! { + !------------------------------------------------------ + smw.adm $r0, [$sp], $r4, 2 ! store $lp, when use BASELINE_V1,and must store $r0-$r3 + srli $r7, $r6, 16 ! $r7 = d1 =__ll_highpart (d) + movi $ta, 65535 + and $r8, $r6, $ta ! $r8 = d0 = __ll_lowpart (d) + + divr $r9, $r10, $r4, $r7 ! $r9 = q1, $r10 = r1 + and $r4, $r5, $ta ! $r4 = __ll_lowpart (n0) + slli $r10, $r10, 16 ! $r10 = r1 << 16 + srli $ta, $r5, 16 ! $ta = __ll_highpart (n0) + + or $r10, $r10, $ta ! $r10 <- $r0|$r3=__r1 + mul $r5, $r9, $r8 ! $r5 = m = __q1*__d0 + slt $ta, $r10, $r5 ! $ta <- __r1<__m + beqz $ta, .L2 !if yes,skip + !------------------------------------------------------ + ! __q1--, __r1 += (d); + ! if (__r1 >= (d)) + ! { + !------------------------------------------------------ + + add $r10, $r10, $r6 !$r10 <- __r1+d=__r1 + addi $r9, $r9, -1 !$r9 <- __q1--=__q1 + slt $ta, $r10, $r6 !$ta <- __r1<d + bnez $ta, .L2 !if yes,skip + !------------------------------------------------------ + ! if (__r1 < __m) + ! { + !------------------------------------------------------ + + slt $ta, $r10, $r5 !$ta <- __r1<__m + beqz $ta, .L2 !if yes,skip + !------------------------------------------------------ + ! __q1--, __r1 += (d); + ! } + ! } + ! } + !------------------------------------------------------ + + addi $r9, $r9, -1 !$r9 <- __q1--=__q1 + add $r10, $r10, $r6 !$r2 <- __r1+d=__r1 +.L2: + !------------------------------------------------------ + ! __r1 -= __m; + ! __r0 = __r1 % __d1; + ! __q0 = __r1 / __d1; + ! __m = (USItype) __q0 * __d0; + ! __r0 = __r0 * ((USItype) 1 << ((4 * 8) / 2)) \ + ! | ((USItype) (n0) & (((USItype) 1 << ((4 * 8) / 2)) - 1)); + ! if (__r0 < __m) + ! { + !------------------------------------------------------ + sub $r10, $r10, $r5 !$r10 <- __r1-__m=__r1 + divr $r7, $r10, $r10, $r7 !$r7 <- r1/__d1=__q0,$r10 <- r1%__d1=__r0 + slli $r10, $r10, 16 !$r10 <- __r0<<16 + mul $r5, $r8, $r7 !$r5 <- __q0*__d0=__m + or $r10, $r4, $r10 !$r3 <- $r0|__ll_lowpart (n0) =__r0 + slt $ta, $r10, $r5 !$ta <- __r0<__m + beqz $ta, .L5 !if yes,skip + !------------------------------------------------------ + ! __q0--, __r0 += (d); + ! if (__r0 >= (d)) + ! { + !------------------------------------------------------ + + add $r10, $r10, $r6 !$r10 <- __r0+d=__r0 + addi $r7, $r7, -1 !$r7 <- __q0--=__q0 + slt $ta, $r10, $r6 !$ta <- __r0<d + bnez $ta, .L5 !if yes,skip + !------------------------------------------------------ + ! if (__r0 < __m) + ! { + !------------------------------------------------------ + + slt $ta, $r10, $r5 !$ta <- __r0<__m + beqz $ta, .L5 !if yes,skip + !------------------------------------------------------ + ! __q0--, __r0 += (d); + ! } + ! } + ! } + !------------------------------------------------------ + + add $r10, $r10, $r6 !$r3 <- __r0+d=__r0 + addi $r7, $r7, -1 !$r2 <- __q0--=__q0 +.L5: + !------------------------------------------------------ + ! __r0 -= __m; + ! *q = (USItype) __q1 * ((USItype) 1 << ((4 * 8) / 2)) | __q0; + ! *r = __r0; + !} + !------------------------------------------------------ + + sub $r8, $r10, $r5 !$r8 = r = r0 = __r0-__m + slli $r9, $r9, 16 !$r9 <- __q1<<16 + or $r7, $r9, $r7 !$r7 = q = $r9|__q0 + lmw.bim $r0, [$sp], $r4, 2 + ret + .size fudiv_qrnnd, .-fudiv_qrnnd + + .align 2 + .globl __udivmoddi4 + .type __udivmoddi4, @function +__udivmoddi4: + ! ===================================================================== + ! stack allocation: + ! sp+40 +------------------+ + ! | q1 | + ! sp+36 +------------------+ + ! | q0 | + ! sp+32 +------------------+ + ! | bm | + ! sp+28 +------------------+ + ! | $lp | + ! sp+24 +------------------+ + ! | $fp | + ! sp+20 +------------------+ + ! | $r6 - $r10 | + ! sp +------------------+ + ! ===================================================================== + + addi $sp, $sp, -40 + smw.bi $r6, [$sp], $r10, 10 + !------------------------------------------------------ + ! d0 = dd.s.low; + ! d1 = dd.s.high; + ! n0 = nn.s.low; + ! n1 = nn.s.high; + ! if (d1 == 0) + ! { + !------------------------------------------------------ + + move $fp, $r4 !$fp <- rp + bnez P2H, .L9 !if yes,skip + !------------------------------------------------------ + ! if (d0 > n1) + ! { + !------------------------------------------------------ + + slt $ta, P1H, P2L !$ta <- n1<d0 + beqz $ta, .L10 !if yes,skip +#ifndef __NDS32_PERF_EXT__ + smw.adm $r0, [$sp], $r5, 0 + move $r0, P2L + bal __clzsi2 + move $r7, $r0 + lmw.bim $r0, [$sp], $r5, 0 +#else + clz $r7, P2L +#endif + swi $r7, [$sp+(28)] + beqz $r7, .L18 !if yes,skip + !------------------------------------------------------ + ! d0 = d0 << bm; + ! n1 = (n1 << bm) | (n0 >> ((4 * 8) - bm)); + ! n0 = n0 << bm; + ! } + !------------------------------------------------------ + + subri $r5, $r7, 32 !$r5 <- 32-bm + srl $r5, P1L, $r5 !$r5 <- n0>>$r5 + sll $r6, P1H, $r7 !$r6 <- n1<<bm + or P1H, $r6, $r5 !P2h <- $r5|$r6=n1 + sll P1L, P1L, $r7 !P1H <- n0<<bm=n0 + sll P2L, P2L, $r7 !P2L <- d0<<bm=d0 +.L18: + !------------------------------------------------------ + ! fudiv_qrnnd (&q0, &n0, n1, n0, d0); + ! q1 = 0; + ! } #if (d0 > n1) + !------------------------------------------------------ + + move $r4,P1H ! give fudiv_qrnnd args + move $r5,P1L ! + move $r6,P2L ! + bal fudiv_qrnnd !calcaulte q0 n0 + movi $r6, 0 !P1L <- 0 + swi $r7,[$sp+32] !q0 + swi $r6,[$sp+36] !q1 + move P1L,$r8 !n0 + b .L19 +.L10: + !------------------------------------------------------ + ! else #if (d0 > n1) + ! { + ! if(d0 == 0) + !------------------------------------------------------ + + bnez P2L, .L20 !if yes,skip + !------------------------------------------------------ + ! d0 = 1 / d0; + !------------------------------------------------------ + + movi $r4, 1 !P1L <- 1 + divr P2L, $r4, $r4, P2L !$r9=1/d0,P1L=1%d0 +.L20: + +#ifndef __NDS32_PERF_EXT__ + smw.adm $r0, [$sp], $r5, 0 + move $r0, P2L + bal __clzsi2 + move $r7, $r0 + lmw.bim $r0, [$sp], $r5, 0 +#else + clz $r7, P2L +#endif + swi $r7,[$sp+(28)] ! store bm + beqz $r7, .L28 ! if yes,skip + !------------------------------------------------------ + ! b = (4 * 8) - bm; + ! d0 = d0 << bm; + ! n2 = n1 >> b; + ! n1 = (n1 << bm) | (n0 >> b); + ! n0 = n0 << bm; + ! fudiv_qrnnd (&q1, &n1, n2, n1, d0); + ! } + !------------------------------------------------------ + + subri $r10, $r7, 32 !$r10 <- 32-bm=b + srl $r4, P1L, $r10 !$r4 <- n0>>b + sll $r5, P1H, $r7 !$r5 <- n1<<bm + or $r5, $r5, $r4 !$r5 <- $r5|$r4=n1 !for fun + sll P2L, P2L, $r7 !P2L <- d0<<bm=d0 !for fun + sll P1L, P1L, $r7 !P1L <- n0<<bm=n0 + srl $r4, P1H, $r10 !$r4 <- n1>>b=n2 !for fun + + move $r6,P2L !for fun + bal fudiv_qrnnd !caculate q1, n1 + + swi $r7,[$sp+(36)] ! q1 store + move P1H,$r8 ! n1 store + + move $r4,$r8 ! prepare for next fudiv_qrnnd() + move $r5,P1L + move $r6,P2L + b .L29 +.L28: + !------------------------------------------------------ + ! else // bm != 0 + ! { + ! n1 -= d0; + ! q1 = 1; + ! + !------------------------------------------------------ + + sub P1H, P1H, P2L !P1L <- n1-d0=n1 + movi $ta, 1 ! + swi $ta, [$sp+(36)] !1 -> [$sp+(36)] + + move $r4,P1H ! give fudiv_qrnnd args + move $r5,P1L + move $r6,P2L +.L29: + !------------------------------------------------------ + ! fudiv_qrnnd (&q0, &n0, n1, n0, d0); + !------------------------------------------------------ + + bal fudiv_qrnnd !calcuate q0, n0 + swi $r7,[$sp+(32)] !q0 store + move P1L,$r8 !n0 +.L19: + !------------------------------------------------------ + ! if (rp != 0) + ! { + !------------------------------------------------------ + + beqz $fp, .L31 !if yes,skip + !------------------------------------------------------ + ! rr.s.low = n0 >> bm; + ! rr.s.high = 0; + ! *rp = rr.ll; + ! } + !------------------------------------------------------ + + movi $r5, 0 !$r5 <- 0 + lwi $r7,[$sp+(28)] !load bm + srl $r4, P1L, $r7 !$r4 <- n0>>bm + swi $r4, [$fp+OFFSET_L] !r0 !$r4 -> [$sp+(48)] + swi $r5, [$fp+OFFSET_H] !r1 !0 -> [$sp+(52)] + b .L31 +.L9: + !------------------------------------------------------ + ! else # d1 == 0 + ! { + ! if(d1 > n1) + ! { + !------------------------------------------------------ + + slt $ta, P1H, P2H !$ta <- n1<d1 + beqz $ta, .L32 !if yes,skip + !------------------------------------------------------ + ! q0 = 0; + ! q1 = 0; + ! if (rp != 0) + ! { + !------------------------------------------------------ + + movi $r5, 0 !$r5 <- 0 + swi $r5, [$sp+(32)] !q0 !0 -> [$sp+(40)]=q1 + swi $r5, [$sp+(36)] !q1 !0 -> [$sp+(32)]=q0 + beqz $fp, .L31 !if yes,skip + !------------------------------------------------------ + ! rr.s.low = n0; + ! rr.s.high = n1; + ! *rp = rr.ll; + ! } + !------------------------------------------------------ + + swi P1L, [$fp+OFFSET_L] !P1L -> [rp] + swi P1H, [$fp+OFFSET_H] !P1H -> [rp+4] + b .L31 +.L32: +#ifndef __NDS32_PERF_EXT__ + smw.adm $r0, [$sp], $r5, 0 + move $r0, P2H + bal __clzsi2 + move $r7, $r0 + lmw.bim $r0, [$sp], $r5, 0 +#else + clz $r7,P2H +#endif + swi $r7,[$sp+(28)] !$r7=bm store + beqz $r7, .L42 !if yes,skip + !------------------------------------------------------ + ! USItype m1, m0; + ! b = (4 * 8) - bm; + ! d1 = (d0 >> b) | (d1 << bm); + ! d0 = d0 << bm; + ! n2 = n1 >> b; + ! n1 = (n0 >> b) | (n1 << bm); + ! n0 = n0 << bm; + ! fudiv_qrnnd (&q0, &n1, n2, n1, d1); + !------------------------------------------------------ + + subri $r10, $r7, 32 !$r10 <- 32-bm=b + srl $r5, P2L, $r10 !$r5 <- d0>>b + sll $r6, P2H, $r7 !$r6 <- d1<<bm + or $r6, $r5, $r6 !$r6 <- $r5|$r6=d1 !! func + move P2H, $r6 !P2H <- d1 + srl $r4, P1H, $r10 !$r4 <- n1>>b=n2 !!! func + srl $r8, P1L, $r10 !$r8 <- n0>>b !!$r8 + sll $r9, P1H, $r7 !$r9 <- n1<<bm + or $r5, $r8, $r9 !$r5 <- $r8|$r9=n1 !func + sll P2L, P2L, $r7 !P2L <- d0<<bm=d0 + sll P1L, P1L, $r7 !P1L <- n0<<bm=n0 + + bal fudiv_qrnnd ! cal q0,n1 + swi $r7,[$sp+(32)] + move P1H,$r8 ! fudiv_qrnnd (&q0, &n1, n2, n1, d1); + move $r6, $r7 ! from func + + !---------------------------------------------------- + ! #umul_ppmm (m1, m0, q0, d0); + ! do + ! { USItype __x0, __x1, __x2, __x3; + ! USItype __ul, __vl, __uh, __vh; + ! __ul = ((USItype) (q0) & (((USItype) 1 << ((4 * 8) / 2)) - 1)); + ! __uh = ((USItype) (q0) >> ((4 * 8) / 2)); + ! __vl = ((USItype) (d0) & (((USItype) 1 << ((4 * 8) / 2)) - 1)); + ! __vh = ((USItype) (d0) >> ((4 * 8) / 2)); + ! __x0 = (USItype) __ul * __vl; + ! __x1 = (USItype) __ul * __vh; + ! __x2 = (USItype) __uh * __vl; + ! __x3 = (USItype) __uh * __vh; + ! __x1 += ((USItype) (__x0) >> ((4 * 8) / 2)); + ! __x1 += __x2; + ! if (__x1 < __x2) + ! __x3 += ((USItype) 1 << ((4 * 8) / 2)); + ! (m1) = __x3 + ((USItype) (__x1) >> ((4 * 8) / 2)); + ! (m0) = (USItype)(q0*d0); + ! } + ! if (m1 > n1) + !--------------------------------------------------- +#ifdef __NDS32_ISA_V3M__ + !mulr64 $r4, P2L, $r6 + smw.adm $r0, [$sp], $r3, 0 + move P1L, P2L + move P2L, $r6 + movi P1H, 0 + movi P2H, 0 + bal __muldi3 + movd44 $r4, $r0 + lmw.bim $r0, [$sp], $r3, 0 + move $r8, W6H + move $r5, W6L +#else + mulr64 $r4, P2L, $r6 + move $r8, W6H + move $r5, W6L +#endif + slt $ta, P1H, $r8 !$ta <- n1<m1 + bnez $ta, .L46 !if yes,skip + !------------------------------------------------------ + ! if(m1 == n1) + !------------------------------------------------------ + + bne $r8, P1H, .L45 !if yes,skip + !------------------------------------------------------ + ! if(m0 > n0) + !------------------------------------------------------ + + slt $ta, P1L, $r5 !$ta <- n0<m0 + beqz $ta, .L45 !if yes,skip +.L46: + !------------------------------------------------------ + ! { + ! q0--; + ! # sub_ddmmss (m1, m0, m1, m0, d1, d0); + ! do + ! { USItype __x; + ! __x = (m0) - (d0); + ! (m1) = (m1) - (d1) - (__x > (m0)); + ! (m0) = __x; + ! } + ! } + !------------------------------------------------------ + + sub $r4, $r5, P2L !$r4 <- m0-d0=__x + addi $r6, $r6, -1 !$r6 <- q0--=q0 + sub $r8, $r8, P2H !$r8 <- m1-d1 + swi $r6, [$sp+(32)] ! q0 !$r6->[$sp+(32)] + slt $ta, $r5, $r4 !$ta <- m0<__x + sub $r8, $r8, $ta !$r8 <- P1H-P1L=m1 + move $r5, $r4 !$r5 <- __x=m0 +.L45: + !------------------------------------------------------ + ! q1 = 0; + ! if (rp != 0) + ! { + !------------------------------------------------------ + + movi $r4, 0 !$r4 <- 0 + swi $r4, [$sp+(36)] !0 -> [$sp+(40)]=q1 + beqz $fp, .L31 !if yes,skip + !------------------------------------------------------ + ! # sub_ddmmss (n1, n0, n1, n0, m1, m0); + ! do + ! { USItype __x; + ! __x = (n0) - (m0); + ! (n1) = (n1) - (m1) - (__x > (n0)); + ! (n0) = __x; + ! } + ! rr.s.low = (n1 << b) | (n0 >> bm); + ! rr.s.high = n1 >> bm; + ! *rp = rr.ll; + !------------------------------------------------------ + + sub $r4, P1H, $r8 !$r4 <- n1-m1 + sub $r6, P1L, $r5 !$r6 <- n0-m0=__x=n0 + slt $ta, P1L, $r6 !$ta <- n0<__x + sub P1H, $r4, $ta !P1H <- $r4-$ta=n1 + move P1L, $r6 + + lwi $r7,[$sp+(28)] ! load bm + subri $r10,$r7,32 + sll $r4, P1H, $r10 !$r4 <- n1<<b + srl $r5, P1L, $r7 !$r5 <- __x>>bm + or $r6, $r5, $r4 !$r6 <- $r5|$r4=rr.s.low + srl $r8, P1H, $r7 !$r8 <- n1>>bm =rr.s.high + swi $r6, [$fp+OFFSET_L] ! + swi $r8, [$fp+OFFSET_H] ! + b .L31 +.L42: + !------------------------------------------------------ + ! else + ! { + ! if(n1 > d1) + !------------------------------------------------------ + + slt $ta, P2H, P1H !$ta <- P2H<P1H + bnez $ta, .L52 !if yes,skip + !------------------------------------------------------ + ! if (n0 >= d0) + !------------------------------------------------------ + + slt $ta, P1L, P2L !$ta <- P1L<P2L + bnez $ta, .L51 !if yes,skip + !------------------------------------------------------ + ! q0 = 1; + ! do + ! { USItype __x; + ! __x = (n0) - (d0); + ! (n1) = (n1) - (d1) - (__x > (n0)); + ! (n0) = __x; + ! } + !------------------------------------------------------ +.L52: + sub $r4, P1H, P2H !$r4 <- P1H-P2H + sub $r6, P1L, P2L !$r6 <- no-d0=__x=n0 + slt $ta, P1L, $r6 !$ta <- no<__x + sub P1H, $r4, $ta !P1H <- $r4-$ta=n1 + move P1L, $r6 !n0 + movi $r5, 1 ! + swi $r5, [$sp+(32)] !1 -> [$sp+(32)]=q0 + b .L54 +.L51: + !------------------------------------------------------ + ! q0 = 0; + !------------------------------------------------------ + + movi $r5,0 + swi $r5, [$sp+(32)] !$r5=0 -> [$sp+(32)] +.L54: + !------------------------------------------------------ + ! q1 = 0; + ! if (rp != 0) + ! { + !------------------------------------------------------ + + movi $r5, 0 ! + swi $r5, [$sp+(36)] !0 -> [$sp+(36)] + beqz $fp, .L31 + !------------------------------------------------------ + ! rr.s.low = n0; + ! rr.s.high = n1; + ! *rp = rr.ll; + ! } + !------------------------------------------------------ + + swi P1L, [$fp+OFFSET_L] !remainder + swi P1H, [$fp+OFFSET_H] ! +.L31: + !------------------------------------------------------ + ! const DWunion ww = {{.low = q0, .high = q1}}; + ! return ww.ll; + !} + !------------------------------------------------------ + + lwi P1L, [$sp+(32)] !quotient + lwi P1H, [$sp+(36)] + lmw.bim $r6, [$sp], $r10, 10 + addi $sp, $sp, 12 + ret + .size __udivmoddi4, .-__udivmoddi4 +#endif /* L_udivmoddi4 */ + + + +#ifdef L_umodsi3 + + ! ===================================================================== + .text + .align 2 + .globl __umodsi3 + .type __umodsi3, @function +__umodsi3: + ! --------------------------------------------------------------------- + !!res=udivmodsi4(a,b,1); + ! if (den==0) + ! return num; + ! --------------------------------------------------------------------- + beqz $r1, .L1 ! if den==0, skip + ! --------------------------------------------------------------------- + ! bit=1; + ! res=0; + ! --------------------------------------------------------------------- + movi $r4, 1 ! $r4 <- bit=1 +#ifndef __OPTIMIZE_SIZE__ +.L6: +#endif + ! --------------------------------------------------------------------- + ! while (den<num + ! --------------------------------------------------------------------- + slt $ta, $r1, $r0 ! $ta <- den<num? + beqz $ta, .L5 ! if no, skip + ! --------------------------------------------------------------------- + ! &&bit&&!(den&(1L<<31))) + ! --------------------------------------------------------------------- + bltz $r1, .L5 ! if den<0, skip + ! --------------------------------------------------------------------- + ! { den<<=1; + ! bit<<=1; + ! } + ! --------------------------------------------------------------------- +#if defined (__OPTIMIZE_SIZE__) && ! defined (__NDS32_ISA_V3M__) + clz $r3, $r1 ! $r3 <- leading zero count for den + clz $ta, $r0 ! $ta <- leading zero count for num + sub $r3, $r3, $ta ! $r3 <- number of bits to shift + sll $r1, $r1, $r3 ! $r1 <- den + sll $r4, $r4, $r3 ! $r2 <- bit +#else + slli $r1, $r1, 1 ! $r1 <- den<<=1 + slli $r4, $r4, 1 ! $r4 <- bit<<=1 + b .L6 ! continue loop +#endif +.L5: + ! --------------------------------------------------------------------- + ! while (bit) + ! { if (num>=den) + ! { num-=den; + ! res|=bit; + ! } + ! bit>>=1; + ! den>>=1; + ! } + !!if (modwanted) + !! return num; + !!return res; + ! --------------------------------------------------------------------- + sub $r2, $r0, $r1 ! $r2 <- num-den + slt $ta, $r0, $r1 ! $ta <- num<den? + srli $r4, $r4, 1 ! $r4 <- bit>>=1 + cmovz $r0, $r2, $ta ! $r0 <- num=(num<den)?num:num-den + srli $r1, $r1, 1 ! $r1 <- den>>=1 + bnez $r4, .L5 ! if bit!=0, continue loop +.L1: + ! --------------------------------------------------------------------- + ! return res; + ! --------------------------------------------------------------------- + ret + .size __umodsi3, .-__umodsi3 +#endif /* L_umodsi3 */ + + + +#ifdef L_umoddi3 + + !-------------------------------------- + #ifdef __big_endian__ + #define V1H $r0 + #define V1L $r1 + #define V2H $r2 + #define V2L $r3 + #else + #define V1H $r1 + #define V1L $r0 + #define V2H $r3 + #define V2L $r2 + #endif + !-------------------------------------- + .text + .align 2 + .globl __umoddi3 + .type __umoddi3, @function +__umoddi3: + ! prologue + addi $sp, $sp, -12 + swi $lp, [$sp+(0)] + ! end of prologue + addi $r4, $sp, 4 + bal __udivmoddi4 + lwi $r0, [$sp+(4)] ! __udivmoddi4 return low when LE mode or return high when BE mode + lwi $r1, [$sp+(8)] ! +.L82: + ! epilogue + lwi $lp, [$sp+(0)] + addi $sp, $sp, 12 + ret + .size __umoddi3, .-__umoddi3 +#endif /* L_umoddi3 */ + + + +#ifdef L_muldi3 + +#ifdef __big_endian__ + #define P1H $r0 + #define P1L $r1 + #define P2H $r2 + #define P2L $r3 + + #define V2H $r4 + #define V2L $r5 +#else + #define P1H $r1 + #define P1L $r0 + #define P2H $r3 + #define P2L $r2 + + #define V2H $r5 + #define V2L $r4 +#endif + + ! ==================================================================== + .text + .align 2 + .globl __muldi3 + .type __muldi3, @function +__muldi3: + ! parameter passing for libgcc functions normally involves 2 doubles + !--------------------------------------- +#ifdef __NDS32_ISA_V3M__ + ! There is no mulr64 instruction in Andes ISA V3M. + ! So we must provide a sequence of calculations to complete the job. + smw.adm $r6, [$sp], $r9, 0x0 + zeh33 $r4, P1L + srli $r7, P1L, 16 + zeh33 $r5, P2L + mul $r6, $r5, $r4 + mul33 $r5, $r7 + srli $r8, P2L, 16 + mov55 $r9, $r5 + maddr32 $r9, $r8, $r4 + srli $r4, $r6, 16 + add $r4, $r9, $r4 + slt45 $r4, $r5 + slli $r5, $r15, 16 + maddr32 $r5, $r8, $r7 + mul P2L, P1H, P2L + srli $r7, $r4, 16 + maddr32 P2L, P2H, P1L + add333 P1H, $r5, $r7 + slli $r4, $r4, 16 + zeh33 $r6, $r6 + add333 P1L, $r4, $r6 + add333 P1H, P2L, P1H + lmw.bim $r6, [$sp], $r9, 0x0 + ret +#else /* not __NDS32_ISA_V3M__ */ + mul $ta, P1L, P2H + mulr64 $r4, P1L, P2L + maddr32 $ta, P1H, P2L + move P1L, V2L + add P1H, $ta, V2H + ret +#endif /* not __NDS32_ISA_V3M__ */ + .size __muldi3, .-__muldi3 +#endif /* L_muldi3 */ + + + +#ifdef L_addsub_df + +#ifndef __big_endian__ + #define P1L $r0 + #define P1H $r1 + #define P2L $r2 + #define P2H $r3 + #define P3L $r4 + #define P3H $r5 + #define O1L $r7 + #define O1H $r8 +#else + #define P1H $r0 + #define P1L $r1 + #define P2H $r2 + #define P2L $r3 + #define P3H $r4 + #define P3L $r5 + #define O1H $r7 + #define O1L $r8 +#endif + .text + .align 2 + .global __subdf3 + .type __subdf3, @function +__subdf3: + push $lp + pushm $r6, $r10 + + move $r4, #0x80000000 + xor P2H, P2H, $r4 + + j .Lsdpadd + + .global __adddf3 + .type __adddf3, @function +__adddf3: + push $lp + pushm $r6, $r10 +.Lsdpadd: + slli $r6, P1H, #1 + srli $r6, $r6, #21 + slli P3H, P1H, #11 + srli $r10, P1L, #21 + or P3H, P3H, $r10 + slli P3L, P1L, #11 + move O1L, #0x80000000 + or P3H, P3H, O1L + slli $r9, P2H, #1 + srli $r9, $r9, #21 + slli O1H, P2H, #11 + srli $r10, P2L, #21 + or O1H, O1H, $r10 + or O1H, O1H, O1L + slli O1L, P2L, #11 + + addi $r10, $r6, #-1 + slti $r15, $r10, #0x7fe + beqzs8 .LEspecA + +.LElab1: + addi $r10, $r9, #-1 + slti $r15, $r10, #0x7fe + beqzs8 .LEspecB + +.LElab2: + #NORMd($r4, P2L, P1L) + bnez P3H, .LL1 + bnez P3L, .LL2 + move $r6, #0 + j .LL3 +.LL2: + move P3H, P3L + move P3L, #0 + move P2L, #32 + sub $r6, $r6, P2L +.LL1: +#ifndef __big_endian__ +#ifdef __NDS32_PERF_EXT__ + clz $r2, $r5 +#else + pushm $r0, $r1 + pushm $r3, $r5 + move $r0, $r5 + bal __clzsi2 + move $r2, $r0 + popm $r3, $r5 + popm $r0, $r1 +#endif +#else /* __big_endian__ */ +#ifdef __NDS32_PERF_EXT__ + clz $r3, $r4 +#else + pushm $r0, $r2 + pushm $r4, $r5 + move $r0, $r4 + bal __clzsi2 + move $r3, $r0 + popm $r4, $r5 + popm $r0, $r2 +#endif +#endif /* __big_endian__ */ + beqz P2L, .LL3 + sub $r6, $r6, P2L + subri P1L, P2L, #32 + srl P1L, P3L, P1L + sll P3L, P3L, P2L + sll P3H, P3H, P2L + or P3H, P3H, P1L +.LL3: + #NORMd End + + #NORMd($r7, P2L, P1L) + bnez O1H, .LL4 + bnez O1L, .LL5 + move $r9, #0 + j .LL6 +.LL5: + move O1H, O1L + move O1L, #0 + move P2L, #32 + sub $r9, $r9, P2L +.LL4: +#ifndef __big_endian__ +#ifdef __NDS32_PERF_EXT__ + clz $r2, O1H +#else + pushm $r0, $r1 + pushm $r3, $r5 + move $r0, O1H + bal __clzsi2 + move $r2, $r0 + popm $r3, $r5 + popm $r0, $r1 +#endif +#else /* __big_endian__ */ +#ifdef __NDS32_PERF_EXT__ + clz $r3, O1H +#else + pushm $r0, $r2 + pushm $r4, $r5 + move $r0, O1H + bal __clzsi2 + move $r3, $r0 + popm $r4, $r5 + popm $r0, $r2 +#endif +#endif /* __big_endian__ */ + beqz P2L, .LL6 + sub $r9, $r9, P2L + subri P1L, P2L, #32 + srl P1L, O1L, P1L + sll O1L, O1L, P2L + sll O1H, O1H, P2L + or O1H, O1H, P1L +.LL6: + #NORMd End + + move $r10, #0x80000000 + and P1H, P1H, $r10 + + beq $r6, $r9, .LEadd3 + slts $r15, $r9, $r6 + beqzs8 .Li1 + sub $r9, $r6, $r9 + move P2L, #0 +.LL7: + move $r10, #0x20 + slt $r15, $r9, $r10 + bnezs8 .LL8 + or P2L, P2L, O1L + move O1L, O1H + move O1H, #0 + addi $r9, $r9, #0xffffffe0 + bnez O1L, .LL7 +.LL8: + beqz $r9, .LEadd3 + move P1L, O1H + move $r10, O1L + srl O1L, O1L, $r9 + srl O1H, O1H, $r9 + subri $r9, $r9, #0x20 + sll P1L, P1L, $r9 + or O1L, O1L, P1L + sll $r10, $r10, $r9 + or P2L, P2L, $r10 + beqz P2L, .LEadd3 + ori O1L, O1L, #1 + j .LEadd3 +.Li1: + move $r15, $r6 + move $r6, $r9 + sub $r9, $r9, $r15 + move P2L, #0 +.LL10: + move $r10, #0x20 + slt $r15, $r9, $r10 + bnezs8 .LL11 + or P2L, P2L, P3L + move P3L, P3H + move P3H, #0 + addi $r9, $r9, #0xffffffe0 + bnez P3L, .LL10 +.LL11: + beqz $r9, .LEadd3 + move P1L, P3H + move $r10, P3L + srl P3L, P3L, $r9 + srl P3H, P3H, $r9 + subri $r9, $r9, #0x20 + sll P1L, P1L, $r9 + or P3L, P3L, P1L + sll $r10, $r10, $r9 + or P2L, P2L, $r10 + beqz P2L, .LEadd3 + ori P3L, P3L, #1 + +.LEadd3: + xor $r10, P1H, P2H + sltsi $r15, $r10, #0 + bnezs8 .LEsub1 + + #ADD(P3L, O1L) + add P3L, P3L, O1L + slt $r15, P3L, O1L + + #ADDCC(P3H, O1H) + beqzs8 .LL13 + add P3H, P3H, O1H + slt $r15, P3H, O1H + beqzs8 .LL14 + addi P3H, P3H, #0x1 + j .LL15 +.LL14: + move $r15, #1 + add P3H, P3H, $r15 + slt $r15, P3H, $r15 + j .LL15 +.LL13: + add P3H, P3H, O1H + slt $r15, P3H, O1H +.LL15: + + beqzs8 .LEres + andi $r10, P3L, #1 + beqz $r10, .Li3 + ori P3L, P3L, #2 +.Li3: + srli P3L, P3L, #1 + slli $r10, P3H, #31 + or P3L, P3L, $r10 + srli P3H, P3H, #1 + move $r10, #0x80000000 + or P3H, P3H, $r10 + addi $r6, $r6, #1 + subri $r15, $r6, #0x7ff + bnezs8 .LEres + move $r10, #0x7ff00000 + or P1H, P1H, $r10 + move P1L, #0 + j .LEretA + +.LEsub1: + #SUB(P3L, O1L) + move $r15, P3L + sub P3L, P3L, O1L + slt $r15, $r15, P3L + + #SUBCC(P3H, O1H) + beqzs8 .LL16 + move $r15, P3H + sub P3H, P3H, O1H + slt $r15, $r15, P3H + beqzs8 .LL17 + subi333 P3H, P3H, #1 + j .LL18 +.LL17: + move $r15, P3H + subi333 P3H, P3H, #1 + slt $r15, $r15, P3H + j .LL18 +.LL16: + move $r15, P3H + sub P3H, P3H, O1H + slt $r15, $r15, P3H +.LL18: + + beqzs8 .Li5 + move $r10, #0x80000000 + xor P1H, P1H, $r10 + + subri P3H, P3H, #0 + beqz P3L, .LL19 + subri P3L, P3L, #0 + subi45 P3H, #1 +.LL19: + +.Li5: + #NORMd($r4, $r9, P1L) + bnez P3H, .LL20 + bnez P3L, .LL21 + move $r6, #0 + j .LL22 +.LL21: + move P3H, P3L + move P3L, #0 + move $r9, #32 + sub $r6, $r6, $r9 +.LL20: +#ifdef __NDS32_PERF_EXT__ + clz $r9, P3H +#else + pushm $r0, $r5 + move $r0, P3H + bal __clzsi2 + move $r9, $r0 + popm $r0, $r5 +#endif + beqz $r9, .LL22 + sub $r6, $r6, $r9 + subri P1L, $r9, #32 + srl P1L, P3L, P1L + sll P3L, P3L, $r9 + sll P3H, P3H, $r9 + or P3H, P3H, P1L +.LL22: + #NORMd End + + or $r10, P3H, P3L + bnez $r10, .LEres + move P1H, #0 + +.LEres: + blez $r6, .LEund + +.LElab8: + #ADD(P3L, $0x400) + move $r15, #0x400 + add P3L, P3L, $r15 + slt $r15, P3L, $r15 + + #ADDCC(P3H, $0x0) + beqzs8 .LL25 + add P3H, P3H, $r15 + slt $r15, P3H, $r15 +.LL25: + + #ADDC($r6, $0x0) + add $r6, $r6, $r15 + srli $r10, P3L, #11 + andi $r10, $r10, #1 + sub P3L, P3L, $r10 + srli P1L, P3L, #11 + slli $r10, P3H, #21 + or P1L, P1L, $r10 + slli $r10, P3H, #1 + srli $r10, $r10, #12 + or P1H, P1H, $r10 + slli $r10, $r6, #20 + or P1H, P1H, $r10 + +.LEretA: +.LE999: + popm $r6, $r10 + pop $lp + ret5 $lp + +.LEspecA: + #ADD(P3L, P3L) + move $r15, P3L + add P3L, P3L, P3L + slt $r15, P3L, $r15 + + #ADDC(P3H, P3H) + add P3H, P3H, P3H + add P3H, P3H, $r15 + bnez $r6, .Li7 + or $r10, P3H, P3L + beqz $r10, .Li8 + j .LElab1 +.Li8: + subri $r15, $r9, #0x7ff + beqzs8 .LEspecB + add P3L, P2H, P2H + or $r10, P3L, P2L + bnez $r10, .LEretB + sltsi $r15, P2H, #0 + bnezs8 .LEretA + +.LEretB: + move P1L, P2L + move P1H, P2H + j .LE999 +.Li7: + or $r10, P3H, P3L + bnez $r10, .LEnan + subri $r15, $r9, #0x7ff + bnezs8 .LEretA + xor $r10, P1H, P2H + sltsi $r15, $r10, #0 + bnezs8 .LEnan + j .LEretB + +.LEspecB: + #ADD(O1L, O1L) + move $r15, O1L + add O1L, O1L, O1L + slt $r15, O1L, $r15 + + #ADDC(O1H, O1H) + add O1H, O1H, O1H + add O1H, O1H, $r15 + bnez $r9, .Li11 + or $r10, O1H, O1L + beqz $r10, .LEretA + j .LElab2 +.Li11: + or $r10, O1H, O1L + beqz $r10, .LEretB + +.LEnan: + move P1H, #0xfff80000 + move P1L, #0 + j .LEretA + +.LEund: + subri $r9, $r6, #1 + move P2L, #0 +.LL26: + move $r10, #0x20 + slt $r15, $r9, $r10 + bnezs8 .LL27 + or P2L, P2L, P3L + move P3L, P3H + move P3H, #0 + addi $r9, $r9, #0xffffffe0 + bnez P3L, .LL26 +.LL27: + beqz $r9, .LL28 + move P1L, P3H + move $r10, P3L + srl P3L, P3L, $r9 + srl P3H, P3H, $r9 + subri $r9, $r9, #0x20 + sll P1L, P1L, $r9 + or P3L, P3L, P1L + sll $r10, $r10, $r9 + or P2L, P2L, $r10 + beqz P2L, .LL28 + ori P3L, P3L, #1 +.LL28: + move $r6, #0 + j .LElab8 + .size __subdf3, .-__subdf3 + .size __adddf3, .-__adddf3 +#endif /* L_addsub_df */ + + + +#ifdef L_mul_sf + +#if !defined (__big_endian__) + #define P1L $r0 + #define P1H $r1 + #define P2L $r2 + #define P2H $r3 +#else + #define P1H $r0 + #define P1L $r1 + #define P2H $r2 + #define P2L $r3 +#endif + .text + .align 2 + .global __mulsf3 + .type __mulsf3, @function +__mulsf3: + push $lp + pushm $r6, $r10 + + srli $r3, $r0, #23 + andi $r3, $r3, #0xff + srli $r5, $r1, #23 + andi $r5, $r5, #0xff + move $r6, #0x80000000 + slli $r2, $r0, #8 + or $r2, $r2, $r6 + slli $r4, $r1, #8 + or $r4, $r4, $r6 + xor $r8, $r0, $r1 + and $r6, $r6, $r8 + + addi $r8, $r3, #-1 + slti $r15, $r8, #0xfe + beqzs8 .LFspecA + +.LFlab1: + addi $r8, $r5, #-1 + slti $r15, $r8, #0xfe + beqzs8 .LFspecB + +.LFlab2: + move $r10, $r3 +/* This is a 64-bit multiple. ($r2, $r7) is (high, low). */ +#ifndef __NDS32_ISA_V3M__ + mulr64 $r2, $r2, $r4 +#else + pushm $r0, $r1 + pushm $r4, $r5 + move P1L, $r2 + movi P1H, #0 + move P2L, $r4 + movi P2H, #0 + bal __muldi3 + movd44 $r2, $r0 + popm $r4, $r5 + popm $r0, $r1 +#endif +#ifndef __big_endian__ + move $r7, $r2 + move $r2, $r3 +#else + move $r7, $r3 +#endif + move $r3, $r10 + + beqz $r7, .Li17 + ori $r2, $r2, #1 + +.Li17: + sltsi $r15, $r2, #0 + bnezs8 .Li18 + slli $r2, $r2, #1 + addi $r3, $r3, #-1 +.Li18: + addi $r8, $r5, #0xffffff82 + add $r3, $r3, $r8 + addi $r8, $r3, #-1 + slti $r15, $r8, #0xfe + beqzs8 .LFoveund + +.LFlab8: + #ADD($r2, $0x80) + move $r15, #0x80 + add $r2, $r2, $r15 + slt $r15, $r2, $r15 + + #ADDC($r3, $0x0) + add $r3, $r3, $r15 + srli $r8, $r2, #8 + andi $r8, $r8, #1 + sub $r2, $r2, $r8 + slli $r2, $r2, #1 + srli $r2, $r2, #9 + slli $r8, $r3, #23 + or $r2, $r2, $r8 + or $r0, $r2, $r6 + +.LF999: + popm $r6, $r10 + pop $lp + ret5 $lp + +.LFspecA: + bnez $r3, .Li19 + add $r2, $r2, $r2 + beqz $r2, .Li20 +#ifdef __NDS32_PERF_EXT__ + clz $r7, $r2 +#else + pushm $r0, $r5 + move $r0, $r2 + bal __clzsi2 + move $r7, $r0 + popm $r0, $r5 +#endif + sub $r3, $r3, $r7 + sll $r2, $r2, $r7 + j .LFlab1 +.Li20: + subri $r15, $r5, #0xff + beqzs8 .LFnan + j .LFzer +.Li19: + add $r8, $r2, $r2 + bnez $r8, .LFnan + bnez $r5, .Li21 + add $r8, $r4, $r4 + beqz $r8, .LFnan +.Li21: + subri $r15, $r5, #0xff + bnezs8 .LFinf + +.LFspecB: + bnez $r5, .Li22 + add $r4, $r4, $r4 + beqz $r4, .LFzer +#ifdef __NDS32_PERF_EXT__ + clz $r7, $r4 +#else + pushm $r0, $r5 + move $r0, $r4 + bal __clzsi2 + move $r7, $r0 + popm $r0, $r5 +#endif + sub $r5, $r5, $r7 + sll $r4, $r4, $r7 + j .LFlab2 + +.LFzer: + move $r0, $r6 + j .LF999 +.Li22: + add $r8, $r4, $r4 + bnez $r8, .LFnan + +.LFinf: + move $r8, #0x7f800000 + or $r0, $r6, $r8 + j .LF999 + +.LFnan: + move $r0, #0xffc00000 + j .LF999 + +.LFoveund: + bgtz $r3, .LFinf + subri $r7, $r3, #1 + slti $r15, $r7, #0x20 + beqzs8 .LFzer + subri $r8, $r7, #0x20 + sll $r3, $r2, $r8 + srl $r2, $r2, $r7 + beqz $r3, .Li25 + ori $r2, $r2, #2 +.Li25: + move $r3, #0 + addi $r8, $r2, #0x80 + sltsi $r15, $r8, #0 + beqzs8 .LFlab8 + move $r3, #1 + j .LFlab8 + .size __mulsf3, .-__mulsf3 +#endif /* L_mul_sf */ + + + +#ifdef L_mul_df + +#ifndef __big_endian__ + #define P1L $r0 + #define P1H $r1 + #define P2L $r2 + #define P2H $r3 + #define P3L $r4 + #define P3H $r5 + #define O1L $r7 + #define O1H $r8 +#else + #define P1H $r0 + #define P1L $r1 + #define P2H $r2 + #define P2L $r3 + #define P3H $r4 + #define P3L $r5 + #define O1H $r7 + #define O1L $r8 +#endif + .text + .align 2 + .global __muldf3 + .type __muldf3, @function +__muldf3: + push $lp + pushm $r6, $r10 + + slli $r6, P1H, #1 + srli $r6, $r6, #21 + slli P3H, P1H, #11 + srli $r10, P1L, #21 + or P3H, P3H, $r10 + slli P3L, P1L, #11 + move O1L, #0x80000000 + or P3H, P3H, O1L + slli $r9, P2H, #1 + srli $r9, $r9, #21 + slli O1H, P2H, #11 + srli $r10, P2L, #21 + or O1H, O1H, $r10 + or O1H, O1H, O1L + xor P1H, P1H, P2H + and P1H, P1H, O1L + slli O1L, P2L, #11 + + addi $r10, $r6, #-1 + slti $r15, $r10, #0x7fe + beqzs8 .LFspecA + +.LFlab1: + addi $r10, $r9, #-1 + slti $r15, $r10, #0x7fe + beqzs8 .LFspecB + +.LFlab2: + addi $r10, $r9, #0xfffffc02 + add $r6, $r6, $r10 + + move $r10, $r8 +/* This is a 64-bit multiple. */ +#ifndef __big_endian__ +/* For little endian: ($r9, $r3) is (high, low). */ +#ifndef __NDS32_ISA_V3M__ + mulr64 $r8, $r5, $r8 +#else + pushm $r0, $r5 + move $r0, $r5 + movi $r1, #0 + move $r2, $r8 + movi $r3, #0 + bal __muldi3 + movd44 $r8, $r0 + popm $r0, $r5 +#endif + move $r3, $r8 +#else /* __big_endian__ */ +/* For big endain: ($r9, $r2) is (high, low). */ +#ifndef __NDS32_ISA_V3M__ + mulr64 $r8, $r4, $r7 +#else + pushm $r0, $r5 + move $r1, $r4 + movi $r0, #0 + move $r3, $r7 + movi $r2, #0 + bal __muldi3 + movd44 $r8, $r0 + popm $r0, $r5 +#endif + move $r2, $r9 + move $r9, $r8 +#endif /* __big_endian__ */ + move $r8, $r10 + + move $r10, P1H +/* This is a 64-bit multiple. */ +#ifndef __big_endian__ +/* For little endian: ($r0, $r2) is (high, low). */ +#ifndef __NDS32_ISA_V3M__ + mulr64 $r0, $r4, $r8 +#else + pushm $r2, $r5 + move $r0, $r4 + movi $r1, #0 + move $r2, $r8 + movi $r3, #0 + bal __muldi3 + popm $r2, $r5 +#endif + move $r2, $r0 + move $r0, $r1 +#else /* __big_endian__ */ +/* For big endain: ($r1, $r3) is (high, low). */ +#ifndef __NDS32_ISA_V3M__ + mulr64 $r0, $r5, $r7 +#else + pushm $r2, $r5 + move $r1, $r5 + movi $r0, #0 + move $r3, $r7 + movi $r2, #0 + bal __muldi3 + popm $r2, $r5 +#endif + move $r3, $r1 + move $r1, $r0 +#endif /* __big_endian__ */ + move P1H, $r10 + + #ADD(P2H, P1L) + add P2H, P2H, P1L + slt $r15, P2H, P1L + + #ADDC($r9, $0x0) + add $r9, $r9, $r15 + + move $r10, P1H +/* This is a 64-bit multiple. */ +#ifndef __big_endian__ +/* For little endian: ($r0, $r8) is (high, low). */ +#ifndef __NDS32_ISA_V3M__ + mulr64 $r0, $r5, $r7 +#else + pushm $r2, $r5 + move $r0, $r5 + movi $r1, #0 + move $r2, $r7 + movi $r3, #0 + bal __muldi3 + popm $r2, $r5 +#endif + move $r8, $r0 + move $r0, $r1 +#else /* __big_endian__ */ +/* For big endian: ($r1, $r7) is (high, low). */ +#ifndef __NDS32_ISA_V3M__ + mulr64 $r0, $r4, $r8 +#else + pushm $r2, $r5 + move $r1, $r4 + movi $r0, #0 + move $r3, $r8 + movi $r2, #0 + bal __muldi3 + popm $r2, $r5 +#endif + move $r7, $r1 + move $r1, $r0 +#endif /* __big_endian__ */ + move P1H, $r10 + + #ADD(P2L, O1H) + add P2L, P2L, O1H + slt $r15, P2L, O1H + + + #ADDCC(P2H, P1L) + beqzs8 .LL29 + add P2H, P2H, P1L + slt $r15, P2H, P1L + beqzs8 .LL30 + addi P2H, P2H, #0x1 + j .LL31 +.LL30: + move $r15, #1 + add P2H, P2H, $r15 + slt $r15, P2H, $r15 + j .LL31 +.LL29: + add P2H, P2H, P1L + slt $r15, P2H, P1L +.LL31: + + #ADDC($r9, $0x0) + add $r9, $r9, $r15 + +/* This is a 64-bit multiple. */ +#ifndef __big_endian__ +/* For little endian: ($r8, $r0) is (high, low). */ + move $r10, $r9 +#ifndef __NDS32_ISA_V3M__ + mulr64 $r8, $r4, $r7 +#else + pushm $r0, $r5 + move $r0, $r4 + movi $r1, #0 + move $r2, $r7 + movi $r3, #0 + bal __muldi3 + movd44 $r8, $r0 + popm $r0, $r5 +#endif + move $r0, $r8 + move $r8, $r9 + move $r9, $r10 +#else /* __big_endian__ */ +/* For big endian: ($r7, $r1) is (high, low). */ + move $r10, $r6 +#ifndef __NDS32_ISA_V3M__ + mulr64 $r6, $r5, $r8 +#else + pushm $r0, $r5 + move $r1, $r5 + movi $r0, #0 + move $r3, $r8 + movi $r2, #0 + bal __muldi3 + movd44 $r6, $r0 + popm $r0, $r5 +#endif + move $r1, $r7 + move $r7, $r6 + move $r6, $r10 +#endif /* __big_endian__ */ + + #ADD(P2L, O1H) + add P2L, P2L, O1H + slt $r15, P2L, O1H + + + #ADDCC(P2H, $0x0) + beqzs8 .LL34 + add P2H, P2H, $r15 + slt $r15, P2H, $r15 +.LL34: + + #ADDC($r9, $0x0) + add $r9, $r9, $r15 + or $r10, P1L, P2L + beqz $r10, .Li13 + ori P2H, P2H, #1 +.Li13: + move P3H, $r9 + move P3L, P2H + sltsi $r15, P3H, #0 + bnezs8 .Li14 + + move $r15, P3L + add P3L, P3L, P3L + slt $r15, P3L, $r15 + add P3H, P3H, P3H + add P3H, P3H, $r15 + addi $r6, $r6, #-1 +.Li14: + addi $r10, $r6, #-1 + slti $r15, $r10, #0x7fe + beqzs8 .LFoveund + + #ADD(P3L, $0x400) + move $r15, #0x400 + add P3L, P3L, $r15 + slt $r15, P3L, $r15 + + + #ADDCC(P3H, $0x0) + beqzs8 .LL37 + add P3H, P3H, $r15 + slt $r15, P3H, $r15 +.LL37: + + #ADDC($r6, $0x0) + add $r6, $r6, $r15 + +.LFlab8: + srli $r10, P3L, #11 + andi $r10, $r10, #1 + sub P3L, P3L, $r10 + srli P1L, P3L, #11 + slli $r10, P3H, #21 + or P1L, P1L, $r10 + slli $r10, P3H, #1 + srli $r10, $r10, #12 + or P1H, P1H, $r10 + slli $r10, $r6, #20 + or P1H, P1H, $r10 + +.LFret: +.LF999: + popm $r6, $r10 + pop $lp + ret5 $lp + +.LFspecA: + #ADD(P3L, P3L) + move $r15, P3L + add P3L, P3L, P3L + slt $r15, P3L, $r15 + + #ADDC(P3H, P3H) + add P3H, P3H, P3H + add P3H, P3H, $r15 + bnez $r6, .Li15 + or $r10, P3H, P3L + beqz $r10, .Li16 + + + #NORMd($r4, P1L, P2H) + bnez P3H, .LL38 + bnez P3L, .LL39 + move $r6, #0 + j .LL40 +.LL39: + move P3H, P3L + move P3L, #0 + move P1L, #32 + sub $r6, $r6, P1L +.LL38: +#ifndef __big_endian__ +#ifdef __NDS32_PERF_EXT__ + clz $r0, P3H +#else + pushm $r1, P3H + move $r0, P3H + bal __clzsi2 + popm $r1, $r5 +#endif +#else /* __big_endian__ */ +#ifdef __NDS32_PERF_EXT__ + clz $r1, $r4 +#else + push $r0 + pushm $r2, $r5 + move $r0, $r4 + bal __clzsi2 + move $r1, $r0 + popm $r2, $r5 + pop $r0 +#endif +#endif /* __big_endian__ */ + beqz P1L, .LL40 + sub $r6, $r6, P1L + subri P2H, P1L, #32 + srl P2H, P3L, P2H + sll P3L, P3L, P1L + sll P3H, P3H, P1L + or P3H, P3H, P2H +.LL40: + #NORMd End + + j .LFlab1 +.Li16: + subri $r15, $r9, #0x7ff + beqzs8 .LFnan + j .LFret +.Li15: + or $r10, P3H, P3L + bnez $r10, .LFnan + bnez $r9, .Li17 + slli $r10, O1H, #1 + or $r10, $r10, O1L + beqz $r10, .LFnan +.Li17: + subri $r15, $r9, #0x7ff + bnezs8 .LFinf + +.LFspecB: + #ADD(O1L, O1L) + move $r15, O1L + add O1L, O1L, O1L + slt $r15, O1L, $r15 + + #ADDC(O1H, O1H) + add O1H, O1H, O1H + add O1H, O1H, $r15 + bnez $r9, .Li18 + or $r10, O1H, O1L + beqz $r10, .Li19 + + + #NORMd($r7, P2L, P1L) + bnez O1H, .LL41 + bnez O1L, .LL42 + move $r9, #0 + j .LL43 +.LL42: + move O1H, O1L + move O1L, #0 + move P2L, #32 + sub $r9, $r9, P2L +.LL41: +#ifndef __big_endian__ +#ifdef __NDS32_PERF_EXT__ + clz $r2, $r8 +#else + pushm $r0, $r1 + pushm $r3, $r5 + move $r0, $r8 + bal __clzsi2 + move $r2, $r0 + popm $r3, $r5 + popm $r0, $r1 +#endif +#else /* __big_endian__ */ +#ifdef __NDS32_PERF_EXT__ + clz $r3, $r7 +#else + pushm $r0, $r2 + pushm $r4, $r5 + move $r0, $r7 + bal __clzsi2 + move $r3, $r0 + popm $r4, $r5 + popm $r0, $r2 +#endif +#endif /* __big_endian__ */ + beqz P2L, .LL43 + sub $r9, $r9, P2L + subri P1L, P2L, #32 + srl P1L, O1L, P1L + sll O1L, O1L, P2L + sll O1H, O1H, P2L + or O1H, O1H, P1L +.LL43: + #NORMd End + + j .LFlab2 +.Li19: + move P1L, #0 + j .LFret +.Li18: + or $r10, O1H, O1L + bnez $r10, .LFnan + +.LFinf: + move $r10, #0x7ff00000 + or P1H, P1H, $r10 + move P1L, #0 + j .LFret + +.LFnan: + move P1H, #0xfff80000 + move P1L, #0 + j .LFret + +.LFoveund: + bgtz $r6, .LFinf + subri P1L, $r6, #1 + move P2L, #0 +.LL44: + move $r10, #0x20 + slt $r15, P1L, $r10 + bnezs8 .LL45 + or P2L, P2L, P3L + move P3L, P3H + move P3H, #0 + addi P1L, P1L, #0xffffffe0 + bnez P3L, .LL44 +.LL45: + beqz P1L, .LL46 + move P2H, P3H + move $r10, P3L + srl P3L, P3L, P1L + srl P3H, P3H, P1L + subri P1L, P1L, #0x20 + sll P2H, P2H, P1L + or P3L, P3L, P2H + sll $r10, $r10, P1L + or P2L, P2L, $r10 + beqz P2L, .LL46 + ori P3L, P3L, #1 +.LL46: + #ADD(P3L, $0x400) + move $r15, #0x400 + add P3L, P3L, $r15 + slt $r15, P3L, $r15 + + #ADDC(P3H, $0x0) + add P3H, P3H, $r15 + srli $r6, P3H, #31 + j .LFlab8 + .size __muldf3, .-__muldf3 +#endif /* L_mul_df */ + + + +#ifdef L_div_sf + + .text + .align 2 + .global __divsf3 + .type __divsf3, @function +__divsf3: + push $lp + pushm $r6, $r10 + + move $r7, #0x80000000 + srli $r4, $r0, #23 + andi $r4, $r4, #0xff + srli $r6, $r1, #23 + andi $r6, $r6, #0xff + slli $r3, $r0, #8 + or $r3, $r3, $r7 + slli $r5, $r1, #8 + or $r5, $r5, $r7 + xor $r10, $r0, $r1 + and $r7, $r7, $r10 + + addi $r10, $r4, #-1 + slti $r15, $r10, #0xfe + beqzs8 .LGspecA + +.LGlab1: + addi $r10, $r6, #-1 + slti $r15, $r10, #0xfe + beqzs8 .LGspecB + +.LGlab2: + slt $r15, $r3, $r5 + bnezs8 .Li27 + srli $r3, $r3, #1 + addi $r4, $r4, #1 +.Li27: + srli $r8, $r5, #14 + divr $r0, $r2, $r3, $r8 + andi $r9, $r5, #0x3fff + mul $r1, $r9, $r0 + slli $r2, $r2, #14 + + #SUB($r2, $r1) + move $r15, $r2 + sub $r2, $r2, $r1 + slt $r15, $r15, $r2 + beqzs8 .Li28 + addi $r0, $r0, #-1 + + #ADD($r2, $r5) + add $r2, $r2, $r5 + slt $r15, $r2, $r5 +.Li28: + divr $r3, $r2, $r2, $r8 + mul $r1, $r9, $r3 + slli $r2, $r2, #14 + + #SUB($r2, $r1) + move $r15, $r2 + sub $r2, $r2, $r1 + slt $r15, $r15, $r2 + beqzs8 .Li29 + addi $r3, $r3, #-1 + + #ADD($r2, $r5) + add $r2, $r2, $r5 + slt $r15, $r2, $r5 +.Li29: + slli $r10, $r0, #14 + add $r3, $r3, $r10 + slli $r3, $r3, #4 + beqz $r2, .Li30 + ori $r3, $r3, #1 +.Li30: + subri $r10, $r6, #0x7e + add $r4, $r4, $r10 + addi $r10, $r4, #-1 + slti $r15, $r10, #0xfe + beqzs8 .LGoveund + +.LGlab8: + #ADD($r3, $0x80) + move $r15, #0x80 + add $r3, $r3, $r15 + slt $r15, $r3, $r15 + + #ADDC($r4, $0x0) + add $r4, $r4, $r15 + srli $r10, $r3, #8 + andi $r10, $r10, #1 + sub $r3, $r3, $r10 + slli $r3, $r3, #1 + srli $r3, $r3, #9 + slli $r10, $r4, #23 + or $r3, $r3, $r10 + or $r0, $r3, $r7 + +.LG999: + popm $r6, $r10 + pop $lp + ret5 $lp + +.LGspecA: + bnez $r4, .Li31 + add $r3, $r3, $r3 + beqz $r3, .Li31 +#ifdef __NDS32_PERF_EXT__ + clz $r8, $r3 +#else + pushm $r0, $r5 + move $r0, $r3 + bal __clzsi2 + move $r8, $r0 + popm $r0, $r5 +#endif + sub $r4, $r4, $r8 + sll $r3, $r3, $r8 + j .LGlab1 +.Li31: + bne $r6, $r4, .Li33 + add $r10, $r5, $r5 + beqz $r10, .LGnan +.Li33: + subri $r15, $r6, #0xff + beqzs8 .LGspecB + beqz $r4, .LGzer + add $r10, $r3, $r3 + bnez $r10, .LGnan + j .LGinf + +.LGspecB: + bnez $r6, .Li34 + add $r5, $r5, $r5 + beqz $r5, .LGinf +#ifdef __NDS32_PERF_EXT__ + clz $r8, $r5 +#else + pushm $r0, $r5 + move $r0, $r5 + bal __clzsi2 + move $r8, $r0 + popm $r0, $r5 +#endif + sub $r6, $r6, $r8 + sll $r5, $r5, $r8 + j .LGlab2 +.Li34: + add $r10, $r5, $r5 + bnez $r10, .LGnan + +.LGzer: + move $r0, $r7 + j .LG999 + +.LGoveund: + bgtz $r4, .LGinf + subri $r8, $r4, #1 + slti $r15, $r8, #0x20 + beqzs8 .LGzer + subri $r10, $r8, #0x20 + sll $r4, $r3, $r10 + srl $r3, $r3, $r8 + beqz $r4, .Li37 + ori $r3, $r3, #2 +.Li37: + move $r4, #0 + addi $r10, $r3, #0x80 + sltsi $r15, $r10, #0 + beqzs8 .LGlab8 + move $r4, #1 + j .LGlab8 + +.LGinf: + move $r10, #0x7f800000 + or $r0, $r7, $r10 + j .LG999 + +.LGnan: + move $r0, #0xffc00000 + j .LG999 + .size __divsf3, .-__divsf3 +#endif /* L_div_sf */ + + + +#ifdef L_div_df + +#ifndef __big_endian__ + #define P1L $r0 + #define P1H $r1 + #define P2L $r2 + #define P2H $r3 + #define P3L $r4 + #define P3H $r5 + #define O1L $r7 + #define O1H $r8 +#else + #define P1H $r0 + #define P1L $r1 + #define P2H $r2 + #define P2L $r3 + #define P3H $r4 + #define P3L $r5 + #define O1H $r7 + #define O1L $r8 +#endif + .text + .align 2 + .global __divdf3 + .type __divdf3, @function +__divdf3: + push $lp + pushm $r6, $r10 + + slli $r6, P1H, #1 + srli $r6, $r6, #21 + slli P3H, P1H, #11 + srli $r10, P1L, #21 + or P3H, P3H, $r10 + slli P3L, P1L, #11 + move O1L, #0x80000000 + or P3H, P3H, O1L + slli $r9, P2H, #1 + srli $r9, $r9, #21 + slli O1H, P2H, #11 + srli $r10, P2L, #21 + or O1H, O1H, $r10 + or O1H, O1H, O1L + xor P1H, P1H, P2H + and P1H, P1H, O1L + slli O1L, P2L, #11 + + addi $r10, $r6, #-1 + slti $r15, $r10, #0x7fe + beqzs8 .LGspecA + +.LGlab1: + addi $r10, $r9, #-1 + slti $r15, $r10, #0x7fe + beqzs8 .LGspecB + +.LGlab2: + sub $r6, $r6, $r9 + addi $r6, $r6, #0x3ff + srli P3L, P3L, #1 + slli $r10, P3H, #31 + or P3L, P3L, $r10 + srli P3H, P3H, #1 + srli $r9, O1H, #16 + divr P2H, P3H, P3H, $r9 + move $r10, #0xffff + and P2L, O1H, $r10 + mul P1L, P2L, P2H + slli P3H, P3H, #16 + srli $r10, P3L, #16 + or P3H, P3H, $r10 + + #SUB(P3H, P1L) + move $r15, P3H + sub P3H, P3H, P1L + slt $r15, $r15, P3H + beqzs8 .Li20 + +.Lb21: + addi P2H, P2H, #-1 + add P3H, P3H, O1H + slt $r15, P3H, O1H + beqzs8 .Lb21 +.Li20: + divr $r9, P3H, P3H, $r9 + mul P1L, P2L, $r9 + slli P3H, P3H, #16 + move $r15, #0xffff + and $r10, P3L, $r15 + or P3H, P3H, $r10 + + #SUB(P3H, P1L) + move $r15, P3H + sub P3H, P3H, P1L + slt $r15, $r15, P3H + beqzs8 .Li22 + +.Lb23: + addi $r9, $r9, #-1 + add P3H, P3H, O1H + slt $r15, P3H, O1H + beqzs8 .Lb23 +.Li22: + slli P2H, P2H, #16 + add P2H, P2H, $r9 + +/* This is a 64-bit multiple. */ +#ifndef __big_endian__ +/* For little endian: ($r0, $r9) is (high, low). */ + move $r10, $r1 +#ifndef __NDS32_ISA_V3M__ + mulr64 $r0, $r3, $r7 +#else + pushm $r2, $r5 + move $r0, $r3 + movi $r1, #0 + move $r2, $r7 + movi $r3, #0 + bal __muldi3 + popm $r2, $r5 +#endif + move $r9, $r0 + move $r0, $r1 + move $r1, $r10 +#else /* __big_endian__ */ +/* For big endian: ($r1, $r9) is (high, low). */ + move $r10, $r0 +#ifndef __NDS32_ISA_V3M__ + mulr64 $r0, $r2, $r8 +#else + pushm $r2, $r5 + move $r1, $r2 + movi $r0, #0 + move $r3, $r8 + movi $r2, #0 + bal __muldi3 + popm $r2, $r5 +#endif + move $r9, $r1 + move $r1, $r0 + move $r0, $r10 +#endif /* __big_endian__ */ + + move P3L, #0 + + #SUB(P3L, $r9) + move $r15, P3L + sub P3L, P3L, $r9 + slt $r15, $r15, P3L + + + #SUBCC(P3H, P1L) + beqzs8 .LL47 + move $r15, P3H + sub P3H, P3H, P1L + slt $r15, $r15, P3H + beqzs8 .LL48 + subi333 P3H, P3H, #1 + j .LL49 +.LL48: + move $r15, P3H + subi333 P3H, P3H, #1 + slt $r15, $r15, P3H + j .LL49 +.LL47: + move $r15, P3H + sub P3H, P3H, P1L + slt $r15, $r15, P3H +.LL49: + + beqzs8 .Li24 + +.LGlab3: + addi P2H, P2H, #-1 + + #ADD(P3L, O1L) + add P3L, P3L, O1L + slt $r15, P3L, O1L + + + #ADDCC(P3H, O1H) + beqzs8 .LL50 + add P3H, P3H, O1H + slt $r15, P3H, O1H + beqzs8 .LL51 + addi P3H, P3H, #0x1 + j .LL52 +.LL51: + move $r15, #1 + add P3H, P3H, $r15 + slt $r15, P3H, $r15 + j .LL52 +.LL50: + add P3H, P3H, O1H + slt $r15, P3H, O1H +.LL52: + + beqzs8 .LGlab3 +.Li24: + bne P3H, O1H, .Li25 + move P1L, O1L + move P3H, P3L + move $r9, #0 + move P2L, $r9 + j .Le25 +.Li25: + srli P2L, O1H, #16 + divr $r9, P3H, P3H, P2L + move $r10, #0xffff + and $r10, O1H, $r10 + mul P1L, $r10, $r9 + slli P3H, P3H, #16 + srli $r15, P3L, #16 + or P3H, P3H, $r15 + + #SUB(P3H, P1L) + move $r15, P3H + sub P3H, P3H, P1L + slt $r15, $r15, P3H + beqzs8 .Li26 + +.Lb27: + addi $r9, $r9, #-1 + add P3H, P3H, O1H + slt $r15, P3H, O1H + beqzs8 .Lb27 +.Li26: + divr P2L, P3H, P3H, P2L + mul P1L, $r10, P2L + slli P3H, P3H, #16 + move $r10, #0xffff + and $r10, P3L, $r10 + or P3H, P3H, $r10 + + #SUB(P3H, P1L) + move $r15, P3H + sub P3H, P3H, P1L + slt $r15, $r15, P3H + beqzs8 .Li28 + +.Lb29: + addi P2L, P2L, #-1 + add P3H, P3H, O1H + slt $r15, P3H, O1H + beqzs8 .Lb29 +.Li28: + slli $r9, $r9, #16 + add $r9, $r9, P2L + +/* This is a 64-bit multiple. */ +#ifndef __big_endian__ +/* For little endian: ($r0, $r2) is (high, low). */ + move $r10, $r1 +#ifndef __NDS32_ISA_V3M__ + mulr64 $r0, $r9, $r7 +#else + pushm $r2, $r5 + move $r0, $r9 + movi $r1, #0 + move $r2, $r7 + movi $r3, #0 + bal __muldi3 + popm $r2, $r5 +#endif + move $r2, $r0 + move $r0, $r1 + move $r1, $r10 +#else /* __big_endian__ */ +/* For big endian: ($r1, $r3) is (high, low). */ + move $r10, $r0 +#ifndef __NDS32_ISA_V3M__ + mulr64 $r0, $r9, $r8 +#else + pushm $r2, $r5 + move $r0, $r9 + movi $r1, #0 + move $r2, $r7 + movi $r3, #0 + bal __muldi3 + popm $r2, $r5 +#endif + move $r3, $r1 + move $r1, $r0 + move $r0, $r10 +#endif /* __big_endian__ */ + +.Le25: + move P3L, #0 + + #SUB(P3L, P2L) + move $r15, P3L + sub P3L, P3L, P2L + slt $r15, $r15, P3L + + + #SUBCC(P3H, P1L) + beqzs8 .LL53 + move $r15, P3H + sub P3H, P3H, P1L + slt $r15, $r15, P3H + beqzs8 .LL54 + subi333 P3H, P3H, #1 + j .LL55 +.LL54: + move $r15, P3H + subi333 P3H, P3H, #1 + slt $r15, $r15, P3H + j .LL55 +.LL53: + move $r15, P3H + sub P3H, P3H, P1L + slt $r15, $r15, P3H +.LL55: + + beqzs8 .Li30 + +.LGlab4: + addi $r9, $r9, #-1 + + #ADD(P3L, O1L) + add P3L, P3L, O1L + slt $r15, P3L, O1L + + + #ADDCC(P3H, O1H) + beqzs8 .LL56 + add P3H, P3H, O1H + slt $r15, P3H, O1H + beqzs8 .LL57 + addi P3H, P3H, #0x1 + j .LL58 +.LL57: + move $r15, #1 + add P3H, P3H, $r15 + slt $r15, P3H, $r15 + j .LL58 +.LL56: + add P3H, P3H, O1H + slt $r15, P3H, O1H +.LL58: + + beqzs8 .LGlab4 +.Li30: + sltsi $r15, P2H, #0 + bnezs8 .Li31 + + #ADD($r9, $r9) + move $r15, $r9 + add $r9, $r9, $r9 + slt $r15, $r9, $r15 + + #ADDC(P2H, P2H) + add P2H, P2H, P2H + add P2H, P2H, $r15 + addi $r6, $r6, #-1 +.Li31: + or $r10, P3H, P3L + beqz $r10, .Li32 + ori $r9, $r9, #1 +.Li32: + move P3H, P2H + move P3L, $r9 + addi $r10, $r6, #-1 + slti $r15, $r10, #0x7fe + beqzs8 .LGoveund + + #ADD(P3L, $0x400) + move $r15, #0x400 + add P3L, P3L, $r15 + slt $r15, P3L, $r15 + + + #ADDCC(P3H, $0x0) + beqzs8 .LL61 + add P3H, P3H, $r15 + slt $r15, P3H, $r15 +.LL61: + + #ADDC($r6, $0x0) + add $r6, $r6, $r15 + +.LGlab8: + srli $r10, P3L, #11 + andi $r10, $r10, #1 + sub P3L, P3L, $r10 + srli P1L, P3L, #11 + slli $r10, P3H, #21 + or P1L, P1L, $r10 + slli $r10, P3H, #1 + srli $r10, $r10, #12 + or P1H, P1H, $r10 + slli $r10, $r6, #20 + or P1H, P1H, $r10 + +.LGret: +.LG999: + popm $r6, $r10 + pop $lp + ret5 $lp + +.LGoveund: + bgtz $r6, .LGinf + subri P2H, $r6, #1 + move P1L, #0 +.LL62: + move $r10, #0x20 + slt $r15, P2H, $r10 + bnezs8 .LL63 + or P1L, P1L, P3L + move P3L, P3H + move P3H, #0 + addi P2H, P2H, #0xffffffe0 + bnez P3L, .LL62 +.LL63: + beqz P2H, .LL64 + move P2L, P3H + move $r10, P3L + srl P3L, P3L, P2H + srl P3H, P3H, P2H + subri P2H, P2H, #0x20 + sll P2L, P2L, P2H + or P3L, P3L, P2L + sll $r10, $r10, P2H + or P1L, P1L, $r10 + beqz P1L, .LL64 + ori P3L, P3L, #1 +.LL64: + #ADD(P3L, $0x400) + move $r15, #0x400 + add P3L, P3L, $r15 + slt $r15, P3L, $r15 + + #ADDC(P3H, $0x0) + add P3H, P3H, $r15 + srli $r6, P3H, #31 + j .LGlab8 + +.LGspecA: + #ADD(P3L, P3L) + move $r15, P3L + add P3L, P3L, P3L + slt $r15, P3L, $r15 + + #ADDC(P3H, P3H) + add P3H, P3H, P3H + add P3H, P3H, $r15 + bnez $r6, .Li33 + or $r10, P3H, P3L + beqz $r10, .Li33 + + + #NORMd($r4, P2H, P2L) + bnez P3H, .LL65 + bnez P3L, .LL66 + move $r6, #0 + j .LL67 +.LL66: + move P3H, P3L + move P3L, #0 + move P2H, #32 + sub $r6, $r6, P2H +.LL65: +#ifndef __big_endian__ +#ifdef __NDS32_PERF_EXT__ + clz $r3, $r5 +#else + pushm $r0, $r2 + pushm $r4, $r5 + move $r0, $r5 + bal __clzsi2 + move $r3, $r0 + popm $r4, $r5 + popm $r0, $r2 +#endif +#else /* __big_endian__ */ +#ifdef __NDS32_PERF_EXT__ + clz $r2, $r4 +#else + pushm $r0, $r1 + pushm $r3, $r5 + move $r0, $r4 + bal __clzsi2 + move $r2, $r0 + popm $r3, $r5 + popm $r0, $r1 +#endif +#endif /* __big_endian_ */ + beqz P2H, .LL67 + sub $r6, $r6, P2H + subri P2L, P2H, #32 + srl P2L, P3L, P2L + sll P3L, P3L, P2H + sll P3H, P3H, P2H + or P3H, P3H, P2L +.LL67: + #NORMd End + + j .LGlab1 +.Li33: + bne $r6, $r9, .Li35 + slli $r10, O1H, #1 + or $r10, $r10, O1L + beqz $r10, .LGnan +.Li35: + subri $r15, $r9, #0x7ff + beqzs8 .LGspecB + beqz $r6, .LGret + or $r10, P3H, P3L + bnez $r10, .LGnan + +.LGinf: + move $r10, #0x7ff00000 + or P1H, P1H, $r10 + move P1L, #0 + j .LGret + +.LGspecB: + #ADD(O1L, O1L) + move $r15, O1L + add O1L, O1L, O1L + slt $r15, O1L, $r15 + + #ADDC(O1H, O1H) + add O1H, O1H, O1H + add O1H, O1H, $r15 + bnez $r9, .Li36 + or $r10, O1H, O1L + beqz $r10, .LGinf + + + #NORMd($r7, P2H, P2L) + bnez O1H, .LL68 + bnez O1L, .LL69 + move $r9, #0 + j .LL70 +.LL69: + move O1H, O1L + move O1L, #0 + move P2H, #32 + sub $r9, $r9, P2H +.LL68: +#ifndef __big_endian__ +#ifdef __NDS32_PERF_EXT__ + clz $r3, $r8 +#else + pushm $r0, $r2 + pushm $r4, $r5 + move $r0, $r8 + bal __clzsi2 + move $r3, $r0 + popm $r4, $r5 + popm $r0, $r2 +#endif +#else /* __big_endian__ */ +#ifdef __NDS32_PERF_EXT__ + clz $r2, $r7 +#else + pushm $r0, $r1 + pushm $r3, $r5 + move $r0, $r7 + bal __clzsi2 + move $r2, $r0 + popm $r3, $r5 + popm $r0, $r1 +#endif +#endif /* __big_endian__ */ + beqz P2H, .LL70 + sub $r9, $r9, P2H + subri P2L, P2H, #32 + srl P2L, O1L, P2L + sll O1L, O1L, P2H + sll O1H, O1H, P2H + or O1H, O1H, P2L +.LL70: + #NORMd End + + j .LGlab2 +.Li36: + or $r10, O1H, O1L + beqz $r10, .Li38 + +.LGnan: + move P1H, #0xfff80000 +.Li38: + move P1L, #0 + j .LGret + .size __divdf3, .-__divdf3 +#endif /* L_div_df */ + + + +#ifdef L_negate_sf + + .text + .align 2 + .global __negsf2 + .type __negsf2, @function +__negsf2: + push $lp + + move $r1, #0x80000000 + xor $r0, $r0, $r1 + +.LN999: + pop $lp + ret5 $lp + .size __negsf2, .-__negsf2 +#endif /* L_negate_sf */ + + + +#ifdef L_negate_df + +#ifndef __big_endian__ + #define P1H $r1 +#else + #define P1H $r0 +#endif + .text + .align 2 + .global __negdf2 + .type __negdf2, @function +__negdf2: + push $lp + + move $r2, #0x80000000 + xor P1H, P1H, $r2 + +.LP999: + pop $lp + ret5 $lp + .size __negdf2, .-__negdf2 +#endif /* L_negate_df */ + + + +#ifdef L_sf_to_df + +#ifndef __big_endian__ + #define O1L $r1 + #define O1H $r2 +#else + #define O1H $r1 + #define O1L $r2 +#endif + .text + .align 2 + .global __extendsfdf2 + .type __extendsfdf2, @function +__extendsfdf2: + push $lp + + srli $r3, $r0, #23 + andi $r3, $r3, #0xff + move $r5, #0x80000000 + and O1H, $r0, $r5 + addi $r5, $r3, #-1 + slti $r15, $r5, #0xfe + beqzs8 .LJspec + +.LJlab1: + addi $r3, $r3, #0x380 + slli $r5, $r0, #9 + srli $r5, $r5, #12 + or O1H, O1H, $r5 + slli O1L, $r0, #29 + +.LJret: + slli $r5, $r3, #20 + or O1H, O1H, $r5 + move $r0, $r1 + move $r1, $r2 + +.LJ999: + pop $lp + ret5 $lp + +.LJspec: + move O1L, #0 + add $r0, $r0, $r0 + beqz $r0, .LJret + bnez $r3, .Li42 + +.Lb43: + addi $r3, $r3, #-1 + add $r0, $r0, $r0 + move $r5, #0x800000 + slt $r15, $r0, $r5 + bnezs8 .Lb43 + j .LJlab1 +.Li42: + move $r3, #0x7ff + move $r5, #0xff000000 + slt $r15, $r5, $r0 + beqzs8 .LJret + move O1H, #0xfff80000 + j .LJret + .size __extendsfdf2, .-__extendsfdf2 +#endif /* L_sf_to_df */ + + + +#ifdef L_df_to_sf + +#ifndef __big_endian__ + #define P1L $r0 + #define P1H $r1 + #define P2L $r2 + #define P2H $r3 +#else + #define P1H $r0 + #define P1L $r1 + #define P2H $r2 + #define P2L $r3 +#endif + .text + .align 2 + .global __truncdfsf2 + .type __truncdfsf2, @function +__truncdfsf2: + push $lp + pushm $r6, $r8 + + slli P2H, P1H, #11 + srli $r7, P1L, #21 + or P2H, P2H, $r7 + slli P2L, P1L, #11 + move $r7, #0x80000000 + or P2H, P2H, $r7 + and $r5, P1H, $r7 + slli $r4, P1H, #1 + srli $r4, $r4, #21 + addi $r4, $r4, #0xfffffc80 + addi $r7, $r4, #-1 + slti $r15, $r7, #0xfe + beqzs8 .LKspec + +.LKlab1: + beqz P2L, .Li45 + ori P2H, P2H, #1 +.Li45: + #ADD(P2H, $0x80) + move $r15, #0x80 + add P2H, P2H, $r15 + slt $r15, P2H, $r15 + + #ADDC($r4, $0x0) + add $r4, $r4, $r15 + srli $r7, P2H, #8 + andi $r7, $r7, #1 + sub P2H, P2H, $r7 + slli P2H, P2H, #1 + srli P2H, P2H, #9 + slli $r7, $r4, #23 + or P2H, P2H, $r7 + or $r0, P2H, $r5 + +.LK999: + popm $r6, $r8 + pop $lp + ret5 $lp + +.LKspec: + subri $r15, $r4, #0x47f + bnezs8 .Li46 + slli $r7, P2H, #1 + or $r7, $r7, P2L + beqz $r7, .Li46 + move $r0, #0xffc00000 + j .LK999 +.Li46: + sltsi $r15, $r4, #0xff + bnezs8 .Li48 + move $r7, #0x7f800000 + or $r0, $r5, $r7 + j .LK999 +.Li48: + subri $r6, $r4, #1 + move $r7, #0x20 + slt $r15, $r6, $r7 + bnezs8 .Li49 + move $r0, $r5 + j .LK999 +.Li49: + subri $r8, $r6, #0x20 + sll $r7, P2H, $r8 + or P2L, P2L, $r7 + srl P2H, P2H, $r6 + move $r4, #0 + move $r7, #0x80000000 + or P2H, P2H, $r7 + j .LKlab1 + .size __truncdfsf2, .-__truncdfsf2 +#endif /* L_df_to_sf */ + + + +#ifdef L_df_to_si + +#ifndef __big_endian__ + #define P1L $r0 + #define P1H $r1 +#else + #define P1H $r0 + #define P1L $r1 +#endif + .global __fixdfsi + .type __fixdfsi, @function +__fixdfsi: + push $lp + pushm $r6, $r6 + + slli $r3, P1H, #11 + srli $r6, P1L, #21 + or $r3, $r3, $r6 + move $r6, #0x80000000 + or $r3, $r3, $r6 + slli $r6, P1H, #1 + srli $r6, $r6, #21 + subri $r2, $r6, #0x41e + blez $r2, .LLnaninf + move $r6, #0x20 + slt $r15, $r2, $r6 + bnezs8 .LL72 + move $r3, #0 +.LL72: + srl $r3, $r3, $r2 + sltsi $r15, P1H, #0 + beqzs8 .Li50 + subri $r3, $r3, #0 +.Li50: + move $r0, $r3 + +.LL999: + popm $r6, $r6 + pop $lp + ret5 $lp + +.LLnaninf: + beqz P1L, .Li51 + ori P1H, P1H, #1 +.Li51: + move $r6, #0x7ff00000 + slt $r15, $r6, P1H + beqzs8 .Li52 + move $r0, #0x80000000 + j .LL999 +.Li52: + move $r0, #0x7fffffff + j .LL999 + .size __fixdfsi, .-__fixdfsi +#endif /* L_df_to_si */ + + + +#ifdef L_fixsfdi + +#ifndef __big_endian__ + #define O1L $r1 + #define O1H $r2 +#else + #define O1H $r1 + #define O1L $r2 +#endif + .text + .align 2 + .global __fixsfdi + .type __fixsfdi, @function +__fixsfdi: + push $lp + + srli $r3, $r0, #23 + andi $r3, $r3, #0xff + slli O1H, $r0, #8 + move $r5, #0x80000000 + or O1H, O1H, $r5 + move O1L, #0 + sltsi $r15, $r3, #0xbe + beqzs8 .LCinfnan + subri $r3, $r3, #0xbe +.LL8: + move $r5, #0x20 + slt $r15, $r3, $r5 + bnezs8 .LL9 + move O1L, O1H + move O1H, #0 + addi $r3, $r3, #0xffffffe0 + bnez O1L, .LL8 +.LL9: + beqz $r3, .LL10 + move $r4, O1H + srl O1L, O1L, $r3 + srl O1H, O1H, $r3 + subri $r3, $r3, #0x20 + sll $r4, $r4, $r3 + or O1L, O1L, $r4 +.LL10: + sltsi $r15, $r0, #0 + beqzs8 .LCret + + subri O1H, O1H, #0 + beqz O1L, .LL11 + subri O1L, O1L, #0 + subi45 O1H, #1 +.LL11: + +.LCret: + move $r0, $r1 + move $r1, $r2 + +.LC999: + pop $lp + ret5 $lp + +.LCinfnan: + sltsi $r15, $r0, #0 + bnezs8 .LCret3 + subri $r15, $r3, #0xff + bnezs8 .Li7 + slli $r5, O1H, #1 + beqz $r5, .Li7 + +.LCret3: + move O1H, #0x80000000 + j .LCret +.Li7: + move O1H, #0x7fffffff + move O1L, #-1 + j .LCret + .size __fixsfdi, .-__fixsfdi +#endif /* L_fixsfdi */ + + + +#ifdef L_fixdfdi + +#ifndef __big_endian__ + #define P1L $r0 + #define P1H $r1 + #define O1L $r3 + #define O1H $r4 +#else + #define P1H $r0 + #define P1L $r1 + #define O1H $r3 + #define O1L $r4 +#endif + .text + .align 2 + .global __fixdfdi + .type __fixdfdi, @function +__fixdfdi: + push $lp + pushm $r6, $r6 + + slli $r5, P1H, #1 + srli $r5, $r5, #21 + slli O1H, P1H, #11 + srli $r6, P1L, #21 + or O1H, O1H, $r6 + slli O1L, P1L, #11 + move $r6, #0x80000000 + or O1H, O1H, $r6 + slti $r15, $r5, #0x43e + beqzs8 .LCnaninf + subri $r2, $r5, #0x43e +.LL14: + move $r6, #0x20 + slt $r15, $r2, $r6 + bnezs8 .LL15 + move O1L, O1H + move O1H, #0 + addi $r2, $r2, #0xffffffe0 + bnez O1L, .LL14 +.LL15: + beqz $r2, .LL16 + move P1L, O1H + srl O1L, O1L, $r2 + srl O1H, O1H, $r2 + subri $r2, $r2, #0x20 + sll P1L, P1L, $r2 + or O1L, O1L, P1L +.LL16: + sltsi $r15, P1H, #0 + beqzs8 .LCret + + subri O1H, O1H, #0 + beqz O1L, .LL17 + subri O1L, O1L, #0 + subi45 O1H, #1 +.LL17: + +.LCret: + move P1L, O1L + move P1H, O1H + +.LC999: + popm $r6, $r6 + pop $lp + ret5 $lp + +.LCnaninf: + sltsi $r15, P1H, #0 + bnezs8 .LCret3 + subri $r15, $r5, #0x7ff + bnezs8 .Li5 + slli $r6, O1H, #1 + or $r6, $r6, O1L + beqz $r6, .Li5 + +.LCret3: + move O1H, #0x80000000 + move O1L, #0 + j .LCret +.Li5: + move O1H, #0x7fffffff + move O1L, #-1 + j .LCret + .size __fixdfdi, .-__fixdfdi +#endif /* L_fixdfdi */ + + + +#ifdef L_fixunssfsi + + .global __fixunssfsi + .type __fixunssfsi, @function +__fixunssfsi: + push $lp + + slli $r1, $r0, #8 + move $r3, #0x80000000 + or $r1, $r1, $r3 + srli $r3, $r0, #23 + andi $r3, $r3, #0xff + subri $r2, $r3, #0x9e + sltsi $r15, $r2, #0 + bnezs8 .LLspec + sltsi $r15, $r2, #0x20 + bnezs8 .Li45 + move $r0, #0 + j .LL999 +.Li45: + srl $r1, $r1, $r2 + sltsi $r15, $r0, #0 + beqzs8 .Li46 + subri $r1, $r1, #0 +.Li46: + move $r0, $r1 + +.LL999: + pop $lp + ret5 $lp + +.LLspec: + move $r3, #0x7f800000 + slt $r15, $r3, $r0 + beqzs8 .Li47 + move $r0, #0x80000000 + j .LL999 +.Li47: + move $r0, #-1 + j .LL999 + .size __fixunssfsi, .-__fixunssfsi +#endif /* L_fixunssfsi */ + + + +#ifdef L_fixunsdfsi + +#ifndef __big_endian__ + #define P1L $r0 + #define P1H $r1 +#else + #define P1H $r0 + #define P1L $r1 +#endif + .text + .align 2 + .global __fixunsdfsi + .type __fixunsdfsi, @function +__fixunsdfsi: + push $lp + pushm $r6, $r6 + + slli $r3, P1H, #11 + srli $r6, P1L, #21 + or $r3, $r3, $r6 + move $r6, #0x80000000 + or $r3, $r3, $r6 + slli $r6, P1H, #1 + srli $r6, $r6, #21 + subri $r2, $r6, #0x41e + sltsi $r15, $r2, #0 + bnezs8 .LNnaninf + move $r6, #0x20 + slt $r15, $r2, $r6 + bnezs8 .LL73 + move $r3, #0 +.LL73: + srl $r3, $r3, $r2 + sltsi $r15, P1H, #0 + beqzs8 .Li53 + subri $r3, $r3, #0 +.Li53: + move $r0, $r3 + +.LN999: + popm $r6, $r6 + pop $lp + ret5 $lp + +.LNnaninf: + beqz P1L, .Li54 + ori P1H, P1H, #1 +.Li54: + move $r6, #0x7ff00000 + slt $r15, $r6, P1H + beqzs8 .Li55 + move $r0, #0x80000000 + j .LN999 +.Li55: + move $r0, #-1 + j .LN999 + .size __fixunsdfsi, .-__fixunsdfsi +#endif /* L_fixunsdfsi */ + + + +#ifdef L_fixunssfdi + +#ifndef __big_endian__ + #define O1L $r1 + #define O1H $r2 +#else + #define O1H $r1 + #define O1L $r2 +#endif + .text + .align 2 + .global __fixunssfdi + .type __fixunssfdi, @function +__fixunssfdi: + push $lp + + srli $r3, $r0, #23 + andi $r3, $r3, #0xff + slli O1H, $r0, #8 + move $r5, #0x80000000 + or O1H, O1H, $r5 + move O1L, #0 + sltsi $r15, $r3, #0xbe + beqzs8 .LDinfnan + subri $r3, $r3, #0xbe +.LL12: + move $r5, #0x20 + slt $r15, $r3, $r5 + bnezs8 .LL13 + move O1L, O1H + move O1H, #0 + addi $r3, $r3, #0xffffffe0 + bnez O1L, .LL12 +.LL13: + beqz $r3, .LL14 + move $r4, O1H + srl O1L, O1L, $r3 + srl O1H, O1H, $r3 + subri $r3, $r3, #0x20 + sll $r4, $r4, $r3 + or O1L, O1L, $r4 +.LL14: + sltsi $r15, $r0, #0 + beqzs8 .LDret + + subri O1H, O1H, #0 + beqz O1L, .LL15 + subri O1L, O1L, #0 + subi45 O1H, #1 +.LL15: + +.LDret: + move $r0, $r1 + move $r1, $r2 + +.LD999: + pop $lp + ret5 $lp + +.LDinfnan: + move O1H, #0x80000000 + move O1L, #0 + j .LDret + .size __fixunssfdi, .-__fixunssfdi +#endif /* L_fixunssfdi */ + + + +#ifdef L_fixunsdfdi + +#ifndef __big_endian__ + #define P1L $r0 + #define P1H $r1 + #define O1L $r3 + #define O1H $r4 +#else + #define P1H $r0 + #define P1L $r1 + #define O1H $r3 + #define O1L $r4 +#endif + .text + .align 2 + .global __fixunsdfdi + .type __fixunsdfdi, @function +__fixunsdfdi: + push $lp + pushm $r6, $r6 + + slli $r5, P1H, #1 + srli $r5, $r5, #21 + slli O1H, P1H, #11 + srli $r6, P1L, #21 + or O1H, O1H, $r6 + slli O1L, P1L, #11 + move $r6, #0x80000000 + or O1H, O1H, $r6 + slti $r15, $r5, #0x43e + beqzs8 .LDnaninf + subri $r2, $r5, #0x43e +.LL18: + move $r6, #0x20 + slt $r15, $r2, $r6 + bnezs8 .LL19 + move O1L, O1H + move O1H, #0 + addi $r2, $r2, #0xffffffe0 + bnez O1L, .LL18 +.LL19: + beqz $r2, .LL20 + move P1L, O1H + srl O1L, O1L, $r2 + srl O1H, O1H, $r2 + subri $r2, $r2, #0x20 + sll P1L, P1L, $r2 + or O1L, O1L, P1L +.LL20: + sltsi $r15, P1H, #0 + beqzs8 .LDret + + subri O1H, O1H, #0 + beqz O1L, .LL21 + subri O1L, O1L, #0 + subi45 O1H, #1 +.LL21: + +.LDret: + move P1L, O1L + move P1H, O1H + +.LD999: + popm $r6, $r6 + pop $lp + ret5 $lp + +.LDnaninf: + move O1H, #0x80000000 + move O1L, #0 + j .LDret + .size __fixunsdfdi, .-__fixunsdfdi +#endif /* L_fixunsdfdi */ + + + +#ifdef L_si_to_sf + + .text + .align 2 + .global __floatsisf + .type __floatsisf, @function +__floatsisf: + push $lp + + move $r4, #0x80000000 + and $r2, $r0, $r4 + beqz $r0, .Li39 + sltsi $r15, $r0, #0 + beqzs8 .Li40 + subri $r0, $r0, #0 +.Li40: + move $r1, #0x9e +#ifdef __NDS32_PERF_EXT__ + clz $r3, $r0 +#else + pushm $r0, $r2 + pushm $r4, $r5 + bal __clzsi2 + move $r3, $r0 + popm $r4, $r5 + popm $r0, $r2 +#endif + sub $r1, $r1, $r3 + sll $r0, $r0, $r3 + + #ADD($r0, $0x80) + move $r15, #0x80 + add $r0, $r0, $r15 + slt $r15, $r0, $r15 + + #ADDC($r1, $0x0) + add $r1, $r1, $r15 + srai $r4, $r0, #8 + andi $r4, $r4, #1 + sub $r0, $r0, $r4 + slli $r0, $r0, #1 + srli $r0, $r0, #9 + slli $r4, $r1, #23 + or $r0, $r0, $r4 +.Li39: + or $r0, $r0, $r2 + +.LH999: + pop $lp + ret5 $lp + .size __floatsisf, .-__floatsisf +#endif /* L_si_to_sf */ + + + +#ifdef L_si_to_df + +#ifndef __big_endian__ + #define O1L $r1 + #define O1H $r2 + #define O2L $r4 + #define O2H $r5 +#else + #define O1H $r1 + #define O1L $r2 + #define O2H $r4 + #define O2L $r5 +#endif + .text + .align 2 + .global __floatsidf + .type __floatsidf, @function +__floatsidf: + push $lp + pushm $r6, $r6 + + move O1L, #0 + move O2H, O1L + move $r3, O1L + move O1H, $r0 + beqz O1H, .Li39 + sltsi $r15, O1H, #0 + beqzs8 .Li40 + move O2H, #0x80000000 + + subri O1H, O1H, #0 + beqz O1L, .LL71 + subri O1L, O1L, #0 + subi45 O1H, #1 +.LL71: +.Li40: + move $r3, #0x41e +#ifndef __big_endian__ +#ifdef __NDS32_PERF_EXT__ + clz $r4, $r2 +#else + pushm $r0, $r3 + push $r5 + move $r0, $r2 + bal __clzsi2 + move $r4, $r0 + pop $r5 + popm $r0, $r3 +#endif +#else /* __big_endian__ */ +#ifdef __NDS32_PERF_EXT__ + clz $r5, $r1 +#else + pushm $r0, $r4 + move $r0, $r1 + bal __clzsi2 + move $r5, $r0 + popm $r0, $r4 +#endif +#endif /* __big_endian__ */ + sub $r3, $r3, O2L + sll O1H, O1H, O2L +.Li39: + srli O2L, O1L, #11 + slli $r6, O1H, #21 + or O2L, O2L, $r6 + slli $r6, O1H, #1 + srli $r6, $r6, #12 + or O2H, O2H, $r6 + slli $r6, $r3, #20 + or O2H, O2H, $r6 + move $r0, $r4 + move $r1, $r5 + +.LH999: + popm $r6, $r6 + pop $lp + ret5 $lp + .size __floatsidf, .-__floatsidf +#endif /* L_si_to_df */ + + + +#ifdef L_floatdisf + +#ifndef __big_endian__ + #define P1L $r0 + #define P1H $r1 + #define P2L $r2 + #define P2H $r3 +#else + #define P1H $r0 + #define P1L $r1 + #define P2H $r2 + #define P2L $r3 +#endif + .text + .align 2 + .global __floatdisf + .type __floatdisf, @function +__floatdisf: + push $lp + pushm $r6, $r7 + + move $r7, #0x80000000 + and $r5, P1H, $r7 + move P2H, P1H + move P2L, P1L + or $r7, P1H, P1L + beqz $r7, .Li1 + sltsi $r15, P1H, #0 + beqzs8 .Li2 + + subri P2H, P2H, #0 + beqz P2L, .LL1 + subri P2L, P2L, #0 + subi45 P2H, #1 +.LL1: +.Li2: + move $r4, #0xbe + + + #NORMd($r2, $r6, P1L) + bnez P2H, .LL2 + bnez P2L, .LL3 + move $r4, #0 + j .LL4 +.LL3: + move P2H, P2L + move P2L, #0 + move $r6, #32 + sub $r4, $r4, $r6 +.LL2: +#ifdef __NDS32_PERF_EXT__ + clz $r6, P2H +#else + pushm $r0, $r5 + move $r0, P2H + bal __clzsi2 + move $r6, $r0 + popm $r0, $r5 +#endif + beqz $r6, .LL4 + sub $r4, $r4, $r6 + subri P1L, $r6, #32 + srl P1L, P2L, P1L + sll P2L, P2L, $r6 + sll P2H, P2H, $r6 + or P2H, P2H, P1L +.LL4: + #NORMd End + + beqz P2L, .Li3 + ori P2H, P2H, #1 +.Li3: + #ADD(P2H, $0x80) + move $r15, #0x80 + add P2H, P2H, $r15 + slt $r15, P2H, $r15 + + #ADDC($r4, $0x0) + add $r4, $r4, $r15 + srli $r7, P2H, #8 + andi $r7, $r7, #1 + sub P2H, P2H, $r7 + slli P2H, P2H, #1 + srli P2H, P2H, #9 + slli $r7, $r4, #23 + or P2H, P2H, $r7 +.Li1: + or $r0, P2H, $r5 + +.LA999: + popm $r6, $r7 + pop $lp + ret5 $lp + .size __floatdisf, .-__floatdisf +#endif /* L_floatdisf */ + + + +#ifdef L_floatdidf + +#ifndef __big_endian__ + #define P1L $r0 + #define P1H $r1 + #define P2L $r2 + #define P2H $r3 + #define O1L $r5 + #define O1H $r6 +#else + #define P1H $r0 + #define P1L $r1 + #define P2H $r2 + #define P2L $r3 + #define O1H $r5 + #define O1L $r6 +#endif + .text + .align 2 + .global __floatdidf + .type __floatdidf, @function +__floatdidf: + push $lp + pushm $r6, $r8 + + move $r4, #0 + move $r7, $r4 + move P2H, P1H + move P2L, P1L + or $r8, P1H, P1L + beqz $r8, .Li1 + move $r4, #0x43e + sltsi $r15, P1H, #0 + beqzs8 .Li2 + move $r7, #0x80000000 + + subri P2H, P2H, #0 + beqz P2L, .LL1 + subri P2L, P2L, #0 + subi45 P2H, #1 +.LL1: + +.Li2: + #NORMd($r2, O1H, O1L) + bnez P2H, .LL2 + bnez P2L, .LL3 + move $r4, #0 + j .LL4 +.LL3: + move P2H, P2L + move P2L, #0 + move O1H, #32 + sub $r4, $r4, O1H +.LL2: +#ifdef __NDS32_PERF_EXT__ + clz O1H, P2H +#else /* not __NDS32_PERF_EXT__ */ +/* + Replace clz with function call. + clz O1H, P2H + EL: clz $r6, $r3 + EB: clz $r5, $r2 +*/ +#ifndef __big_endian__ + pushm $r0, $r5 + move $r0, $r3 + bal __clzsi2 + move $r6, $r0 + popm $r0, $r5 +#else + pushm $r0, $r4 + move $r0, $r2 + bal __clzsi2 + move $r5, $r0 + popm $r0, $r4 +#endif +#endif /* not __NDS32_PERF_EXT__ */ + beqz O1H, .LL4 + sub $r4, $r4, O1H + subri O1L, O1H, #32 + srl O1L, P2L, O1L + sll P2L, P2L, O1H + sll P2H, P2H, O1H + or P2H, P2H, O1L +.LL4: + #NORMd End + + #ADD(P2L, $0x400) + move $r15, #0x400 + add P2L, P2L, $r15 + slt $r15, P2L, $r15 + + + #ADDCC(P2H, $0x0) + beqzs8 .LL7 + add P2H, P2H, $r15 + slt $r15, P2H, $r15 +.LL7: + + #ADDC($r4, $0x0) + add $r4, $r4, $r15 + srli $r8, P2L, #11 + andi $r8, $r8, #1 + sub P2L, P2L, $r8 +.Li1: + srli O1L, P2L, #11 + slli $r8, P2H, #21 + or O1L, O1L, $r8 + slli O1H, P2H, #1 + srli O1H, O1H, #12 + slli $r8, $r4, #20 + or O1H, O1H, $r8 + or O1H, O1H, $r7 + move P1L, O1L + move P1H, O1H + +.LA999: + popm $r6, $r8 + pop $lp + ret5 $lp + .size __floatdidf, .-__floatdidf +#endif /* L_floatdidf */ + + + +#ifdef L_floatunsisf + + .text + .align 2 + .global __floatunsisf + .type __floatunsisf, @function +__floatunsisf: + push $lp + + beqz $r0, .Li41 + move $r2, #0x9e +#ifdef __NDS32_PERF_EXT__ + clz $r1, $r0 +#else + push $r0 + pushm $r2, $r5 + bal __clzsi2 + move $r1, $r0 + popm $r2, $r5 + pop $r0 +#endif + + sub $r2, $r2, $r1 + sll $r0, $r0, $r1 + + #ADD($r0, $0x80) + move $r15, #0x80 + add $r0, $r0, $r15 + slt $r15, $r0, $r15 + + #ADDC($r2, $0x0) + add $r2, $r2, $r15 + srli $r3, $r0, #8 + andi $r3, $r3, #1 + sub $r0, $r0, $r3 + slli $r0, $r0, #1 + srli $r0, $r0, #9 + slli $r3, $r2, #23 + or $r0, $r0, $r3 + +.Li41: +.LI999: + pop $lp + ret5 $lp + .size __floatunsisf, .-__floatunsisf +#endif /* L_floatunsisf */ + + + +#ifdef L_floatunsidf + +#ifndef __big_endian__ + #define O1L $r1 + #define O1H $r2 + #define O2L $r4 + #define O2H $r5 +#else + #define O1H $r1 + #define O1L $r2 + #define O2H $r4 + #define O2L $r5 +#endif + .text + .align 2 + .global __floatunsidf + .type __floatunsidf, @function +__floatunsidf: + push $lp + pushm $r6, $r6 + + move O1L, #0 + move $r3, O1L + move O1H, $r0 + beqz O1H, .Li41 + move $r3, #0x41e +#ifndef __big_endian__ +#ifdef __NDS32_PERF_EXT__ + clz $r5, $r2 +#else + pushm $r0, $r4 + move $r0, $r2 + bal __clzsi2 + move $r5, $r0 + popm $r0, $r4 +#endif +#else /* __big_endian__ */ +#ifdef __NDS32_PERF_EXT__ + clz $r4, $r1 +#else + pushm $r0, $r3 + push $r5 + move $r0, $r1 + bal __clzsi2 + move $r4, $r0 + pop $r5 + popm $r0, $r3 +#endif +#endif /* __big_endian__ */ + sub $r3, $r3, O2H + sll O1H, O1H, O2H +.Li41: + srli O2L, O1L, #11 + slli $r6, O1H, #21 + or O2L, O2L, $r6 + slli O2H, O1H, #1 + srli O2H, O2H, #12 + slli $r6, $r3, #20 + or O2H, O2H, $r6 + move $r0, $r4 + move $r1, $r5 + +.LI999: + popm $r6, $r6 + pop $lp + ret5 $lp + .size __floatunsidf, .-__floatunsidf +#endif /* L_floatunsidf */ + + + +#ifdef L_floatundisf + +#ifndef __big_endian__ + #define P1L $r0 + #define P1H $r1 + #define P2L $r2 + #define P2H $r3 +#else + #define P1H $r0 + #define P1L $r1 + #define P2H $r2 + #define P2L $r3 +#endif + .text + .align 2 + .global __floatundisf + .type __floatundisf, @function +__floatundisf: + push $lp + pushm $r6, $r6 + + move P2H, P1H + move P2L, P1L + or $r6, P1H, P1L + beqz $r6, .Li4 + move $r4, #0xbe + + + #NORMd($r2, $r5, P1L) + bnez P2H, .LL5 + bnez P2L, .LL6 + move $r4, #0 + j .LL7 +.LL6: + move P2H, P2L + move P2L, #0 + move $r5, #32 + sub $r4, $r4, $r5 +.LL5: +#ifdef __NDS32_PERF_EXT__ + clz $r5, P2H +#else + pushm $r0, $r4 + move $r0, P2H + bal __clzsi2 + move $r5, $r0 + popm $r0, $r4 +#endif + beqz $r5, .LL7 + sub $r4, $r4, $r5 + subri P1L, $r5, #32 + srl P1L, P2L, P1L + sll P2L, P2L, $r5 + sll P2H, P2H, $r5 + or P2H, P2H, P1L +.LL7: + #NORMd End + + beqz P2L, .Li5 + ori P2H, P2H, #1 +.Li5: + #ADD(P2H, $0x80) + move $r15, #0x80 + add P2H, P2H, $r15 + slt $r15, P2H, $r15 + + #ADDC($r4, $0x0) + add $r4, $r4, $r15 + srli $r6, P2H, #8 + andi $r6, $r6, #1 + sub P2H, P2H, $r6 + slli P2H, P2H, #1 + srli P2H, P2H, #9 + slli $r6, $r4, #23 + or P2H, P2H, $r6 +.Li4: + move $r0, P2H + +.LB999: + popm $r6, $r6 + pop $lp + ret5 $lp + .size __floatundisf, .-__floatundisf +#endif /* L_floatundisf */ + + + +#ifdef L_floatundidf + +#ifndef __big_endian__ + #define P1L $r0 + #define P1H $r1 + #define P2L $r2 + #define P2H $r3 + #define O1L $r5 + #define O1H $r6 +#else + #define P1H $r0 + #define P1L $r1 + #define P2H $r2 + #define P2L $r3 + #define O1H $r5 + #define O1L $r6 +#endif + .text + .align 2 + .global __floatundidf + .type __floatundidf, @function +__floatundidf: + push $lp + pushm $r6, $r7 + + move $r4, #0 + move P2H, P1H + move P2L, P1L + or $r7, P1H, P1L + beqz $r7, .Li3 + move $r4, #0x43e + + + #NORMd($r2, O1H, O1L) + bnez P2H, .LL8 + bnez P2L, .LL9 + move $r4, #0 + j .LL10 +.LL9: + move P2H, P2L + move P2L, #0 + move O1H, #32 + sub $r4, $r4, O1H +.LL8: +#ifdef __NDS32_PERF_EXT__ + clz O1H, P2H +#else /* not __NDS32_PERF_EXT__ */ +/* + Replace clz with function call. + clz O1H, P2H + EL: clz $r6, $r3 + EB: clz $r5, $r2 +*/ +#ifndef __big_endian__ + pushm $r0, $r5 + move $r0, $r3 + bal __clzsi2 + move $r6, $r0 + popm $r0, $r5 +#else + pushm $r0, $r4 + move $r0, $r2 + bal __clzsi2 + move $r5, $r0 + popm $r0, $r4 +#endif +#endif /* not __NDS32_PERF_EXT__ */ + beqz O1H, .LL10 + sub $r4, $r4, O1H + subri O1L, O1H, #32 + srl O1L, P2L, O1L + sll P2L, P2L, O1H + sll P2H, P2H, O1H + or P2H, P2H, O1L +.LL10: + #NORMd End + + #ADD(P2L, $0x400) + move $r15, #0x400 + add P2L, P2L, $r15 + slt $r15, P2L, $r15 + + + #ADDCC(P2H, $0x0) + beqzs8 .LL13 + add P2H, P2H, $r15 + slt $r15, P2H, $r15 +.LL13: + + #ADDC($r4, $0x0) + add $r4, $r4, $r15 + srli $r7, P2L, #11 + andi $r7, $r7, #1 + sub P2L, P2L, $r7 +.Li3: + srli O1L, P2L, #11 + slli $r7, P2H, #21 + or O1L, O1L, $r7 + slli O1H, P2H, #1 + srli O1H, O1H, #12 + slli $r7, $r4, #20 + or O1H, O1H, $r7 + move P1L, O1L + move P1H, O1H + +.LB999: + popm $r6, $r7 + pop $lp + ret5 $lp + .size __floatundidf, .-__floatundidf +#endif /* L_floatundidf */ + + + +#ifdef L_compare_sf + + .text + .align 2 + .global __cmpsf2 + .type __cmpsf2, @function +__cmpsf2: + .global __eqsf2 + .type __eqsf2, @function +__eqsf2: + .global __ltsf2 + .type __ltsf2, @function +__ltsf2: + .global __lesf2 + .type __lesf2, @function +__lesf2: + .global __nesf2 + .type __nesf2, @function +__nesf2: + move $r4, #1 + j .LA + + .global __gesf2 + .type __gesf2, @function +__gesf2: + .global __gtsf2 + .type __gtsf2, @function +__gtsf2: + move $r4, #-1 +.LA: + push $lp + + slli $r2, $r0, #1 + slli $r3, $r1, #1 + or $r5, $r2, $r3 + beqz $r5, .LMequ + move $r5, #0xff000000 + slt $r15, $r5, $r2 + bnezs8 .LMnan + slt $r15, $r5, $r3 + bnezs8 .LMnan + srli $r2, $r2, #1 + sltsi $r15, $r0, #0 + beqzs8 .Li48 + subri $r2, $r2, #0 +.Li48: + srli $r3, $r3, #1 + sltsi $r15, $r1, #0 + beqzs8 .Li49 + subri $r3, $r3, #0 +.Li49: + slts $r15, $r2, $r3 + beqzs8 .Li50 + move $r0, #-1 + j .LM999 +.Li50: + slts $r15, $r3, $r2 + beqzs8 .LMequ + move $r0, #1 + j .LM999 + +.LMequ: + move $r0, #0 + +.LM999: + pop $lp + ret5 $lp + +.LMnan: + move $r0, $r4 + j .LM999 + .size __cmpsf2, .-__cmpsf2 + .size __eqsf2, .-__eqsf2 + .size __ltsf2, .-__ltsf2 + .size __lesf2, .-__lesf2 + .size __nesf2, .-__nesf2 + .size __gesf2, .-__gesf2 + .size __gtsf2, .-__gtsf2 +#endif /* L_compare_sf */ + + + +#ifdef L_compare_df + +#ifdef __big_endian__ + #define P1H $r0 + #define P1L $r1 + #define P2H $r2 + #define P2L $r3 +#else + #define P1H $r1 + #define P1L $r0 + #define P2H $r3 + #define P2L $r2 +#endif + .align 2 + .globl __gtdf2 + .globl __gedf2 + .globl __ltdf2 + .globl __ledf2 + .globl __eqdf2 + .globl __nedf2 + .globl __cmpdf2 + .type __gtdf2, @function + .type __gedf2, @function + .type __ltdf2, @function + .type __ledf2, @function + .type __eqdf2, @function + .type __nedf2, @function + .type __cmpdf2, @function +__gtdf2: +__gedf2: + movi $r4, -1 + b .L1 + +__ltdf2: +__ledf2: +__cmpdf2: +__nedf2: +__eqdf2: + movi $r4, 1 +.L1: +#if defined (__NDS32_ISA_V3M__) + push25 $r10, 0 +#else + smw.adm $r6, [$sp], $r9, 0 +#endif + + sethi $r5, 0x7ff00 + and $r6, P1H, $r5 ! r6=aExp + and $r7, P2H, $r5 ! r7=bExp + slli $r8, P1H, 12 ! r8=aSig0 + slli $r9, P2H, 12 ! r9=bSig0 + beq $r6, $r5, .L11 ! aExp==0x7ff + beq $r7, $r5, .L12 ! bExp==0x7ff +.L2: + slli $ta, P1H, 1 ! ta=ahigh<<1 + or $ta, P1L, $ta ! + xor $r5, P1H, P2H ! r5=ahigh^bhigh + beqz $ta, .L3 ! if(ahigh<<1)==0,go .L3 + !------------------------------- + ! (ahigh<<1)!=0 || (bhigh<<1)!=0 + !------------------------------- +.L4: + beqz $r5, .L5 ! ahigh==bhigh, go .L5 + !-------------------- + ! a != b + !-------------------- +.L6: + bltz $r5, .L7 ! if(aSign!=bSign), go .L7 + !-------------------- + ! aSign==bSign + !-------------------- + slt $ta, $r6, $r7 ! ta=(aExp<bExp) + bne $r6, $r7, .L8 ! if(aExp!=bExp),go .L8 + slt $ta, $r8, $r9 ! ta=(aSig0<bSig0) + bne $r8, $r9, .L8 ! if(aSig0!=bSig0),go .L8 + slt $ta, P1L, P2L ! ta=(aSig1<bSig1) +.L8: + beqz $ta, .L10 ! if(|a|>|b|), go .L10 + nor $r0, P2H, P2H ! if(|a|<|b|),return (~yh) +.L14: +#if defined (__NDS32_ISA_V3M__) + pop25 $r10, 0 +#else + lmw.bim $r6, [$sp], $r9, 0 + ret +#endif +.L10: + ori $r0, P2H, 1 ! return (yh|1) + b .L14 + !-------------------- + ! (ahigh<<1)=0 + !-------------------- +.L3: + slli $ta, P2H, 1 ! ta=bhigh<<1 + or $ta, P2L, $ta ! + bnez $ta, .L4 ! ta=(bhigh<<1)!=0,go .L4 +.L5: + xor $ta, P1L, P2L ! ta=alow^blow + bnez $ta, .L6 ! alow!=blow,go .L6 + movi $r0, 0 ! a==b, return 0 + b .L14 + !-------------------- + ! aExp=0x7ff; + !-------------------- +.L11: + or P1L, P1L, $r8 ! x1=(aSig0|aSig1) + bnez P1L, .L13 ! if(a=nan), go.L13 + xor $ta, $r7, $r5 ! ta=(bExp^0x7ff) + bnez $ta, .L2 ! if(bExp!=0x7ff), go .L2 + !-------------------- + ! bExp=0x7ff; + !-------------------- +.L12: + or $ta, P2L, $r9 ! ta=(bSig0|bSig1) + beqz $ta, .L2 ! if(b!=nan), go .L2 +.L13: + move $r0, $r4 + b .L14 + !-------------------- + ! aSign!=bSign + !-------------------- +.L7: + ori $r0, P1H, 1 ! if(aSign!=bSign), return (ahigh|1) + b .L14 + + .size __gtdf2, .-__gtdf2 + .size __gedf2, .-__gedf2 + .size __ltdf2, .-__ltdf2 + .size __ledf2, .-__ledf2 + .size __eqdf2, .-__eqdf2 + .size __nedf2, .-__nedf2 + .size __cmpdf2, .-__cmpdf2 +#endif /* L_compare_df */ + + + +#ifdef L_unord_sf + + .text + .align 2 + .global __unordsf2 + .type __unordsf2, @function +__unordsf2: + push $lp + + slli $r2, $r0, #1 + move $r3, #0xff000000 + slt $r15, $r3, $r2 + beqzs8 .Li52 + move $r0, #1 + j .LP999 +.Li52: + slli $r2, $r1, #1 + move $r3, #0xff000000 + slt $r15, $r3, $r2 + beqzs8 .Li53 + move $r0, #1 + j .LP999 +.Li53: + move $r0, #0 + +.LP999: + pop $lp + ret5 $lp + .size __unordsf2, .-__unordsf2 +#endif /* L_unord_sf */ + + + +#ifdef L_unord_df + +#ifndef __big_endian__ + #define P1L $r0 + #define P1H $r1 + #define P2L $r2 + #define P2H $r3 +#else + #define P1H $r0 + #define P1L $r1 + #define P2H $r2 + #define P2L $r3 +#endif + .text + .align 2 + .global __unorddf2 + .type __unorddf2, @function +__unorddf2: + push $lp + + slli $r4, P1H, #1 + beqz P1L, .Li66 + addi $r4, $r4, #1 +.Li66: + move $r5, #0xffe00000 + slt $r15, $r5, $r4 + beqzs8 .Li67 + move $r0, #1 + j .LR999 +.Li67: + slli $r4, P2H, #1 + beqz P2L, .Li68 + addi $r4, $r4, #1 +.Li68: + move $r5, #0xffe00000 + slt $r15, $r5, $r4 + beqzs8 .Li69 + move $r0, #1 + j .LR999 +.Li69: + move $r0, #0 + +.LR999: + pop $lp + ret5 $lp + .size __unorddf2, .-__unorddf2 +#endif /* L_unord_df */ +/* ------------------------------------------- */ +/* DPBIT floating point operations for libgcc */ +/* ------------------------------------------- */ diff --git a/libgcc/config/nds32/lib1asmsrc-newlib.S b/libgcc/config/nds32/lib1asmsrc-newlib.S new file mode 100644 index 00000000000..6eb3fb0a753 --- /dev/null +++ b/libgcc/config/nds32/lib1asmsrc-newlib.S @@ -0,0 +1,204 @@ +/* newlib libgcc routines of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + + .section .mdebug.abi_nds32 + .previous + +#ifdef L_divsi3 + + .text + .align 2 + .globl __divsi3 + .type __divsi3, @function +__divsi3: + movi $r5, 0 ! res = 0 + xor $r4, $r0, $r1 ! neg + bltz $r0, .L1 + bltz $r1, .L2 +.L3: + movi $r2, 1 ! bit = 1 + slt $r3, $r1, $r0 ! test if dividend is smaller than or equal to divisor + beqz $r3, .L5 + bltz $r1, .L5 + +.L4: + slli $r2, $r2, 1 + beqz $r2, .L6 + slli $r1, $r1, 1 + slt $r3, $r1, $r0 + beqz $r3, .L5 + bgez $r1, .L4 + +.L5: + slt $r3, $r0, $r1 + bnez $r3, .L8 + sub $r0, $r0, $r1 + or $r5, $r5, $r2 +.L8: + srli $r1, $r1, 1 + srli $r2, $r2, 1 + bnez $r2, .L5 +.L6: + bgez $r4, .L7 + subri $r5, $r5, 0 ! negate if $r4 < 0 +.L7: + move $r0, $r5 + ret +.L1: + subri $r0, $r0, 0 ! change neg to pos + bgez $r1, .L3 +.L2: + subri $r1, $r1, 0 ! change neg to pos + j .L3 + .size __divsi3, .-__divsi3 + +#endif /* L_divsi3 */ + + +#ifdef L_modsi3 + + .text + .align 2 + .globl __modsi3 + .type __modsi3, @function +__modsi3: + movi $r5, 0 ! res = 0 + move $r4, $r0 ! neg + bltz $r0, .L1 + bltz $r1, .L2 +.L3: + movi $r2, 1 ! bit = 1 + slt $r3, $r1, $r0 ! test if dividend is smaller than or equal to divisor + beqz $r3, .L5 + bltz $r1, .L5 + +.L4: + slli $r2, $r2, 1 + beqz $r2, .L6 + slli $r1, $r1, 1 + slt $r3, $r1, $r0 + beqz $r3, .L5 + bgez $r1, .L4 + +.L5: + slt $r3, $r0, $r1 + bnez $r3, .L8 + sub $r0, $r0, $r1 + or $r5, $r5, $r2 +.L8: + srli $r1, $r1, 1 + srli $r2, $r2, 1 + bnez $r2, .L5 +.L6: + bgez $r4, .L7 + subri $r0, $r0, 0 ! negate if $r4 < 0 +.L7: + ret +.L1: + subri $r0, $r0, 0 ! change neg to pos + bgez $r1, .L3 +.L2: + subri $r1, $r1, 0 ! change neg to pos + j .L3 + .size __modsi3, .-__modsi3 + +#endif /* L_modsi3 */ + + +#ifdef L_udivsi3 + + .text + .align 2 + .globl __udivsi3 + .type __udivsi3, @function +__udivsi3: + movi $r5, 0 ! res = 0 + movi $r2, 1 ! bit = 1 + slt $r3, $r1, $r0 ! test if dividend is smaller than or equal to divisor + beqz $r3, .L5 + bltz $r1, .L5 + +.L4: + slli $r2, $r2, 1 + beqz $r2, .L6 + slli $r1, $r1, 1 + slt $r3, $r1, $r0 + beqz $r3, .L5 + bgez $r1, .L4 + +.L5: + slt $r3, $r0, $r1 + bnez $r3, .L8 + sub $r0, $r0, $r1 + or $r5, $r5, $r2 +.L8: + srli $r1, $r1, 1 + srli $r2, $r2, 1 + bnez $r2, .L5 +.L6: + move $r0, $r5 + ret + .size __udivsi3, .-__udivsi3 + +#endif /* L_udivsi3 */ + + +#ifdef L_umodsi3 + + .text + .align 2 + .globl __umodsi3 + .type __umodsi3, @function +__umodsi3: + movi $r5, 0 ! res = 0 + movi $r2, 1 ! bit = 1 + slt $r3, $r1, $r0 ! test if dividend is smaller than or equal to divisor + beqz $r3, .L5 + bltz $r1, .L5 + +.L4: + slli $r2, $r2, 1 + beqz $r2, .L6 + slli $r1, $r1, 1 + slt $r3, $r1, $r0 + beqz $r3, .L5 + bgez $r1, .L4 + +.L5: + slt $r3, $r0, $r1 + bnez $r3, .L8 + sub $r0, $r0, $r1 + or $r5, $r5, $r2 +.L8: + srli $r1, $r1, 1 + srli $r2, $r2, 1 + bnez $r2, .L5 +.L6: + ret + .size __umodsi3, .-__umodsi3 + +#endif /* L_umodsi3 */ + +/* ----------------------------------------------------------- */ diff --git a/libgcc/config/nds32/lib2csrc-mculib/_clzdi2.c b/libgcc/config/nds32/lib2csrc-mculib/_clzdi2.c new file mode 100644 index 00000000000..7d39ea85b7a --- /dev/null +++ b/libgcc/config/nds32/lib2csrc-mculib/_clzdi2.c @@ -0,0 +1,38 @@ +/* mculib libgcc routines of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +extern int __clzsi2 (int val); +int +__clzdi2 (long long val) +{ + if (val >> 32) + { + return __clzsi2 (val >> 32); + } + else + { + return __clzsi2 (val) + 32; + } +} diff --git a/libgcc/config/nds32/lib2csrc-mculib/_clzsi2.c b/libgcc/config/nds32/lib2csrc-mculib/_clzsi2.c new file mode 100644 index 00000000000..9d0bdd96d80 --- /dev/null +++ b/libgcc/config/nds32/lib2csrc-mculib/_clzsi2.c @@ -0,0 +1,49 @@ +/* mculib libgcc routines of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + <http://www.gnu.org/licenses/>. */ + +int +__clzsi2 (int val) +{ + int i = 32; + int j = 16; + int temp; + + for (; j; j >>= 1) + { + if (temp = val >> j) + { + if (j == 1) + { + return (i - 2); + } + else + { + i -= j; + val = temp; + } + } + } + return (i - val); +} diff --git a/libgcc/config/nds32/sfp-machine.h b/libgcc/config/nds32/sfp-machine.h new file mode 100644 index 00000000000..62a1532de60 --- /dev/null +++ b/libgcc/config/nds32/sfp-machine.h @@ -0,0 +1,91 @@ +/* Machine settings for software floating-point emulation + of Andes NDS32 cpu for GNU compiler + Copyright (C) 2012-2013 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + In addition to the permissions in the GNU Lesser General Public + License, the Free Software Foundation gives you unlimited + permission to link the compiled version of this file into + combinations with other programs, and to distribute those + combinations without any restriction coming from the use of this + file. (The Lesser General Public License restrictions do apply in + other respects; for example, they cover modification of the file, + and distribution when not linked into a combine executable.) + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#define _FP_W_TYPE_SIZE 32 +#define _FP_W_TYPE unsigned long +#define _FP_WS_TYPE signed long +#define _FP_I_TYPE long + +/* The type of the result of a floating point comparison. This must + match `__libgcc_cmp_return__' in GCC for the target. */ +typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); +#define CMPtype __gcc_CMPtype + +#define _FP_MUL_MEAT_S(R,X,Y) \ + _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_D(R,X,Y) \ + _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) +#define _FP_MUL_MEAT_Q(R,X,Y) \ + _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) + +#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_loop(S,R,X,Y) +#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) +#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y) + +#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) +#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1 +#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1 +#define _FP_NANSIGN_S 0 +#define _FP_NANSIGN_D 0 +#define _FP_NANSIGN_Q 0 + +#define _FP_KEEPNANFRACP 1 +#define _FP_QNANNEGATEDP 0 + +/* Someone please check this. */ +#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ + do { \ + if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \ + && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \ + { \ + R##_s = Y##_s; \ + _FP_FRAC_COPY_##wc(R,Y); \ + } \ + else \ + { \ + R##_s = X##_s; \ + _FP_FRAC_COPY_##wc(R,X); \ + } \ + R##_c = FP_CLS_NAN; \ + } while (0) + +#define __LITTLE_ENDIAN 1234 +#define __BIG_ENDIAN 4321 + +#if defined __big_endian__ +# define __BYTE_ORDER __BIG_ENDIAN +#else +# define __BYTE_ORDER __LITTLE_ENDIAN +#endif + +/* Define ALIASNAME as a strong alias for NAME. */ +# define strong_alias(name, aliasname) _strong_alias(name, aliasname) +# define _strong_alias(name, aliasname) \ + extern __typeof (name) aliasname __attribute__ ((alias (#name))); diff --git a/libgcc/config/nds32/t-nds32 b/libgcc/config/nds32/t-nds32 new file mode 100644 index 00000000000..25c184aa2a9 --- /dev/null +++ b/libgcc/config/nds32/t-nds32 @@ -0,0 +1,58 @@ +# Rules of libgcc and crtstuff of Andes NDS32 cpu for GNU compiler +# Copyright (C) 2012-2013 Free Software Foundation, Inc. +# Contributed by Andes Technology Corporation. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published +# by the Free Software Foundation; either version 3, or (at your +# option) any later version. +# +# GCC is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +# License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + + +# Note: +# Because GCC has its own make rules for crtbegin.o and crtend.o, +# we cannot use crtbegin.o and crtend.o rules. +# So we create crtbegin1.o and crtend1.o instead. +# Make sure the linker script include these two objects +# for building .ctors/.dtors sections. + +# Use -DCRT_BEGIN to create beginning parts of .init and .fini content +# Make sure you are building crtbegin1.o with -O0 optimization, +# otherwise the static function will be optimized out +crtbegin1.o: $(srcdir)/config/nds32/initfini.c $(GCC_PASSES) $(CONFIG_H) + $(GCC_FOR_TARGET) $(INCLUDES) \ + $(CFLAGS) \ + -DCRT_BEGIN \ + -finhibit-size-directive -fno-inline-functions \ + -O0 -c $(srcdir)/config/nds32/initfini.c -o crtbegin1.o + +# Use -DCRT_END to create ending parts of .init and .fini content +# Make sure you are building crtend1.o with -O0 optimization, +# otherwise the static function will be optimized out +crtend1.o: $(srcdir)/config/nds32/initfini.c $(GCC_PASSES) $(CONFIG_H) + $(GCC_FOR_TARGET) $(INCLUDES) \ + $(CFLAGS) \ + -DCRT_END \ + -finhibit-size-directive -fno-inline-functions \ + -O0 -c $(srcdir)/config/nds32/initfini.c -o crtend1.o + +# Use this rule if and only if your crt0.o does not come from library +# Also, be sure to add 'crtzero.o' in extra_parts in libgcc/config.host +# and change STARTFILE_SPEC in nds32.h +# +#crtzero.o: $(srcdir)/config/nds32/crtzero.S $(GCC_PASSES) $(CONFIG_H) +# $(GCC_FOR_TARGET) $(INCLUDES) \ +# -c $(srcdir)/config/nds32/crtzero.S -o crtzero.o + + +# ------------------------------------------------------------------------ diff --git a/libgcc/config/nds32/t-nds32-isr b/libgcc/config/nds32/t-nds32-isr new file mode 100644 index 00000000000..24f798c3a56 --- /dev/null +++ b/libgcc/config/nds32/t-nds32-isr @@ -0,0 +1,212 @@ +# Rules of c-isr library stuff of Andes NDS32 cpu for GNU compiler +# Copyright (C) 2012-2013 Free Software Foundation, Inc. +# Contributed by Andes Technology Corporation. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published +# by the Free Software Foundation; either version 3, or (at your +# option) any later version. +# +# GCC is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +# License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + + +############################################################################### +# Makfile fragment rules for libnds32_isr.a to support ISR attribute extension +############################################################################### + +# basic flags setting +ISR_CFLAGS = $(CFLAGS) -c + +# the object files we would like to create +LIBNDS32_ISR_16B_OBJS = \ + vec_vid00.o vec_vid01.o vec_vid02.o vec_vid03.o \ + vec_vid04.o vec_vid05.o vec_vid06.o vec_vid07.o \ + vec_vid08.o vec_vid09.o vec_vid10.o vec_vid11.o \ + vec_vid12.o vec_vid13.o vec_vid14.o vec_vid15.o \ + vec_vid16.o vec_vid17.o vec_vid18.o vec_vid19.o \ + vec_vid20.o vec_vid21.o vec_vid22.o vec_vid23.o \ + vec_vid24.o vec_vid25.o vec_vid26.o vec_vid27.o \ + vec_vid28.o vec_vid29.o vec_vid30.o vec_vid31.o \ + vec_vid32.o vec_vid33.o vec_vid34.o vec_vid35.o \ + vec_vid36.o vec_vid37.o vec_vid38.o vec_vid39.o \ + vec_vid40.o vec_vid41.o vec_vid42.o vec_vid43.o \ + vec_vid44.o vec_vid45.o vec_vid46.o vec_vid47.o \ + vec_vid48.o vec_vid49.o vec_vid50.o vec_vid51.o \ + vec_vid52.o vec_vid53.o vec_vid54.o vec_vid55.o \ + vec_vid56.o vec_vid57.o vec_vid58.o vec_vid59.o \ + vec_vid60.o vec_vid61.o vec_vid62.o vec_vid63.o \ + vec_vid64.o vec_vid65.o vec_vid66.o vec_vid67.o \ + vec_vid68.o vec_vid69.o vec_vid70.o vec_vid71.o \ + vec_vid72.o \ + excp_isr_ps_nn.o excp_isr_ps_ns.o excp_isr_ps_nr.o \ + excp_isr_sa_nn.o excp_isr_sa_ns.o excp_isr_sa_nr.o \ + intr_isr_ps_nn.o intr_isr_ps_ns.o intr_isr_ps_nr.o \ + intr_isr_sa_nn.o intr_isr_sa_ns.o intr_isr_sa_nr.o \ + reset.o + +LIBNDS32_ISR_4B_OBJS = \ + vec_vid00_4b.o vec_vid01_4b.o vec_vid02_4b.o vec_vid03_4b.o \ + vec_vid04_4b.o vec_vid05_4b.o vec_vid06_4b.o vec_vid07_4b.o \ + vec_vid08_4b.o vec_vid09_4b.o vec_vid10_4b.o vec_vid11_4b.o \ + vec_vid12_4b.o vec_vid13_4b.o vec_vid14_4b.o vec_vid15_4b.o \ + vec_vid16_4b.o vec_vid17_4b.o vec_vid18_4b.o vec_vid19_4b.o \ + vec_vid20_4b.o vec_vid21_4b.o vec_vid22_4b.o vec_vid23_4b.o \ + vec_vid24_4b.o vec_vid25_4b.o vec_vid26_4b.o vec_vid27_4b.o \ + vec_vid28_4b.o vec_vid29_4b.o vec_vid30_4b.o vec_vid31_4b.o \ + vec_vid32_4b.o vec_vid33_4b.o vec_vid34_4b.o vec_vid35_4b.o \ + vec_vid36_4b.o vec_vid37_4b.o vec_vid38_4b.o vec_vid39_4b.o \ + vec_vid40_4b.o vec_vid41_4b.o vec_vid42_4b.o vec_vid43_4b.o \ + vec_vid44_4b.o vec_vid45_4b.o vec_vid46_4b.o vec_vid47_4b.o \ + vec_vid48_4b.o vec_vid49_4b.o vec_vid50_4b.o vec_vid51_4b.o \ + vec_vid52_4b.o vec_vid53_4b.o vec_vid54_4b.o vec_vid55_4b.o \ + vec_vid56_4b.o vec_vid57_4b.o vec_vid58_4b.o vec_vid59_4b.o \ + vec_vid60_4b.o vec_vid61_4b.o vec_vid62_4b.o vec_vid63_4b.o \ + vec_vid64_4b.o vec_vid65_4b.o vec_vid66_4b.o vec_vid67_4b.o \ + vec_vid68_4b.o vec_vid69_4b.o vec_vid70_4b.o vec_vid71_4b.o \ + vec_vid72_4b.o \ + excp_isr_ps_nn_4b.o excp_isr_ps_ns_4b.o excp_isr_ps_nr_4b.o \ + excp_isr_sa_nn_4b.o excp_isr_sa_ns_4b.o excp_isr_sa_nr_4b.o \ + intr_isr_ps_nn_4b.o intr_isr_ps_ns_4b.o intr_isr_ps_nr_4b.o \ + intr_isr_sa_nn_4b.o intr_isr_sa_ns_4b.o intr_isr_sa_nr_4b.o \ + reset_4b.o + +LIBNDS32_ISR_COMMON_OBJS = \ + jmptbl_vid00.o jmptbl_vid01.o jmptbl_vid02.o jmptbl_vid03.o \ + jmptbl_vid04.o jmptbl_vid05.o jmptbl_vid06.o jmptbl_vid07.o \ + jmptbl_vid08.o jmptbl_vid09.o jmptbl_vid10.o jmptbl_vid11.o \ + jmptbl_vid12.o jmptbl_vid13.o jmptbl_vid14.o jmptbl_vid15.o \ + jmptbl_vid16.o jmptbl_vid17.o jmptbl_vid18.o jmptbl_vid19.o \ + jmptbl_vid20.o jmptbl_vid21.o jmptbl_vid22.o jmptbl_vid23.o \ + jmptbl_vid24.o jmptbl_vid25.o jmptbl_vid26.o jmptbl_vid27.o \ + jmptbl_vid28.o jmptbl_vid29.o jmptbl_vid30.o jmptbl_vid31.o \ + jmptbl_vid32.o jmptbl_vid33.o jmptbl_vid34.o jmptbl_vid35.o \ + jmptbl_vid36.o jmptbl_vid37.o jmptbl_vid38.o jmptbl_vid39.o \ + jmptbl_vid40.o jmptbl_vid41.o jmptbl_vid42.o jmptbl_vid43.o \ + jmptbl_vid44.o jmptbl_vid45.o jmptbl_vid46.o jmptbl_vid47.o \ + jmptbl_vid48.o jmptbl_vid49.o jmptbl_vid50.o jmptbl_vid51.o \ + jmptbl_vid52.o jmptbl_vid53.o jmptbl_vid54.o jmptbl_vid55.o \ + jmptbl_vid56.o jmptbl_vid57.o jmptbl_vid58.o jmptbl_vid59.o \ + jmptbl_vid60.o jmptbl_vid61.o jmptbl_vid62.o jmptbl_vid63.o \ + jmptbl_vid64.o jmptbl_vid65.o jmptbl_vid66.o jmptbl_vid67.o \ + jmptbl_vid68.o jmptbl_vid69.o jmptbl_vid70.o jmptbl_vid71.o \ + jmptbl_vid72.o \ + nmih.o \ + wrh.o + +LIBNDS32_ISR_COMPLETE_OBJS = $(LIBNDS32_ISR_16B_OBJS) $(LIBNDS32_ISR_4B_OBJS) $(LIBNDS32_ISR_COMMON_OBJS) + + +# Build common objects for ISR library +nmih.o: $(srcdir)/config/nds32/isr-library/nmih.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/nmih.S -o nmih.o + +wrh.o: $(srcdir)/config/nds32/isr-library/wrh.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/wrh.S -o wrh.o + +jmptbl_vid%.o: $(srcdir)/config/nds32/isr-library/jmptbl_vid%.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@ + + + +# Build 16b version objects for ISR library. (no "_4b" postfix string) +vec_vid%.o: $(srcdir)/config/nds32/isr-library/vec_vid%.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@ + +excp_isr_ps_nn.o: $(srcdir)/config/nds32/isr-library/excp_isr.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_nn.o + +excp_isr_ps_ns.o: $(srcdir)/config/nds32/isr-library/excp_isr.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_ns.o + +excp_isr_ps_nr.o: $(srcdir)/config/nds32/isr-library/excp_isr.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_ps_nr.o + +excp_isr_sa_nn.o: $(srcdir)/config/nds32/isr-library/excp_isr.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_sa_nn.o + +excp_isr_sa_ns.o: $(srcdir)/config/nds32/isr-library/excp_isr.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_sa_ns.o + +excp_isr_sa_nr.o: $(srcdir)/config/nds32/isr-library/excp_isr.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr.S -o excp_isr_sa_nr.o + +intr_isr_ps_nn.o: $(srcdir)/config/nds32/isr-library/intr_isr.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_ps_nn.o + +intr_isr_ps_ns.o: $(srcdir)/config/nds32/isr-library/intr_isr.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_ps_ns.o + +intr_isr_ps_nr.o: $(srcdir)/config/nds32/isr-library/intr_isr.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_ps_nr.o + +intr_isr_sa_nn.o: $(srcdir)/config/nds32/isr-library/intr_isr.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_sa_nn.o + +intr_isr_sa_ns.o: $(srcdir)/config/nds32/isr-library/intr_isr.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_sa_ns.o + +intr_isr_sa_nr.o: $(srcdir)/config/nds32/isr-library/intr_isr.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr.S -o intr_isr_sa_nr.o + +reset.o: $(srcdir)/config/nds32/isr-library/reset.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset.S -o reset.o + +# Build 4b version objects for ISR library. +vec_vid%_4b.o: $(srcdir)/config/nds32/isr-library/vec_vid%_4b.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $< -o $@ + +excp_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nn_4b.o + +excp_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_ns_4b.o + +excp_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_ps_nr_4b.o + +excp_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nn_4b.o + +excp_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_ns_4b.o + +excp_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/excp_isr_4b.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/excp_isr_4b.S -o excp_isr_sa_nr_4b.o + +intr_isr_ps_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nn_4b.o + +intr_isr_ps_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_ns_4b.o + +intr_isr_ps_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_ps_nr_4b.o + +intr_isr_sa_nn_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nn_4b.o + +intr_isr_sa_ns_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_ns_4b.o + +intr_isr_sa_nr_4b.o: $(srcdir)/config/nds32/isr-library/intr_isr_4b.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) -DNDS32_SAVE_ALL_REGS -DNDS32_NESTED_READY $(srcdir)/config/nds32/isr-library/intr_isr_4b.S -o intr_isr_sa_nr_4b.o + +reset_4b.o: $(srcdir)/config/nds32/isr-library/reset_4b.S + $(GCC_FOR_TARGET) $(ISR_CFLAGS) $(srcdir)/config/nds32/isr-library/reset_4b.S -o reset_4b.o + + +# The rule to create libnds32_isr.a file +libnds32_isr.a: $(LIBNDS32_ISR_COMPLETE_OBJS) + $(AR) rc libnds32_isr.a $(LIBNDS32_ISR_COMPLETE_OBJS) + + +# ------------------------------------------------------------------------ diff --git a/libgcc/config/nds32/t-nds32-mculib b/libgcc/config/nds32/t-nds32-mculib new file mode 100644 index 00000000000..4fbcf4ff52e --- /dev/null +++ b/libgcc/config/nds32/t-nds32-mculib @@ -0,0 +1,77 @@ +# Rules of mculib library makefile of Andes NDS32 cpu for GNU compiler +# Copyright (C) 2012-2013 Free Software Foundation, Inc. +# Contributed by Andes Technology Corporation. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published +# by the Free Software Foundation; either version 3, or (at your +# option) any later version. +# +# GCC is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +# License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# Compiler flags to use when compiling 'libgcc2.c' +HOST_LIBGCC2_CFLAGS = -Os + + +LIB1ASMSRC = nds32/lib1asmsrc-mculib.S + +LIB1ASMFUNCS = \ + _addsub_sf \ + _sf_to_si \ + _divsi3 \ + _divdi3 \ + _modsi3 \ + _moddi3 \ + _mulsi3 \ + _udivsi3 \ + _udivdi3 \ + _udivmoddi4 \ + _umodsi3 \ + _umoddi3 \ + _muldi3 \ + _addsub_df \ + _mul_sf \ + _mul_df \ + _div_sf \ + _div_df \ + _negate_sf \ + _negate_df \ + _sf_to_df \ + _df_to_sf \ + _df_to_si \ + _fixsfdi \ + _fixdfdi \ + _fixunssfsi \ + _fixunsdfsi \ + _fixunssfdi \ + _fixunsdfdi \ + _si_to_sf \ + _si_to_df \ + _floatdisf \ + _floatdidf \ + _floatunsisf \ + _floatunsidf \ + _floatundisf \ + _floatundidf \ + _compare_sf \ + _compare_df \ + _unord_sf \ + _unord_df + +# List of functions not to build from libgcc2.c. +LIB2FUNCS_EXCLUDE = _clzsi2 _clzdi2 + +# List of extra C and assembler files(*.S) to add to static libgcc2. +LIB2ADD_ST += $(srcdir)/config/nds32/lib2csrc-mculib/_clzsi2.c +LIB2ADD_ST += $(srcdir)/config/nds32/lib2csrc-mculib/_clzdi2.c + +# ------------------------------------------------------------------------ diff --git a/libgcc/config/nds32/t-nds32-newlib b/libgcc/config/nds32/t-nds32-newlib new file mode 100644 index 00000000000..b2549a084e9 --- /dev/null +++ b/libgcc/config/nds32/t-nds32-newlib @@ -0,0 +1,34 @@ +# Rules of newlib library makefile of Andes NDS32 cpu for GNU compiler +# Copyright (C) 2012-2013 Free Software Foundation, Inc. +# Contributed by Andes Technology Corporation. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published +# by the Free Software Foundation; either version 3, or (at your +# option) any later version. +# +# GCC is distributed in the hope that it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +# License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# Compiler flags to use when compiling 'libgcc2.c' +HOST_LIBGCC2_CFLAGS = -O2 + + +#LIB1ASMSRC = nds32/lib1asmsrc-newlib.S +#LIB1ASMFUNCS = _divsi3 _modsi3 _udivsi3 _umodsi3 + +# List of functions not to build from libgcc2.c. +#LIB2FUNCS_EXCLUDE = _clzsi2 + +# List of extra C and assembler files(*.S) to add to static libgcc2. +#LIB2ADD_ST += $(srcdir)/config/nds32/lib2csrc-newlib/_clzsi2.c + +# ------------------------------------------------------------------------ |