diff options
| -rw-r--r-- | gcc/config/fx80/fx80.md | 37 | ||||
| -rw-r--r-- | gcc/config/gmicro/gmicro.md | 37 | ||||
| -rw-r--r-- | gcc/config/i860/i860.md | 37 | ||||
| -rw-r--r-- | gcc/config/m68k/m68k.md | 37 | ||||
| -rw-r--r-- | gcc/config/ns32k/ns32k.md | 37 |
5 files changed, 185 insertions, 0 deletions
diff --git a/gcc/config/fx80/fx80.md b/gcc/config/fx80/fx80.md index 0e8c04bb3e3..abadd8f3b10 100644 --- a/gcc/config/fx80/fx80.md +++ b/gcc/config/fx80/fx80.md @@ -2432,6 +2432,43 @@ return \"mov%.l a6@(-4),a0\"; }") +;; Call subroutine returning any type. + +(define_expand "untyped_call" + [(parallel [(call (match_operand 0 "" "") + (const_int 0)) + (match_operand 1 "" "") + (match_operand 2 "" "")])] + "" + " +{ + int i; + + emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + /* The optimizer does not know that the call sets the function value + registers we stored in the result block. We avoid problems by + claiming that all hard registers are used and clobbered at this + point. */ + emit_insn (gen_blockage ()); + + DONE; +}") + +;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and +;; all of memory. This blocks insns from being moved across this point. + +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] 0)] + "" + "") + (define_insn "nop" [(const_int 0)] "" diff --git a/gcc/config/gmicro/gmicro.md b/gcc/config/gmicro/gmicro.md index 5fccdd45491..95b6f5d511f 100644 --- a/gcc/config/gmicro/gmicro.md +++ b/gcc/config/gmicro/gmicro.md @@ -2493,6 +2493,43 @@ return \"jsr %1\"; }") +;; Call subroutine returning any type. + +(define_expand "untyped_call" + [(parallel [(call (match_operand 0 "" "") + (const_int 0)) + (match_operand 1 "" "") + (match_operand 2 "" "")])] + "" + " +{ + int i; + + emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + /* The optimizer does not know that the call sets the function value + registers we stored in the result block. We avoid problems by + claiming that all hard registers are used and clobbered at this + point. */ + emit_insn (gen_blockage ()); + + DONE; +}") + +;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and +;; all of memory. This blocks insns from being moved across this point. + +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] 0)] + "" + "") + (define_insn "nop" [(const_int 0)] "" diff --git a/gcc/config/i860/i860.md b/gcc/config/i860/i860.md index 411b53b3c41..471b5b2a079 100644 --- a/gcc/config/i860/i860.md +++ b/gcc/config/i860/i860.md @@ -2235,6 +2235,43 @@ fmul.ss %1,%0,%4\;fmul.ss %3,%4,%0\"; return output_delayed_branch (\"calli %3\", operands, insn); return output_delayed_branch (\"call %3\", operands, insn); }") + +;; Call subroutine returning any type. + +(define_expand "untyped_call" + [(parallel [(call (match_operand 0 "" "") + (const_int 0)) + (match_operand 1 "" "") + (match_operand 2 "" "")])] + "" + " +{ + int i; + + emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + /* The optimizer does not know that the call sets the function value + registers we stored in the result block. We avoid problems by + claiming that all hard registers are used and clobbered at this + point. */ + emit_insn (gen_blockage ()); + + DONE; +}") + +;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and +;; all of memory. This blocks insns from being moved across this point. + +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] 0)] + "" + "") (define_insn "nop" [(const_int 0)] diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 2c313c71949..6217028fa79 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -4780,6 +4780,43 @@ return \"jsr %1\"; ") +;; Call subroutine returning any type. + +(define_expand "untyped_call" + [(parallel [(call (match_operand 0 "" "") + (const_int 0)) + (match_operand 1 "" "") + (match_operand 2 "" "")])] + "NEEDS_UNTYPED_CALL" + " +{ + int i; + + emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + /* The optimizer does not know that the call sets the function value + registers we stored in the result block. We avoid problems by + claiming that all hard registers are used and clobbered at this + point. */ + emit_insn (gen_blockage ()); + + DONE; +}") + +;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and +;; all of memory. This blocks insns from being moved across this point. + +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] 0)] + "" + "") + (define_insn "nop" [(const_int 0)] "" diff --git a/gcc/config/ns32k/ns32k.md b/gcc/config/ns32k/ns32k.md index b3ea5ef27d4..dd0c21f07d4 100644 --- a/gcc/config/ns32k/ns32k.md +++ b/gcc/config/ns32k/ns32k.md @@ -2273,6 +2273,43 @@ return \"jsr %1\"; }") +;; Call subroutine returning any type. + +(define_expand "untyped_call" + [(parallel [(call (match_operand 0 "" "") + (const_int 0)) + (match_operand 1 "" "") + (match_operand 2 "" "")])] + "" + " +{ + int i; + + emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + /* The optimizer does not know that the call sets the function value + registers we stored in the result block. We avoid problems by + claiming that all hard registers are used and clobbered at this + point. */ + emit_insn (gen_blockage ()); + + DONE; +}") + +;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and +;; all of memory. This blocks insns from being moved across this point. + +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] 0)] + "" + "") + (define_insn "return" [(return)] "0" |