diff options
| -rw-r--r-- | gcc/ChangeLog | 64 | ||||
| -rw-r--r-- | gcc/common/config/i386/i386-common.c | 226 | ||||
| -rw-r--r-- | gcc/config/i386/i386-builtin.def | 128 | ||||
| -rw-r--r-- | gcc/config/i386/i386-builtins.c | 14 | ||||
| -rw-r--r-- | gcc/config/i386/i386-c.c | 32 | ||||
| -rw-r--r-- | gcc/config/i386/i386-options.c | 102 | ||||
| -rw-r--r-- | gcc/config/i386/i386.h | 76 | ||||
| -rw-r--r-- | gcc/config/i386/i386.opt | 38 |
8 files changed, 372 insertions, 308 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3d98bef0136..58ffe7629e3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,67 @@ +2019-12-09 Hongtao Liu <hongtao.liu@intel.com> + + * gcc/common/config/i386/i386-common.c + (OPTION_MASK_ISA_AVX5124FMAPS_SET): Rename to + OPTION_MASK_ISA2_AVX5124FMAPS_SET. + (OPTION_MASK_ISA_AVX5124VNNIW_SET, OPTION_MASK_ISA_AVX512BF16_SET, + OPTION_MASK_ISA_AVX512VP2INTERSECT_SET, + OPTION_MASK_ISA_PCONFIG_SET, OPTION_MASK_ISA_WBNOINVD_SET, + OPTION_MASK_ISA_SGX_SET, OPTION_MASK_ISA_CX16_SET, + OPTION_MASK_ISA_MOVBE_SET, OPTION_MASK_ISA_PTWRITE_SET, + OPTION_MASK_ISA_MWAITX_SET, OPTION_MASK_ISA_CLZERO_SET, + OPTION_MASK_ISA_RDPID_SET, OPTION_MASK_ISA_VAES_SET, + OPTION_MASK_ISA_MOVDIR64B_SET, OPTION_MASK_ISA_WAITPKG_SET, + OPTION_MASK_ISA_CLDEMOTE_SET, OPTION_MASK_ISA_ENQCMD_SET, + OPTION_MASK_ISA_AVX5124FMAPS_UNSET, + OPTION_MASK_ISA_AVX5124VNNIW_UNSET, + OPTION_MASK_ISA_AVX512BF16_UNSET, + OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET, + OPTION_MASK_ISA_PCONFIG_UNSET, OPTION_MASK_ISA_WBNOINVD_UNSET, + OPTION_MASK_ISA_SGX_UNSET, OPTION_MASK_ISA_CX16_UNSET, + OPTION_MASK_ISA_MOVBE_UNSET, OPTION_MASK_ISA_PTWRITE_UNSET, + OPTION_MASK_ISA_MWAITX_UNSET, OPTION_MASK_ISA_CLZERO_UNSET, + OPTION_MASK_ISA_RDPID_UNSET, OPTION_MASK_ISA_VAES_UNSET, + OPTION_MASK_ISA_MOVDIR64B_UNSET, OPTION_MASK_ISA_WAITPKG_UNSET, + OPTION_MASK_ISA_CLDEMOTE_UNSET, OPTION_MASK_ISA_ENQCMD_UNSET, + OPTION_MASK_ISA_AVX5124FMAPS, OPTION_MASK_ISA_AVX5124VNNIW, + OPTION_MASK_ISA_AVX512BF16, OPTION_MASK_ISA_AVX512VP2INTERSECT, + OPTION_MASK_ISA_PCONFIG, OPTION_MASK_ISA_WBNOINVD, + OPTION_MASK_ISA_SGX, OPTION_MASK_ISA_CX16, OPTION_MASK_ISA_MOVBE, + OPTION_MASK_ISA_PTWRITE, OPTION_MASK_ISA_MWAITX, + OPTION_MASK_ISA_CLZERO, OPTION_MASK_ISA_RDPID, + OPTION_MASK_ISA_VAES, OPTION_MASK_ISA_MOVDIR64B, + OPTION_MASK_ISA_WAITPKG, OPTION_MASK_ISA_CLDEMOTE, + OPTION_MASK_ISA_ENQCMD): Ditto. + * gcc/config/i386/i386-builtin.def + (OPTION_MASK_ISA_AVX5124FMAPS, OPTION_MASK_ISA_AVX5124VNNIW, + OPTION_MASK_ISA_AVX512BF16, OPTION_MASK_ISA_AVX512VP2INTERSECT, + OPTION_MASK_ISA_WBNOINVD, OPTION_MASK_ISA_PTWRITE, + OPTION_MASK_ISA_RDPID, OPTION_MASK_ISA_VAES, + OPTION_MASK_ISA_MOVDIR64B, OPTION_MASK_ISA_ENQCMD): Ditto. + * gcc/config/i386/i386-builtins.c (OPTION_MASK_ISA_MWAITX, + OPTION_MASK_ISA_CLZERO, OPTION_MASK_ISA_WAITPKG, + OPTION_MASK_ISA_CLDEMOTE, OPTION_MASK_ISA_WBNOINVD): Ditto. + * gcc/config/i386/i386-c.c + (OPTION_MASK_ISA_AVX5124FMAPS, OPTION_MASK_ISA_AVX5124VNNIW, + OPTION_MASK_ISA_AVX512BF16, OPTION_MASK_ISA_AVX512VP2INTERSECT, + OPTION_MASK_ISA_PCONFIG, OPTION_MASK_ISA_WBNOINVD, + OPTION_MASK_ISA_SGX, OPTION_MASK_ISA_CX16, OPTION_MASK_ISA_MOVBE, + OPTION_MASK_ISA_PTWRITE, OPTION_MASK_ISA_MWAITX, + OPTION_MASK_ISA_CLZERO, OPTION_MASK_ISA_RDPID, + OPTION_MASK_ISA_VAES, OPTION_MASK_ISA_MOVDIR64B, + OPTION_MASK_ISA_WAITPKG, OPTION_MASK_ISA_CLDEMOTE, + OPTION_MASK_ISA_ENQCMD): Ditto. + * gcc/config/i386/i386-option.c: Ditto + * gcc/config/i386/i386.opt: Ditto.. + * gcc/config/i386/i386.h: (TARGET_ISA_AVX5124FMAPS, + TARGET_ISA_AVX5124VNNIW, TARGET_ISA_AVX512BF16, + TARGET_ISA_AVX512VP2INTERSECT, TARGET_ISA_PCONFIG, + TARGET_ISA_WBNOINVD, TARGET_ISA_SGX, TARGET_ISA_CX16, + TARGET_ISA_MOVBE, TARGET_ISA_PTWRITE, TARGET_ISA_MWAITX, + TARGET_ISA_CLZERO, TARGET_ISA_RDPID, TARGET_ISA_VAES, + TARGET_ISA_MOVDIR64B, TARGET_ISA_WAITPKG, TARGET_ISA_CLDEMOTE) + TARGET_ISA_ENQCMD): Ditto. + 2019-12-09 Sudakshina Das <sudi.das@arm.com> Richard Sandiford <richard.sandiford@arm.com> diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 5cb1dccee45..d3e861b91d4 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -78,8 +78,8 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET) #define OPTION_MASK_ISA_AVX512VBMI_SET \ (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET) -#define OPTION_MASK_ISA_AVX5124FMAPS_SET OPTION_MASK_ISA_AVX5124FMAPS -#define OPTION_MASK_ISA_AVX5124VNNIW_SET OPTION_MASK_ISA_AVX5124VNNIW +#define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS +#define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW #define OPTION_MASK_ISA_AVX512VBMI2_SET \ (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET) #define OPTION_MASK_ISA_AVX512VNNI_SET \ @@ -88,7 +88,7 @@ along with GCC; see the file COPYING3. If not see (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET) #define OPTION_MASK_ISA_AVX512BITALG_SET \ (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET) -#define OPTION_MASK_ISA_AVX512BF16_SET OPTION_MASK_ISA_AVX512BF16 +#define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED @@ -100,7 +100,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_XSAVEC_SET \ (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET) #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB -#define OPTION_MASK_ISA_AVX512VP2INTERSECT_SET OPTION_MASK_ISA_AVX512VP2INTERSECT +#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -127,37 +127,37 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_ABM_SET \ (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT) -#define OPTION_MASK_ISA_PCONFIG_SET OPTION_MASK_ISA_PCONFIG -#define OPTION_MASK_ISA_WBNOINVD_SET OPTION_MASK_ISA_WBNOINVD -#define OPTION_MASK_ISA_SGX_SET OPTION_MASK_ISA_SGX +#define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG +#define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD +#define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT -#define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16 +#define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF -#define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE +#define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND -#define OPTION_MASK_ISA_PTWRITE_SET OPTION_MASK_ISA_PTWRITE +#define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE #define OPTION_MASK_ISA_F16C_SET \ (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET) -#define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX -#define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO +#define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX +#define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU -#define OPTION_MASK_ISA_RDPID_SET OPTION_MASK_ISA_RDPID +#define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK -#define OPTION_MASK_ISA_VAES_SET OPTION_MASK_ISA_VAES +#define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI -#define OPTION_MASK_ISA_MOVDIR64B_SET OPTION_MASK_ISA_MOVDIR64B -#define OPTION_MASK_ISA_WAITPKG_SET OPTION_MASK_ISA_WAITPKG -#define OPTION_MASK_ISA_CLDEMOTE_SET OPTION_MASK_ISA_CLDEMOTE -#define OPTION_MASK_ISA_ENQCMD_SET OPTION_MASK_ISA_ENQCMD +#define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B +#define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG +#define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE +#define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD /* Define a set of ISAs which aren't available when a given ISA is disabled. MMX and SSE ISAs are handled separately. */ @@ -212,13 +212,13 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI -#define OPTION_MASK_ISA_AVX5124FMAPS_UNSET OPTION_MASK_ISA_AVX5124FMAPS -#define OPTION_MASK_ISA_AVX5124VNNIW_UNSET OPTION_MASK_ISA_AVX5124VNNIW +#define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS +#define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG -#define OPTION_MASK_ISA_AVX512BF16_UNSET OPTION_MASK_ISA_AVX512BF16 +#define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED @@ -228,20 +228,20 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB -#define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX -#define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO +#define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX +#define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU -#define OPTION_MASK_ISA_RDPID_UNSET OPTION_MASK_ISA_RDPID +#define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK -#define OPTION_MASK_ISA_VAES_UNSET OPTION_MASK_ISA_VAES +#define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI -#define OPTION_MASK_ISA_MOVDIR64B_UNSET OPTION_MASK_ISA_MOVDIR64B -#define OPTION_MASK_ISA_WAITPKG_UNSET OPTION_MASK_ISA_WAITPKG -#define OPTION_MASK_ISA_CLDEMOTE_UNSET OPTION_MASK_ISA_CLDEMOTE -#define OPTION_MASK_ISA_ENQCMD_UNSET OPTION_MASK_ISA_ENQCMD -#define OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA_AVX512VP2INTERSECT +#define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B +#define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG +#define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE +#define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD +#define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -259,22 +259,22 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM -#define OPTION_MASK_ISA_PCONFIG_UNSET OPTION_MASK_ISA_PCONFIG -#define OPTION_MASK_ISA_WBNOINVD_UNSET OPTION_MASK_ISA_WBNOINVD -#define OPTION_MASK_ISA_SGX_UNSET OPTION_MASK_ISA_SGX +#define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG +#define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD +#define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT -#define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16 +#define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF -#define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE +#define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND -#define OPTION_MASK_ISA_PTWRITE_UNSET OPTION_MASK_ISA_PTWRITE +#define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \ @@ -282,14 +282,14 @@ along with GCC; see the file COPYING3. If not see | OPTION_MASK_ISA_SSE_UNSET) #define OPTION_MASK_ISA2_AVX512F_UNSET \ - (OPTION_MASK_ISA_AVX512BF16_UNSET \ - | OPTION_MASK_ISA_AVX5124FMAPS_UNSET \ - | OPTION_MASK_ISA_AVX5124VNNIW_UNSET \ - | OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET) + (OPTION_MASK_ISA2_AVX512BF16_UNSET \ + | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \ + | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \ + | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET) #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ (OPTION_MASK_ISA2_AVX512F_UNSET) -#define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA_AVX512BF16_UNSET +#define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA2_AVX512BF16_UNSET /* Set 1 << value as value of -malign-FLAG option. */ @@ -550,13 +550,13 @@ ix86_handle_option (struct gcc_options *opts, case OPT_mrdpid: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_RDPID_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET; } return true; @@ -589,13 +589,13 @@ ix86_handle_option (struct gcc_options *opts, case OPT_mvaes: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_VAES_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET; } return true; @@ -628,82 +628,82 @@ ix86_handle_option (struct gcc_options *opts, case OPT_mmovdir64b: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVDIR64B_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVDIR64B_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET; } return true; case OPT_mcldemote: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLDEMOTE_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLDEMOTE_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLDEMOTE_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLDEMOTE_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET; } return true; case OPT_mwaitpkg: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WAITPKG_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WAITPKG_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET; } return true; case OPT_menqcmd: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_ENQCMD_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_ENQCMD_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_ENQCMD_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_ENQCMD_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET; } return true; case OPT_mavx5124fmaps: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124FMAPS_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_SET; opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124FMAPS_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124FMAPS_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_UNSET; } return true; case OPT_mavx5124vnniw: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124VNNIW_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_SET; opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124VNNIW_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_UNSET; } return true; @@ -765,54 +765,54 @@ ix86_handle_option (struct gcc_options *opts, case OPT_mavx512bf16: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512BF16_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX512BF16_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET; opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX512BF16_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX512BF16_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET; } return true; case OPT_msgx: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_SGX_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SGX_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_UNSET; } return true; case OPT_mpconfig: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_PCONFIG_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PCONFIG_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_UNSET; } return true; case OPT_mwbnoinvd: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WBNOINVD_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WBNOINVD_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_UNSET; } return true; @@ -886,17 +886,17 @@ ix86_handle_option (struct gcc_options *opts, case OPT_mavx512vp2intersect: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512VP2INTERSECT_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET; opts->x_ix86_isa_flags2_explicit |= - OPTION_MASK_ISA_AVX512VP2INTERSECT_SET; + OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET; opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET; opts->x_ix86_isa_flags2_explicit |= - OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET; + OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET; } return true; @@ -1084,26 +1084,26 @@ ix86_handle_option (struct gcc_options *opts, case OPT_mcx16: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CX16_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CX16_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_UNSET; } return true; case OPT_mmovbe: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVBE_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVBE_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_UNSET; } return true; @@ -1188,13 +1188,13 @@ ix86_handle_option (struct gcc_options *opts, case OPT_mptwrite: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PTWRITE_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PTWRITE_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_PTWRITE_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PTWRITE_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PTWRITE_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_UNSET; } return true; @@ -1357,26 +1357,26 @@ ix86_handle_option (struct gcc_options *opts, case OPT_mmwaitx: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MWAITX_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAITX_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_UNSET; } return true; case OPT_mclzero: if (value) { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_SET; + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_SET; } else { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLZERO_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_UNSET; + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLZERO_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_UNSET; } return true; diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 11028331cda..a6500f9d9b5 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -289,12 +289,12 @@ BDESC (OPTION_MASK_ISA_AVX512BW, 0, CODE_FOR_avx512bw_storev32hi_mask, "__builti BDESC (OPTION_MASK_ISA_AVX512BW, 0, CODE_FOR_avx512bw_storev64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PCHAR_V64QI_UDI) /* AVX512VP2INTERSECT */ -BDESC (0, OPTION_MASK_ISA_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectd512", IX86_BUILTIN_2INTERSECTD512, UNKNOWN, (int) VOID_FTYPE_PUHI_PUHI_V16SI_V16SI) -BDESC (0, OPTION_MASK_ISA_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectq512", IX86_BUILTIN_2INTERSECTQ512, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V8DI_V8DI) -BDESC (0, OPTION_MASK_ISA_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectd256", IX86_BUILTIN_2INTERSECTD256, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V8SI_V8SI) -BDESC (0, OPTION_MASK_ISA_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectq256", IX86_BUILTIN_2INTERSECTQ256, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V4DI_V4DI) -BDESC (0, OPTION_MASK_ISA_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectd128", IX86_BUILTIN_2INTERSECTD128, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V4SI_V4SI) -BDESC (0, OPTION_MASK_ISA_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectq128", IX86_BUILTIN_2INTERSECTQ128, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V2DI_V2DI) +BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectd512", IX86_BUILTIN_2INTERSECTD512, UNKNOWN, (int) VOID_FTYPE_PUHI_PUHI_V16SI_V16SI) +BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectq512", IX86_BUILTIN_2INTERSECTQ512, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V8DI_V8DI) +BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectd256", IX86_BUILTIN_2INTERSECTD256, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V8SI_V8SI) +BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectq256", IX86_BUILTIN_2INTERSECTQ256, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V4DI_V4DI) +BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectd128", IX86_BUILTIN_2INTERSECTD128, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V4SI_V4SI) +BDESC (0, OPTION_MASK_ISA2_AVX512VP2INTERSECT, CODE_FOR_nothing, "__builtin_ia32_2intersectq128", IX86_BUILTIN_2INTERSECTQ128, UNKNOWN, (int) VOID_FTYPE_PUQI_PUQI_V2DI_V2DI) /* AVX512VL */ BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_loadv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCSHORT_V16HI_UHI) @@ -435,16 +435,16 @@ BDESC (OPTION_MASK_ISA_MOVDIRI, 0, CODE_FOR_movdirisi, "__builtin_ia32_directsto BDESC (OPTION_MASK_ISA_MOVDIRI | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_movdiridi, "__builtin_ia32_directstoreu_u64", IX86_BUILTIN_MOVDIRIDI64, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG) /* MASK2. */ -BDESC (0, OPTION_MASK_ISA_WBNOINVD, CODE_FOR_wbnoinvd, "__builtin_ia32_wbnoinvd", IX86_BUILTIN_WBNOINVD, UNKNOWN, (int) VOID_FTYPE_VOID) -BDESC (0, OPTION_MASK_ISA_MOVDIR64B, CODE_FOR_nothing, "__builtin_ia32_movdir64b", IX86_BUILTIN_MOVDIR64B, UNKNOWN, (int) VOID_FTYPE_PVOID_PCVOID) +BDESC (0, OPTION_MASK_ISA2_WBNOINVD, CODE_FOR_wbnoinvd, "__builtin_ia32_wbnoinvd", IX86_BUILTIN_WBNOINVD, UNKNOWN, (int) VOID_FTYPE_VOID) +BDESC (0, OPTION_MASK_ISA2_MOVDIR64B, CODE_FOR_nothing, "__builtin_ia32_movdir64b", IX86_BUILTIN_MOVDIR64B, UNKNOWN, (int) VOID_FTYPE_PVOID_PCVOID) /* PTWRITE. */ -BDESC (0, OPTION_MASK_ISA_PTWRITE, CODE_FOR_ptwritesi, "__builtin_ia32_ptwrite32", IX86_BUILTIN_PTWRITE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED) -BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA_PTWRITE, CODE_FOR_ptwritedi, "__builtin_ia32_ptwrite64", IX86_BUILTIN_PTWRITE64, UNKNOWN, (int) VOID_FTYPE_UINT64) +BDESC (0, OPTION_MASK_ISA2_PTWRITE, CODE_FOR_ptwritesi, "__builtin_ia32_ptwrite32", IX86_BUILTIN_PTWRITE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED) +BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_PTWRITE, CODE_FOR_ptwritedi, "__builtin_ia32_ptwrite64", IX86_BUILTIN_PTWRITE64, UNKNOWN, (int) VOID_FTYPE_UINT64) /* ENQCMD */ -BDESC (0, OPTION_MASK_ISA_ENQCMD, CODE_FOR_nothing, "__builtin_ia32_enqcmd", IX86_BUILTIN_ENQCMD, UNKNOWN, (int) INT_FTYPE_PVOID_PCVOID) -BDESC (0, OPTION_MASK_ISA_ENQCMD, CODE_FOR_nothing, "__builtin_ia32_enqcmds", IX86_BUILTIN_ENQCMDS, UNKNOWN, (int) INT_FTYPE_PVOID_PCVOID) +BDESC (0, OPTION_MASK_ISA2_ENQCMD, CODE_FOR_nothing, "__builtin_ia32_enqcmd", IX86_BUILTIN_ENQCMD, UNKNOWN, (int) INT_FTYPE_PVOID_PCVOID) +BDESC (0, OPTION_MASK_ISA2_ENQCMD, CODE_FOR_nothing, "__builtin_ia32_enqcmds", IX86_BUILTIN_ENQCMDS, UNKNOWN, (int) INT_FTYPE_PVOID_PCVOID) BDESC_END (SPECIAL_ARGS, ARGS) @@ -2685,64 +2685,64 @@ BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA BDESC (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_vpshufbitqmbv16qi_mask, "__builtin_ia32_vpshufbitqmb128_mask", IX86_BUILTIN_VPSHUFBITQMB128_MASK, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_UHI) /* AVX512_4FMAPS and AVX512_4VNNIW builtins with variable number of arguments. Defined in additional ix86_isa_flags2. */ -BDESC (0, OPTION_MASK_ISA_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fmaddps_mask, "__builtin_ia32_4fmaddps_mask", IX86_BUILTIN_4FMAPS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF_V16SF_UHI) -BDESC (0, OPTION_MASK_ISA_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fmaddps, "__builtin_ia32_4fmaddps", IX86_BUILTIN_4FMAPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF) -BDESC (0, OPTION_MASK_ISA_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fmaddss, "__builtin_ia32_4fmaddss", IX86_BUILTIN_4FMASS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF) -BDESC (0, OPTION_MASK_ISA_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fmaddss_mask, "__builtin_ia32_4fmaddss_mask", IX86_BUILTIN_4FMASS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF_V4SF_UQI) -BDESC (0, OPTION_MASK_ISA_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fnmaddps_mask, "__builtin_ia32_4fnmaddps_mask", IX86_BUILTIN_4FNMAPS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF_V16SF_UHI) -BDESC (0, OPTION_MASK_ISA_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fnmaddps, "__builtin_ia32_4fnmaddps", IX86_BUILTIN_4FNMAPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF) -BDESC (0, OPTION_MASK_ISA_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fnmaddss, "__builtin_ia32_4fnmaddss", IX86_BUILTIN_4FNMASS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF) -BDESC (0, OPTION_MASK_ISA_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fnmaddss_mask, "__builtin_ia32_4fnmaddss_mask", IX86_BUILTIN_4FNMASS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF_V4SF_UQI) -BDESC (0, OPTION_MASK_ISA_AVX5124VNNIW, CODE_FOR_avx5124vnniw_vp4dpwssd, "__builtin_ia32_vp4dpwssd", IX86_BUILTIN_4DPWSSD, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI) -BDESC (0, OPTION_MASK_ISA_AVX5124VNNIW, CODE_FOR_avx5124vnniw_vp4dpwssd_mask, "__builtin_ia32_vp4dpwssd_mask", IX86_BUILTIN_4DPWSSD_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI_V16SI_UHI) -BDESC (0, OPTION_MASK_ISA_AVX5124VNNIW, CODE_FOR_avx5124vnniw_vp4dpwssds, "__builtin_ia32_vp4dpwssds", IX86_BUILTIN_4DPWSSDS, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI) -BDESC (0, OPTION_MASK_ISA_AVX5124VNNIW, CODE_FOR_avx5124vnniw_vp4dpwssds_mask, "__builtin_ia32_vp4dpwssds_mask", IX86_BUILTIN_4DPWSSDS_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI_V16SI_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fmaddps_mask, "__builtin_ia32_4fmaddps_mask", IX86_BUILTIN_4FMAPS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF_V16SF_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fmaddps, "__builtin_ia32_4fmaddps", IX86_BUILTIN_4FMAPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF) +BDESC (0, OPTION_MASK_ISA2_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fmaddss, "__builtin_ia32_4fmaddss", IX86_BUILTIN_4FMASS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF) +BDESC (0, OPTION_MASK_ISA2_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fmaddss_mask, "__builtin_ia32_4fmaddss_mask", IX86_BUILTIN_4FMASS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF_V4SF_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fnmaddps_mask, "__builtin_ia32_4fnmaddps_mask", IX86_BUILTIN_4FNMAPS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF_V16SF_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fnmaddps, "__builtin_ia32_4fnmaddps", IX86_BUILTIN_4FNMAPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_V16SF_V16SF_PCV4SF) +BDESC (0, OPTION_MASK_ISA2_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fnmaddss, "__builtin_ia32_4fnmaddss", IX86_BUILTIN_4FNMASS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF) +BDESC (0, OPTION_MASK_ISA2_AVX5124FMAPS, CODE_FOR_avx5124fmaddps_4fnmaddss_mask, "__builtin_ia32_4fnmaddss_mask", IX86_BUILTIN_4FNMASS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_V4SF_V4SF_PCV4SF_V4SF_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX5124VNNIW, CODE_FOR_avx5124vnniw_vp4dpwssd, "__builtin_ia32_vp4dpwssd", IX86_BUILTIN_4DPWSSD, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI) +BDESC (0, OPTION_MASK_ISA2_AVX5124VNNIW, CODE_FOR_avx5124vnniw_vp4dpwssd_mask, "__builtin_ia32_vp4dpwssd_mask", IX86_BUILTIN_4DPWSSD_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI_V16SI_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX5124VNNIW, CODE_FOR_avx5124vnniw_vp4dpwssds, "__builtin_ia32_vp4dpwssds", IX86_BUILTIN_4DPWSSDS, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI) +BDESC (0, OPTION_MASK_ISA2_AVX5124VNNIW, CODE_FOR_avx5124vnniw_vp4dpwssds_mask, "__builtin_ia32_vp4dpwssds_mask", IX86_BUILTIN_4DPWSSDS_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_V16SI_V16SI_PCV4SI_V16SI_UHI) /* RDPID. */ -BDESC (0, OPTION_MASK_ISA_RDPID, CODE_FOR_rdpid, "__builtin_ia32_rdpid", IX86_BUILTIN_RDPID, UNKNOWN, (int) UNSIGNED_FTYPE_VOID) +BDESC (0, OPTION_MASK_ISA2_RDPID, CODE_FOR_rdpid, "__builtin_ia32_rdpid", IX86_BUILTIN_RDPID, UNKNOWN, (int) UNSIGNED_FTYPE_VOID) /* VAES. */ -BDESC (0, OPTION_MASK_ISA_VAES, CODE_FOR_vaesdec_v16qi, "__builtin_ia32_vaesdec_v16qi", IX86_BUILTIN_VAESDEC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA_VAES, CODE_FOR_vaesdec_v32qi, "__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA_VAES, CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) -BDESC (0, OPTION_MASK_ISA_VAES, CODE_FOR_vaesdeclast_v16qi, "__builtin_ia32_vaesdeclast_v16qi", IX86_BUILTIN_VAESDECLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA_VAES, CODE_FOR_vaesdeclast_v32qi, "__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA_VAES, CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdeclast_v64qi", IX86_BUILTIN_VAESDECLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) -BDESC (0, OPTION_MASK_ISA_VAES, CODE_FOR_vaesenc_v16qi, "__builtin_ia32_vaesenc_v16qi", IX86_BUILTIN_VAESENC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA_VAES, CODE_FOR_vaesenc_v32qi, "__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA_VAES, CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) -BDESC (0, OPTION_MASK_ISA_VAES, CODE_FOR_vaesenclast_v16qi, "__builtin_ia32_vaesenclast_v16qi", IX86_BUILTIN_VAESENCLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) -BDESC (0, OPTION_MASK_ISA_VAES, CODE_FOR_vaesenclast_v32qi, "__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) -BDESC (0, OPTION_MASK_ISA_VAES, CODE_FOR_vaesenclast_v64qi, "__builtin_ia32_vaesenclast_v64qi", IX86_BUILTIN_VAESENCLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v16qi, "__builtin_ia32_vaesdec_v16qi", IX86_BUILTIN_VAESDEC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) +BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v32qi, "__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v16qi, "__builtin_ia32_vaesdeclast_v16qi", IX86_BUILTIN_VAESDECLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) +BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v32qi, "__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdeclast_v64qi", IX86_BUILTIN_VAESDECLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v16qi, "__builtin_ia32_vaesenc_v16qi", IX86_BUILTIN_VAESENC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) +BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v32qi, "__builtin_ia32_vaesenc_v32qi", IX86_BUILTIN_VAESENC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenc_v64qi, "__builtin_ia32_vaesenc_v64qi", IX86_BUILTIN_VAESENC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) +BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v16qi, "__builtin_ia32_vaesenclast_v16qi", IX86_BUILTIN_VAESENCLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI) +BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v32qi, "__builtin_ia32_vaesenclast_v32qi", IX86_BUILTIN_VAESENCLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI) +BDESC (0, OPTION_MASK_ISA2_VAES, CODE_FOR_vaesenclast_v64qi, "__builtin_ia32_vaesenclast_v64qi", IX86_BUILTIN_VAESENCLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI) /* BF16 */ -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v32hi, "__builtin_ia32_cvtne2ps2bf16_v32hi", IX86_BUILTIN_CVTNE2PS2HI16_V32HI, UNKNOWN, (int) V32HI_FTYPE_V16SF_V16SF) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v32hi_mask, "__builtin_ia32_cvtne2ps2bf16_v32hi_mask", IX86_BUILTIN_CVTNE2PS2HI16_V32HI_MASK, UNKNOWN, (int) V32HI_FTYPE_V16SF_V16SF_V32HI_USI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v32hi_maskz, "__builtin_ia32_cvtne2ps2bf16_v32hi_maskz", IX86_BUILTIN_CVTNE2PS2HI16_V32HI_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V16SF_V16SF_USI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v16hi, "__builtin_ia32_cvtne2ps2bf16_v16hi", IX86_BUILTIN_CVTNE2PS2HI16_V16HI, UNKNOWN, (int) V16HI_FTYPE_V8SF_V8SF) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v16hi_mask, "__builtin_ia32_cvtne2ps2bf16_v16hi_mask", IX86_BUILTIN_CVTNE2PS2HI16_V16HI_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SF_V8SF_V16HI_UHI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v16hi_maskz, "__builtin_ia32_cvtne2ps2bf16_v16hi_maskz", IX86_BUILTIN_CVTNE2PS2HI16_V16HI_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V8SF_V8SF_UHI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v8hi, "__builtin_ia32_cvtne2ps2bf16_v8hi", IX86_BUILTIN_CVTNE2PS2HI16_V8HI, UNKNOWN, (int) V8HI_FTYPE_V4SF_V4SF) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v8hi_mask, "__builtin_ia32_cvtne2ps2bf16_v8hi_mask", IX86_BUILTIN_CVTNE2PS2HI16_V8HI_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_V4SF_V8HI_UQI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v8hi_maskz, "__builtin_ia32_cvtne2ps2bf16_v8hi_maskz", IX86_BUILTIN_CVTNE2PS2HI16_V8HI_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V4SF_V4SF_UQI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v16sf, "__builtin_ia32_cvtneps2bf16_v16sf", IX86_BUILTIN_CVTNEPS2HI16_V16SF, UNKNOWN, (int) V16HI_FTYPE_V16SF) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v16sf_mask, "__builtin_ia32_cvtneps2bf16_v16sf_mask", IX86_BUILTIN_CVTNEPS2HI16_V16SF_MASK, UNKNOWN, (int) V16HI_FTYPE_V16SF_V16HI_UHI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v16sf_maskz, "__builtin_ia32_cvtneps2bf16_v16sf_maskz", IX86_BUILTIN_CVTNE2PS2HI16_V16SF_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16SF_UHI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v8sf, "__builtin_ia32_cvtneps2bf16_v8sf", IX86_BUILTIN_CVTNEPS2HI16_V8SF, UNKNOWN, (int) V8HI_FTYPE_V8SF) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v8sf_mask, "__builtin_ia32_cvtneps2bf16_v8sf_mask", IX86_BUILTIN_CVTNEPS2HI16_V8SF_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_V8HI_UQI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v8sf_maskz, "__builtin_ia32_cvtneps2bf16_v8sf_maskz", IX86_BUILTIN_CVTNE2PS2HI16_V8SF_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8SF_UQI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v4sf, "__builtin_ia32_cvtneps2bf16_v4sf", IX86_BUILTIN_CVTNEPS2HI16_V4SF, UNKNOWN, (int) V8HI_FTYPE_V4SF) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v4sf_mask, "__builtin_ia32_cvtneps2bf16_v4sf_mask", IX86_BUILTIN_CVTNEPS2HI16_V4SF_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_V8HI_UQI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v4sf_maskz, "__builtin_ia32_cvtneps2bf16_v4sf_maskz", IX86_BUILTIN_CVTNE2PS2HI16_V4SF_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V4SF_UQI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v16sf, "__builtin_ia32_dpbf16ps_v16sf", IX86_BUILTIN_DPHI16PS_V16SF, UNKNOWN, (int) V16SF_FTYPE_V16SF_V32HI_V32HI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v16sf_mask, "__builtin_ia32_dpbf16ps_v16sf_mask", IX86_BUILTIN_DPHI16PS_V16SF_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V32HI_V32HI_UHI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v16sf_maskz, "__builtin_ia32_dpbf16ps_v16sf_maskz", IX86_BUILTIN_DPHI16PS_V16SF_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V32HI_V32HI_UHI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v8sf, "__builtin_ia32_dpbf16ps_v8sf", IX86_BUILTIN_DPHI16PS_V8SF, UNKNOWN, (int) V8SF_FTYPE_V8SF_V16HI_V16HI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v8sf_mask, "__builtin_ia32_dpbf16ps_v8sf_mask", IX86_BUILTIN_DPHI16PS_V8SF_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V16HI_V16HI_UQI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v8sf_maskz, "__builtin_ia32_dpbf16ps_v8sf_maskz", IX86_BUILTIN_DPHI16PS_V8SF_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V16HI_V16HI_UQI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v4sf, "__builtin_ia32_dpbf16ps_v4sf", IX86_BUILTIN_DPHI16PS_V4SF, UNKNOWN, (int) V4SF_FTYPE_V4SF_V8HI_V8HI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v4sf_mask, "__builtin_ia32_dpbf16ps_v4sf_mask", IX86_BUILTIN_DPHI16PS_V4SF_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V8HI_V8HI_UQI) -BDESC (0, OPTION_MASK_ISA_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v4sf_maskz, "__builtin_ia32_dpbf16ps_v4sf_maskz", IX86_BUILTIN_DPHI16PS_V4SF_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V8HI_V8HI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v32hi, "__builtin_ia32_cvtne2ps2bf16_v32hi", IX86_BUILTIN_CVTNE2PS2HI16_V32HI, UNKNOWN, (int) V32HI_FTYPE_V16SF_V16SF) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v32hi_mask, "__builtin_ia32_cvtne2ps2bf16_v32hi_mask", IX86_BUILTIN_CVTNE2PS2HI16_V32HI_MASK, UNKNOWN, (int) V32HI_FTYPE_V16SF_V16SF_V32HI_USI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v32hi_maskz, "__builtin_ia32_cvtne2ps2bf16_v32hi_maskz", IX86_BUILTIN_CVTNE2PS2HI16_V32HI_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V16SF_V16SF_USI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v16hi, "__builtin_ia32_cvtne2ps2bf16_v16hi", IX86_BUILTIN_CVTNE2PS2HI16_V16HI, UNKNOWN, (int) V16HI_FTYPE_V8SF_V8SF) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v16hi_mask, "__builtin_ia32_cvtne2ps2bf16_v16hi_mask", IX86_BUILTIN_CVTNE2PS2HI16_V16HI_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SF_V8SF_V16HI_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v16hi_maskz, "__builtin_ia32_cvtne2ps2bf16_v16hi_maskz", IX86_BUILTIN_CVTNE2PS2HI16_V16HI_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V8SF_V8SF_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v8hi, "__builtin_ia32_cvtne2ps2bf16_v8hi", IX86_BUILTIN_CVTNE2PS2HI16_V8HI, UNKNOWN, (int) V8HI_FTYPE_V4SF_V4SF) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v8hi_mask, "__builtin_ia32_cvtne2ps2bf16_v8hi_mask", IX86_BUILTIN_CVTNE2PS2HI16_V8HI_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_V4SF_V8HI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtne2ps2bf16_v8hi_maskz, "__builtin_ia32_cvtne2ps2bf16_v8hi_maskz", IX86_BUILTIN_CVTNE2PS2HI16_V8HI_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V4SF_V4SF_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v16sf, "__builtin_ia32_cvtneps2bf16_v16sf", IX86_BUILTIN_CVTNEPS2HI16_V16SF, UNKNOWN, (int) V16HI_FTYPE_V16SF) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v16sf_mask, "__builtin_ia32_cvtneps2bf16_v16sf_mask", IX86_BUILTIN_CVTNEPS2HI16_V16SF_MASK, UNKNOWN, (int) V16HI_FTYPE_V16SF_V16HI_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v16sf_maskz, "__builtin_ia32_cvtneps2bf16_v16sf_maskz", IX86_BUILTIN_CVTNE2PS2HI16_V16SF_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16SF_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v8sf, "__builtin_ia32_cvtneps2bf16_v8sf", IX86_BUILTIN_CVTNEPS2HI16_V8SF, UNKNOWN, (int) V8HI_FTYPE_V8SF) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v8sf_mask, "__builtin_ia32_cvtneps2bf16_v8sf_mask", IX86_BUILTIN_CVTNEPS2HI16_V8SF_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_V8HI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v8sf_maskz, "__builtin_ia32_cvtneps2bf16_v8sf_maskz", IX86_BUILTIN_CVTNE2PS2HI16_V8SF_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8SF_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v4sf, "__builtin_ia32_cvtneps2bf16_v4sf", IX86_BUILTIN_CVTNEPS2HI16_V4SF, UNKNOWN, (int) V8HI_FTYPE_V4SF) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v4sf_mask, "__builtin_ia32_cvtneps2bf16_v4sf_mask", IX86_BUILTIN_CVTNEPS2HI16_V4SF_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_V8HI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_cvtneps2bf16_v4sf_maskz, "__builtin_ia32_cvtneps2bf16_v4sf_maskz", IX86_BUILTIN_CVTNE2PS2HI16_V4SF_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V4SF_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v16sf, "__builtin_ia32_dpbf16ps_v16sf", IX86_BUILTIN_DPHI16PS_V16SF, UNKNOWN, (int) V16SF_FTYPE_V16SF_V32HI_V32HI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v16sf_mask, "__builtin_ia32_dpbf16ps_v16sf_mask", IX86_BUILTIN_DPHI16PS_V16SF_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V32HI_V32HI_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v16sf_maskz, "__builtin_ia32_dpbf16ps_v16sf_maskz", IX86_BUILTIN_DPHI16PS_V16SF_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V32HI_V32HI_UHI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v8sf, "__builtin_ia32_dpbf16ps_v8sf", IX86_BUILTIN_DPHI16PS_V8SF, UNKNOWN, (int) V8SF_FTYPE_V8SF_V16HI_V16HI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v8sf_mask, "__builtin_ia32_dpbf16ps_v8sf_mask", IX86_BUILTIN_DPHI16PS_V8SF_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V16HI_V16HI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v8sf_maskz, "__builtin_ia32_dpbf16ps_v8sf_maskz", IX86_BUILTIN_DPHI16PS_V8SF_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V16HI_V16HI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v4sf, "__builtin_ia32_dpbf16ps_v4sf", IX86_BUILTIN_DPHI16PS_V4SF, UNKNOWN, (int) V4SF_FTYPE_V4SF_V8HI_V8HI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v4sf_mask, "__builtin_ia32_dpbf16ps_v4sf_mask", IX86_BUILTIN_DPHI16PS_V4SF_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V8HI_V8HI_UQI) +BDESC (0, OPTION_MASK_ISA2_AVX512BF16, CODE_FOR_avx512f_dpbf16ps_v4sf_maskz, "__builtin_ia32_dpbf16ps_v4sf_maskz", IX86_BUILTIN_DPHI16PS_V4SF_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V8HI_V8HI_UQI) /* Builtins with rounding support. */ BDESC_END (ARGS, ROUND_ARGS) diff --git a/gcc/config/i386/i386-builtins.c b/gcc/config/i386/i386-builtins.c index 0764aa48ab1..4646d044086 100644 --- a/gcc/config/i386/i386-builtins.c +++ b/gcc/config/i386/i386-builtins.c @@ -1169,25 +1169,25 @@ ix86_init_mmx_sse_builtins (void) VOID_FTYPE_PCVOID, IX86_BUILTIN_CLWB); /* MONITORX and MWAITX. */ - def_builtin (0, OPTION_MASK_ISA_MWAITX, "__builtin_ia32_monitorx", + def_builtin (0, OPTION_MASK_ISA2_MWAITX, "__builtin_ia32_monitorx", VOID_FTYPE_PCVOID_UNSIGNED_UNSIGNED, IX86_BUILTIN_MONITORX); - def_builtin (0, OPTION_MASK_ISA_MWAITX, "__builtin_ia32_mwaitx", + def_builtin (0, OPTION_MASK_ISA2_MWAITX, "__builtin_ia32_mwaitx", VOID_FTYPE_UNSIGNED_UNSIGNED_UNSIGNED, IX86_BUILTIN_MWAITX); /* CLZERO. */ - def_builtin (0, OPTION_MASK_ISA_CLZERO, "__builtin_ia32_clzero", + def_builtin (0, OPTION_MASK_ISA2_CLZERO, "__builtin_ia32_clzero", VOID_FTYPE_PCVOID, IX86_BUILTIN_CLZERO); /* WAITPKG. */ - def_builtin (0, OPTION_MASK_ISA_WAITPKG, "__builtin_ia32_umonitor", + def_builtin (0, OPTION_MASK_ISA2_WAITPKG, "__builtin_ia32_umonitor", VOID_FTYPE_PVOID, IX86_BUILTIN_UMONITOR); - def_builtin (0, OPTION_MASK_ISA_WAITPKG, "__builtin_ia32_umwait", + def_builtin (0, OPTION_MASK_ISA2_WAITPKG, "__builtin_ia32_umwait", UINT8_FTYPE_UNSIGNED_UINT64, IX86_BUILTIN_UMWAIT); - def_builtin (0, OPTION_MASK_ISA_WAITPKG, "__builtin_ia32_tpause", + def_builtin (0, OPTION_MASK_ISA2_WAITPKG, "__builtin_ia32_tpause", UINT8_FTYPE_UNSIGNED_UINT64, IX86_BUILTIN_TPAUSE); /* CLDEMOTE. */ - def_builtin (0, OPTION_MASK_ISA_CLDEMOTE, "__builtin_ia32_cldemote", + def_builtin (0, OPTION_MASK_ISA2_CLDEMOTE, "__builtin_ia32_cldemote", VOID_FTYPE_PCVOID, IX86_BUILTIN_CLDEMOTE); /* Add FMA4 multi-arg argument instructions */ diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 3f054ca8faa..35590ec2992 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -415,9 +415,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, ; } - if (isa_flag2 & OPTION_MASK_ISA_WBNOINVD) + if (isa_flag2 & OPTION_MASK_ISA2_WBNOINVD) def_or_undef (parse_in, "__WBNOINVD__"); - if (isa_flag2 & OPTION_MASK_ISA_AVX512VP2INTERSECT) + if (isa_flag2 & OPTION_MASK_ISA2_AVX512VP2INTERSECT) def_or_undef (parse_in, "__AVX512VP2INTERSECT__"); if (isa_flag & OPTION_MASK_ISA_MMX) def_or_undef (parse_in, "__MMX__"); @@ -465,17 +465,17 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__AVX512VBMI__"); if (isa_flag & OPTION_MASK_ISA_AVX512IFMA) def_or_undef (parse_in, "__AVX512IFMA__"); - if (isa_flag2 & OPTION_MASK_ISA_AVX5124VNNIW) + if (isa_flag2 & OPTION_MASK_ISA2_AVX5124VNNIW) def_or_undef (parse_in, "__AVX5124VNNIW__"); if (isa_flag & OPTION_MASK_ISA_AVX512VBMI2) def_or_undef (parse_in, "__AVX512VBMI2__"); if (isa_flag & OPTION_MASK_ISA_AVX512VNNI) def_or_undef (parse_in, "__AVX512VNNI__"); - if (isa_flag2 & OPTION_MASK_ISA_PCONFIG) + if (isa_flag2 & OPTION_MASK_ISA2_PCONFIG) def_or_undef (parse_in, "__PCONFIG__"); - if (isa_flag2 & OPTION_MASK_ISA_SGX) + if (isa_flag2 & OPTION_MASK_ISA2_SGX) def_or_undef (parse_in, "__SGX__"); - if (isa_flag2 & OPTION_MASK_ISA_AVX5124FMAPS) + if (isa_flag2 & OPTION_MASK_ISA2_AVX5124FMAPS) def_or_undef (parse_in, "__AVX5124FMAPS__"); if (isa_flag & OPTION_MASK_ISA_AVX512BITALG) def_or_undef (parse_in, "__AVX512BITALG__"); @@ -531,7 +531,7 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__SSE2_MATH__"); if (isa_flag & OPTION_MASK_ISA_CLFLUSHOPT) def_or_undef (parse_in, "__CLFLUSHOPT__"); - if (isa_flag2 & OPTION_MASK_ISA_CLZERO) + if (isa_flag2 & OPTION_MASK_ISA2_CLZERO) def_or_undef (parse_in, "__CLZERO__"); if (isa_flag & OPTION_MASK_ISA_XSAVEC) def_or_undef (parse_in, "__XSAVEC__"); @@ -539,35 +539,35 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__XSAVES__"); if (isa_flag & OPTION_MASK_ISA_CLWB) def_or_undef (parse_in, "__CLWB__"); - if (isa_flag2 & OPTION_MASK_ISA_MWAITX) + if (isa_flag2 & OPTION_MASK_ISA2_MWAITX) def_or_undef (parse_in, "__MWAITX__"); if (isa_flag & OPTION_MASK_ISA_PKU) def_or_undef (parse_in, "__PKU__"); - if (isa_flag2 & OPTION_MASK_ISA_RDPID) + if (isa_flag2 & OPTION_MASK_ISA2_RDPID) def_or_undef (parse_in, "__RDPID__"); if (isa_flag & OPTION_MASK_ISA_GFNI) def_or_undef (parse_in, "__GFNI__"); if ((isa_flag & OPTION_MASK_ISA_SHSTK)) def_or_undef (parse_in, "__SHSTK__"); - if (isa_flag2 & OPTION_MASK_ISA_VAES) + if (isa_flag2 & OPTION_MASK_ISA2_VAES) def_or_undef (parse_in, "__VAES__"); if (isa_flag & OPTION_MASK_ISA_VPCLMULQDQ) def_or_undef (parse_in, "__VPCLMULQDQ__"); if (isa_flag & OPTION_MASK_ISA_MOVDIRI) def_or_undef (parse_in, "__MOVDIRI__"); - if (isa_flag2 & OPTION_MASK_ISA_MOVDIR64B) + if (isa_flag2 & OPTION_MASK_ISA2_MOVDIR64B) def_or_undef (parse_in, "__MOVDIR64B__"); - if (isa_flag2 & OPTION_MASK_ISA_WAITPKG) + if (isa_flag2 & OPTION_MASK_ISA2_WAITPKG) def_or_undef (parse_in, "__WAITPKG__"); - if (isa_flag2 & OPTION_MASK_ISA_CLDEMOTE) + if (isa_flag2 & OPTION_MASK_ISA2_CLDEMOTE) def_or_undef (parse_in, "__CLDEMOTE__"); - if (isa_flag2 & OPTION_MASK_ISA_PTWRITE) + if (isa_flag2 & OPTION_MASK_ISA2_PTWRITE) def_or_undef (parse_in, "__PTWRITE__"); - if (isa_flag2 & OPTION_MASK_ISA_AVX512BF16) + if (isa_flag2 & OPTION_MASK_ISA2_AVX512BF16) def_or_undef (parse_in, "__AVX512BF16__"); if (TARGET_MMX_WITH_SSE) def_or_undef (parse_in, "__MMX_WITH_SSE__"); - if (isa_flag2 & OPTION_MASK_ISA_ENQCMD) + if (isa_flag2 & OPTION_MASK_ISA2_ENQCMD) def_or_undef (parse_in, "__ENQCMD__"); if (TARGET_IAMCU) { diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c index 79ccc3292b4..be33821174b 100644 --- a/gcc/config/i386/i386-options.c +++ b/gcc/config/i386/i386-options.c @@ -187,25 +187,25 @@ struct ix86_target_opts ISAs come first. Target string will be displayed in the same order. */ static struct ix86_target_opts isa2_opts[] = { - { "-mcx16", OPTION_MASK_ISA_CX16 }, - { "-mvaes", OPTION_MASK_ISA_VAES }, - { "-mrdpid", OPTION_MASK_ISA_RDPID }, - { "-mpconfig", OPTION_MASK_ISA_PCONFIG }, - { "-mwbnoinvd", OPTION_MASK_ISA_WBNOINVD }, - { "-mavx512vp2intersect", OPTION_MASK_ISA_AVX512VP2INTERSECT }, - { "-msgx", OPTION_MASK_ISA_SGX }, - { "-mavx5124vnniw", OPTION_MASK_ISA_AVX5124VNNIW }, - { "-mavx5124fmaps", OPTION_MASK_ISA_AVX5124FMAPS }, - { "-mhle", OPTION_MASK_ISA_HLE }, - { "-mmovbe", OPTION_MASK_ISA_MOVBE }, - { "-mclzero", OPTION_MASK_ISA_CLZERO }, - { "-mmwaitx", OPTION_MASK_ISA_MWAITX }, - { "-mmovdir64b", OPTION_MASK_ISA_MOVDIR64B }, - { "-mwaitpkg", OPTION_MASK_ISA_WAITPKG }, - { "-mcldemote", OPTION_MASK_ISA_CLDEMOTE }, - { "-mptwrite", OPTION_MASK_ISA_PTWRITE }, - { "-mavx512bf16", OPTION_MASK_ISA_AVX512BF16 }, - { "-menqcmd", OPTION_MASK_ISA_ENQCMD } + { "-mcx16", OPTION_MASK_ISA2_CX16 }, + { "-mvaes", OPTION_MASK_ISA2_VAES }, + { "-mrdpid", OPTION_MASK_ISA2_RDPID }, + { "-mpconfig", OPTION_MASK_ISA2_PCONFIG }, + { "-mwbnoinvd", OPTION_MASK_ISA2_WBNOINVD }, + { "-mavx512vp2intersect", OPTION_MASK_ISA2_AVX512VP2INTERSECT }, + { "-msgx", OPTION_MASK_ISA2_SGX }, + { "-mavx5124vnniw", OPTION_MASK_ISA2_AVX5124VNNIW }, + { "-mavx5124fmaps", OPTION_MASK_ISA2_AVX5124FMAPS }, + { "-mhle", OPTION_MASK_ISA2_HLE }, + { "-mmovbe", OPTION_MASK_ISA2_MOVBE }, + { "-mclzero", OPTION_MASK_ISA2_CLZERO }, + { "-mmwaitx", OPTION_MASK_ISA2_MWAITX }, + { "-mmovdir64b", OPTION_MASK_ISA2_MOVDIR64B }, + { "-mwaitpkg", OPTION_MASK_ISA2_WAITPKG }, + { "-mcldemote", OPTION_MASK_ISA2_CLDEMOTE }, + { "-mptwrite", OPTION_MASK_ISA2_PTWRITE }, + { "-mavx512bf16", OPTION_MASK_ISA2_AVX512BF16 }, + { "-menqcmd", OPTION_MASK_ISA2_ENQCMD } }; static struct ix86_target_opts isa_opts[] = { @@ -2030,8 +2030,8 @@ ix86_option_override_internal (bool main_args_p, && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI2)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2; if (((processor_alias_table[i].flags & PTA_CX16) != 0) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_CX16)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16; + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_CX16)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16; if (((processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)) != 0) && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT; @@ -2040,8 +2040,8 @@ ix86_option_override_internal (bool main_args_p, && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF; if (((processor_alias_table[i].flags & PTA_MOVBE) != 0) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MOVBE)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE; + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_MOVBE)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE; if (((processor_alias_table[i].flags & PTA_AES) != 0) && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES)) ix86_isa_flags |= OPTION_MASK_ISA_AES; @@ -2064,8 +2064,8 @@ ix86_option_override_internal (bool main_args_p, && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RTM)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM; if (((processor_alias_table[i].flags & PTA_HLE) != 0) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_HLE)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_HLE; + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_HLE)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_HLE; if (((processor_alias_table[i].flags & PTA_PRFCHW) != 0) && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PRFCHW)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW; @@ -2106,8 +2106,8 @@ ix86_option_override_internal (bool main_args_p, && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLFLUSHOPT)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT; if (((processor_alias_table[i].flags & PTA_CLZERO) != 0) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_CLZERO)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO; + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_CLZERO)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO; if (((processor_alias_table[i].flags & PTA_XSAVEC) != 0) && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVEC)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC; @@ -2149,55 +2149,55 @@ ix86_option_override_internal (bool main_args_p, if (((processor_alias_table[i].flags & PTA_AVX512VP2INTERSECT) != 0) && !(opts->x_ix86_isa_flags2_explicit - & OPTION_MASK_ISA_AVX512VP2INTERSECT)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512VP2INTERSECT; + & OPTION_MASK_ISA2_AVX512VP2INTERSECT)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT; if (((processor_alias_table[i].flags & PTA_AVX5124VNNIW) != 0) && !(opts->x_ix86_isa_flags2_explicit - & OPTION_MASK_ISA_AVX5124VNNIW)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW; + & OPTION_MASK_ISA2_AVX5124VNNIW)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124VNNIW; if (((processor_alias_table[i].flags & PTA_AVX5124FMAPS) != 0) && !(opts->x_ix86_isa_flags2_explicit - & OPTION_MASK_ISA_AVX5124FMAPS)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS; + & OPTION_MASK_ISA2_AVX5124FMAPS)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124FMAPS; if (((processor_alias_table[i].flags & PTA_AVX512VPOPCNTDQ) != 0) && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VPOPCNTDQ)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ; if (((processor_alias_table[i].flags & PTA_AVX512BF16) != 0) && !(opts->x_ix86_isa_flags2_explicit - & OPTION_MASK_ISA_AVX512BF16)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512BF16; + & OPTION_MASK_ISA2_AVX512BF16)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16; if (((processor_alias_table[i].flags & PTA_MOVDIRI) != 0) && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVDIRI)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI; if (((processor_alias_table[i].flags & PTA_MOVDIR64B) != 0) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MOVDIR64B)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVDIR64B; + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_MOVDIR64B)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B; if (((processor_alias_table[i].flags & PTA_SGX) != 0) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX; + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_SGX)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX; if (((processor_alias_table[i].flags & PTA_VAES) != 0) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_VAES)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES; + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_VAES)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES; if (((processor_alias_table[i].flags & PTA_RDPID) != 0) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID; + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_RDPID)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID; if (((processor_alias_table[i].flags & PTA_PCONFIG) != 0) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_PCONFIG)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG; + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_PCONFIG)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG; if (((processor_alias_table[i].flags & PTA_WBNOINVD) != 0) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_WBNOINVD)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD; + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_WBNOINVD)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD; if (((processor_alias_table[i].flags & PTA_PTWRITE) != 0) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_PTWRITE)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PTWRITE; + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_PTWRITE)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE; if ((processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)) != 0) x86_prefetch_sse = true; if (((processor_alias_table[i].flags & PTA_MWAITX) != 0) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MWAITX)) - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX; + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_MWAITX)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX; if (((processor_alias_table[i].flags & PTA_PKU) != 0) && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PKU)) opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 108456b14d4..2542cb31783 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -81,10 +81,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_AVX512VBMI_P(x) TARGET_ISA_AVX512VBMI_P(x) #define TARGET_AVX512IFMA TARGET_ISA_AVX512IFMA #define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x) -#define TARGET_AVX5124FMAPS TARGET_ISA_AVX5124FMAPS -#define TARGET_AVX5124FMAPS_P(x) TARGET_ISA_AVX5124FMAPS_P(x) -#define TARGET_AVX5124VNNIW TARGET_ISA_AVX5124VNNIW -#define TARGET_AVX5124VNNIW_P(x) TARGET_ISA_AVX5124VNNIW_P(x) +#define TARGET_AVX5124FMAPS TARGET_ISA2_AVX5124FMAPS +#define TARGET_AVX5124FMAPS_P(x) TARGET_ISA2_AVX5124FMAPS_P(x) +#define TARGET_AVX5124VNNIW TARGET_ISA2_AVX5124VNNIW +#define TARGET_AVX5124VNNIW_P(x) TARGET_ISA2_AVX5124VNNIW_P(x) #define TARGET_AVX512VBMI2 TARGET_ISA_AVX512VBMI2 #define TARGET_AVX512VBMI2_P(x) TARGET_ISA_AVX512VBMI2_P(x) #define TARGET_AVX512VPOPCNTDQ TARGET_ISA_AVX512VPOPCNTDQ @@ -93,8 +93,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_AVX512VNNI_P(x) TARGET_ISA_AVX512VNNI_P(x) #define TARGET_AVX512BITALG TARGET_ISA_AVX512BITALG #define TARGET_AVX512BITALG_P(x) TARGET_ISA_AVX512BITALG_P(x) -#define TARGET_AVX512VP2INTERSECT TARGET_ISA_AVX512VP2INTERSECT -#define TARGET_AVX512VP2INTERSECT_P(x) TARGET_ISA_AVX512VP2INTERSECT_P(x) +#define TARGET_AVX512VP2INTERSECT TARGET_ISA2_AVX512VP2INTERSECT +#define TARGET_AVX512VP2INTERSECT_P(x) TARGET_ISA2_AVX512VP2INTERSECT_P(x) #define TARGET_FMA TARGET_ISA_FMA #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) #define TARGET_SSE4A TARGET_ISA_SSE4A @@ -107,18 +107,18 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x) #define TARGET_ABM TARGET_ISA_ABM #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) -#define TARGET_PCONFIG TARGET_ISA_PCONFIG -#define TARGET_PCONFIG_P(x) TARGET_ISA_PCONFIG_P(x) -#define TARGET_WBNOINVD TARGET_ISA_WBNOINVD -#define TARGET_WBNOINVD_P(x) TARGET_ISA_WBNOINVD_P(x) -#define TARGET_SGX TARGET_ISA_SGX -#define TARGET_SGX_P(x) TARGET_ISA_SGX_P(x) -#define TARGET_RDPID TARGET_ISA_RDPID -#define TARGET_RDPID_P(x) TARGET_ISA_RDPID_P(x) +#define TARGET_PCONFIG TARGET_ISA2_PCONFIG +#define TARGET_PCONFIG_P(x) TARGET_ISA2_PCONFIG_P(x) +#define TARGET_WBNOINVD TARGET_ISA2_WBNOINVD +#define TARGET_WBNOINVD_P(x) TARGET_ISA2_WBNOINVD_P(x) +#define TARGET_SGX TARGET_ISA2_SGX +#define TARGET_SGX_P(x) TARGET_ISA2_SGX_P(x) +#define TARGET_RDPID TARGET_ISA2_RDPID +#define TARGET_RDPID_P(x) TARGET_ISA2_RDPID_P(x) #define TARGET_GFNI TARGET_ISA_GFNI #define TARGET_GFNI_P(x) TARGET_ISA_GFNI_P(x) -#define TARGET_VAES TARGET_ISA_VAES -#define TARGET_VAES_P(x) TARGET_ISA_VAES_P(x) +#define TARGET_VAES TARGET_ISA2_VAES +#define TARGET_VAES_P(x) TARGET_ISA2_VAES_P(x) #define TARGET_VPCLMULQDQ TARGET_ISA_VPCLMULQDQ #define TARGET_VPCLMULQDQ_P(x) TARGET_ISA_VPCLMULQDQ_P(x) #define TARGET_BMI TARGET_ISA_BMI @@ -133,8 +133,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x) #define TARGET_SAHF TARGET_ISA_SAHF #define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x) -#define TARGET_MOVBE TARGET_ISA_MOVBE -#define TARGET_MOVBE_P(x) TARGET_ISA_MOVBE_P(x) +#define TARGET_MOVBE TARGET_ISA2_MOVBE +#define TARGET_MOVBE_P(x) TARGET_ISA2_MOVBE_P(x) #define TARGET_CRC32 TARGET_ISA_CRC32 #define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x) #define TARGET_AES TARGET_ISA_AES @@ -143,16 +143,16 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x) #define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT #define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x) -#define TARGET_CLZERO TARGET_ISA_CLZERO -#define TARGET_CLZERO_P(x) TARGET_ISA_CLZERO_P(x) +#define TARGET_CLZERO TARGET_ISA2_CLZERO +#define TARGET_CLZERO_P(x) TARGET_ISA2_CLZERO_P(x) #define TARGET_XSAVEC TARGET_ISA_XSAVEC #define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x) #define TARGET_XSAVES TARGET_ISA_XSAVES #define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x) #define TARGET_PCLMUL TARGET_ISA_PCLMUL #define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x) -#define TARGET_CMPXCHG16B TARGET_ISA_CX16 -#define TARGET_CMPXCHG16B_P(x) TARGET_ISA_CX16_P(x) +#define TARGET_CMPXCHG16B TARGET_ISA2_CX16 +#define TARGET_CMPXCHG16B_P(x) TARGET_ISA2_CX16_P(x) #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE #define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x) #define TARGET_RDRND TARGET_ISA_RDRND @@ -161,8 +161,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x) #define TARGET_RTM TARGET_ISA_RTM #define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x) -#define TARGET_HLE TARGET_ISA_HLE -#define TARGET_HLE_P(x) TARGET_ISA_HLE_P(x) +#define TARGET_HLE TARGET_ISA2_HLE +#define TARGET_HLE_P(x) TARGET_ISA2_HLE_P(x) #define TARGET_RDSEED TARGET_ISA_RDSEED #define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x) #define TARGET_PRFCHW TARGET_ISA_PRFCHW @@ -179,26 +179,26 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) #define TARGET_CLWB TARGET_ISA_CLWB #define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) -#define TARGET_MWAITX TARGET_ISA_MWAITX -#define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x) +#define TARGET_MWAITX TARGET_ISA2_MWAITX +#define TARGET_MWAITX_P(x) TARGET_ISA2_MWAITX_P(x) #define TARGET_PKU TARGET_ISA_PKU #define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x) #define TARGET_SHSTK TARGET_ISA_SHSTK #define TARGET_SHSTK_P(x) TARGET_ISA_SHSTK_P(x) #define TARGET_MOVDIRI TARGET_ISA_MOVDIRI #define TARGET_MOVDIRI_P(x) TARGET_ISA_MOVDIRI_P(x) -#define TARGET_MOVDIR64B TARGET_ISA_MOVDIR64B -#define TARGET_MOVDIR64B_P(x) TARGET_ISA_MOVDIR64B_P(x) -#define TARGET_WAITPKG TARGET_ISA_WAITPKG -#define TARGET_WAITPKG_P(x) TARGET_ISA_WAITPKG_P(x) -#define TARGET_CLDEMOTE TARGET_ISA_CLDEMOTE -#define TARGET_CLDEMOTE_P(x) TARGET_ISA_CLDEMOTE_P(x) -#define TARGET_PTWRITE TARGET_ISA_PTWRITE -#define TARGET_PTWRITE_P(x) TARGET_ISA_PTWRITE_P(x) -#define TARGET_AVX512BF16 TARGET_ISA_AVX512BF16 -#define TARGET_AVX512BF16_P(x) TARGET_ISA_AVX512BF16_P(x) -#define TARGET_ENQCMD TARGET_ISA_ENQCMD -#define TARGET_ENQCMD_P(x) TARGET_ISA_ENQCMD_P(x) +#define TARGET_MOVDIR64B TARGET_ISA2_MOVDIR64B +#define TARGET_MOVDIR64B_P(x) TARGET_ISA2_MOVDIR64B_P(x) +#define TARGET_WAITPKG TARGET_ISA2_WAITPKG +#define TARGET_WAITPKG_P(x) TARGET_ISA2_WAITPKG_P(x) +#define TARGET_CLDEMOTE TARGET_ISA2_CLDEMOTE +#define TARGET_CLDEMOTE_P(x) TARGET_ISA2_CLDEMOTE_P(x) +#define TARGET_PTWRITE TARGET_ISA2_PTWRITE +#define TARGET_PTWRITE_P(x) TARGET_ISA2_PTWRITE_P(x) +#define TARGET_AVX512BF16 TARGET_ISA2_AVX512BF16 +#define TARGET_AVX512BF16_P(x) TARGET_ISA2_AVX512BF16_P(x) +#define TARGET_ENQCMD TARGET_ISA2_ENQCMD +#define TARGET_ENQCMD_P(x) TARGET_ISA2_ENQCMD_P(x) #define TARGET_LP64 TARGET_ABI_64 #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 0483bb5ef94..c47b639b319 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -725,11 +725,11 @@ Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation. mavx5124fmaps -Target Report Mask(ISA_AVX5124FMAPS) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_AVX5124FMAPS) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation. mavx5124vnniw -Target Report Mask(ISA_AVX5124VNNIW) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_AVX5124VNNIW) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation. mavx512vpopcntdq @@ -749,7 +749,7 @@ Target Report Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BITALG built-in functions and code generation. mavx512vp2intersect -Target Report Mask(ISA_AVX512VP2INTERSECT) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_AVX512VP2INTERSECT) Var(ix86_isa_flags2) Save Support AVX512VP2INTERSECT built-in functions and code generation. mfma @@ -781,23 +781,23 @@ Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save Support code generation of popcnt instruction. mpconfig -Target Report Mask(ISA_PCONFIG) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_PCONFIG) Var(ix86_isa_flags2) Save Support PCONFIG built-in functions and code generation. mwbnoinvd -Target Report Mask(ISA_WBNOINVD) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_WBNOINVD) Var(ix86_isa_flags2) Save Support WBNOINVD built-in functions and code generation. mptwrite -Target Report Mask(ISA_PTWRITE) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_PTWRITE) Var(ix86_isa_flags2) Save Support PTWRITE built-in functions and code generation. msgx -Target Report Mask(ISA_SGX) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_SGX) Var(ix86_isa_flags2) Save Support SGX built-in functions and code generation. mrdpid -Target Report Mask(ISA_RDPID) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_RDPID) Var(ix86_isa_flags2) Save Support RDPID built-in functions and code generation. mgfni @@ -805,7 +805,7 @@ Target Report Mask(ISA_GFNI) Var(ix86_isa_flags) Save Support GFNI built-in functions and code generation. mvaes -Target Report Mask(ISA_VAES) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_VAES) Var(ix86_isa_flags2) Save Support VAES built-in functions and code generation. mvpclmulqdq @@ -825,7 +825,7 @@ Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save Support LZCNT built-in function and code generation. mhle -Target Report Mask(ISA_HLE) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_HLE) Var(ix86_isa_flags2) Save Support Hardware Lock Elision prefixes. mrdseed @@ -876,7 +876,7 @@ Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save Support TBM built-in functions and code generation. mcx16 -Target Report Mask(ISA_CX16) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_CX16) Var(ix86_isa_flags2) Save Support code generation of cmpxchg16b instruction. msahf @@ -884,7 +884,7 @@ Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save Support code generation of sahf instruction in 64bit x86-64 code. mmovbe -Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_MOVBE) Var(ix86_isa_flags2) Save Support code generation of movbe instruction. mcrc32 @@ -969,11 +969,11 @@ Target WarnRemoved Removed in GCC 9. This switch has no effect. mmwaitx -Target Report Mask(ISA_MWAITX) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_MWAITX) Var(ix86_isa_flags2) Save Support MWAITX and MONITORX built-in functions and code generation. mclzero -Target Report Mask(ISA_CLZERO) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_CLZERO) Var(ix86_isa_flags2) Save Support CLZERO built-in functions and code generation. mpku @@ -1071,15 +1071,15 @@ Target Report Mask(ISA_MOVDIRI) Var(ix86_isa_flags) Save Support MOVDIRI built-in functions and code generation. mmovdir64b -Target Report Mask(ISA_MOVDIR64B) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_MOVDIR64B) Var(ix86_isa_flags2) Save Support MOVDIR64B built-in functions and code generation. mwaitpkg -Target Report Mask(ISA_WAITPKG) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_WAITPKG) Var(ix86_isa_flags2) Save Support WAITPKG built-in functions and code generation. mcldemote -Target Report Mask(ISA_CLDEMOTE) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_CLDEMOTE) Var(ix86_isa_flags2) Save Support CLDEMOTE built-in functions and code generation. minstrument-return= @@ -1104,10 +1104,10 @@ Target Report Var(ix86_flag_record_return) Init(0) Generate a __return_loc section pointing to all return instrumentation code. mavx512bf16 -Target Report Mask(ISA_AVX512BF16) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_AVX512BF16) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BF16 built-in functions and code generation. menqcmd -Target Report Mask(ISA_ENQCMD) Var(ix86_isa_flags2) Save +Target Report Mask(ISA2_ENQCMD) Var(ix86_isa_flags2) Save Support ENQCMD built-in functions and code generation. |