diff options
| -rw-r--r-- | gcc/ChangeLog | 15 | ||||
| -rw-r--r-- | gcc/config/mips/mips.h | 4 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 23 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 3 |
4 files changed, 41 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 49139aaf906..1d7a0d58c12 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2005-06-15 David Ung <davidu@mips.com> + + * config/mips/mips.h (GENERATE_MIPS16E): New definition. + * config/mips/mips.md (zero_extend<SHORT:mode><GPR:mode>2): + Changed expand condition to exclude generating of "and" if + GENERATE_MIPS16E is true. + (*zero_extend<SHORT:mode><GPR:mode>2_mips16e): New pattern for + matching mips16e zeb/zeh. + (*extend<SHORT:mode><GPR:mode>2_mips16e): New pattern for matching + mips16e seb/seh. + (*extend<SHORT:mode><GPR:mode>2): Disable this pattern for + GENERATE_MIPS16E. + * doc/invoke.texi (MIPS Options): Add comment to -mips16 + indicating MIPS16e ASE is used if targetting for MIPS32 or MIPS64. + 2005-06-15 Diego Novillo <dnovillo@redhat.com> PR 22018 diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 6c9d343b530..6eb4f4aabdd 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -168,8 +168,10 @@ extern const struct mips_rtx_cost_data *mips_cost; We therefore disable GP-relative switch tables for n64 on IRIX targets. */ #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX)) - /* Generate mips16 code */ +/* Generate mips16 code */ #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) +/* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */ +#define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32) /* Generic ISA defines. */ #define ISA_MIPS1 (mips_isa == 1) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index e8a6b2a8576..84f0767d395 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -2319,7 +2319,8 @@ beq\t%2,%.,1b\;\ (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))] "" { - if (TARGET_MIPS16 && !memory_operand (operands[1], <SHORT:MODE>mode)) + if (TARGET_MIPS16 && !GENERATE_MIPS16E + && !memory_operand (operands[1], <SHORT:MODE>mode)) { emit_insn (gen_and<GPR:mode>3 (operands[0], gen_lowpart (<GPR:MODE>mode, operands[1]), @@ -2340,6 +2341,14 @@ beq\t%2,%.,1b\;\ [(set_attr "type" "arith,load") (set_attr "mode" "<GPR:MODE>")]) +(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e" + [(set (match_operand:GPR 0 "register_operand" "=d") + (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))] + "GENERATE_MIPS16E" + "ze<SHORT:size>\t%0" + [(set_attr "type" "arith") + (set_attr "mode" "<GPR:MODE>")]) + (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16" [(set (match_operand:GPR 0 "register_operand" "=d") (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))] @@ -2418,11 +2427,21 @@ beq\t%2,%.,1b\;\ (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))] "") +(define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e" + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))] + "GENERATE_MIPS16E" + "@ + se<SHORT:size>\t%0 + l<SHORT:size>\t%0,%1" + [(set_attr "type" "arith,load") + (set_attr "mode" "<GPR:MODE>")]) + (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2" [(set (match_operand:GPR 0 "register_operand" "=d,d") (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))] - "!ISA_HAS_SEB_SEH" + "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E" "@ # l<SHORT:size>\t%0,%1" diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 76318943153..47f7766cf32 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -9861,7 +9861,8 @@ Equivalent to @samp{-march=mips64}. @itemx -mno-mips16 @opindex mips16 @opindex mno-mips16 -Use (do not use) the MIPS16 ISA@. +Generate (do not generate) MIPS16 code. If GCC is targetting a +MIP32 or MIPS64 architecture, it will make use of the MIPS16e ASE@. @item -mabi=32 @itemx -mabi=o64 |