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-rw-r--r--gcc/ChangeLog22
-rw-r--r--gcc/config/rs6000/constraints.md7
-rw-r--r--gcc/config/rs6000/dfp.md21
-rw-r--r--gcc/config/rs6000/predicates.md6
-rw-r--r--gcc/config/rs6000/rs6000.c4
-rw-r--r--gcc/config/rs6000/rs6000.h26
-rw-r--r--gcc/config/rs6000/rs6000.md74
7 files changed, 80 insertions, 80 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 04e42f8a123..13f1da70ab4 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,25 @@
+2012-07-27 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * config/rs6000/constraints.md: Delete "q" constraint.
+ * config/rs6000/dfp.md (movsd_hardfloat, movsd_softfloat):
+ Delete the "q" alternative.
+ * config/rs6000/predicates.md (gpc_reg_operand): Adjust.
+ * config/rs6000/rs6000.c (rs6000_debug_reg_global,
+ rs6000_init_hard_regno_mode_ok, rs6000_dbx_register_number):
+ Adjust to MQ_REGNO removal.
+ * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Adjust
+ comment.
+ (REG_ALLOC_ORDER): Adjust comment. Remove MQ from alloc order.
+ (enum reg_class): Adjust comment. Delete MQ_REGS.
+ (REG_CLASS_CONTENTS): Adjust.
+ (REGISTER_NAMES, ADDITIONAL_REGISTER_NAMES): Adjust comment.
+ * config/rs6000/rs6000.md: Delete MQ_REGNO.
+ (movsi_internal1, movsi_internal1_single, movhi_internal,
+ movqi_internal, movcc_internal1, movsf_hardfloat,
+ movsf_softfloat): Delete the "q" alternative.
+ (ctr<mode>_internal1, ctr<mode>_internal2, ctr<mode>_internal5,
+ ctr<mode>_internal6): Delete "q" constraint.
+
2012-07-27 Richard Guenther <rguenther@suse.de>
* tree-into-ssa.c (def_blocks_p): New typedef.
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index e53320e0f5a..4a153d4c20e 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -1,5 +1,5 @@
;; Constraint definitions for RS6000
-;; Copyright (C) 2006, 2007, 2009, 2010 Free Software Foundation, Inc.
+;; Copyright (C) 2006-2012 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
@@ -17,7 +17,7 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-;; Available constraint letters: "e", "k", "u", "A", "B", "C", "D"
+;; Available constraint letters: "e", "k", "q", "u", "A", "B", "C", "D"
;; Register constraints
@@ -33,9 +33,6 @@
(define_register_constraint "h" "SPECIAL_REGS"
"@internal")
-(define_register_constraint "q" "MQ_REGS"
- "@internal")
-
(define_register_constraint "c" "CTR_REGS"
"@internal")
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index 4fc7310636f..d2fd12b2510 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -1,6 +1,5 @@
;; Decimal Floating Point (DFP) patterns.
-;; Copyright (C) 2007, 2008, 2010, 2011
-;; Free Software Foundation, Inc.
+;; Copyright (C) 2007-2012 Free Software Foundation, Inc.
;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner
;; (bergner@vnet.ibm.com).
@@ -62,8 +61,8 @@
}")
(define_insn "movsd_hardfloat"
- [(set (match_operand:SD 0 "nonimmediate_operand" "=r,r,m,f,*c*l,*q,!r,*h,!r,!r")
- (match_operand:SD 1 "input_operand" "r,m,r,f,r,r,h,0,G,Fn"))]
+ [(set (match_operand:SD 0 "nonimmediate_operand" "=r,r,m,f,*c*l,!r,*h,!r,!r")
+ (match_operand:SD 1 "input_operand" "r,m,r,f,r,h,0,G,Fn"))]
"(gpc_reg_operand (operands[0], SDmode)
|| gpc_reg_operand (operands[1], SDmode))
&& (TARGET_HARD_FLOAT && TARGET_FPRS)"
@@ -73,24 +72,22 @@
{st%U0%X0|stw%U0%X0} %1,%0
fmr %0,%1
mt%0 %1
- mt%0 %1
mf%1 %0
{cror 0,0,0|nop}
#
#"
- [(set_attr "type" "*,load,store,fp,mtjmpr,*,mfjmpr,*,*,*")
- (set_attr "length" "4,4,4,4,4,4,4,4,4,8")])
+ [(set_attr "type" "*,load,store,fp,mtjmpr,mfjmpr,*,*,*")
+ (set_attr "length" "4,4,4,4,4,4,4,4,8")])
(define_insn "movsd_softfloat"
- [(set (match_operand:SD 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
- (match_operand:SD 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
+ [(set (match_operand:SD 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,r,*h")
+ (match_operand:SD 1 "input_operand" "r,r,h,m,r,I,L,R,G,Fn,0"))]
"(gpc_reg_operand (operands[0], SDmode)
|| gpc_reg_operand (operands[1], SDmode))
&& (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
"@
mr %0,%1
mt%0 %1
- mt%0 %1
mf%1 %0
{l%U1%X1|lwz%U1%X1} %0,%1
{st%U0%X0|stw%U0%X0} %1,%0
@@ -100,8 +97,8 @@
#
#
{cror 0,0,0|nop}"
- [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
+ [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*,*")
+ (set_attr "length" "4,4,4,4,4,4,4,4,4,8,4")])
(define_insn "movsd_store"
[(set (match_operand:DD 0 "nonimmediate_operand" "=m")
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index f29d0918f58..e2c3e70d226 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1,6 +1,5 @@
;; Predicate definitions for POWER and PowerPC.
-;; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
-;; Free Software Foundation, Inc.
+;; Copyright (C) 2005-2012 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
@@ -128,7 +127,8 @@
(match_test "(GET_CODE (op) != REG
|| (REGNO (op) >= ARG_POINTER_REGNUM
&& !CA_REGNO_P (REGNO (op)))
- || REGNO (op) < MQ_REGNO)
+ || INT_REGNO_P (REGNO (op))
+ || FP_REGNO_P (REGNO (op)))
&& !((TARGET_E500_DOUBLE || TARGET_SPE)
&& invalid_e500_subreg (op, mode))")))
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1ed915543bf..ef7d46fe382 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1750,7 +1750,6 @@ rs6000_debug_reg_global (void)
rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
- rs6000_debug_reg_print (MQ_REGNO, MQ_REGNO, "mq");
rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
@@ -1973,7 +1972,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
rs6000_regno_regclass[r] = CR_REGS;
- rs6000_regno_regclass[MQ_REGNO] = MQ_REGS;
rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
rs6000_regno_regclass[CA_REGNO] = CA_REGS;
@@ -27167,8 +27165,6 @@ rs6000_dbx_register_number (unsigned int regno)
{
if (regno <= 63 || write_symbols != DWARF2_DEBUG)
return regno;
- if (regno == MQ_REGNO)
- return 100;
if (regno == LR_REGNO)
return 108;
if (regno == CTR_REGNO)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 612d202960f..ec62fc6ea65 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -772,9 +772,9 @@ extern unsigned rs6000_pointer_size;
even those that are not normally considered general registers.
RS/6000 has 32 fixed-point registers, 32 floating-point registers,
- an MQ register, a count register, a link register, and 8 condition
- register fields, which we view here as separate registers. AltiVec
- adds 32 vector registers and a VRsave register.
+ a count register, a link register, and 8 condition register fields,
+ which we view here as separate registers. AltiVec adds 32 vector
+ registers and a VRsave register.
In addition, the difference between the frame and argument pointers is
a function of the number of registers saved, so we need to have a
@@ -918,7 +918,6 @@ extern unsigned rs6000_pointer_size;
r0 (not saved; cannot be base reg)
r31 - r13 (saved; order given to save least number)
r12 (not saved; if used for DImode or DFmode would use r13)
- mq (not saved; best to use it if we can)
ctr (not saved; when we have the choice ctr is better)
lr (saved)
cr5, r1, r2, ap, ca (fixed)
@@ -960,7 +959,7 @@ extern unsigned rs6000_pointer_size;
3, EARLY_R12 11, 0, \
31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
18, 17, 16, 15, 14, 13, LATE_R12 \
- 64, 66, 65, \
+ 66, 65, \
73, 1, MAYBE_R2_FIXED 67, 76, \
/* AltiVec registers. */ \
77, 78, \
@@ -1158,7 +1157,7 @@ extern unsigned rs6000_pointer_size;
class that represents their union. */
/* The RS/6000 has three types of registers, fixed-point, floating-point, and
- condition registers, plus three special registers, MQ, CTR, and the link
+ condition registers, plus three special registers, CTR, and the link
register. AltiVec adds a vector register class. VSX registers overlap the
FPR registers and the Altivec registers.
@@ -1181,7 +1180,6 @@ enum reg_class
SPE_ACC_REGS,
SPEFSCR_REGS,
NON_SPECIAL_REGS,
- MQ_REGS,
LINK_REGS,
CTR_REGS,
LINK_OR_CTR_REGS,
@@ -1212,7 +1210,6 @@ enum reg_class
"SPE_ACC_REGS", \
"SPEFSCR_REGS", \
"NON_SPECIAL_REGS", \
- "MQ_REGS", \
"LINK_REGS", \
"CTR_REGS", \
"LINK_OR_CTR_REGS", \
@@ -1242,17 +1239,16 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
{ 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
- { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
{ 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
{ 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
{ 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
- { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
- { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
+ { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, /* SPECIAL_REGS */ \
+ { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
{ 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
{ 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
- { 0xffffffff, 0x00000000, 0x00000fff, 0x00020000 }, /* NON_FLOAT_REGS */ \
+ { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \
{ 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \
- { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
+ { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0003ffff } /* ALL_REGS */ \
}
/* The same information, inverted:
@@ -2104,7 +2100,7 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
&rs6000_reg_names[62][0], /* fr30 */ \
&rs6000_reg_names[63][0], /* fr31 */ \
\
- &rs6000_reg_names[64][0], /* mq */ \
+ &rs6000_reg_names[64][0], /* was mq */ \
&rs6000_reg_names[65][0], /* lr */ \
&rs6000_reg_names[66][0], /* ctr */ \
&rs6000_reg_names[67][0], /* ap */ \
@@ -2188,7 +2184,7 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
{"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
{"vrsave", 109}, {"vscr", 110}, \
{"spe_acc", 111}, {"spefscr", 112}, \
- /* no additional names for: mq, lr, ctr, ap */ \
+ /* no additional names for: lr, ctr, ap */ \
{"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
{"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
{"cc", 68}, {"sp", 1}, {"toc", 2}, \
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 166ec60f8ff..6ade53ca711 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -29,7 +29,6 @@
(TOC_REGNUM 2)
(STATIC_CHAIN_REGNUM 11)
(HARD_FRAME_POINTER_REGNUM 31)
- (MQ_REGNO 64)
(LR_REGNO 65)
(CTR_REGNO 66)
(ARG_POINTER_REGNUM 67)
@@ -8249,8 +8248,8 @@
(set_attr "length" "4")])
(define_insn "*movsi_internal1"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*q,*c*l,*h,*h")
- (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,r,0"))]
+ [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
+ (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
"!TARGET_SINGLE_FPU &&
(gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
"@
@@ -8264,14 +8263,13 @@
mf%1 %0
mt%0 %1
mt%0 %1
- mt%0 %1
{cror 0,0,0|nop}"
- [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,*,mtjmpr,*,*")
- (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")])
+ [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
+ (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
(define_insn "*movsi_internal1_single"
- [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*q,*c*l,*h,*h,m,*f")
- (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,r,0,f,m"))]
+ [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
+ (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
"TARGET_SINGLE_FPU &&
(gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
"@
@@ -8285,12 +8283,11 @@
mf%1 %0
mt%0 %1
mt%0 %1
- mt%0 %1
{cror 0,0,0|nop}
stfs%U0%X0 %1, %0
lfs%U1%X1 %0, %1"
- [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
- (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4")])
+ [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,*,*")
+ (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
;; Split a load of a large constant into the appropriate two-insn
;; sequence.
@@ -8340,8 +8337,8 @@
"")
(define_insn "*movhi_internal"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
- (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
+ (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
"gpc_reg_operand (operands[0], HImode)
|| gpc_reg_operand (operands[1], HImode)"
"@
@@ -8351,9 +8348,8 @@
{lil|li} %0,%w1
mf%1 %0
mt%0 %1
- mt%0 %1
{cror 0,0,0|nop}"
- [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
+ [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
(define_expand "mov<mode>"
[(set (match_operand:INT 0 "general_operand" "")
@@ -8362,8 +8358,8 @@
"{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
(define_insn "*movqi_internal"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
- (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
+ (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
"gpc_reg_operand (operands[0], QImode)
|| gpc_reg_operand (operands[1], QImode)"
"@
@@ -8373,9 +8369,8 @@
{lil|li} %0,%1
mf%1 %0
mt%0 %1
- mt%0 %1
{cror 0,0,0|nop}"
- [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
+ [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
;; Here is how to move condition codes around. When we store CC data in
;; an integer register or memory, we store just the high-order 4 bits.
@@ -8387,8 +8382,8 @@
"")
(define_insn "*movcc_internal1"
- [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
- (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
+ [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
+ (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
"register_operand (operands[0], CCmode)
|| register_operand (operands[1], CCmode)"
"@
@@ -8402,7 +8397,6 @@
{lil|li} %0,%1
mf%1 %0
mt%0 %1
- mt%0 %1
{l%U1%X1|lwz%U1%X1} %0,%1
{st%U0%U1|stw%U0%U1} %1,%0"
[(set (attr "type")
@@ -8410,21 +8404,21 @@
(const_string "cr_logical")
(eq_attr "alternative" "1,2")
(const_string "mtcr")
- (eq_attr "alternative" "6,7,9")
+ (eq_attr "alternative" "6,7")
(const_string "integer")
(eq_attr "alternative" "8")
(const_string "mfjmpr")
- (eq_attr "alternative" "10")
+ (eq_attr "alternative" "9")
(const_string "mtjmpr")
- (eq_attr "alternative" "11")
+ (eq_attr "alternative" "10")
(const_string "load")
- (eq_attr "alternative" "12")
+ (eq_attr "alternative" "11")
(const_string "store")
(match_test "TARGET_MFCRF")
(const_string "mfcrf")
]
(const_string "mfcr")))
- (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
+ (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
;; For floating-point, we normally deal with the floating-point registers
;; unless -msoft-float is used. The sole exception is that parameter passing
@@ -8463,8 +8457,8 @@
}")
(define_insn "*movsf_hardfloat"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
- (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,!r,*h,!r,!r")
+ (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,h,0,G,Fn"))]
"(gpc_reg_operand (operands[0], SFmode)
|| gpc_reg_operand (operands[1], SFmode))
&& (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
@@ -8476,24 +8470,22 @@
lfs%U1%X1 %0,%1
stfs%U0%X0 %1,%0
mt%0 %1
- mt%0 %1
mf%1 %0
{cror 0,0,0|nop}
#
#"
- [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
- (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
+ [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*")
+ (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
(define_insn "*movsf_softfloat"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,*h")
- (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,G,Fn,0"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
+ (match_operand:SF 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
"(gpc_reg_operand (operands[0], SFmode)
|| gpc_reg_operand (operands[1], SFmode))
&& (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
"@
mr %0,%1
mt%0 %1
- mt%0 %1
mf%1 %0
{l%U1%X1|lwz%U1%X1} %0,%1
{st%U0%X0|stw%U0%X0} %1,%0
@@ -8502,8 +8494,8 @@
#
#
{cror 0,0,0|nop}"
- [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*")
- (set_attr "length" "4,4,4,4,4,4,4,4,4,8,4")])
+ [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
+ (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
(define_expand "movdf"
@@ -13788,7 +13780,7 @@
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
+ (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
(plus:P (match_dup 1)
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
@@ -13812,7 +13804,7 @@
(const_int 1))
(pc)
(label_ref (match_operand 0 "" ""))))
- (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
+ (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
(plus:P (match_dup 1)
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
@@ -13838,7 +13830,7 @@
(const_int 1))
(label_ref (match_operand 0 "" ""))
(pc)))
- (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
+ (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
(plus:P (match_dup 1)
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
@@ -13862,7 +13854,7 @@
(const_int 1))
(pc)
(label_ref (match_operand 0 "" ""))))
- (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
+ (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
(plus:P (match_dup 1)
(const_int -1)))
(clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
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