diff options
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/mips/mips.c | 14 | ||||
| -rw-r--r-- | gcc/config/mips/mips.h | 14 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 20 | ||||
| -rw-r--r-- | gcc/config/mips/t-vr | 10 | ||||
| -rw-r--r-- | gcc/config/mips/vr.h | 6 | ||||
| -rw-r--r-- | gcc/config/mips/vr4120-div.S (renamed from gcc/config/mips/vr4122-div.S) | 22 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 12 |
8 files changed, 60 insertions, 49 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bd948e390c5..b749c71f19d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2004-04-14 Richard Sandiford <rsandifo@redhat.com> + + * doc/invoke.texi: Rename MIPS's -mfix-vr4122-bugs to -mfix-vr4120. + * config/mips/mips.h (MASK_FIX_VR4120): Renamed from MASK_FIX_VR4122. + (TARGET_FIX_VR4120): Likewise TARGET_FIX_VR4122. + (TARGET_SWITCHES): Replace -mfix-vr4122-bugs with -mfix-vr4120. + (ASM_SPEC): Update accordingly. + * config/mips/mips.c: Update after above renaming. + * config/mips/mips.md, config/mips/t-vr, config/mips/vr.h: Likewise. + * config/mips/vr4120-div.S: Renamed from vr4122-div.S. + 2004-04-13 James E Wilson <wilson@specifixinc.com> * c-opt.c (c_common_post_options): If this_input_filename is NULL, diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index de0d9874f4a..b8d27a3c39f 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -8721,10 +8721,10 @@ mips_avoid_hazards (void) cfun->machine->ignore_hazard_length_p = true; shorten_branches (get_insns ()); - /* The profiler code uses assembler macros. -mfix-vr4122-bugs - relies on assembler nop insertion. */ + /* The profiler code uses assembler macros. -mfix-vr4120 relies on + assembler nop insertion. */ cfun->machine->all_noreorder_p = (!current_function_profile - && !TARGET_FIX_VR4122); + && !TARGET_FIX_VR4120); last_insn = 0; hilo_delay = 2; @@ -8764,7 +8764,7 @@ mips_reorg (void) /* This function does three things: - - Register the special divsi3 and modsi3 functions if -mfix-vr4122-bugs. + - Register the special divsi3 and modsi3 functions if -mfix-vr4120. - Register the mips16 hardware floating point stubs. - Register the gofast functions if selected using --enable-gofast. */ @@ -8773,10 +8773,10 @@ mips_reorg (void) static void mips_init_libfuncs (void) { - if (TARGET_FIX_VR4122) + if (TARGET_FIX_VR4120) { - set_optab_libfunc (sdiv_optab, SImode, "__vr4122_divsi3"); - set_optab_libfunc (smod_optab, SImode, "__vr4122_modsi3"); + set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3"); + set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3"); } if (TARGET_MIPS16 && mips16_hard_float) diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 679a378d14c..c4b7769db51 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -173,7 +173,7 @@ extern const struct mips_cpu_info *mips_tune_info; #define MASK_FIX_R4000 0x01000000 /* Work around R4000 errata. */ #define MASK_FIX_R4400 0x02000000 /* Work around R4400 errata. */ #define MASK_FIX_SB1 0x04000000 /* Work around SB-1 errata. */ -#define MASK_FIX_VR4122 0x08000000 /* Work-around VR4122 errata. */ +#define MASK_FIX_VR4120 0x08000000 /* Work around VR4120 errata. */ /* Debug switches, not documented */ #define MASK_DEBUG 0 /* unused */ @@ -257,7 +257,7 @@ extern const struct mips_cpu_info *mips_tune_info; /* Work around R4400 errata. */ #define TARGET_FIX_R4400 (target_flags & MASK_FIX_R4400) -#define TARGET_FIX_VR4122 (target_flags & MASK_FIX_VR4122) +#define TARGET_FIX_VR4120 (target_flags & MASK_FIX_VR4120) /* True if we should use NewABI-style relocation operators for symbolic addresses. This is never true for mips16 code, @@ -608,10 +608,10 @@ extern const struct mips_cpu_info *mips_tune_info; N_("Work around R4400 errata")}, \ {"no-fix-r4400", -MASK_FIX_R4400, \ N_("Don't work around R4400 errata")}, \ - {"fix-vr4122-bugs", MASK_FIX_VR4122, \ - N_("Work around certain VR4122 errata")}, \ - {"no-fix-vr4122-bugs", -MASK_FIX_VR4122, \ - N_("Don't work around certain VR4122 errata")}, \ + {"fix-vr4120", MASK_FIX_VR4120, \ + N_("Work around certain VR4120 errata")}, \ + {"no-fix-vr4120", -MASK_FIX_VR4120, \ + N_("Don't work around certain VR4120 errata")}, \ {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \ N_("Trap on integer divide by zero")}, \ {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \ @@ -1115,7 +1115,7 @@ extern const struct mips_cpu_info *mips_tune_info; %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \ %{mips32} %{mips32r2} %{mips64} \ %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \ -%{mfix-vr4122-bugs} \ +%{mfix-vr4120} \ %(subtarget_asm_optimizing_spec) \ %(subtarget_asm_debugging_spec) \ %{membedded-pic} \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 21b8277af3f..fdf3f96fef0 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -212,19 +212,19 @@ (ne (symbol_ref "TARGET_MIPS16") (const_int 0))) (const_int 8) - ;; Various VR4122 errata require a nop to be inserted after a macc + ;; Various VR4120 errata require a nop to be inserted after a macc ;; instruction. The assembler does this for us, so account for ;; the worst-case length here. (and (eq_attr "type" "imadd") - (ne (symbol_ref "TARGET_FIX_VR4122") (const_int 0))) + (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))) (const_int 8) - ;; VR4122 errata MD(4): if there are consecutive dmult instructions, + ;; VR4120 errata MD(4): if there are consecutive dmult instructions, ;; the result of the second one is missed. The assembler should work ;; around this by inserting a nop after the first dmult. (and (eq_attr "type" "imul") (and (eq_attr "mode" "DI") - (ne (symbol_ref "TARGET_FIX_VR4122") (const_int 0)))) + (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))) (const_int 8) (eq_attr "type" "idiv") @@ -2315,8 +2315,8 @@ [(set_attr "type" "imul") (set_attr "mode" "DI")]) -;; Disable this pattern for -mfix-vr4122-bugs. This is for VR4122 errata -;; MD(0), which says that dmultu does not always produce the correct result. +;; Disable this pattern for -mfix-vr4120. This is for VR4120 errata MD(0), +;; which says that dmultu does not always produce the correct result. (define_insn "umuldi3_highpart" [(set (match_operand:DI 0 "register_operand" "=h") (truncate:DI @@ -2326,7 +2326,7 @@ (zero_extend:TI (match_operand:DI 2 "register_operand" "d"))) (const_int 64)))) (clobber (match_scratch:DI 3 "=l"))] - "TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_FIX_VR4122" + "TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_FIX_VR4120" "dmultu\t%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")]) @@ -2600,7 +2600,7 @@ (const_int 8) (const_int 4)))]) -;; VR4122 errata MD(A1): signed division instructions do not work correctly +;; VR4120 errata MD(A1): signed division instructions do not work correctly ;; with negative operands. We use special libgcc functions instead. (define_insn "divmodsi4" [(set (match_operand:SI 0 "register_operand" "=l") @@ -2609,7 +2609,7 @@ (set (match_operand:SI 3 "register_operand" "=h") (mod:SI (match_dup 1) (match_dup 2)))] - "!TARGET_FIX_VR4122" + "!TARGET_FIX_VR4120" { return mips_output_division ("div\t$0,%1,%2", operands); } [(set_attr "type" "idiv") (set_attr "mode" "SI")]) @@ -2621,7 +2621,7 @@ (set (match_operand:DI 3 "register_operand" "=h") (mod:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT && !TARGET_FIX_VR4122" + "TARGET_64BIT && !TARGET_FIX_VR4120" { return mips_output_division ("ddiv\t$0,%1,%2", operands); } [(set_attr "type" "idiv") (set_attr "mode" "DI")]) diff --git a/gcc/config/mips/t-vr b/gcc/config/mips/t-vr index e342641fc9b..dd4affe57e4 100644 --- a/gcc/config/mips/t-vr +++ b/gcc/config/mips/t-vr @@ -8,7 +8,7 @@ CRTSTUFF_T_CFLAGS = -G 0 TARGET_LIBGCC2_CFLAGS = -G 0 LIB2FUNCS_STATIC_EXTRA = $(srcdir)/config/mips/mips16.S \ - $(srcdir)/config/mips/vr4122-div.S + $(srcdir)/config/mips/vr4120-div.S EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o # Assemble startup files. @@ -34,7 +34,7 @@ $(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES) # mabi=eabi/mgp32 # mabi=eabi/mgp32/mlong64 # -# Architecture: march=vr4120 with -mfix-vr4122-bugs +# Architecture: march=vr4120 with -mfix-vr4120 # march=vr4130 (default) # march=vr5000 # march=vr5400 @@ -64,7 +64,7 @@ $(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES) # mabi=eabi/mlong32 # mabi=eabi/mgp32 # -# Architecture: march=vr4120 with -mfix-vr4122-bugs +# Architecture: march=vr4120 with -mfix-vr4120 # march=vr4130 (default) # # Total: 2 * 3 * 2 = 12 multilibs. @@ -74,7 +74,7 @@ MULTILIB_OPTIONS = \ mgp32 \ mlong64 \ mips16 \ - mfix-vr4122-bugs/march=vr4130/march=vr4300/march=vr5000/march=vr5400/march=vr5500 + mfix-vr4120/march=vr4130/march=vr4300/march=vr5000/march=vr5400/march=vr5500 MULTILIB_DIRNAMES = \ el eb \ @@ -84,7 +84,7 @@ MULTILIB_DIRNAMES = \ mips16 \ vr4120 vr4130 vr4300 vr5000 vr5400 vr5500 -MULTILIB_MATCHES = EL=mel EB=meb mfix-vr4122-bugs=march?vr4120 +MULTILIB_MATCHES = EL=mel EB=meb mfix-vr4120=march?vr4120 # Assume a 41xx-series is the default: we'd need a *mips16 entry if # the default processor didn't support mips16. Also assume the diff --git a/gcc/config/mips/vr.h b/gcc/config/mips/vr.h index cbc73671c9e..38f7e129429 100644 --- a/gcc/config/mips/vr.h +++ b/gcc/config/mips/vr.h @@ -28,10 +28,10 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ "march=" DEFAULT_VR_ARCH } #define DRIVER_SELF_SPECS \ - /* Make -mfix-vr4122-bugs imply -march=vr4120. This cuts down \ + /* Make -mfix-vr4120 imply -march=vr4120. This cuts down \ on command-line tautology and makes it easier for t-vr to \ - provide a -mfix-vr4122-bugs multilib. */ \ - "%{mfix-vr4122-bugs:%{!march=*:-march=vr4120}}", \ + provide a -mfix-vr4120 multilib. */ \ + "%{mfix-vr4120:%{!march=*:-march=vr4120}}", \ \ /* Make -mabi=eabi -mlong32 the default. */ \ "%{!mabi=*:-mabi=eabi %{!mlong*:-mlong32}}", \ diff --git a/gcc/config/mips/vr4122-div.S b/gcc/config/mips/vr4120-div.S index 8936af17d1d..d7ee40e3043 100644 --- a/gcc/config/mips/vr4122-div.S +++ b/gcc/config/mips/vr4120-div.S @@ -1,4 +1,4 @@ -/* Support file for -mfix-vr4122-bugs. +/* Support file for -mfix-vr4120. Copyright (C) 2002, 2004 Free Software Foundation, Inc. This file is part of GCC. @@ -19,8 +19,8 @@ the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* This file contains functions which implement divsi3 and modsi3 for - -mfix-vr4122-bugs. div and ddiv do not give the correct result - when one of the operands is negative. */ + -mfix-vr4120. div and ddiv do not give the correct result when one + of the operands is negative. */ .set nomips16 @@ -54,16 +54,16 @@ Boston, MA 02111-1307, USA. */ .set reorder; \ 4: - .globl __vr4122_divsi3 - .ent __vr4122_divsi3 -__vr4122_divsi3: + .globl __vr4120_divsi3 + .ent __vr4120_divsi3 +__vr4120_divsi3: DIV j $31 - .end __vr4122_divsi3 + .end __vr4120_divsi3 - .globl __vr4122_modsi3 - .ent __vr4122_modsi3 -__vr4122_modsi3: + .globl __vr4120_modsi3 + .ent __vr4120_modsi3 +__vr4120_modsi3: move $6,$4 # x1 = x move $7,$5 # y1 = y DIV @@ -72,4 +72,4 @@ __vr4122_modsi3: .set noreorder j $31 subu $2,$6,$2 # r = x1 - r in delay slot - .end __vr4122_modsi3 + .end __vr4120_modsi3 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 65810252458..60611f22c15 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -480,7 +480,7 @@ in the following sections. -mmemcpy -mno-memcpy -mlong-calls -mno-long-calls @gol -mmad -mno-mad -mfused-madd -mno-fused-madd -nocpp @gol -mfix-r4000 -mno-fix-r4000 -mfix-r4400 -mno-fix-r4400 @gol --mfix-vr4122-bugs -mno-fix-vr4122-bugs -mfix-sb1 -mno-fix-sb1 @gol +-mfix-vr4120 -mno-fix-vr4120 -mfix-sb1 -mno-fix-sb1 @gol -mflush-func=@var{func} -mno-flush-func @gol -mbranch-likely -mno-branch-likely} @@ -8125,10 +8125,10 @@ A double-word or a variable shift may give an incorrect result if executed immediately after starting an integer division. @end itemize -@item -mfix-vr4122-bugs -@itemx -mno-fix-vr4122-bugs -@opindex mfix-vr4122-bugs -Work around certain VR4122 errata: +@item -mfix-vr4120 +@itemx -mno-fix-vr4120 +@opindex mfix-vr4120 +Work around certain VR4120 errata: @itemize @minus @item @code{dmultu} does not always produce the correct result. @@ -8140,7 +8140,7 @@ The workarounds for the division errata rely on special functions in @file{libgcc.a}. At present, these functions are only provided by the @code{mips64vr*-elf} configurations. -Other VR4122 errata require a nop to be inserted between certain pairs of +Other VR4120 errata require a nop to be inserted between certain pairs of instructions. These errata are handled by the assembler, not by GCC itself. @item -mfix-sb1 |