diff options
Diffstat (limited to 'gcc/ChangeLog')
| -rw-r--r-- | gcc/ChangeLog | 496 |
1 files changed, 491 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c67c6ff10c6..eafbbe5f243 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,491 @@ +2014-01-28 Richard Biener <rguenther@suse.de> + + PR rtl-optimization/45364 + PR rtl-optimization/59890 + * var-tracking.c (local_get_addr_clear_given_value): Handle + already cleared slot. + (val_reset): Handle not allocated local_get_addr_cache. + (vt_find_locations): Use post-order on the inverted CFG. + +2014-01-28 Alan Modra <amodra@gmail.com> + + * Makefile.in (BUILD_CPPFLAGS): Do not use ALL_CPPFLAGS. + * configure.ac <recursive call for build != host>: Define + GENERATOR_FILE. Comment. Use CXX_FOR_BUILD, CXXFLAGS_FOR_BUILD + and LD_FOR_BUILD too. + * configure: Regenerate. + +2014-01-27 Allan Sandfeld Jensen <sandfeld@kde.org> + + * config/i386/i386.c (get_builtin_code_for_version): Separate + Westmere from Nehalem, Ivy Bridge from Sandy Bridge and + Broadwell from Haswell. + +2014-01-27 Steve Ellcey <sellcey@mips.com> + + * common/config/mips/mips-common.c (TARGET_DEFAULT_TARGET_FLAGS): + Remove TARGET_FP_EXCEPTIONS_DEFAULT and MASK_FUSED_MADD. + * config/mips/mips.c (mips_option_override): Change setting + of TARGET_DSP. + * config/mips/mips.h (TARGET_FP_EXCEPTIONS_DEFAULT): Remove. + * config/mips/mips.opt (DSP, DSPR2, FP_EXCEPTIONS, FUSED_MADD, MIPS3D): + Change from Mask to Var. + +2014-01-27 Jeff Law <law@redhat.com> + + * ipa-inline.c (inline_small_functions): Fix typo. + +2014-01-27 Ilya Tocar <ilya.tocar@intel.com> + + * config/i386/avx512fintrin.h (_mm512_mask_cvtepi32_storeu_epi8): New. + (_mm512_mask_cvtsepi32_storeu_epi8): Ditto. + (_mm512_mask_cvtusepi32_storeu_epi8): Ditto. + (_mm512_mask_cvtepi32_storeu_epi16): Ditto. + (_mm512_mask_cvtsepi32_storeu_epi16): Ditto. + (_mm512_mask_cvtusepi32_storeu_epi16): Ditto. + (_mm512_mask_cvtepi64_storeu_epi32): Ditto. + (_mm512_mask_cvtsepi64_storeu_epi32): Ditto. + (_mm512_mask_cvtusepi64_storeu_epi32): Ditto. + (_mm512_mask_cvtepi64_storeu_epi16): Ditto. + (_mm512_mask_cvtsepi64_storeu_epi16): Ditto. + (_mm512_mask_cvtusepi64_storeu_epi16): Ditto. + (_mm512_mask_cvtepi64_storeu_epi8): Ditto. + (_mm512_mask_cvtsepi64_storeu_epi8): Ditto. + (_mm512_mask_cvtusepi64_storeu_epi8): Ditto. + (_mm512_storeu_epi64): Ditto. + (_mm512_cmpge_epi32_mask): Ditto. + (_mm512_cmpge_epu32_mask): Ditto. + (_mm512_cmpge_epi64_mask): Ditto. + (_mm512_cmpge_epu64_mask): Ditto. + (_mm512_cmple_epi32_mask): Ditto. + (_mm512_cmple_epu32_mask): Ditto. + (_mm512_cmple_epi64_mask): Ditto. + (_mm512_cmple_epu64_mask): Ditto. + (_mm512_cmplt_epi32_mask): Ditto. + (_mm512_cmplt_epu32_mask): Ditto. + (_mm512_cmplt_epi64_mask): Ditto. + (_mm512_cmplt_epu64_mask): Ditto. + (_mm512_cmpneq_epi32_mask): Ditto. + (_mm512_cmpneq_epu32_mask): Ditto. + (_mm512_cmpneq_epi64_mask): Ditto. + (_mm512_cmpneq_epu64_mask): Ditto. + (_mm512_expand_pd): Ditto. + (_mm512_expand_ps): Ditto. + * config/i386/i386-builtin-types.def: Add PV16QI, PV16QI, PV16HI, + VOID_PV8SI_V8DI_QI, VOID_PV8HI_V8DI_QI, VOID_PV16QI_V8DI_QI, + VOID_PV16QI_V16SI_HI, VOID_PV16HI_V16SI_HI. + * config/i386/i386.c (ix86_builtins): Add + IX86_BUILTIN_EXPANDPD512_NOMASK, IX86_BUILTIN_EXPANDPS512_NOMASK, + IX86_BUILTIN_PMOVDB512_MEM, IX86_BUILTIN_PMOVDW512_MEM, + IX86_BUILTIN_PMOVQB512_MEM, IX86_BUILTIN_PMOVQD512_MEM, + IX86_BUILTIN_PMOVQW512_MEM, IX86_BUILTIN_PMOVSDB512_MEM, + IX86_BUILTIN_PMOVSDW512_MEM, IX86_BUILTIN_PMOVSQB512_MEM, + IX86_BUILTIN_PMOVSQD512_MEM, IX86_BUILTIN_PMOVSQW512_MEM, + IX86_BUILTIN_PMOVUSDB512_MEM, IX86_BUILTIN_PMOVUSDW512_MEM, + IX86_BUILTIN_PMOVUSQB512_MEM, IX86_BUILTIN_PMOVUSQD512_MEM, + IX86_BUILTIN_PMOVUSQW512_MEM. + (bdesc_special_args): Add __builtin_ia32_pmovusqd512mem_mask, + __builtin_ia32_pmovsqd512mem_mask, + __builtin_ia32_pmovqd512mem_mask, + __builtin_ia32_pmovusqw512mem_mask, + __builtin_ia32_pmovsqw512mem_mask, + __builtin_ia32_pmovqw512mem_mask, + __builtin_ia32_pmovusdw512mem_mask, + __builtin_ia32_pmovsdw512mem_mask, + __builtin_ia32_pmovdw512mem_mask, + __builtin_ia32_pmovqb512mem_mask, + __builtin_ia32_pmovusqb512mem_mask, + __builtin_ia32_pmovsqb512mem_mask, + __builtin_ia32_pmovusdb512mem_mask, + __builtin_ia32_pmovsdb512mem_mask, + __builtin_ia32_pmovdb512mem_mask. + (bdesc_args): Add __builtin_ia32_expanddf512, + __builtin_ia32_expandsf512. + (ix86_expand_special_args_builtin): Handle VOID_FTYPE_PV8SI_V8DI_QI, + VOID_FTYPE_PV8HI_V8DI_QI, VOID_FTYPE_PV16HI_V16SI_HI, + VOID_FTYPE_PV16QI_V8DI_QI, VOID_FTYPE_PV16QI_V16SI_HI. + * config/i386/sse.md (unspec): Add UNSPEC_EXPAND_NOMASK. + (avx512f_<code><pmov_src_lower><mode>2_mask_store): New. + (*avx512f_<code>v8div16qi2_store_mask): Renamed to ... + (avx512f_<code>v8div16qi2_mask_store): This. + (avx512f_expand<mode>): New. + +2014-01-27 Kirill Yukhin <kirill.yukhin@intel.com> + + * config/i386/avx512pfintrin.h (_mm512_mask_prefetch_i32gather_pd): + New. + (_mm512_mask_prefetch_i64gather_pd): Ditto. + (_mm512_prefetch_i32scatter_pd): Ditto. + (_mm512_mask_prefetch_i32scatter_pd): Ditto. + (_mm512_prefetch_i64scatter_pd): Ditto. + (_mm512_mask_prefetch_i64scatter_pd): Ditto. + (_mm512_mask_prefetch_i32gather_ps): Fix operand type. + (_mm512_mask_prefetch_i64gather_ps): Ditto. + (_mm512_prefetch_i32scatter_ps): Ditto. + (_mm512_mask_prefetch_i32scatter_ps): Ditto. + (_mm512_prefetch_i64scatter_ps): Ditto. + (_mm512_mask_prefetch_i64scatter_ps): Ditto. + * config/i386/i386-builtin-types.def: Define + VOID_FTYPE_QI_V8SI_PCINT64_INT_INT + and VOID_FTYPE_QI_V8DI_PCINT64_INT_INT. + * config/i386/i386.c (ix86_builtins): Define IX86_BUILTIN_GATHERPFQPD, + IX86_BUILTIN_GATHERPFDPD, IX86_BUILTIN_SCATTERPFDPD, + IX86_BUILTIN_SCATTERPFQPD. + (ix86_init_mmx_sse_builtins): Define __builtin_ia32_gatherpfdpd, + __builtin_ia32_gatherpfdps, __builtin_ia32_gatherpfqpd, + __builtin_ia32_gatherpfqps, __builtin_ia32_scatterpfdpd, + __builtin_ia32_scatterpfdps, __builtin_ia32_scatterpfqpd, + __builtin_ia32_scatterpfqps. + (ix86_expand_builtin): Expand new built-ins. + * config/i386/sse.md (avx512pf_gatherpf<mode>): Add SF suffix, + fix memory access data type. + (*avx512pf_gatherpf<mode>_mask): Ditto. + (*avx512pf_gatherpf<mode>): Ditto. + (avx512pf_scatterpf<mode>): Ditto. + (*avx512pf_scatterpf<mode>_mask): Ditto. + (*avx512pf_scatterpf<mode>): Ditto. + (GATHER_SCATTER_SF_MEM_MODE): New. + (avx512pf_gatherpf<mode>df): Ditto. + (*avx512pf_gatherpf<mode>df_mask): Ditto. + (*avx512pf_scatterpf<mode>df): Ditto. + +2014-01-27 Jakub Jelinek <jakub@redhat.com> + + PR bootstrap/59934 + * expmed.h (expmed_mode_index): Rework so that analysis and optimziers + know when the MODE_PARTIAL_INT and MODE_VECTOR_INT cases can never be + reached. + +2014-01-27 James Greenhalgh <james.greenhalgh@arm.com> + + * common/config/arm/arm-common.c + (arm_rewrite_mcpu): Handle multiple names. + * config/arm/arm.h + (BIG_LITTLE_SPEC): Do not discard mcpu switches. + +2014-01-27 James Greenhalgh <james.greenhalgh@arm.com> + + * gimple-builder.h (create_gimple_tmp): Delete. + +2014-01-27 Christian Bruel <christian.bruel@st.com> + + * config/sh/sh-mem.cc (sh_expand_cmpnstr): Fix remaining bytes after + words comparisons. + +2014-01-26 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/pa.md (call): Generate indirect long calls to non-local + functions when outputing 32-bit code. + (call_value): Likewise except for special call to buggy powf function. + + * config/pa/pa.c (pa_attr_length_indirect_call): Adjust length of + portable runtime and PIC indirect calls. + (pa_output_indirect_call): Remove unnecessary nop from portable runtime + and PIC call sequences. Use ldo instead of blr to set return register + in PIC call sequence. + +2014-01-25 Walter Lee <walt@tilera.com> + + * config/tilegx/sync.md (atomic_fetch_sub): Fix negation and + avoid clobbering a live register. + +2014-01-25 Walter Lee <walt@tilera.com> + + * config/tilegx/tilegx-c.c (tilegx_cpu_cpp_builtins): + Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2}. + * config/tilegx/tilepro-c.c (tilepro_cpu_cpp_builtins): + Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_{1,2,4,8}. + +2014-01-25 Walter Lee <walt@tilera.com> + + * config/tilegx/tilegx.c (tilegx_function_arg): Start 16-byte + arguments on even registers. + (tilegx_gimplify_va_arg_expr): Align 16-byte var args to + STACK_BOUNDARY. + * config/tilegx/tilegx.h (STACK_BOUNDARY): Change to 16 bytes. + (BIGGEST_ALIGNMENT): Ditto. + (BIGGEST_FIELD_ALIGNMENT): Ditto. + +2014-01-25 Walter Lee <walt@tilera.com> + + * config/tilegx/tilegx.c (tilegx_gen_bundles): Delete barrier + insns before bundling. + * config/tilegx/tilegx.md (tile_network_barrier): Update comment. + +2014-01-25 Walter Lee <walt@tilera.com> + + * config/tilegx/tilegx.c (tilegx_expand_builtin): Set + PREFETCH_SCHEDULE_BARRIER_P to true for prefetches. + * config/tilepro/tilepro.c (tilepro_expand_builtin): Ditto. + +2014-01-25 Richard Sandiford <rdsandiford@googlemail.com> + + * config/mips/constraints.md (kl): Delete. + * config/mips/mips.md (divmod<mode>4, udivmod<mode>4): Turn into + define expands, using... + (divmod<mode>4_mips16, udivmod<mode>4_mips16): ...these new + instructions for MIPS16. + (*divmod<mode>4, *udivmod<mode>4): New patterns, taken from the + non-MIPS16 version of the old divmod<mode>4 and udivmod<mode>4. + +2014-01-25 Walter Lee <walt@tilera.com> + + * config/tilepro/tilepro.md (ctzdi2): Use register_operand predicate. + (clzdi2): Ditto. + (ffsdi2): Ditto. + +2014-01-25 Walter Lee <walt@tilera.com> + + * config/tilegx/tilegx.c (tilegx_expand_to_rtl_hook): New. + (TARGET_EXPAND_TO_RTL_HOOK): Define. + +2014-01-25 Richard Sandiford <rdsandiford@googlemail.com> + + * rtlanal.c (canonicalize_condition): Split out duplicated mode check. + Handle XOR. + +2014-01-25 Jakub Jelinek <jakub@redhat.com> + + * print-rtl.c (in_call_function_usage): New var. + (print_rtx): When in CALL_INSN_FUNCTION_USAGE, always print + EXPR_LIST mode as mode and not as reg note name. + + PR middle-end/59561 + * cfgloopmanip.c (copy_loop_info): If + loop->warned_aggressive_loop_optimizations, make sure + the flag is set in target loop too. + +2014-01-24 Balaji V. Iyer <balaji.v.iyer@intel.com> + + * builtins.c (is_builtin_name): Renamed flag_enable_cilkplus to + flag_cilkplus. + * builtins.def: Likewise. + * cilk.h (fn_contains_cilk_spawn_p): Likewise. + * cppbuiltin.c (define_builtin_macros_for_compilation_flags): Likewise. + * ira.c (ira_setup_eliminable_regset): Likewise. + * omp-low.c (gate_expand_omp): Likewise. + (execute_lower_omp): Likewise. + (diagnose_sb_0): Likewise. + (gate_diagnose_omp_blocks): Likewise. + (simd_clone_clauses_extract): Likewise. + (gate): Likewise. + +2014-01-24 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/rs6000.c (rs6000_expand_vec_perm_const_1): Remove + correction for little endian... + * config/rs6000/vsx.md (vsx_xxpermdi2_<mode>_1): ...and move it to + here. + +2014-01-24 Jeff Law <law@redhat.com> + + PR tree-optimization/59919 + * tree-vrp.c (find_assert_locations_1): Do not register asserts + for non-returning calls. + +2014-01-24 James Greenhalgh <james.greenhalgh@arm.com> + + * common/config/aarch64/aarch64-common.c + (aarch64_rewrite_mcpu): Handle multiple names. + * config/aarch64/aarch64.h + (BIG_LITTLE_SPEC): Do not discard mcpu switches. + +2014-01-24 Dodji Seketeli <dodji@redhat.com> + + * input.c (add_file_to_cache_tab): Handle the case where fopen + returns NULL. + +2014-01-23 H.J. Lu <hongjiu.lu@intel.com> + + PR target/59929 + * config/i386/i386.md (pushsf splitter): Get stack adjustment + from push operand if code of push isn't PRE_DEC. + +2014-01-23 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/59909 + * doc/invoke.texi (RS/6000 and PowerPC Options): Document + -mquad-memory-atomic. Update -mquad-memory documentation to say + it is only used for non-atomic loads/stores. + + * config/rs6000/predicates.md (quad_int_reg_operand): Allow either + -mquad-memory or -mquad-memory-atomic switches. + + * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add + -mquad-memory-atomic to ISA 2.07 support. + + * config/rs6000/rs6000.opt (-mquad-memory-atomic): Add new switch + to separate support of normal quad word memory operations (ldq, stq) + from the atomic quad word memory operations. + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Add + support to separate non-atomic quad word operations from atomic + quad word operations. Disable non-atomic quad word operations in + little endian mode so that we don't have to swap words after the + load and before the store. + (quad_load_store_p): Add comment about atomic quad word support. + (rs6000_opt_masks): Add -mquad-memory-atomic to the list of + options printed with -mdebug=reg. + + * config/rs6000/rs6000.h (TARGET_SYNC_TI): Use + -mquad-memory-atomic as the test for whether we have quad word + atomic instructions. + (TARGET_SYNC_HI_QI): If either -mquad-memory-atomic, -mquad-memory, + or -mp8-vector are used, allow byte/half-word atomic operations. + + * config/rs6000/sync.md (load_lockedti): Insure that the address + is a proper indexed or indirect address for the lqarx instruction. + On little endian systems, swap the hi/lo registers after the lqarx + instruction. + (load_lockedpti): Use indexed_or_indirect_operand predicate to + insure the address is valid for the lqarx instruction. + (store_conditionalti): Insure that the address is a proper indexed + or indirect address for the stqcrx. instruction. On little endian + systems, swap the hi/lo registers before doing the stqcrx. + instruction. + (store_conditionalpti): Use indexed_or_indirect_operand predicate to + insure the address is valid for the stqcrx. instruction. + + * gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros): + Define __QUAD_MEMORY__ and __QUAD_MEMORY_ATOMIC__ based on what + type of quad memory support is available. + +2014-01-23 Vladimir Makarov <vmakarov@redhat.com> + + PR regression/59915 + * lra-constraints.c (simplify_operand_subreg): Spill pseudo if + there is a danger of looping. + +2014-01-23 Pat Haugen <pthaugen@us.ibm.com> + + * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't + force flag_ira_loop_pressure if set via command line. + +2014-01-23 Alex Velenko <Alex.Velenko@arm.com> + + * config/aarch64/aarch64-simd-builtins.def (ashr): DI mode removed. + (ashr_simd): New builtin handling DI mode. + * config/aarch64/aarch64-simd.md (aarch64_ashr_simddi): New pattern. + (aarch64_sshr_simddi): New match pattern. + * config/aarch64/arm_neon.h (vshr_n_s32): Builtin call modified. + (vshrd_n_s64): Likewise. + * config/aarch64/predicates.md (aarch64_shift_imm64_di): New predicate. + +2014-01-23 Nick Clifton <nickc@redhat.com> + + * config/msp430/msp430.h (ASM_SPEC): Pass the -mcpu as -mcpu. + (LIB_SPEC): Drop use of memory.ld and peripherals.ld scripts in + favour of mcu specific scripts. + * config/msp430/t-msp430 (MULTILIB_MATCHES): Add more matches for + 430x multilibs. + +2014-01-23 James Greenhalgh <james.greenhalgh@arm.com> + Alex Velenko <Alex.Velenko@arm.com> + + * config/aarch64/arm_neon.h (vaddv_s8): __LANE0 cleanup. + (vaddv_s16): Likewise. + (vaddv_s32): Likewise. + (vaddv_u8): Likewise. + (vaddv_u16): Likewise. + (vaddv_u32): Likewise. + (vaddvq_s8): Likewise. + (vaddvq_s16): Likewise. + (vaddvq_s32): Likewise. + (vaddvq_s64): Likewise. + (vaddvq_u8): Likewise. + (vaddvq_u16): Likewise. + (vaddvq_u32): Likewise. + (vaddvq_u64): Likewise. + (vaddv_f32): Likewise. + (vaddvq_f32): Likewise. + (vaddvq_f64): Likewise. + (vmaxv_f32): Likewise. + (vmaxv_s8): Likewise. + (vmaxv_s16): Likewise. + (vmaxv_s32): Likewise. + (vmaxv_u8): Likewise. + (vmaxv_u16): Likewise. + (vmaxv_u32): Likewise. + (vmaxvq_f32): Likewise. + (vmaxvq_f64): Likewise. + (vmaxvq_s8): Likewise. + (vmaxvq_s16): Likewise. + (vmaxvq_s32): Likewise. + (vmaxvq_u8): Likewise. + (vmaxvq_u16): Likewise. + (vmaxvq_u32): Likewise. + (vmaxnmv_f32): Likewise. + (vmaxnmvq_f32): Likewise. + (vmaxnmvq_f64): Likewise. + (vminv_f32): Likewise. + (vminv_s8): Likewise. + (vminv_s16): Likewise. + (vminv_s32): Likewise. + (vminv_u8): Likewise. + (vminv_u16): Likewise. + (vminv_u32): Likewise. + (vminvq_f32): Likewise. + (vminvq_f64): Likewise. + (vminvq_s8): Likewise. + (vminvq_s16): Likewise. + (vminvq_s32): Likewise. + (vminvq_u8): Likewise. + (vminvq_u16): Likewise. + (vminvq_u32): Likewise. + (vminnmv_f32): Likewise. + (vminnmvq_f32): Likewise. + (vminnmvq_f64): Likewise. + +2014-01-23 James Greenhalgh <james.greenhalgh@arm.com> + + * config/aarch64/aarch64-simd.md + (aarch64_dup_lane<mode>): Correct lane number on big-endian. + (aarch64_dup_lane_<vswap_widthi_name><mode>): Likewise. + (*aarch64_mul3_elt<mode>): Likewise. + (*aarch64_mul3_elt<vswap_width_name><mode>): Likewise. + (*aarch64_mul3_elt_to_64v2df): Likewise. + (*aarch64_mla_elt<mode>): Likewise. + (*aarch64_mla_elt_<vswap_width_name><mode>): Likewise. + (*aarch64_mls_elt<mode>): Likewise. + (*aarch64_mls_elt_<vswap_width_name><mode>): Likewise. + (*aarch64_fma4_elt<mode>): Likewise. + (*aarch64_fma4_elt_<vswap_width_name><mode>): Likewise. + (*aarch64_fma4_elt_to_64v2df): Likewise. + (*aarch64_fnma4_elt<mode>): Likewise. + (*aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise. + (*aarch64_fnma4_elt_to_64v2df): Likewise. + (aarch64_sq<r>dmulh_lane<mode>): Likewise. + (aarch64_sq<r>dmulh_laneq<mode>): Likewise. + (aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal): Likewise. + (aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal): Likewise. + (aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise. + (aarch64_sqdmull_lane<mode>_internal): Likewise. + (aarch64_sqdmull2_lane<mode>_internal): Likewise. + +2013-01-23 Alex Velenko <Alex.Velenko@arm.com> + + * config/aarch64/aarch64-simd.md + (aarch64_be_checked_get_lane<mode>): New define_expand. + * config/aarch64/aarch64-simd-builtins.def + (BUILTIN_VALL (GETLANE, be_checked_get_lane, 0)): + New builtin definition. + * config/aarch64/arm_neon.h: (__aarch64_vget_lane_any): + Use new safe be builtin. + +2014-01-23 Alex Velenko <Alex.Velenko@arm.com> + + * config/aarch64/aarch64-simd.md (aarch64_be_ld1<mode>): + New define_insn. + (aarch64_be_st1<mode>): Likewise. + (aarch_ld1<VALL:mode>): Define_expand modified. + (aarch_st1<VALL:mode>): Likewise. + * config/aarch64/aarch64.md (UNSPEC_LD1): New unspec definition. + (UNSPEC_ST1): Likewise. + +2014-01-23 David Holsgrove <david.holsgrove@xilinx.com> + + * config/microblaze/microblaze.md: Add trap insn and attribute + 2014-01-23 Dodji Seketeli <dodji@redhat.com> PR preprocessor/58580 @@ -79,8 +567,7 @@ PR rtl-optimization/59477 * lra-constraints.c (inherit_in_ebb): Process call for living hard - regs. Update reloads_num and potential_reload_hard_regs for all - insns. + regs. Update reloads_num and potential_reload_hard_regs for all insns. 2014-01-22 Tom Tromey <tromey@redhat.com> @@ -134,14 +621,13 @@ MAX_INLINE_INSNS_AUTO_LIMIT, INLINE_UNIT_GROWTH_LIMIT, RECURSIVE_INLINING, UNLIKELY_CALL, NOT_DECLARED_INLINED, OPTIMIZING_FOR_SIZE, ORIGINALLY_INDIRECT_CALL, - INDIRECT_UNKNOWN_CALL, USES_COMDAT_LOCAL. + INDIRECT_UNKNOWN_CALL, USES_COMDAT_LOCAL. Add CIF_FINAL_ERROR to UNSPECIFIED, BODY_NOT_AVAILABLE, FUNCTION_NOT_INLINABLE, OVERWRITABLE, MISMATCHED_ARGUMENTS, EH_PERSONALITY, NON_CALL_EXCEPTIONS, TARGET_OPTION_MISMATCH, OPTIMIZATION_MISMATCH. * tree-inline.c (expand_call_inline): Emit errors during - early_inlining if cgraph_inline_failed_type returns - CIF_FINAL_ERROR. + early_inlining if cgraph_inline_failed_type returns CIF_FINAL_ERROR. 2014-01-20 Uros Bizjak <ubizjak@gmail.com> |