diff options
Diffstat (limited to 'gcc/config/arm/arm.c')
| -rw-r--r-- | gcc/config/arm/arm.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index a838372b486..a8934c3e475 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2108,7 +2108,7 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond, Therefore, we calculate how many insns would be required to emit the constant starting from `best_start', and also starting from - zero (ie with bit 31 first to be output). If `best_start' doesn't + zero (i.e. with bit 31 first to be output). If `best_start' doesn't yield a shorter sequence, we may as well use zero. */ if (best_start != 0 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder) @@ -3133,7 +3133,7 @@ arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer, { rtx addend = XEXP (XEXP (x, 1), 1); - /* Don't allow ldrd post increment by register becuase it's hard + /* Don't allow ldrd post increment by register because it's hard to fixup invalid register choices. */ if (use_ldrd && GET_CODE (x) == POST_MODIFY @@ -5051,7 +5051,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, abort (); /* Loop over the operands and check that the memory references are - suitable (ie immediate offsets from the same base register). At + suitable (i.e. immediate offsets from the same base register). At the same time, extract the target register, and the memory offsets. */ for (i = 0; i < nops; i++) @@ -5280,7 +5280,7 @@ store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, abort (); /* Loop over the operands and check that the memory references are - suitable (ie immediate offsets from the same base register). At + suitable (i.e. immediate offsets from the same base register). At the same time, extract the target register, and the memory offsets. */ for (i = 0; i < nops; i++) @@ -8844,7 +8844,7 @@ output_return_instruction (rtx operand, int really_return, int reverse) const char * return_reg; /* If we do not have any special requirements for function exit - (eg interworking, or ISR) then we can load the return address + (e.g. interworking, or ISR) then we can load the return address directly into the PC. Otherwise we must load it into LR. */ if (really_return && ! TARGET_INTERWORK) @@ -9408,7 +9408,7 @@ arm_output_epilogue (rtx sibling) { if (saved_regs_mask & (1 << SP_REGNUM)) /* Note - write back to the stack register is not enabled - (ie "ldmfd sp!..."). We know that the stack pointer is + (i.e. "ldmfd sp!..."). We know that the stack pointer is in the list of registers and if we add writeback the instruction becomes UNPREDICTABLE. */ print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask); @@ -10422,7 +10422,7 @@ arm_print_operand (FILE *stream, rtx x, int code) return; case 'D': - /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever + /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever want to do that. */ if (x == const_true_rtx) abort (); @@ -11002,7 +11002,7 @@ arm_final_prescan_insn (rtx insn) else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) fail = TRUE; } - /* Fail if a conditional return is undesirable (eg on a + /* Fail if a conditional return is undesirable (e.g. on a StrongARM), but still allow this if optimizing for size. */ else if (GET_CODE (scanbody) == RETURN && !use_return_insn (TRUE, NULL) @@ -11026,7 +11026,7 @@ arm_final_prescan_insn (rtx insn) } } else - fail = TRUE; /* Unrecognized jump (eg epilogue). */ + fail = TRUE; /* Unrecognized jump (e.g. epilogue). */ break; @@ -12650,7 +12650,7 @@ thumb_unexpanded_epilogue (void) size = GET_MODE_SIZE (mode); /* The prolog may have pushed some high registers to use as - work registers. eg the testsuite file: + work registers. e.g. the testsuite file: gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c compiles to produce: push {r4, r5, r6, r7, lr} |