diff options
Diffstat (limited to 'gcc/config/arm/arm.md')
| -rw-r--r-- | gcc/config/arm/arm.md | 1176 |
1 files changed, 668 insertions, 508 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 83a3cf41252..7253f0c1517 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1,6 +1,6 @@ ;;- Machine description for ARM for GNU compiler ;; Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000, -;; 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. +;; 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. ;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) ;; and Martin Simmons (@harleqn.co.uk). ;; More major hacks by Richard Earnshaw (rearnsha@arm.com). @@ -93,6 +93,8 @@ (UNSPEC_TLS 20) ; A symbol that has been treated properly for TLS usage. (UNSPEC_PIC_LABEL 21) ; A label used for PIC access that does not appear in the ; instruction stream. + (UNSPEC_STACK_ALIGN 20) ; Doubleword aligned stack pointer. Used to + ; generate correct unwind information. ] ) @@ -297,6 +299,10 @@ (define_attr "far_jump" "yes,no" (const_string "no")) +;; The number of machine instructions this pattern expands to. +;; Used for Thumb-2 conditional execution. +(define_attr "ce_count" "" (const_int 1)) + ;;--------------------------------------------------------------------------- ;; Mode macros @@ -368,7 +374,7 @@ DONE; } - if (TARGET_THUMB) + if (TARGET_THUMB1) { if (GET_CODE (operands[1]) != REG) operands[1] = force_reg (SImode, operands[1]); @@ -378,13 +384,13 @@ " ) -(define_insn "*thumb_adddi3" +(define_insn "*thumb1_adddi3" [(set (match_operand:DI 0 "register_operand" "=l") (plus:DI (match_operand:DI 1 "register_operand" "%0") (match_operand:DI 2 "register_operand" "l"))) (clobber (reg:CC CC_REGNUM)) ] - "TARGET_THUMB" + "TARGET_THUMB1" "add\\t%Q0, %Q0, %Q2\;adc\\t%R0, %R0, %R2" [(set_attr "length" "4")] ) @@ -394,9 +400,9 @@ (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0") (match_operand:DI 2 "s_register_operand" "r, 0"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" "#" - "TARGET_ARM && reload_completed" + "TARGET_32BIT && reload_completed" [(parallel [(set (reg:CC_C CC_REGNUM) (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1))) @@ -422,9 +428,9 @@ (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "r,0"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" "#" - "TARGET_ARM && reload_completed" + "TARGET_32BIT && reload_completed" [(parallel [(set (reg:CC_C CC_REGNUM) (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1))) @@ -451,9 +457,9 @@ (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "r,0"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" + "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" "#" - "TARGET_ARM && reload_completed" + "TARGET_32BIT && reload_completed" [(parallel [(set (reg:CC_C CC_REGNUM) (compare:CC_C (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1))) @@ -478,7 +484,7 @@ (match_operand:SI 2 "reg_or_int_operand" "")))] "TARGET_EITHER" " - if (TARGET_ARM && GET_CODE (operands[2]) == CONST_INT) + if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT) { arm_split_constant (PLUS, SImode, NULL_RTX, INTVAL (operands[2]), operands[0], operands[1], @@ -495,7 +501,7 @@ (set (match_operand:SI 0 "arm_general_register_operand" "") (plus:SI (match_operand:SI 1 "arm_general_register_operand" "") (match_operand:SI 2 "const_int_operand" "")))] - "TARGET_ARM && + "TARGET_32BIT && !(const_ok_for_arm (INTVAL (operands[2])) || const_ok_for_arm (-INTVAL (operands[2]))) && const_ok_for_arm (~INTVAL (operands[2]))" @@ -508,12 +514,12 @@ [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (plus:SI (match_operand:SI 1 "s_register_operand" "%r,r,r") (match_operand:SI 2 "reg_or_int_operand" "rI,L,?n")))] - "TARGET_ARM" + "TARGET_32BIT" "@ add%?\\t%0, %1, %2 sub%?\\t%0, %1, #%n2 #" - "TARGET_ARM && + "TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT && !(const_ok_for_arm (INTVAL (operands[2])) || const_ok_for_arm (-INTVAL (operands[2])))" @@ -532,11 +538,11 @@ ;; register. Trying to reload it will always fail catastrophically, ;; so never allow those alternatives to match if reloading is needed. -(define_insn "*thumb_addsi3" +(define_insn "*thumb1_addsi3" [(set (match_operand:SI 0 "register_operand" "=l,l,l,*r,*h,l,!k") (plus:SI (match_operand:SI 1 "register_operand" "%0,0,l,*0,*0,!k,!k") (match_operand:SI 2 "nonmemory_operand" "I,J,lL,*h,*r,!M,!O")))] - "TARGET_THUMB" + "TARGET_THUMB1" "* static const char * const asms[] = { @@ -564,13 +570,14 @@ (match_operand:SI 1 "const_int_operand" "")) (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI SP_REGNUM)))] - "TARGET_THUMB + "TARGET_THUMB1 && (unsigned HOST_WIDE_INT) (INTVAL (operands[1])) < 1024 && (INTVAL (operands[1]) & 3) == 0" [(set (match_dup 0) (plus:SI (reg:SI SP_REGNUM) (match_dup 1)))] "" ) +;; ??? Make Thumb-2 variants which prefer low regs (define_insn "*addsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV @@ -579,10 +586,10 @@ (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_ARM" + "TARGET_32BIT" "@ - add%?s\\t%0, %1, %2 - sub%?s\\t%0, %1, #%n2" + add%.\\t%0, %1, %2 + sub%.\\t%0, %1, #%n2" [(set_attr "conds" "set")] ) @@ -592,7 +599,7 @@ (plus:SI (match_operand:SI 0 "s_register_operand" "r, r") (match_operand:SI 1 "arm_add_operand" "rI,L")) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "@ cmn%?\\t%0, %1 cmp%?\\t%0, #%n1" @@ -604,7 +611,7 @@ (compare:CC_Z (neg:SI (match_operand:SI 0 "s_register_operand" "r")) (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_ARM" + "TARGET_32BIT" "cmn%?\\t%1, %0" [(set_attr "conds" "set")] ) @@ -619,10 +626,10 @@ (set (match_operand:SI 0 "s_register_operand" "=r,r") (plus:SI (match_dup 1) (match_operand:SI 3 "arm_addimm_operand" "L,I")))] - "TARGET_ARM && INTVAL (operands[2]) == -INTVAL (operands[3])" + "TARGET_32BIT && INTVAL (operands[2]) == -INTVAL (operands[3])" "@ - sub%?s\\t%0, %1, %2 - add%?s\\t%0, %1, #%n2" + sub%.\\t%0, %1, %2 + add%.\\t%0, %1, #%n2" [(set_attr "conds" "set")] ) @@ -646,7 +653,7 @@ [(match_dup 2) (const_int 0)]) (match_operand 4 "" "") (match_operand 5 "" "")))] - "TARGET_ARM && peep2_reg_dead_p (3, operands[2])" + "TARGET_32BIT && peep2_reg_dead_p (3, operands[2])" [(parallel[ (set (match_dup 2) (compare:CC @@ -675,10 +682,10 @@ (match_dup 1))) (set (match_operand:SI 0 "s_register_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_ARM" + "TARGET_32BIT" "@ - add%?s\\t%0, %1, %2 - sub%?s\\t%0, %1, #%n2" + add%.\\t%0, %1, %2 + sub%.\\t%0, %1, #%n2" [(set_attr "conds" "set")] ) @@ -690,10 +697,10 @@ (match_dup 2))) (set (match_operand:SI 0 "s_register_operand" "=r,r") (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_ARM" + "TARGET_32BIT" "@ - add%?s\\t%0, %1, %2 - sub%?s\\t%0, %1, #%n2" + add%.\\t%0, %1, %2 + sub%.\\t%0, %1, #%n2" [(set_attr "conds" "set")] ) @@ -703,7 +710,7 @@ (plus:SI (match_operand:SI 0 "s_register_operand" "r,r") (match_operand:SI 1 "arm_add_operand" "rI,L")) (match_dup 0)))] - "TARGET_ARM" + "TARGET_32BIT" "@ cmn%?\\t%0, %1 cmp%?\\t%0, #%n1" @@ -716,7 +723,7 @@ (plus:SI (match_operand:SI 0 "s_register_operand" "r,r") (match_operand:SI 1 "arm_add_operand" "rI,L")) (match_dup 1)))] - "TARGET_ARM" + "TARGET_32BIT" "@ cmn%?\\t%0, %1 cmp%?\\t%0, #%n1" @@ -728,7 +735,7 @@ (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) (plus:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rI"))))] - "TARGET_ARM" + "TARGET_32BIT" "adc%?\\t%0, %1, %2" [(set_attr "conds" "use")] ) @@ -741,7 +748,7 @@ [(match_operand:SI 3 "s_register_operand" "r") (match_operand:SI 4 "reg_or_int_operand" "rM")]) (match_operand:SI 1 "s_register_operand" "r"))))] - "TARGET_ARM" + "TARGET_32BIT" "adc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use") (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") @@ -754,7 +761,7 @@ (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rI")) (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] - "TARGET_ARM" + "TARGET_32BIT" "adc%?\\t%0, %1, %2" [(set_attr "conds" "use")] ) @@ -764,7 +771,7 @@ (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) (match_operand:SI 1 "s_register_operand" "r")) (match_operand:SI 2 "arm_rhs_operand" "rI")))] - "TARGET_ARM" + "TARGET_32BIT" "adc%?\\t%0, %1, %2" [(set_attr "conds" "use")] ) @@ -774,12 +781,21 @@ (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) (match_operand:SI 2 "arm_rhs_operand" "rI")) (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_ARM" + "TARGET_32BIT" "adc%?\\t%0, %1, %2" [(set_attr "conds" "use")] ) -(define_insn "incscc" +(define_expand "incscc" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") + (plus:SI (match_operator:SI 2 "arm_comparison_operator" + [(match_operand:CC 3 "cc_register" "") (const_int 0)]) + (match_operand:SI 1 "s_register_operand" "0,?r")))] + "TARGET_32BIT" + "" +) + +(define_insn "*arm_incscc" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (plus:SI (match_operator:SI 2 "arm_comparison_operator" [(match_operand:CC 3 "cc_register" "") (const_int 0)]) @@ -799,7 +815,7 @@ (match_operand:SI 2 "s_register_operand" "")) (const_int -1))) (clobber (match_operand:SI 3 "s_register_operand" ""))] - "TARGET_ARM" + "TARGET_32BIT" [(set (match_dup 3) (match_dup 1)) (set (match_dup 0) (not:SI (ashift:SI (match_dup 3) (match_dup 2))))] " @@ -810,7 +826,7 @@ [(set (match_operand:SF 0 "s_register_operand" "") (plus:SF (match_operand:SF 1 "s_register_operand" "") (match_operand:SF 2 "arm_float_add_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" " if (TARGET_MAVERICK && !cirrus_fp_register (operands[2], SFmode)) @@ -821,7 +837,7 @@ [(set (match_operand:DF 0 "s_register_operand" "") (plus:DF (match_operand:DF 1 "s_register_operand" "") (match_operand:DF 2 "arm_float_add_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" " if (TARGET_MAVERICK && !cirrus_fp_register (operands[2], DFmode)) @@ -837,7 +853,7 @@ "TARGET_EITHER" " if (TARGET_HARD_FLOAT && TARGET_MAVERICK - && TARGET_ARM + && TARGET_32BIT && cirrus_fp_register (operands[0], DImode) && cirrus_fp_register (operands[1], DImode)) { @@ -845,7 +861,7 @@ DONE; } - if (TARGET_THUMB) + if (TARGET_THUMB1) { if (GET_CODE (operands[1]) != REG) operands[1] = force_reg (SImode, operands[1]); @@ -860,7 +876,7 @@ (minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0") (match_operand:DI 2 "s_register_operand" "r,0,0"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" + "TARGET_32BIT" "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2" [(set_attr "conds" "clob") (set_attr "length" "8")] @@ -871,7 +887,7 @@ (minus:DI (match_operand:DI 1 "register_operand" "0") (match_operand:DI 2 "register_operand" "l"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_THUMB" + "TARGET_THUMB1" "sub\\t%Q0, %Q0, %Q2\;sbc\\t%R0, %R0, %R2" [(set_attr "length" "4")] ) @@ -882,7 +898,7 @@ (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" + "TARGET_32BIT" "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, #0" [(set_attr "conds" "clob") (set_attr "length" "8")] @@ -894,7 +910,7 @@ (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" + "TARGET_32BIT" "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, %2, asr #31" [(set_attr "conds" "clob") (set_attr "length" "8")] @@ -931,8 +947,8 @@ (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r")))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" - "subs\\t%Q0, %1, %2\;rsc\\t%R0, %1, %1" + "TARGET_32BIT" + "subs\\t%Q0, %1, %2\;sbc\\t%R0, %1, %1" [(set_attr "conds" "clob") (set_attr "length" "8")] ) @@ -945,37 +961,38 @@ " if (GET_CODE (operands[1]) == CONST_INT) { - if (TARGET_ARM) + if (TARGET_32BIT) { arm_split_constant (MINUS, SImode, NULL_RTX, INTVAL (operands[1]), operands[0], operands[2], optimize && !no_new_pseudos); DONE; } - else /* TARGET_THUMB */ + else /* TARGET_THUMB1 */ operands[1] = force_reg (SImode, operands[1]); } " ) -(define_insn "*thumb_subsi3_insn" +(define_insn "*thumb1_subsi3_insn" [(set (match_operand:SI 0 "register_operand" "=l") (minus:SI (match_operand:SI 1 "register_operand" "l") (match_operand:SI 2 "register_operand" "l")))] - "TARGET_THUMB" + "TARGET_THUMB1" "sub\\t%0, %1, %2" [(set_attr "length" "2")] ) +; ??? Check Thumb-2 split length (define_insn_and_split "*arm_subsi3_insn" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,?n") (match_operand:SI 2 "s_register_operand" "r,r")))] - "TARGET_ARM" + "TARGET_32BIT" "@ rsb%?\\t%0, %2, %1 #" - "TARGET_ARM + "TARGET_32BIT && GET_CODE (operands[1]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[1]))" [(clobber (const_int 0))] @@ -993,7 +1010,7 @@ (set (match_operand:SI 0 "arm_general_register_operand" "") (minus:SI (match_operand:SI 1 "const_int_operand" "") (match_operand:SI 2 "arm_general_register_operand" "")))] - "TARGET_ARM + "TARGET_32BIT && !const_ok_for_arm (INTVAL (operands[1])) && const_ok_for_arm (~INTVAL (operands[1]))" [(set (match_dup 3) (match_dup 1)) @@ -1009,14 +1026,23 @@ (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r,r") (minus:SI (match_dup 1) (match_dup 2)))] - "TARGET_ARM" + "TARGET_32BIT" "@ - sub%?s\\t%0, %1, %2 - rsb%?s\\t%0, %2, %1" + sub%.\\t%0, %1, %2 + rsb%.\\t%0, %2, %1" [(set_attr "conds" "set")] ) -(define_insn "decscc" +(define_expand "decscc" + [(set (match_operand:SI 0 "s_register_operand" "=r,r") + (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") + (match_operator:SI 2 "arm_comparison_operator" + [(match_operand 3 "cc_register" "") (const_int 0)])))] + "TARGET_32BIT" + "" +) + +(define_insn "*arm_decscc" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (minus:SI (match_operand:SI 1 "s_register_operand" "0,?r") (match_operator:SI 2 "arm_comparison_operator" @@ -1033,7 +1059,7 @@ [(set (match_operand:SF 0 "s_register_operand" "") (minus:SF (match_operand:SF 1 "arm_float_rhs_operand" "") (match_operand:SF 2 "arm_float_rhs_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" " if (TARGET_MAVERICK) { @@ -1048,7 +1074,7 @@ [(set (match_operand:DF 0 "s_register_operand" "") (minus:DF (match_operand:DF 1 "arm_float_rhs_operand" "") (match_operand:DF 2 "arm_float_rhs_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" " if (TARGET_MAVERICK) { @@ -1075,7 +1101,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=&r,&r") (mult:SI (match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 1 "s_register_operand" "%?r,0")))] - "TARGET_ARM" + "TARGET_32BIT" "mul%?\\t%0, %2, %1" [(set_attr "insn" "mul") (set_attr "predicable" "yes")] @@ -1090,7 +1116,7 @@ [(set (match_operand:SI 0 "register_operand" "=&l,&l,&l") (mult:SI (match_operand:SI 1 "register_operand" "%l,*h,0") (match_operand:SI 2 "register_operand" "l,l,l")))] - "TARGET_THUMB" + "TARGET_THUMB1" "* if (which_alternative < 2) return \"mov\\t%0, %1\;mul\\t%0, %2\"; @@ -1110,7 +1136,7 @@ (set (match_operand:SI 0 "s_register_operand" "=&r,&r") (mult:SI (match_dup 2) (match_dup 1)))] "TARGET_ARM" - "mul%?s\\t%0, %2, %1" + "mul%.\\t%0, %2, %1" [(set_attr "conds" "set") (set_attr "insn" "muls")] ) @@ -1123,7 +1149,7 @@ (const_int 0))) (clobber (match_scratch:SI 0 "=&r,&r"))] "TARGET_ARM" - "mul%?s\\t%0, %2, %1" + "mul%.\\t%0, %2, %1" [(set_attr "conds" "set") (set_attr "insn" "muls")] ) @@ -1136,7 +1162,7 @@ (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r") (match_operand:SI 1 "s_register_operand" "%r,0,r,0")) (match_operand:SI 3 "s_register_operand" "?r,r,0,0")))] - "TARGET_ARM" + "TARGET_32BIT" "mla%?\\t%0, %2, %1, %3" [(set_attr "insn" "mla") (set_attr "predicable" "yes")] @@ -1154,7 +1180,7 @@ (plus:SI (mult:SI (match_dup 2) (match_dup 1)) (match_dup 3)))] "TARGET_ARM" - "mla%?s\\t%0, %2, %1, %3" + "mla%.\\t%0, %2, %1, %3" [(set_attr "conds" "set") (set_attr "insn" "mlas")] ) @@ -1169,7 +1195,7 @@ (const_int 0))) (clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))] "TARGET_ARM" - "mla%?s\\t%0, %2, %1, %3" + "mla%.\\t%0, %2, %1, %3" [(set_attr "conds" "set") (set_attr "insn" "mlas")] ) @@ -1183,7 +1209,7 @@ (sign_extend:DI (match_operand:SI 2 "s_register_operand" "%r")) (sign_extend:DI (match_operand:SI 3 "s_register_operand" "r"))) (match_operand:DI 1 "s_register_operand" "0")))] - "TARGET_ARM && arm_arch3m" + "TARGET_32BIT && arm_arch3m" "smlal%?\\t%Q0, %R0, %3, %2" [(set_attr "insn" "smlal") (set_attr "predicable" "yes")] @@ -1194,7 +1220,7 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r")) (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))] - "TARGET_ARM && arm_arch3m" + "TARGET_32BIT && arm_arch3m" "smull%?\\t%Q0, %R0, %1, %2" [(set_attr "insn" "smull") (set_attr "predicable" "yes")] @@ -1205,7 +1231,7 @@ (mult:DI (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%r")) (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))] - "TARGET_ARM && arm_arch3m" + "TARGET_32BIT && arm_arch3m" "umull%?\\t%Q0, %R0, %1, %2" [(set_attr "insn" "umull") (set_attr "predicable" "yes")] @@ -1220,7 +1246,7 @@ (zero_extend:DI (match_operand:SI 2 "s_register_operand" "%r")) (zero_extend:DI (match_operand:SI 3 "s_register_operand" "r"))) (match_operand:DI 1 "s_register_operand" "0")))] - "TARGET_ARM && arm_arch3m" + "TARGET_32BIT && arm_arch3m" "umlal%?\\t%Q0, %R0, %3, %2" [(set_attr "insn" "umlal") (set_attr "predicable" "yes")] @@ -1235,7 +1261,7 @@ (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r"))) (const_int 32)))) (clobber (match_scratch:SI 3 "=&r,&r"))] - "TARGET_ARM && arm_arch3m" + "TARGET_32BIT && arm_arch3m" "smull%?\\t%3, %0, %2, %1" [(set_attr "insn" "smull") (set_attr "predicable" "yes")] @@ -1250,7 +1276,7 @@ (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r"))) (const_int 32)))) (clobber (match_scratch:SI 3 "=&r,&r"))] - "TARGET_ARM && arm_arch3m" + "TARGET_32BIT && arm_arch3m" "umull%?\\t%3, %0, %2, %1" [(set_attr "insn" "umull") (set_attr "predicable" "yes")] @@ -1262,7 +1288,7 @@ (match_operand:HI 1 "s_register_operand" "%r")) (sign_extend:SI (match_operand:HI 2 "s_register_operand" "r"))))] - "TARGET_ARM && arm_arch5e" + "TARGET_DSP_MULTIPLY" "smulbb%?\\t%0, %1, %2" [(set_attr "insn" "smulxy") (set_attr "predicable" "yes")] @@ -1275,7 +1301,7 @@ (const_int 16)) (sign_extend:SI (match_operand:HI 2 "s_register_operand" "r"))))] - "TARGET_ARM && arm_arch5e" + "TARGET_DSP_MULTIPLY" "smultb%?\\t%0, %1, %2" [(set_attr "insn" "smulxy") (set_attr "predicable" "yes")] @@ -1288,7 +1314,7 @@ (ashiftrt:SI (match_operand:SI 2 "s_register_operand" "r") (const_int 16))))] - "TARGET_ARM && arm_arch5e" + "TARGET_DSP_MULTIPLY" "smulbt%?\\t%0, %1, %2" [(set_attr "insn" "smulxy") (set_attr "predicable" "yes")] @@ -1302,7 +1328,7 @@ (ashiftrt:SI (match_operand:SI 2 "s_register_operand" "r") (const_int 16))))] - "TARGET_ARM && arm_arch5e" + "TARGET_DSP_MULTIPLY" "smultt%?\\t%0, %1, %2" [(set_attr "insn" "smulxy") (set_attr "predicable" "yes")] @@ -1315,7 +1341,7 @@ (match_operand:HI 2 "s_register_operand" "%r")) (sign_extend:SI (match_operand:HI 3 "s_register_operand" "r")))))] - "TARGET_ARM && arm_arch5e" + "TARGET_DSP_MULTIPLY" "smlabb%?\\t%0, %2, %3, %1" [(set_attr "insn" "smlaxy") (set_attr "predicable" "yes")] @@ -1329,7 +1355,7 @@ (match_operand:HI 2 "s_register_operand" "%r")) (sign_extend:DI (match_operand:HI 3 "s_register_operand" "r")))))] - "TARGET_ARM && arm_arch5e" + "TARGET_DSP_MULTIPLY" "smlalbb%?\\t%Q0, %R0, %2, %3" [(set_attr "insn" "smlalxy") (set_attr "predicable" "yes")]) @@ -1338,7 +1364,7 @@ [(set (match_operand:SF 0 "s_register_operand" "") (mult:SF (match_operand:SF 1 "s_register_operand" "") (match_operand:SF 2 "arm_float_rhs_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" " if (TARGET_MAVERICK && !cirrus_fp_register (operands[2], SFmode)) @@ -1349,7 +1375,7 @@ [(set (match_operand:DF 0 "s_register_operand" "") (mult:DF (match_operand:DF 1 "s_register_operand" "") (match_operand:DF 2 "arm_float_rhs_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" " if (TARGET_MAVERICK && !cirrus_fp_register (operands[2], DFmode)) @@ -1362,14 +1388,14 @@ [(set (match_operand:SF 0 "s_register_operand" "") (div:SF (match_operand:SF 1 "arm_float_rhs_operand" "") (match_operand:SF 2 "arm_float_rhs_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "") (define_expand "divdf3" [(set (match_operand:DF 0 "s_register_operand" "") (div:DF (match_operand:DF 1 "arm_float_rhs_operand" "") (match_operand:DF 2 "arm_float_rhs_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "") ;; Modulo insns @@ -1378,14 +1404,14 @@ [(set (match_operand:SF 0 "s_register_operand" "") (mod:SF (match_operand:SF 1 "s_register_operand" "") (match_operand:SF 2 "arm_float_rhs_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "") (define_expand "moddf3" [(set (match_operand:DF 0 "s_register_operand" "") (mod:DF (match_operand:DF 1 "s_register_operand" "") (match_operand:DF 2 "arm_float_rhs_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "") ;; Boolean and,ior,xor insns @@ -1399,7 +1425,8 @@ (match_operator:DI 6 "logical_binary_operator" [(match_operand:DI 1 "s_register_operand" "") (match_operand:DI 2 "s_register_operand" "")]))] - "TARGET_ARM && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" + "TARGET_32BIT && reload_completed + && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)])) (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))] " @@ -1418,7 +1445,7 @@ (match_operator:DI 6 "logical_binary_operator" [(sign_extend:DI (match_operand:SI 2 "s_register_operand" "")) (match_operand:DI 1 "s_register_operand" "")]))] - "TARGET_ARM && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)])) (set (match_dup 3) (match_op_dup:SI 6 [(ashiftrt:SI (match_dup 2) (const_int 31)) @@ -1441,7 +1468,7 @@ (ior:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" "")) (match_operand:DI 1 "s_register_operand" "")))] - "TARGET_ARM && operands[0] != operands[1] && reload_completed" + "TARGET_32BIT && operands[0] != operands[1] && reload_completed" [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 2))) (set (match_dup 3) (match_dup 4))] " @@ -1460,7 +1487,7 @@ (xor:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" "")) (match_operand:DI 1 "s_register_operand" "")))] - "TARGET_ARM && operands[0] != operands[1] && reload_completed" + "TARGET_32BIT && operands[0] != operands[1] && reload_completed" [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 2))) (set (match_dup 3) (match_dup 4))] " @@ -1476,7 +1503,7 @@ [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (and:DI (match_operand:DI 1 "s_register_operand" "%0,r") (match_operand:DI 2 "s_register_operand" "r,r")))] - "TARGET_ARM && ! TARGET_IWMMXT" + "TARGET_32BIT && ! TARGET_IWMMXT" "#" [(set_attr "length" "8")] ) @@ -1486,9 +1513,9 @@ (and:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "?r,0")))] - "TARGET_ARM" + "TARGET_32BIT" "#" - "TARGET_ARM && reload_completed" + "TARGET_32BIT && reload_completed" ; The zero extend of operand 2 clears the high word of the output ; operand. [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 2))) @@ -1507,7 +1534,7 @@ (and:DI (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "?r,0")))] - "TARGET_ARM" + "TARGET_32BIT" "#" [(set_attr "length" "8")] ) @@ -1518,7 +1545,7 @@ (match_operand:SI 2 "reg_or_int_operand" "")))] "TARGET_EITHER" " - if (TARGET_ARM) + if (TARGET_32BIT) { if (GET_CODE (operands[2]) == CONST_INT) { @@ -1529,7 +1556,7 @@ DONE; } } - else /* TARGET_THUMB */ + else /* TARGET_THUMB1 */ { if (GET_CODE (operands[2]) != CONST_INT) operands[2] = force_reg (SImode, operands[2]); @@ -1574,16 +1601,17 @@ " ) +; ??? Check split length for Thumb-2 (define_insn_and_split "*arm_andsi3_insn" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r") (match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))] - "TARGET_ARM" + "TARGET_32BIT" "@ and%?\\t%0, %1, %2 bic%?\\t%0, %1, #%B2 #" - "TARGET_ARM + "TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT && !(const_ok_for_arm (INTVAL (operands[2])) || const_ok_for_arm (~INTVAL (operands[2])))" @@ -1597,11 +1625,11 @@ (set_attr "predicable" "yes")] ) -(define_insn "*thumb_andsi3_insn" +(define_insn "*thumb1_andsi3_insn" [(set (match_operand:SI 0 "register_operand" "=l") (and:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "register_operand" "l")))] - "TARGET_THUMB" + "TARGET_THUMB1" "and\\t%0, %0, %2" [(set_attr "length" "2")] ) @@ -1614,10 +1642,10 @@ (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r,r") (and:SI (match_dup 1) (match_dup 2)))] - "TARGET_ARM" + "TARGET_32BIT" "@ - and%?s\\t%0, %1, %2 - bic%?s\\t%0, %1, #%B2" + and%.\\t%0, %1, %2 + bic%.\\t%0, %1, #%B2" [(set_attr "conds" "set")] ) @@ -1628,10 +1656,10 @@ (match_operand:SI 1 "arm_not_operand" "rI,K")) (const_int 0))) (clobber (match_scratch:SI 2 "=X,r"))] - "TARGET_ARM" + "TARGET_32BIT" "@ tst%?\\t%0, %1 - bic%?s\\t%2, %0, #%B1" + bic%.\\t%2, %0, #%B1" [(set_attr "conds" "set")] ) @@ -1642,7 +1670,7 @@ (match_operand 1 "const_int_operand" "n") (match_operand 2 "const_int_operand" "n")) (const_int 0)))] - "TARGET_ARM + "TARGET_32BIT && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32 && INTVAL (operands[1]) > 0 && INTVAL (operands[1]) + (INTVAL (operands[2]) & 1) <= 8 @@ -1664,13 +1692,13 @@ (match_operand:SI 3 "const_int_operand" "n")) (const_int 0))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM + "TARGET_32BIT && (INTVAL (operands[3]) >= 0 && INTVAL (operands[3]) < 32 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)" "#" - "TARGET_ARM + "TARGET_32BIT && (INTVAL (operands[3]) >= 0 && INTVAL (operands[3]) < 32 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8 @@ -1687,7 +1715,10 @@ << INTVAL (operands[3])); " [(set_attr "conds" "clob") - (set_attr "length" "8")] + (set (attr "length") + (if_then_else (eq_attr "is_thumb" "yes") + (const_int 12) + (const_int 8)))] ) (define_insn_and_split "*ne_zeroextractsi_shifted" @@ -1786,7 +1817,7 @@ (match_operand:SI 2 "const_int_operand" "") (match_operand:SI 3 "const_int_operand" ""))) (clobber (match_operand:SI 4 "s_register_operand" ""))] - "TARGET_THUMB" + "TARGET_THUMB1" [(set (match_dup 4) (ashift:SI (match_dup 1) (match_dup 2))) (set (match_dup 0) (lshiftrt:SI (match_dup 4) (match_dup 3)))] "{ @@ -1797,6 +1828,7 @@ }" ) +;; ??? Use Thumb-2 has bitfield insert/extract instructions. (define_split [(set (match_operand:SI 0 "s_register_operand" "") (match_operator:SI 1 "shiftable_operator" @@ -1824,7 +1856,7 @@ (sign_extract:SI (match_operand:SI 1 "s_register_operand" "") (match_operand:SI 2 "const_int_operand" "") (match_operand:SI 3 "const_int_operand" "")))] - "TARGET_THUMB" + "TARGET_THUMB1" [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2))) (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 3)))] "{ @@ -1866,6 +1898,7 @@ ;;; the value before we insert. This loses some of the advantage of having ;;; this insv pattern, so this pattern needs to be reevalutated. +; ??? Use Thumb-2 bitfield insert/extract instructions (define_expand "insv" [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "") (match_operand:SI 1 "general_operand" "") @@ -2007,9 +2040,9 @@ [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (and:DI (not:DI (match_operand:DI 1 "s_register_operand" "r,0")) (match_operand:DI 2 "s_register_operand" "0,r")))] - "TARGET_ARM" + "TARGET_32BIT" "#" - "TARGET_ARM && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" + "TARGET_32BIT && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" [(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2))) (set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))] " @@ -2030,13 +2063,13 @@ (and:DI (not:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r"))) (match_operand:DI 1 "s_register_operand" "0,?r")))] - "TARGET_ARM" + "TARGET_32BIT" "@ bic%?\\t%Q0, %Q1, %2 #" ; (not (zero_extend ...)) allows us to just copy the high word from ; operand1 to operand0. - "TARGET_ARM + "TARGET_32BIT && reload_completed && operands[0] != operands[1]" [(set (match_dup 0) (and:SI (not:SI (match_dup 2)) (match_dup 1))) @@ -2057,9 +2090,9 @@ (and:DI (not:DI (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r"))) (match_operand:DI 1 "s_register_operand" "0,r")))] - "TARGET_ARM" + "TARGET_32BIT" "#" - "TARGET_ARM && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (and:SI (not:SI (match_dup 2)) (match_dup 1))) (set (match_dup 3) (and:SI (not:SI (ashiftrt:SI (match_dup 2) (const_int 31))) @@ -2079,7 +2112,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=r") (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_ARM" + "TARGET_32BIT" "bic%?\\t%0, %1, %2" [(set_attr "predicable" "yes")] ) @@ -2088,7 +2121,7 @@ [(set (match_operand:SI 0 "register_operand" "=l") (and:SI (not:SI (match_operand:SI 1 "register_operand" "l")) (match_operand:SI 2 "register_operand" "0")))] - "TARGET_THUMB" + "TARGET_THUMB1" "bic\\t%0, %0, %1" [(set_attr "length" "2")] ) @@ -2116,8 +2149,8 @@ (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (and:SI (not:SI (match_dup 2)) (match_dup 1)))] - "TARGET_ARM" - "bic%?s\\t%0, %1, %2" + "TARGET_32BIT" + "bic%.\\t%0, %1, %2" [(set_attr "conds" "set")] ) @@ -2128,8 +2161,8 @@ (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] - "TARGET_ARM" - "bic%?s\\t%0, %1, %2" + "TARGET_32BIT" + "bic%.\\t%0, %1, %2" [(set_attr "conds" "set")] ) @@ -2137,7 +2170,7 @@ [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (ior:DI (match_operand:DI 1 "s_register_operand" "%0,r") (match_operand:DI 2 "s_register_operand" "r,r")))] - "TARGET_ARM && ! TARGET_IWMMXT" + "TARGET_32BIT && ! TARGET_IWMMXT" "#" [(set_attr "length" "8") (set_attr "predicable" "yes")] @@ -2148,7 +2181,7 @@ (ior:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "0,?r")))] - "TARGET_ARM" + "TARGET_32BIT" "@ orr%?\\t%Q0, %Q1, %2 #" @@ -2161,7 +2194,7 @@ (ior:DI (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "?r,0")))] - "TARGET_ARM" + "TARGET_32BIT" "#" [(set_attr "length" "8") (set_attr "predicable" "yes")] @@ -2175,14 +2208,14 @@ " if (GET_CODE (operands[2]) == CONST_INT) { - if (TARGET_ARM) + if (TARGET_32BIT) { arm_split_constant (IOR, SImode, NULL_RTX, INTVAL (operands[2]), operands[0], operands[1], optimize && !no_new_pseudos); DONE; } - else /* TARGET_THUMB */ + else /* TARGET_THUMB1 */ operands [2] = force_reg (SImode, operands [2]); } " @@ -2192,11 +2225,11 @@ [(set (match_operand:SI 0 "s_register_operand" "=r,r") (ior:SI (match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "reg_or_int_operand" "rI,?n")))] - "TARGET_ARM" + "TARGET_32BIT" "@ orr%?\\t%0, %1, %2 #" - "TARGET_ARM + "TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[2]))" [(clobber (const_int 0))] @@ -2209,11 +2242,11 @@ (set_attr "predicable" "yes")] ) -(define_insn "*thumb_iorsi3" +(define_insn "*thumb1_iorsi3" [(set (match_operand:SI 0 "register_operand" "=l") (ior:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "register_operand" "l")))] - "TARGET_THUMB" + "TARGET_THUMB1" "orr\\t%0, %0, %2" [(set_attr "length" "2")] ) @@ -2223,7 +2256,7 @@ (set (match_operand:SI 0 "arm_general_register_operand" "") (ior:SI (match_operand:SI 1 "arm_general_register_operand" "") (match_operand:SI 2 "const_int_operand" "")))] - "TARGET_ARM + "TARGET_32BIT && !const_ok_for_arm (INTVAL (operands[2])) && const_ok_for_arm (~INTVAL (operands[2]))" [(set (match_dup 3) (match_dup 2)) @@ -2238,8 +2271,8 @@ (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (ior:SI (match_dup 1) (match_dup 2)))] - "TARGET_ARM" - "orr%?s\\t%0, %1, %2" + "TARGET_32BIT" + "orr%.\\t%0, %1, %2" [(set_attr "conds" "set")] ) @@ -2249,8 +2282,8 @@ (match_operand:SI 2 "arm_rhs_operand" "rI")) (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] - "TARGET_ARM" - "orr%?s\\t%0, %1, %2" + "TARGET_32BIT" + "orr%.\\t%0, %1, %2" [(set_attr "conds" "set")] ) @@ -2258,7 +2291,7 @@ [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (xor:DI (match_operand:DI 1 "s_register_operand" "%0,r") (match_operand:DI 2 "s_register_operand" "r,r")))] - "TARGET_ARM && !TARGET_IWMMXT" + "TARGET_32BIT && !TARGET_IWMMXT" "#" [(set_attr "length" "8") (set_attr "predicable" "yes")] @@ -2269,7 +2302,7 @@ (xor:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "0,?r")))] - "TARGET_ARM" + "TARGET_32BIT" "@ eor%?\\t%Q0, %Q1, %2 #" @@ -2282,7 +2315,7 @@ (xor:DI (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "?r,0")))] - "TARGET_ARM" + "TARGET_32BIT" "#" [(set_attr "length" "8") (set_attr "predicable" "yes")] @@ -2293,7 +2326,7 @@ (xor:SI (match_operand:SI 1 "s_register_operand" "") (match_operand:SI 2 "arm_rhs_operand" "")))] "TARGET_EITHER" - "if (TARGET_THUMB) + "if (TARGET_THUMB1) if (GET_CODE (operands[2]) == CONST_INT) operands[2] = force_reg (SImode, operands[2]); " @@ -2303,16 +2336,16 @@ [(set (match_operand:SI 0 "s_register_operand" "=r") (xor:SI (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "arm_rhs_operand" "rI")))] - "TARGET_ARM" + "TARGET_32BIT" "eor%?\\t%0, %1, %2" [(set_attr "predicable" "yes")] ) -(define_insn "*thumb_xorsi3" +(define_insn "*thumb1_xorsi3" [(set (match_operand:SI 0 "register_operand" "=l") (xor:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "register_operand" "l")))] - "TARGET_THUMB" + "TARGET_THUMB1" "eor\\t%0, %0, %2" [(set_attr "length" "2")] ) @@ -2324,8 +2357,8 @@ (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (xor:SI (match_dup 1) (match_dup 2)))] - "TARGET_ARM" - "eor%?s\\t%0, %1, %2" + "TARGET_32BIT" + "eor%.\\t%0, %1, %2" [(set_attr "conds" "set")] ) @@ -2334,7 +2367,7 @@ (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r") (match_operand:SI 1 "arm_rhs_operand" "rI")) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "teq%?\\t%0, %1" [(set_attr "conds" "set")] ) @@ -2349,7 +2382,7 @@ (not:SI (match_operand:SI 2 "arm_rhs_operand" ""))) (match_operand:SI 3 "arm_rhs_operand" ""))) (clobber (match_operand:SI 4 "s_register_operand" ""))] - "TARGET_ARM" + "TARGET_32BIT" [(set (match_dup 4) (and:SI (ior:SI (match_dup 1) (match_dup 2)) (not:SI (match_dup 3)))) (set (match_dup 0) (not:SI (match_dup 4)))] @@ -2361,12 +2394,15 @@ (and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "r,r,0") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")) (not:SI (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI"))))] - "TARGET_ARM" + "TARGET_32BIT" "orr%?\\t%0, %1, %2\;bic%?\\t%0, %0, %3" [(set_attr "length" "8") + (set_attr "ce_count" "2") (set_attr "predicable" "yes")] ) +; ??? Are these four splitters still beneficial when the Thumb-2 bitfield +; insns are available? (define_split [(set (match_operand:SI 0 "s_register_operand" "") (match_operator:SI 1 "logical_binary_operator" @@ -2378,7 +2414,7 @@ (match_operand:SI 6 "const_int_operand" "")) (match_operand:SI 7 "s_register_operand" "")])])) (clobber (match_operand:SI 8 "s_register_operand" ""))] - "TARGET_ARM + "TARGET_32BIT && GET_CODE (operands[1]) == GET_CODE (operands[9]) && INTVAL (operands[3]) == 32 - INTVAL (operands[6])" [(set (match_dup 8) @@ -2404,7 +2440,7 @@ (match_operand:SI 3 "const_int_operand" "") (match_operand:SI 4 "const_int_operand" ""))])) (clobber (match_operand:SI 8 "s_register_operand" ""))] - "TARGET_ARM + "TARGET_32BIT && GET_CODE (operands[1]) == GET_CODE (operands[9]) && INTVAL (operands[3]) == 32 - INTVAL (operands[6])" [(set (match_dup 8) @@ -2430,7 +2466,7 @@ (match_operand:SI 6 "const_int_operand" "")) (match_operand:SI 7 "s_register_operand" "")])])) (clobber (match_operand:SI 8 "s_register_operand" ""))] - "TARGET_ARM + "TARGET_32BIT && GET_CODE (operands[1]) == GET_CODE (operands[9]) && INTVAL (operands[3]) == 32 - INTVAL (operands[6])" [(set (match_dup 8) @@ -2456,7 +2492,7 @@ (match_operand:SI 3 "const_int_operand" "") (match_operand:SI 4 "const_int_operand" ""))])) (clobber (match_operand:SI 8 "s_register_operand" ""))] - "TARGET_ARM + "TARGET_32BIT && GET_CODE (operands[1]) == GET_CODE (operands[9]) && INTVAL (operands[3]) == 32 - INTVAL (operands[6])" [(set (match_dup 8) @@ -2480,7 +2516,7 @@ (smax:SI (match_operand:SI 1 "s_register_operand" "") (match_operand:SI 2 "arm_rhs_operand" ""))) (clobber (reg:CC CC_REGNUM))])] - "TARGET_ARM" + "TARGET_32BIT" " if (operands[2] == const0_rtx || operands[2] == constm1_rtx) { @@ -2496,7 +2532,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=r") (smax:SI (match_operand:SI 1 "s_register_operand" "r") (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "bic%?\\t%0, %1, %1, asr #31" [(set_attr "predicable" "yes")] ) @@ -2505,12 +2541,12 @@ [(set (match_operand:SI 0 "s_register_operand" "=r") (smax:SI (match_operand:SI 1 "s_register_operand" "r") (const_int -1)))] - "TARGET_ARM" + "TARGET_32BIT" "orr%?\\t%0, %1, %1, asr #31" [(set_attr "predicable" "yes")] ) -(define_insn "*smax_insn" +(define_insn "*arm_smax_insn" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (smax:SI (match_operand:SI 1 "s_register_operand" "%0,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,rI"))) @@ -2529,7 +2565,7 @@ (smin:SI (match_operand:SI 1 "s_register_operand" "") (match_operand:SI 2 "arm_rhs_operand" ""))) (clobber (reg:CC CC_REGNUM))])] - "TARGET_ARM" + "TARGET_32BIT" " if (operands[2] == const0_rtx) { @@ -2545,12 +2581,12 @@ [(set (match_operand:SI 0 "s_register_operand" "=r") (smin:SI (match_operand:SI 1 "s_register_operand" "r") (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "and%?\\t%0, %1, %1, asr #31" [(set_attr "predicable" "yes")] ) -(define_insn "*smin_insn" +(define_insn "*arm_smin_insn" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (smin:SI (match_operand:SI 1 "s_register_operand" "%0,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,rI"))) @@ -2563,7 +2599,17 @@ (set_attr "length" "8,12")] ) -(define_insn "umaxsi3" +(define_expand "umaxsi3" + [(parallel [ + (set (match_operand:SI 0 "s_register_operand" "") + (umax:SI (match_operand:SI 1 "s_register_operand" "") + (match_operand:SI 2 "arm_rhs_operand" ""))) + (clobber (reg:CC CC_REGNUM))])] + "TARGET_32BIT" + "" +) + +(define_insn "*arm_umaxsi3" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) @@ -2577,7 +2623,17 @@ (set_attr "length" "8,8,12")] ) -(define_insn "uminsi3" +(define_expand "uminsi3" + [(parallel [ + (set (match_operand:SI 0 "s_register_operand" "") + (umin:SI (match_operand:SI 1 "s_register_operand" "") + (match_operand:SI 2 "arm_rhs_operand" ""))) + (clobber (reg:CC CC_REGNUM))])] + "TARGET_32BIT" + "" +) + +(define_insn "*arm_uminsi3" [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) @@ -2597,17 +2653,22 @@ [(match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "s_register_operand" "r")])) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" + "TARGET_32BIT" "* operands[3] = gen_rtx_fmt_ee (minmax_code (operands[3]), SImode, operands[1], operands[2]); output_asm_insn (\"cmp\\t%1, %2\", operands); + if (TARGET_THUMB2) + output_asm_insn (\"ite\t%d3\", operands); output_asm_insn (\"str%d3\\t%1, %0\", operands); output_asm_insn (\"str%D3\\t%2, %0\", operands); return \"\"; " [(set_attr "conds" "clob") - (set_attr "length" "12") + (set (attr "length") + (if_then_else (eq_attr "is_thumb" "yes") + (const_int 14) + (const_int 12))) (set_attr "type" "store1")] ) @@ -2621,22 +2682,38 @@ (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) (match_operand:SI 1 "s_register_operand" "0,?r")])) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM && !arm_eliminable_register (operands[1])" + "TARGET_32BIT && !arm_eliminable_register (operands[1])" "* { enum rtx_code code = GET_CODE (operands[4]); + bool need_else; + + if (which_alternative != 0 || operands[3] != const0_rtx + || (code != PLUS && code != MINUS && code != IOR && code != XOR)) + need_else = true; + else + need_else = false; operands[5] = gen_rtx_fmt_ee (minmax_code (operands[5]), SImode, operands[2], operands[3]); output_asm_insn (\"cmp\\t%2, %3\", operands); + if (TARGET_THUMB2) + { + if (need_else) + output_asm_insn (\"ite\\t%d5\", operands); + else + output_asm_insn (\"it\\t%d5\", operands); + } output_asm_insn (\"%i4%d5\\t%0, %1, %2\", operands); - if (which_alternative != 0 || operands[3] != const0_rtx - || (code != PLUS && code != MINUS && code != IOR && code != XOR)) + if (need_else) output_asm_insn (\"%i4%D5\\t%0, %1, %3\", operands); return \"\"; }" [(set_attr "conds" "clob") - (set_attr "length" "12")] + (set (attr "length") + (if_then_else (eq_attr "is_thumb" "yes") + (const_int 14) + (const_int 12)))] ) @@ -2646,7 +2723,7 @@ [(set (match_operand:DI 0 "s_register_operand" "") (ashift:DI (match_operand:DI 1 "s_register_operand" "") (match_operand:SI 2 "reg_or_int_operand" "")))] - "TARGET_ARM" + "TARGET_32BIT" " if (GET_CODE (operands[2]) == CONST_INT) { @@ -2671,7 +2748,7 @@ (ashift:DI (match_operand:DI 1 "s_register_operand" "?r,0") (const_int 1))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" + "TARGET_32BIT" "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1" [(set_attr "conds" "clob") (set_attr "length" "8")] @@ -2692,11 +2769,11 @@ " ) -(define_insn "*thumb_ashlsi3" +(define_insn "*thumb1_ashlsi3" [(set (match_operand:SI 0 "register_operand" "=l,l") (ashift:SI (match_operand:SI 1 "register_operand" "l,0") (match_operand:SI 2 "nonmemory_operand" "N,l")))] - "TARGET_THUMB" + "TARGET_THUMB1" "lsl\\t%0, %1, %2" [(set_attr "length" "2")] ) @@ -2705,7 +2782,7 @@ [(set (match_operand:DI 0 "s_register_operand" "") (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "") (match_operand:SI 2 "reg_or_int_operand" "")))] - "TARGET_ARM" + "TARGET_32BIT" " if (GET_CODE (operands[2]) == CONST_INT) { @@ -2730,7 +2807,7 @@ (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "?r,0") (const_int 1))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" + "TARGET_32BIT" "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" [(set_attr "conds" "clob") (set_attr "length" "8")] @@ -2748,11 +2825,11 @@ " ) -(define_insn "*thumb_ashrsi3" +(define_insn "*thumb1_ashrsi3" [(set (match_operand:SI 0 "register_operand" "=l,l") (ashiftrt:SI (match_operand:SI 1 "register_operand" "l,0") (match_operand:SI 2 "nonmemory_operand" "N,l")))] - "TARGET_THUMB" + "TARGET_THUMB1" "asr\\t%0, %1, %2" [(set_attr "length" "2")] ) @@ -2761,7 +2838,7 @@ [(set (match_operand:DI 0 "s_register_operand" "") (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "") (match_operand:SI 2 "reg_or_int_operand" "")))] - "TARGET_ARM" + "TARGET_32BIT" " if (GET_CODE (operands[2]) == CONST_INT) { @@ -2786,7 +2863,7 @@ (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "?r,0") (const_int 1))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" + "TARGET_32BIT" "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" [(set_attr "conds" "clob") (set_attr "length" "8")] @@ -2807,11 +2884,11 @@ " ) -(define_insn "*thumb_lshrsi3" +(define_insn "*thumb1_lshrsi3" [(set (match_operand:SI 0 "register_operand" "=l,l") (lshiftrt:SI (match_operand:SI 1 "register_operand" "l,0") (match_operand:SI 2 "nonmemory_operand" "N,l")))] - "TARGET_THUMB" + "TARGET_THUMB1" "lsr\\t%0, %1, %2" [(set_attr "length" "2")] ) @@ -2820,7 +2897,7 @@ [(set (match_operand:SI 0 "s_register_operand" "") (rotatert:SI (match_operand:SI 1 "s_register_operand" "") (match_operand:SI 2 "reg_or_int_operand" "")))] - "TARGET_ARM" + "TARGET_32BIT" " if (GET_CODE (operands[2]) == CONST_INT) operands[2] = GEN_INT ((32 - INTVAL (operands[2])) % 32); @@ -2839,13 +2916,13 @@ (match_operand:SI 2 "arm_rhs_operand" "")))] "TARGET_EITHER" " - if (TARGET_ARM) + if (TARGET_32BIT) { if (GET_CODE (operands[2]) == CONST_INT && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) operands[2] = GEN_INT (INTVAL (operands[2]) % 32); } - else /* TARGET_THUMB */ + else /* TARGET_THUMB1 */ { if (GET_CODE (operands [2]) == CONST_INT) operands [2] = force_reg (SImode, operands[2]); @@ -2853,11 +2930,11 @@ " ) -(define_insn "*thumb_rotrsi3" +(define_insn "*thumb1_rotrsi3" [(set (match_operand:SI 0 "register_operand" "=l") (rotatert:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "register_operand" "l")))] - "TARGET_THUMB" + "TARGET_THUMB1" "ror\\t%0, %0, %2" [(set_attr "length" "2")] ) @@ -2867,8 +2944,8 @@ (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "reg_or_int_operand" "rM")]))] - "TARGET_ARM" - "mov%?\\t%0, %1%S3" + "TARGET_32BIT" + "* return arm_output_shift(operands, 0);" [(set_attr "predicable" "yes") (set_attr "shift" "1") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") @@ -2884,8 +2961,8 @@ (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (match_op_dup 3 [(match_dup 1) (match_dup 2)]))] - "TARGET_ARM" - "mov%?s\\t%0, %1%S3" + "TARGET_32BIT" + "* return arm_output_shift(operands, 1);" [(set_attr "conds" "set") (set_attr "shift" "1") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") @@ -2900,13 +2977,13 @@ (match_operand:SI 2 "arm_rhs_operand" "rM")]) (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] - "TARGET_ARM" - "mov%?s\\t%0, %1%S3" + "TARGET_32BIT" + "* return arm_output_shift(operands, 1);" [(set_attr "conds" "set") (set_attr "shift" "1")] ) -(define_insn "*notsi_shiftsi" +(define_insn "*arm_notsi_shiftsi" [(set (match_operand:SI 0 "s_register_operand" "=r") (not:SI (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r") @@ -2920,7 +2997,7 @@ (const_string "alu_shift_reg")))] ) -(define_insn "*notsi_shiftsi_compare0" +(define_insn "*arm_notsi_shiftsi_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r") @@ -2929,7 +3006,7 @@ (set (match_operand:SI 0 "s_register_operand" "=r") (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))] "TARGET_ARM" - "mvn%?s\\t%0, %1%S3" + "mvn%.\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") @@ -2937,7 +3014,7 @@ (const_string "alu_shift_reg")))] ) -(define_insn "*not_shiftsi_compare0_scratch" +(define_insn "*arm_not_shiftsi_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r") @@ -2945,7 +3022,7 @@ (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "TARGET_ARM" - "mvn%?s\\t%0, %1%S3" + "mvn%.\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") @@ -2963,7 +3040,7 @@ (set (match_operand:SI 0 "register_operand" "") (lshiftrt:SI (match_dup 4) (match_operand:SI 3 "const_int_operand" "")))] - "TARGET_THUMB" + "TARGET_THUMB1" " { HOST_WIDE_INT lshift = 32 - INTVAL (operands[2]) - INTVAL (operands[3]); @@ -2992,7 +3069,7 @@ (clobber (reg:CC CC_REGNUM))])] "TARGET_EITHER" " - if (TARGET_THUMB) + if (TARGET_THUMB1) { if (GET_CODE (operands[1]) != REG) operands[1] = force_reg (SImode, operands[1]); @@ -3012,11 +3089,11 @@ (set_attr "length" "8")] ) -(define_insn "*thumb_negdi2" +(define_insn "*thumb1_negdi2" [(set (match_operand:DI 0 "register_operand" "=&l") (neg:DI (match_operand:DI 1 "register_operand" "l"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_THUMB" + "TARGET_THUMB1" "mov\\t%R0, #0\;neg\\t%Q0, %Q1\;sbc\\t%R0, %R1" [(set_attr "length" "6")] ) @@ -3031,15 +3108,15 @@ (define_insn "*arm_negsi2" [(set (match_operand:SI 0 "s_register_operand" "=r") (neg:SI (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_ARM" + "TARGET_32BIT" "rsb%?\\t%0, %1, #0" [(set_attr "predicable" "yes")] ) -(define_insn "*thumb_negsi2" +(define_insn "*thumb1_negsi2" [(set (match_operand:SI 0 "register_operand" "=l") (neg:SI (match_operand:SI 1 "register_operand" "l")))] - "TARGET_THUMB" + "TARGET_THUMB1" "neg\\t%0, %1" [(set_attr "length" "2")] ) @@ -3047,14 +3124,14 @@ (define_expand "negsf2" [(set (match_operand:SF 0 "s_register_operand" "") (neg:SF (match_operand:SF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "" ) (define_expand "negdf2" [(set (match_operand:DF 0 "s_register_operand" "") (neg:DF (match_operand:DF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "") ;; abssi2 doesn't really clobber the condition codes if a different register @@ -3069,7 +3146,7 @@ (clobber (match_dup 2))])] "TARGET_EITHER" " - if (TARGET_THUMB) + if (TARGET_THUMB1) operands[2] = gen_rtx_SCRATCH (SImode); else operands[2] = gen_rtx_REG (CCmode, CC_REGNUM); @@ -3089,13 +3166,13 @@ (set_attr "length" "8")] ) -(define_insn_and_split "*thumb_abssi2" +(define_insn_and_split "*thumb1_abssi2" [(set (match_operand:SI 0 "s_register_operand" "=l") (abs:SI (match_operand:SI 1 "s_register_operand" "l"))) (clobber (match_scratch:SI 2 "=&l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "#" - "TARGET_THUMB && reload_completed" + "TARGET_THUMB1 && reload_completed" [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2))) (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 2)))] @@ -3117,13 +3194,13 @@ (set_attr "length" "8")] ) -(define_insn_and_split "*thumb_neg_abssi2" +(define_insn_and_split "*thumb1_neg_abssi2" [(set (match_operand:SI 0 "s_register_operand" "=l") (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "l")))) (clobber (match_scratch:SI 2 "=&l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "#" - "TARGET_THUMB && reload_completed" + "TARGET_THUMB1 && reload_completed" [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1))) (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 2)))] @@ -3134,33 +3211,33 @@ (define_expand "abssf2" [(set (match_operand:SF 0 "s_register_operand" "") (abs:SF (match_operand:SF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" "") (define_expand "absdf2" [(set (match_operand:DF 0 "s_register_operand" "") (abs:DF (match_operand:DF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" "") (define_expand "sqrtsf2" [(set (match_operand:SF 0 "s_register_operand" "") (sqrt:SF (match_operand:SF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "") (define_expand "sqrtdf2" [(set (match_operand:DF 0 "s_register_operand" "") (sqrt:DF (match_operand:DF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "") (define_insn_and_split "one_cmpldi2" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (not:DI (match_operand:DI 1 "s_register_operand" "?r,0")))] - "TARGET_ARM" + "TARGET_32BIT" "#" - "TARGET_ARM && reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (not:SI (match_dup 1))) (set (match_dup 2) (not:SI (match_dup 3)))] " @@ -3184,15 +3261,15 @@ (define_insn "*arm_one_cmplsi2" [(set (match_operand:SI 0 "s_register_operand" "=r") (not:SI (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_ARM" + "TARGET_32BIT" "mvn%?\\t%0, %1" [(set_attr "predicable" "yes")] ) -(define_insn "*thumb_one_cmplsi2" +(define_insn "*thumb1_one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "=l") (not:SI (match_operand:SI 1 "register_operand" "l")))] - "TARGET_THUMB" + "TARGET_THUMB1" "mvn\\t%0, %1" [(set_attr "length" "2")] ) @@ -3203,8 +3280,8 @@ (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (not:SI (match_dup 1)))] - "TARGET_ARM" - "mvn%?s\\t%0, %1" + "TARGET_32BIT" + "mvn%.\\t%0, %1" [(set_attr "conds" "set")] ) @@ -3213,8 +3290,8 @@ (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] - "TARGET_ARM" - "mvn%?s\\t%0, %1" + "TARGET_32BIT" + "mvn%.\\t%0, %1" [(set_attr "conds" "set")] ) @@ -3223,7 +3300,7 @@ (define_expand "floatsisf2" [(set (match_operand:SF 0 "s_register_operand" "") (float:SF (match_operand:SI 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" " if (TARGET_MAVERICK) { @@ -3235,7 +3312,7 @@ (define_expand "floatsidf2" [(set (match_operand:DF 0 "s_register_operand" "") (float:DF (match_operand:SI 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" " if (TARGET_MAVERICK) { @@ -3247,7 +3324,7 @@ (define_expand "fix_truncsfsi2" [(set (match_operand:SI 0 "s_register_operand" "") (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" " if (TARGET_MAVERICK) { @@ -3263,7 +3340,7 @@ (define_expand "fix_truncdfsi2" [(set (match_operand:SI 0 "s_register_operand" "") (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" " if (TARGET_MAVERICK) { @@ -3280,13 +3357,20 @@ [(set (match_operand:SF 0 "s_register_operand" "") (float_truncate:SF (match_operand:DF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" "" ) ;; Zero and sign extension instructions. -(define_insn "zero_extendsidi2" +(define_expand "zero_extendsidi2" + [(set (match_operand:DI 0 "s_register_operand" "") + (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")))] + "TARGET_32BIT" + "" +) + +(define_insn "*arm_zero_extendsidi2" [(set (match_operand:DI 0 "s_register_operand" "=r") (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))] "TARGET_ARM" @@ -3300,13 +3384,20 @@ (set_attr "predicable" "yes")] ) -(define_insn "zero_extendqidi2" +(define_expand "zero_extendqidi2" + [(set (match_operand:DI 0 "s_register_operand" "") + (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))] + "TARGET_32BIT" + "" +) + +(define_insn "*arm_zero_extendqidi2" [(set (match_operand:DI 0 "s_register_operand" "=r,r") (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] "TARGET_ARM" "@ and%?\\t%Q0, %1, #255\;mov%?\\t%R0, #0 - ldr%?b\\t%Q0, %1\;mov%?\\t%R0, #0" + ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0" [(set_attr "length" "8") (set_attr "predicable" "yes") (set_attr "type" "*,load_byte") @@ -3314,7 +3405,14 @@ (set_attr "neg_pool_range" "*,4084")] ) -(define_insn "extendsidi2" +(define_expand "extendsidi2" + [(set (match_operand:DI 0 "s_register_operand" "") + (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")))] + "TARGET_32BIT" + "" +) + +(define_insn "*arm_extendsidi2" [(set (match_operand:DI 0 "s_register_operand" "=r") (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))] "TARGET_ARM" @@ -3338,7 +3436,7 @@ "TARGET_EITHER" " { - if ((TARGET_THUMB || arm_arch4) && GET_CODE (operands[1]) == MEM) + if ((TARGET_THUMB1 || arm_arch4) && GET_CODE (operands[1]) == MEM) { emit_insn (gen_rtx_SET (VOIDmode, operands[0], gen_rtx_ZERO_EXTEND (SImode, operands[1]))); @@ -3366,10 +3464,10 @@ }" ) -(define_insn "*thumb_zero_extendhisi2" +(define_insn "*thumb1_zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "=l") (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] - "TARGET_THUMB && !arm_arch6" + "TARGET_THUMB1 && !arm_arch6" "* rtx mem = XEXP (operands[1], 0); @@ -3408,10 +3506,10 @@ (set_attr "pool_range" "60")] ) -(define_insn "*thumb_zero_extendhisi2_v6" +(define_insn "*thumb1_zero_extendhisi2_v6" [(set (match_operand:SI 0 "register_operand" "=l,l") (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m")))] - "TARGET_THUMB && arm_arch6" + "TARGET_THUMB1 && arm_arch6" "* rtx mem; @@ -3459,7 +3557,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=r") (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_ARM && arm_arch4 && !arm_arch6" - "ldr%?h\\t%0, %1" + "ldr%(h%)\\t%0, %1" [(set_attr "type" "load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "256") @@ -3472,7 +3570,7 @@ "TARGET_ARM && arm_arch6" "@ uxth%?\\t%0, %1 - ldr%?h\\t%0, %1" + ldr%(h%)\\t%0, %1" [(set_attr "type" "alu_shift,load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") @@ -3483,7 +3581,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (zero_extend:SI (match_operand:HI 1 "s_register_operand" "r")) (match_operand:SI 2 "s_register_operand" "r")))] - "TARGET_ARM && arm_arch6" + "TARGET_INT_SIMD" "uxtah%?\\t%0, %2, %1" [(set_attr "type" "alu_shift") (set_attr "predicable" "yes")] @@ -3529,20 +3627,20 @@ " ) -(define_insn "*thumb_zero_extendqisi2" +(define_insn "*thumb1_zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "=l") (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] - "TARGET_THUMB && !arm_arch6" + "TARGET_THUMB1 && !arm_arch6" "ldrb\\t%0, %1" [(set_attr "length" "2") (set_attr "type" "load_byte") (set_attr "pool_range" "32")] ) -(define_insn "*thumb_zero_extendqisi2_v6" +(define_insn "*thumb1_zero_extendqisi2_v6" [(set (match_operand:SI 0 "register_operand" "=l,l") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,m")))] - "TARGET_THUMB && arm_arch6" + "TARGET_THUMB1 && arm_arch6" "@ uxtb\\t%0, %1 ldrb\\t%0, %1" @@ -3555,7 +3653,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=r") (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] "TARGET_ARM && !arm_arch6" - "ldr%?b\\t%0, %1\\t%@ zero_extendqisi2" + "ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" [(set_attr "type" "load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "4096") @@ -3567,8 +3665,8 @@ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] "TARGET_ARM && arm_arch6" "@ - uxtb%?\\t%0, %1 - ldr%?b\\t%0, %1\\t%@ zero_extendqisi2" + uxtb%(%)\\t%0, %1 + ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" [(set_attr "type" "alu_shift,load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "*,4096") @@ -3579,7 +3677,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (zero_extend:SI (match_operand:QI 1 "s_register_operand" "r")) (match_operand:SI 2 "s_register_operand" "r")))] - "TARGET_ARM && arm_arch6" + "TARGET_INT_SIMD" "uxtab%?\\t%0, %2, %1" [(set_attr "predicable" "yes") (set_attr "type" "alu_shift")] @@ -3589,7 +3687,7 @@ [(set (match_operand:SI 0 "s_register_operand" "") (zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 0))) (clobber (match_operand:SI 2 "s_register_operand" ""))] - "TARGET_ARM && (GET_CODE (operands[1]) != MEM) && ! BYTES_BIG_ENDIAN" + "TARGET_32BIT && (GET_CODE (operands[1]) != MEM) && ! BYTES_BIG_ENDIAN" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))] "" @@ -3599,7 +3697,7 @@ [(set (match_operand:SI 0 "s_register_operand" "") (zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 3))) (clobber (match_operand:SI 2 "s_register_operand" ""))] - "TARGET_ARM && (GET_CODE (operands[1]) != MEM) && BYTES_BIG_ENDIAN" + "TARGET_32BIT && (GET_CODE (operands[1]) != MEM) && BYTES_BIG_ENDIAN" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))] "" @@ -3609,7 +3707,7 @@ [(set (reg:CC_Z CC_REGNUM) (compare:CC_Z (match_operand:QI 0 "s_register_operand" "r") (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "tst\\t%0, #255" [(set_attr "conds" "set")] ) @@ -3626,9 +3724,9 @@ { if (GET_CODE (operands[1]) == MEM) { - if (TARGET_THUMB) + if (TARGET_THUMB1) { - emit_insn (gen_thumb_extendhisi2 (operands[0], operands[1])); + emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1])); DONE; } else if (arm_arch4) @@ -3650,8 +3748,8 @@ if (arm_arch6) { - if (TARGET_THUMB) - emit_insn (gen_thumb_extendhisi2 (operands[0], operands[1])); + if (TARGET_THUMB1) + emit_insn (gen_thumb1_extendhisi2 (operands[0], operands[1])); else emit_insn (gen_rtx_SET (VOIDmode, operands[0], gen_rtx_SIGN_EXTEND (SImode, operands[1]))); @@ -3664,11 +3762,11 @@ }" ) -(define_insn "thumb_extendhisi2" +(define_insn "thumb1_extendhisi2" [(set (match_operand:SI 0 "register_operand" "=l") (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))) (clobber (match_scratch:SI 2 "=&l"))] - "TARGET_THUMB && !arm_arch6" + "TARGET_THUMB1 && !arm_arch6" "* { rtx ops[4]; @@ -3725,11 +3823,11 @@ ;; we try to verify the operands. Fortunately, we don't really need ;; the early-clobber: we can always use operand 0 if operand 2 ;; overlaps the address. -(define_insn "*thumb_extendhisi2_insn_v6" +(define_insn "*thumb1_extendhisi2_insn_v6" [(set (match_operand:SI 0 "register_operand" "=l,l") (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m"))) (clobber (match_scratch:SI 2 "=X,l"))] - "TARGET_THUMB && arm_arch6" + "TARGET_THUMB1 && arm_arch6" "* { rtx ops[4]; @@ -3787,6 +3885,7 @@ (set_attr "pool_range" "*,1020")] ) +;; This pattern will only be used when ldsh is not available (define_expand "extendhisi2_mem" [(set (match_dup 2) (zero_extend:SI (match_operand:HI 1 "" ""))) (set (match_dup 3) @@ -3826,20 +3925,21 @@ [(set (match_operand:SI 0 "s_register_operand" "=r") (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_ARM && arm_arch4 && !arm_arch6" - "ldr%?sh\\t%0, %1" + "ldr%(sh%)\\t%0, %1" [(set_attr "type" "load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "256") (set_attr "neg_pool_range" "244")] ) +;; ??? Check Thumb-2 pool range (define_insn "*arm_extendhisi2_v6" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] - "TARGET_ARM && arm_arch6" + "TARGET_32BIT && arm_arch6" "@ sxth%?\\t%0, %1 - ldr%?sh\\t%0, %1" + ldr%(sh%)\\t%0, %1" [(set_attr "type" "alu_shift,load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") @@ -3850,7 +3950,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (sign_extend:SI (match_operand:HI 1 "s_register_operand" "r")) (match_operand:SI 2 "s_register_operand" "r")))] - "TARGET_ARM && arm_arch6" + "TARGET_INT_SIMD" "sxtah%?\\t%0, %2, %1" ) @@ -3879,11 +3979,11 @@ }" ) -(define_insn "*extendqihi_insn" +(define_insn "*arm_extendqihi_insn" [(set (match_operand:HI 0 "s_register_operand" "=r") (sign_extend:HI (match_operand:QI 1 "memory_operand" "Uq")))] "TARGET_ARM && arm_arch4" - "ldr%?sb\\t%0, %1" + "ldr%(sb%)\\t%0, %1" [(set_attr "type" "load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "256") @@ -3926,7 +4026,7 @@ [(set (match_operand:SI 0 "s_register_operand" "=r") (sign_extend:SI (match_operand:QI 1 "memory_operand" "Uq")))] "TARGET_ARM && arm_arch4 && !arm_arch6" - "ldr%?sb\\t%0, %1" + "ldr%(sb%)\\t%0, %1" [(set_attr "type" "load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "256") @@ -3939,7 +4039,7 @@ "TARGET_ARM && arm_arch6" "@ sxtb%?\\t%0, %1 - ldr%?sb\\t%0, %1" + ldr%(sb%)\\t%0, %1" [(set_attr "type" "alu_shift,load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") @@ -3950,16 +4050,16 @@ [(set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (sign_extend:SI (match_operand:QI 1 "s_register_operand" "r")) (match_operand:SI 2 "s_register_operand" "r")))] - "TARGET_ARM && arm_arch6" + "TARGET_INT_SIMD" "sxtab%?\\t%0, %2, %1" [(set_attr "type" "alu_shift") (set_attr "predicable" "yes")] ) -(define_insn "*thumb_extendqisi2" +(define_insn "*thumb1_extendqisi2" [(set (match_operand:SI 0 "register_operand" "=l,l") (sign_extend:SI (match_operand:QI 1 "memory_operand" "V,m")))] - "TARGET_THUMB && !arm_arch6" + "TARGET_THUMB1 && !arm_arch6" "* { rtx ops[3]; @@ -4034,10 +4134,10 @@ (set_attr "pool_range" "32,32")] ) -(define_insn "*thumb_extendqisi2_v6" +(define_insn "*thumb1_extendqisi2_v6" [(set (match_operand:SI 0 "register_operand" "=l,l,l") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "l,V,m")))] - "TARGET_THUMB && arm_arch6" + "TARGET_THUMB1 && arm_arch6" "* { rtx ops[3]; @@ -4117,7 +4217,7 @@ (define_expand "extendsfdf2" [(set (match_operand:DF 0 "s_register_operand" "") (float_extend:DF (match_operand:SF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" "" ) @@ -4223,7 +4323,7 @@ (define_split [(set (match_operand:ANY64 0 "arm_general_register_operand" "") (match_operand:ANY64 1 "const_double_operand" ""))] - "TARGET_ARM + "TARGET_32BIT && reload_completed && (arm_const_double_inline_cost (operands[1]) <= ((optimize_size || arm_ld_sched) ? 3 : 4))" @@ -4315,10 +4415,10 @@ ;;; ??? This was originally identical to the movdf_insn pattern. ;;; ??? The 'i' constraint looks funny, but it should always be replaced by ;;; thumb_reorg with a memory reference. -(define_insn "*thumb_movdi_insn" +(define_insn "*thumb1_movdi_insn" [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r") (match_operand:DI 1 "general_operand" "l, I,J,>,l,mi,l,*r"))] - "TARGET_THUMB + "TARGET_THUMB1 && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && ( register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" @@ -4363,7 +4463,7 @@ (match_operand:SI 1 "general_operand" ""))] "TARGET_EITHER" " - if (TARGET_ARM) + if (TARGET_32BIT) { /* Everything except mem = const or mem = mem can be done easily. */ if (GET_CODE (operands[0]) == MEM) @@ -4379,7 +4479,7 @@ DONE; } } - else /* TARGET_THUMB.... */ + else /* TARGET_THUMB1... */ { if (!no_new_pseudos) { @@ -4422,8 +4522,8 @@ ) (define_insn "*arm_movsi_insn" - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m") - (match_operand:SI 1 "general_operand" "rI,K,mi,r"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r, m") + (match_operand:SI 1 "general_operand" "rI,K,N,mi,r"))] "TARGET_ARM && ! TARGET_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_VFP) && ( register_operand (operands[0], SImode) @@ -4431,18 +4531,19 @@ "@ mov%?\\t%0, %1 mvn%?\\t%0, #%B1 + movw%?\\t%0, %1 ldr%?\\t%0, %1 str%?\\t%1, %0" - [(set_attr "type" "*,*,load1,store1") + [(set_attr "type" "*,*,*,load1,store1") (set_attr "predicable" "yes") - (set_attr "pool_range" "*,*,4096,*") - (set_attr "neg_pool_range" "*,*,4084,*")] + (set_attr "pool_range" "*,*,*,4096,*") + (set_attr "neg_pool_range" "*,*,*,4084,*")] ) (define_split [(set (match_operand:SI 0 "arm_general_register_operand" "") (match_operand:SI 1 "const_int_operand" ""))] - "TARGET_ARM + "TARGET_32BIT && (!(const_ok_for_arm (INTVAL (operands[1])) || const_ok_for_arm (~INTVAL (operands[1]))))" [(clobber (const_int 0))] @@ -4453,10 +4554,10 @@ " ) -(define_insn "*thumb_movsi_insn" +(define_insn "*thumb1_movsi_insn" [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,l,l,l,>,l, m,*lh") (match_operand:SI 1 "general_operand" "l, I,J,K,>,l,mi,l,*lh"))] - "TARGET_THUMB + "TARGET_THUMB1 && ( register_operand (operands[0], SImode) || register_operand (operands[1], SImode))" "@ @@ -4477,7 +4578,7 @@ (define_split [(set (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "const_int_operand" ""))] - "TARGET_THUMB && satisfies_constraint_J (operands[1])" + "TARGET_THUMB1 && satisfies_constraint_J (operands[1])" [(set (match_dup 0) (match_dup 1)) (set (match_dup 0) (neg:SI (match_dup 0)))] "operands[1] = GEN_INT (- INTVAL (operands[1]));" @@ -4486,7 +4587,7 @@ (define_split [(set (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "const_int_operand" ""))] - "TARGET_THUMB && satisfies_constraint_K (operands[1])" + "TARGET_THUMB1 && satisfies_constraint_K (operands[1])" [(set (match_dup 0) (match_dup 1)) (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))] " @@ -4527,10 +4628,10 @@ (set (attr "neg_pool_range") (const_int 4084))] ) -(define_insn "pic_load_addr_thumb" +(define_insn "pic_load_addr_thumb1" [(set (match_operand:SI 0 "s_register_operand" "=l") (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))] - "TARGET_THUMB && flag_pic" + "TARGET_THUMB1 && flag_pic" "ldr\\t%0, %1" [(set_attr "type" "load1") (set (attr "pool_range") (const_int 1024))] @@ -4575,7 +4676,7 @@ (const (plus:SI (pc) (const_int 4))))] UNSPEC_PIC_BASE)) (use (match_operand 2 "" ""))] - "TARGET_THUMB" + "TARGET_THUMB1" "* (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\", INTVAL (operands[2])); @@ -4656,10 +4757,10 @@ (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r,r") (match_dup 1))] - "TARGET_ARM" + "TARGET_32BIT" "@ cmp%?\\t%0, #0 - sub%?s\\t%0, %1, #0" + sub%.\\t%0, %1, #0" [(set_attr "conds" "set")] ) @@ -4775,7 +4876,7 @@ (define_expand "storehi_single_op" [(set (match_operand:HI 0 "memory_operand" "") (match_operand:HI 1 "general_operand" ""))] - "TARGET_ARM && arm_arch4" + "TARGET_32BIT && arm_arch4" " if (!s_register_operand (operands[1], HImode)) operands[1] = copy_to_mode_reg (HImode, operands[1]); @@ -4893,7 +4994,25 @@ DONE; } } - else /* TARGET_THUMB */ + else if (TARGET_THUMB2) + { + /* Thumb-2 can do everything except mem=mem and mem=const easily. */ + if (!no_new_pseudos) + { + if (GET_CODE (operands[0]) != REG) + operands[1] = force_reg (HImode, operands[1]); + /* Zero extend a constant, and keep it in an SImode reg. */ + else if (GET_CODE (operands[1]) == CONST_INT) + { + rtx reg = gen_reg_rtx (SImode); + HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff; + + emit_insn (gen_movsi (reg, GEN_INT (val))); + operands[1] = gen_lowpart (HImode, reg); + } + } + } + else /* TARGET_THUMB1 */ { if (!no_new_pseudos) { @@ -4955,10 +5074,10 @@ " ) -(define_insn "*thumb_movhi_insn" +(define_insn "*thumb1_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") (match_operand:HI 1 "general_operand" "l,m,l,*h,*r,I"))] - "TARGET_THUMB + "TARGET_THUMB1 && ( register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" "* @@ -5054,8 +5173,8 @@ "@ mov%?\\t%0, %1\\t%@ movhi mvn%?\\t%0, #%B1\\t%@ movhi - str%?h\\t%1, %0\\t%@ movhi - ldr%?h\\t%0, %1\\t%@ movhi" + str%(h%)\\t%1, %0\\t%@ movhi + ldr%(h%)\\t%0, %1\\t%@ movhi" [(set_attr "type" "*,*,store1,load1") (set_attr "predicable" "yes") (set_attr "pool_range" "*,*,*,256") @@ -5076,7 +5195,7 @@ [(set (match_operand:HI 0 "memory_operand" "") (match_operand:HI 1 "register_operand" "")) (clobber (match_operand:DI 2 "register_operand" ""))] - "TARGET_THUMB" + "TARGET_THUMB1" " if (strict_memory_address_p (HImode, XEXP (operands[0], 0)) && REGNO (operands[1]) <= LAST_LO_REGNUM) @@ -5191,22 +5310,22 @@ (define_insn "*arm_movqi_insn" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m") (match_operand:QI 1 "general_operand" "rI,K,m,r"))] - "TARGET_ARM + "TARGET_32BIT && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" "@ mov%?\\t%0, %1 mvn%?\\t%0, #%B1 - ldr%?b\\t%0, %1 - str%?b\\t%1, %0" + ldr%(b%)\\t%0, %1 + str%(b%)\\t%1, %0" [(set_attr "type" "*,*,load1,store1") (set_attr "predicable" "yes")] ) -(define_insn "*thumb_movqi_insn" +(define_insn "*thumb1_movqi_insn" [(set (match_operand:QI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") (match_operand:QI 1 "general_operand" "l, m,l,*h,*r,I"))] - "TARGET_THUMB + "TARGET_THUMB1 && ( register_operand (operands[0], QImode) || register_operand (operands[1], QImode))" "@ @@ -5226,12 +5345,12 @@ (match_operand:SF 1 "general_operand" ""))] "TARGET_EITHER" " - if (TARGET_ARM) + if (TARGET_32BIT) { if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (SFmode, operands[1]); } - else /* TARGET_THUMB */ + else /* TARGET_THUMB1 */ { if (!no_new_pseudos) { @@ -5247,7 +5366,7 @@ (define_split [(set (match_operand:SF 0 "arm_general_register_operand" "") (match_operand:SF 1 "immediate_operand" ""))] - "TARGET_ARM + "TARGET_32BIT && reload_completed && GET_CODE (operands[1]) == CONST_DOUBLE" [(set (match_dup 2) (match_dup 3))] @@ -5278,10 +5397,10 @@ ) ;;; ??? This should have alternatives for constants. -(define_insn "*thumb_movsf_insn" +(define_insn "*thumb1_movsf_insn" [(set (match_operand:SF 0 "nonimmediate_operand" "=l,l,>,l, m,*r,*h") (match_operand:SF 1 "general_operand" "l, >,l,mF,l,*h,*r"))] - "TARGET_THUMB + "TARGET_THUMB1 && ( register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode))" "@ @@ -5302,7 +5421,7 @@ (match_operand:DF 1 "general_operand" ""))] "TARGET_EITHER" " - if (TARGET_ARM) + if (TARGET_32BIT) { if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (DFmode, operands[1]); @@ -5324,7 +5443,7 @@ [(match_operand:DF 0 "arm_reload_memory_operand" "=o") (match_operand:DF 1 "s_register_operand" "r") (match_operand:SI 2 "s_register_operand" "=&r")] - "TARGET_ARM" + "TARGET_32BIT" " { enum rtx_code code = GET_CODE (XEXP (operands[0], 0)); @@ -5392,7 +5511,7 @@ (define_insn "*thumb_movdf_insn" [(set (match_operand:DF 0 "nonimmediate_operand" "=l,l,>,l, m,*r") (match_operand:DF 1 "general_operand" "l, >,l,mF,l,*r"))] - "TARGET_THUMB + "TARGET_THUMB1 && ( register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode))" "* @@ -5428,7 +5547,7 @@ (define_expand "movxf" [(set (match_operand:XF 0 "general_operand" "") (match_operand:XF 1 "general_operand" ""))] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" " if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (XFmode, operands[1]); @@ -5466,7 +5585,7 @@ [(match_par_dup 3 [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" "")) (use (match_operand:SI 2 "" ""))])] - "TARGET_ARM" + "TARGET_32BIT" { HOST_WIDE_INT offset = 0; @@ -5501,13 +5620,13 @@ (mem:SI (plus:SI (match_dup 2) (const_int 8)))) (set (match_operand:SI 6 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 2) (const_int 12))))])] - "TARGET_ARM && XVECLEN (operands[0], 0) == 5" - "ldm%?ia\\t%1!, {%3, %4, %5, %6}" + "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" + "ldm%(ia%)\\t%1!, {%3, %4, %5, %6}" [(set_attr "type" "load4") (set_attr "predicable" "yes")] ) -(define_insn "*ldmsi_postinc4_thumb" +(define_insn "*ldmsi_postinc4_thumb1" [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 1 "s_register_operand" "=l") (plus:SI (match_operand:SI 2 "s_register_operand" "1") @@ -5520,7 +5639,7 @@ (mem:SI (plus:SI (match_dup 2) (const_int 8)))) (set (match_operand:SI 6 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 2) (const_int 12))))])] - "TARGET_THUMB && XVECLEN (operands[0], 0) == 5" + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" "ldmia\\t%1!, {%3, %4, %5, %6}" [(set_attr "type" "load4")] ) @@ -5536,8 +5655,8 @@ (mem:SI (plus:SI (match_dup 2) (const_int 4)))) (set (match_operand:SI 5 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 2) (const_int 8))))])] - "TARGET_ARM && XVECLEN (operands[0], 0) == 4" - "ldm%?ia\\t%1!, {%3, %4, %5}" + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" + "ldm%(ia%)\\t%1!, {%3, %4, %5}" [(set_attr "type" "load3") (set_attr "predicable" "yes")] ) @@ -5551,8 +5670,8 @@ (mem:SI (match_dup 2))) (set (match_operand:SI 4 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 2) (const_int 4))))])] - "TARGET_ARM && XVECLEN (operands[0], 0) == 3" - "ldm%?ia\\t%1!, {%3, %4}" + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" + "ldm%(ia%)\\t%1!, {%3, %4}" [(set_attr "type" "load2") (set_attr "predicable" "yes")] ) @@ -5569,8 +5688,8 @@ (mem:SI (plus:SI (match_dup 1) (const_int 8)))) (set (match_operand:SI 5 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] - "TARGET_ARM && XVECLEN (operands[0], 0) == 4" - "ldm%?ia\\t%1, {%2, %3, %4, %5}" + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" + "ldm%(ia%)\\t%1, {%2, %3, %4, %5}" [(set_attr "type" "load4") (set_attr "predicable" "yes")] ) @@ -5583,8 +5702,8 @@ (mem:SI (plus:SI (match_dup 1) (const_int 4)))) (set (match_operand:SI 4 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] - "TARGET_ARM && XVECLEN (operands[0], 0) == 3" - "ldm%?ia\\t%1, {%2, %3, %4}" + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" + "ldm%(ia%)\\t%1, {%2, %3, %4}" [(set_attr "type" "load3") (set_attr "predicable" "yes")] ) @@ -5595,8 +5714,8 @@ (mem:SI (match_operand:SI 1 "s_register_operand" "r"))) (set (match_operand:SI 3 "arm_hard_register_operand" "") (mem:SI (plus:SI (match_dup 1) (const_int 4))))])] - "TARGET_ARM && XVECLEN (operands[0], 0) == 2" - "ldm%?ia\\t%1, {%2, %3}" + "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" + "ldm%(ia%)\\t%1, {%2, %3}" [(set_attr "type" "load2") (set_attr "predicable" "yes")] ) @@ -5605,7 +5724,7 @@ [(match_par_dup 3 [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" "")) (use (match_operand:SI 2 "" ""))])] - "TARGET_ARM" + "TARGET_32BIT" { HOST_WIDE_INT offset = 0; @@ -5640,13 +5759,13 @@ (match_operand:SI 5 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) (match_operand:SI 6 "arm_hard_register_operand" ""))])] - "TARGET_ARM && XVECLEN (operands[0], 0) == 5" - "stm%?ia\\t%1!, {%3, %4, %5, %6}" + "TARGET_32BIT && XVECLEN (operands[0], 0) == 5" + "stm%(ia%)\\t%1!, {%3, %4, %5, %6}" [(set_attr "predicable" "yes") (set_attr "type" "store4")] ) -(define_insn "*stmsi_postinc4_thumb" +(define_insn "*stmsi_postinc4_thumb1" [(match_parallel 0 "store_multiple_operation" [(set (match_operand:SI 1 "s_register_operand" "=l") (plus:SI (match_operand:SI 2 "s_register_operand" "1") @@ -5659,7 +5778,7 @@ (match_operand:SI 5 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 2) (const_int 12))) (match_operand:SI 6 "arm_hard_register_operand" ""))])] - "TARGET_THUMB && XVECLEN (operands[0], 0) == 5" + "TARGET_THUMB1 && XVECLEN (operands[0], 0) == 5" "stmia\\t%1!, {%3, %4, %5, %6}" [(set_attr "type" "store4")] ) @@ -5675,8 +5794,8 @@ (match_operand:SI 4 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 2) (const_int 8))) (match_operand:SI 5 "arm_hard_register_operand" ""))])] - "TARGET_ARM && XVECLEN (operands[0], 0) == 4" - "stm%?ia\\t%1!, {%3, %4, %5}" + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" + "stm%(ia%)\\t%1!, {%3, %4, %5}" [(set_attr "predicable" "yes") (set_attr "type" "store3")] ) @@ -5690,8 +5809,8 @@ (match_operand:SI 3 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 2) (const_int 4))) (match_operand:SI 4 "arm_hard_register_operand" ""))])] - "TARGET_ARM && XVECLEN (operands[0], 0) == 3" - "stm%?ia\\t%1!, {%3, %4}" + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" + "stm%(ia%)\\t%1!, {%3, %4}" [(set_attr "predicable" "yes") (set_attr "type" "store2")] ) @@ -5708,8 +5827,8 @@ (match_operand:SI 4 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) (match_operand:SI 5 "arm_hard_register_operand" ""))])] - "TARGET_ARM && XVECLEN (operands[0], 0) == 4" - "stm%?ia\\t%1, {%2, %3, %4, %5}" + "TARGET_32BIT && XVECLEN (operands[0], 0) == 4" + "stm%(ia%)\\t%1, {%2, %3, %4, %5}" [(set_attr "predicable" "yes") (set_attr "type" "store4")] ) @@ -5722,8 +5841,8 @@ (match_operand:SI 3 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) (match_operand:SI 4 "arm_hard_register_operand" ""))])] - "TARGET_ARM && XVECLEN (operands[0], 0) == 3" - "stm%?ia\\t%1, {%2, %3, %4}" + "TARGET_32BIT && XVECLEN (operands[0], 0) == 3" + "stm%(ia%)\\t%1, {%2, %3, %4}" [(set_attr "predicable" "yes") (set_attr "type" "store3")] ) @@ -5734,8 +5853,8 @@ (match_operand:SI 2 "arm_hard_register_operand" "")) (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) (match_operand:SI 3 "arm_hard_register_operand" ""))])] - "TARGET_ARM && XVECLEN (operands[0], 0) == 2" - "stm%?ia\\t%1, {%2, %3}" + "TARGET_32BIT && XVECLEN (operands[0], 0) == 2" + "stm%(ia%)\\t%1, {%2, %3}" [(set_attr "predicable" "yes") (set_attr "type" "store2")] ) @@ -5751,13 +5870,13 @@ (match_operand:SI 3 "const_int_operand" "")] "TARGET_EITHER" " - if (TARGET_ARM) + if (TARGET_32BIT) { if (arm_gen_movmemqi (operands)) DONE; FAIL; } - else /* TARGET_THUMB */ + else /* TARGET_THUMB1 */ { if ( INTVAL (operands[3]) != 4 || INTVAL (operands[2]) > 48) @@ -5785,7 +5904,7 @@ (clobber (match_scratch:SI 4 "=&l")) (clobber (match_scratch:SI 5 "=&l")) (clobber (match_scratch:SI 6 "=&l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "* return thumb_output_move_mem_multiple (3, operands);" [(set_attr "length" "4") ; This isn't entirely accurate... It loads as well, but in terms of @@ -5804,7 +5923,7 @@ (plus:SI (match_dup 3) (const_int 8))) (clobber (match_scratch:SI 4 "=&l")) (clobber (match_scratch:SI 5 "=&l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "* return thumb_output_move_mem_multiple (2, operands);" [(set_attr "length" "4") ; This isn't entirely accurate... It loads as well, but in terms of @@ -5838,15 +5957,15 @@ (match_operand:SI 2 "nonmemory_operand" "")]) (label_ref (match_operand 3 "" "")) (pc)))] - "TARGET_THUMB" + "TARGET_THUMB1" " - if (thumb_cmpneg_operand (operands[2], SImode)) + if (thumb1_cmpneg_operand (operands[2], SImode)) { emit_jump_insn (gen_cbranchsi4_scratch (NULL, operands[1], operands[2], operands[3], operands[0])); DONE; } - if (!thumb_cmp_operand (operands[2], SImode)) + if (!thumb1_cmp_operand (operands[2], SImode)) operands[2] = force_reg (SImode, operands[2]); ") @@ -5854,10 +5973,10 @@ [(set (pc) (if_then_else (match_operator 0 "arm_comparison_operator" [(match_operand:SI 1 "s_register_operand" "l,*h") - (match_operand:SI 2 "thumb_cmp_operand" "lI*h,*r")]) + (match_operand:SI 2 "thumb1_cmp_operand" "lI*h,*r")]) (label_ref (match_operand 3 "" "")) (pc)))] - "TARGET_THUMB" + "TARGET_THUMB1" "* output_asm_insn (\"cmp\\t%1, %2\", operands); @@ -5889,11 +6008,11 @@ [(set (pc) (if_then_else (match_operator 4 "arm_comparison_operator" [(match_operand:SI 1 "s_register_operand" "l,0") - (match_operand:SI 2 "thumb_cmpneg_operand" "L,J")]) + (match_operand:SI 2 "thumb1_cmpneg_operand" "L,J")]) (label_ref (match_operand 3 "" "")) (pc))) (clobber (match_scratch:SI 0 "=l,l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "* output_asm_insn (\"add\\t%0, %1, #%n2\", operands); @@ -5930,7 +6049,7 @@ (pc))) (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*h,*m") (match_dup 1))] - "TARGET_THUMB" + "TARGET_THUMB1" "*{ if (which_alternative == 0) output_asm_insn (\"cmp\t%0, #0\", operands); @@ -5991,7 +6110,7 @@ (neg:SI (match_operand:SI 2 "s_register_operand" "l"))]) (label_ref (match_operand 3 "" "")) (pc)))] - "TARGET_THUMB" + "TARGET_THUMB1" "* output_asm_insn (\"cmn\\t%1, %2\", operands); switch (get_attr_length (insn)) @@ -6029,7 +6148,7 @@ (label_ref (match_operand 3 "" "")) (pc))) (clobber (match_scratch:SI 4 "=l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "* { rtx op[3]; @@ -6073,7 +6192,7 @@ (label_ref (match_operand 3 "" "")) (pc))) (clobber (match_scratch:SI 4 "=l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "* { rtx op[3]; @@ -6115,7 +6234,7 @@ (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] - "TARGET_THUMB" + "TARGET_THUMB1" "* { output_asm_insn (\"tst\\t%0, %1\", operands); @@ -6155,7 +6274,7 @@ (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") (and:SI (match_dup 2) (match_dup 3))) (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "* { if (which_alternative == 0) @@ -6220,7 +6339,7 @@ (label_ref (match_operand 3 "" "")) (pc))) (clobber (match_scratch:SI 0 "=l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "* { output_asm_insn (\"orr\\t%0, %2\", operands); @@ -6260,7 +6379,7 @@ (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") (ior:SI (match_dup 2) (match_dup 3))) (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "* { if (which_alternative == 0) @@ -6325,7 +6444,7 @@ (label_ref (match_operand 3 "" "")) (pc))) (clobber (match_scratch:SI 0 "=l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "* { output_asm_insn (\"eor\\t%0, %2\", operands); @@ -6365,7 +6484,7 @@ (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") (xor:SI (match_dup 2) (match_dup 3))) (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "* { if (which_alternative == 0) @@ -6430,7 +6549,7 @@ (label_ref (match_operand 3 "" "")) (pc))) (clobber (match_scratch:SI 0 "=l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "* { output_asm_insn (\"bic\\t%0, %2\", operands); @@ -6470,7 +6589,7 @@ (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=!l,l,*?h,*?m,*?m") (and:SI (not:SI (match_dup 3)) (match_dup 2))) (clobber (match_scratch:SI 1 "=X,l,l,&l,&l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "* { if (which_alternative == 0) @@ -6537,7 +6656,7 @@ (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") (plus:SI (match_dup 2) (const_int -1))) (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "* { rtx cond[2]; @@ -6644,7 +6763,7 @@ (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*!h,*?h,*?m,*?m") (plus:SI (match_dup 2) (match_dup 3))) (clobber (match_scratch:SI 1 "=X,X,X,l,&l,&l"))] - "TARGET_THUMB + "TARGET_THUMB1 && (GET_CODE (operands[4]) == EQ || GET_CODE (operands[4]) == NE || GET_CODE (operands[4]) == GE @@ -6723,7 +6842,7 @@ (label_ref (match_operand 4 "" "")) (pc))) (clobber (match_scratch:SI 0 "=X,X,l,l"))] - "TARGET_THUMB + "TARGET_THUMB1 && (GET_CODE (operands[3]) == EQ || GET_CODE (operands[3]) == NE || GET_CODE (operands[3]) == GE @@ -6793,7 +6912,7 @@ (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") (minus:SI (match_dup 2) (match_dup 3))) (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] - "TARGET_THUMB + "TARGET_THUMB1 && (GET_CODE (operands[4]) == EQ || GET_CODE (operands[4]) == NE || GET_CODE (operands[4]) == GE @@ -6870,7 +6989,7 @@ (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] - "TARGET_THUMB + "TARGET_THUMB1 && (GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE || GET_CODE (operands[0]) == GE @@ -6906,7 +7025,7 @@ (define_expand "cmpsi" [(match_operand:SI 0 "s_register_operand" "") (match_operand:SI 1 "arm_add_operand" "")] - "TARGET_ARM" + "TARGET_32BIT" "{ arm_compare_op0 = operands[0]; arm_compare_op1 = operands[1]; @@ -6917,7 +7036,7 @@ (define_expand "cmpsf" [(match_operand:SF 0 "s_register_operand" "") (match_operand:SF 1 "arm_float_compare_operand" "")] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" " arm_compare_op0 = operands[0]; arm_compare_op1 = operands[1]; @@ -6928,7 +7047,7 @@ (define_expand "cmpdf" [(match_operand:DF 0 "s_register_operand" "") (match_operand:DF 1 "arm_float_compare_operand" "")] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_32BIT && TARGET_HARD_FLOAT" " arm_compare_op0 = operands[0]; arm_compare_op1 = operands[1]; @@ -6940,14 +7059,14 @@ [(set (reg:CC CC_REGNUM) (compare:CC (match_operand:SI 0 "s_register_operand" "r,r") (match_operand:SI 1 "arm_add_operand" "rI,L")))] - "TARGET_ARM" + "TARGET_32BIT" "@ cmp%?\\t%0, %1 cmn%?\\t%0, #%n1" [(set_attr "conds" "set")] ) -(define_insn "*cmpsi_shiftsi" +(define_insn "*arm_cmpsi_shiftsi" [(set (reg:CC CC_REGNUM) (compare:CC (match_operand:SI 0 "s_register_operand" "r") (match_operator:SI 3 "shift_operator" @@ -6962,7 +7081,7 @@ (const_string "alu_shift_reg")))] ) -(define_insn "*cmpsi_shiftsi_swp" +(define_insn "*arm_cmpsi_shiftsi_swp" [(set (reg:CC_SWP CC_REGNUM) (compare:CC_SWP (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r") @@ -6977,7 +7096,7 @@ (const_string "alu_shift_reg")))] ) -(define_insn "*cmpsi_negshiftsi_si" +(define_insn "*arm_cmpsi_negshiftsi_si" [(set (reg:CC_Z CC_REGNUM) (compare:CC_Z (neg:SI (match_operator:SI 1 "shift_operator" @@ -7043,7 +7162,7 @@ (define_insn "*deleted_compare" [(set (match_operand 0 "cc_register" "") (match_dup 0))] - "TARGET_ARM" + "TARGET_32BIT" "\\t%@ deleted compare" [(set_attr "conds" "set") (set_attr "length" "0")] @@ -7057,7 +7176,7 @@ (if_then_else (eq (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1);" ) @@ -7066,7 +7185,7 @@ (if_then_else (ne (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (NE, arm_compare_op0, arm_compare_op1);" ) @@ -7075,7 +7194,7 @@ (if_then_else (gt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (GT, arm_compare_op0, arm_compare_op1);" ) @@ -7084,7 +7203,7 @@ (if_then_else (le (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" ) @@ -7093,7 +7212,7 @@ (if_then_else (ge (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" ) @@ -7102,7 +7221,7 @@ (if_then_else (lt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (LT, arm_compare_op0, arm_compare_op1);" ) @@ -7111,7 +7230,7 @@ (if_then_else (gtu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1);" ) @@ -7120,7 +7239,7 @@ (if_then_else (leu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" ) @@ -7129,7 +7248,7 @@ (if_then_else (geu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" ) @@ -7138,7 +7257,7 @@ (if_then_else (ltu (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1);" ) @@ -7147,7 +7266,7 @@ (if_then_else (unordered (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, arm_compare_op1);" ) @@ -7157,7 +7276,7 @@ (if_then_else (ordered (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, arm_compare_op1);" ) @@ -7167,7 +7286,7 @@ (if_then_else (ungt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" ) @@ -7176,7 +7295,7 @@ (if_then_else (unlt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" ) @@ -7185,7 +7304,7 @@ (if_then_else (unge (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" ) @@ -7194,7 +7313,7 @@ (if_then_else (unle (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" ) @@ -7205,7 +7324,7 @@ (if_then_else (uneq (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" ) @@ -7214,7 +7333,7 @@ (if_then_else (ltgt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" ) @@ -7228,7 +7347,7 @@ (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "* gcc_assert (!arm_ccfsm_state); @@ -7244,7 +7363,7 @@ (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "* gcc_assert (!arm_ccfsm_state); @@ -7260,7 +7379,7 @@ [(match_operand 2 "cc_register" "") (const_int 0)]) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM" + "TARGET_32BIT" "* if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) { @@ -7311,7 +7430,7 @@ [(match_operand 2 "cc_register" "") (const_int 0)]) (pc) (label_ref (match_operand 0 "" ""))))] - "TARGET_ARM" + "TARGET_32BIT" "* if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) { @@ -7331,77 +7450,77 @@ (define_expand "seq" [(set (match_operand:SI 0 "s_register_operand" "") (eq:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1);" ) (define_expand "sne" [(set (match_operand:SI 0 "s_register_operand" "") (ne:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (NE, arm_compare_op0, arm_compare_op1);" ) (define_expand "sgt" [(set (match_operand:SI 0 "s_register_operand" "") (gt:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (GT, arm_compare_op0, arm_compare_op1);" ) (define_expand "sle" [(set (match_operand:SI 0 "s_register_operand" "") (le:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" ) (define_expand "sge" [(set (match_operand:SI 0 "s_register_operand" "") (ge:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" ) (define_expand "slt" [(set (match_operand:SI 0 "s_register_operand" "") (lt:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (LT, arm_compare_op0, arm_compare_op1);" ) (define_expand "sgtu" [(set (match_operand:SI 0 "s_register_operand" "") (gtu:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1);" ) (define_expand "sleu" [(set (match_operand:SI 0 "s_register_operand" "") (leu:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" ) (define_expand "sgeu" [(set (match_operand:SI 0 "s_register_operand" "") (geu:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" ) (define_expand "sltu" [(set (match_operand:SI 0 "s_register_operand" "") (ltu:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM" + "TARGET_32BIT" "operands[1] = arm_gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1);" ) (define_expand "sunordered" [(set (match_operand:SI 0 "s_register_operand" "") (unordered:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, arm_compare_op1);" ) @@ -7409,7 +7528,7 @@ (define_expand "sordered" [(set (match_operand:SI 0 "s_register_operand" "") (ordered:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, arm_compare_op1);" ) @@ -7417,7 +7536,7 @@ (define_expand "sungt" [(set (match_operand:SI 0 "s_register_operand" "") (ungt:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" ) @@ -7425,7 +7544,7 @@ (define_expand "sunge" [(set (match_operand:SI 0 "s_register_operand" "") (unge:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" ) @@ -7433,7 +7552,7 @@ (define_expand "sunlt" [(set (match_operand:SI 0 "s_register_operand" "") (unlt:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" ) @@ -7441,7 +7560,7 @@ (define_expand "sunle" [(set (match_operand:SI 0 "s_register_operand" "") (unle:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" ) @@ -7452,14 +7571,14 @@ ; (define_expand "suneq" ; [(set (match_operand:SI 0 "s_register_operand" "") ; (uneq:SI (match_dup 1) (const_int 0)))] -; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" +; "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ; "gcc_unreachable ();" ; ) ; ; (define_expand "sltgt" ; [(set (match_operand:SI 0 "s_register_operand" "") ; (ltgt:SI (match_dup 1) (const_int 0)))] -; "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" +; "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" ; "gcc_unreachable ();" ; ) @@ -7498,7 +7617,7 @@ (match_operator:SI 1 "arm_comparison_operator" [(match_operand:SI 2 "s_register_operand" "") (match_operand:SI 3 "reg_or_int_operand" "")]))] - "TARGET_THUMB" + "TARGET_THUMB1" "{ rtx op3, scratch, scratch2; @@ -7507,11 +7626,11 @@ switch (GET_CODE (operands[1])) { case EQ: - emit_insn (gen_cstoresi_eq0_thumb (operands[0], operands[2])); + emit_insn (gen_cstoresi_eq0_thumb1 (operands[0], operands[2])); break; case NE: - emit_insn (gen_cstoresi_ne0_thumb (operands[0], operands[2])); + emit_insn (gen_cstoresi_ne0_thumb1 (operands[0], operands[2])); break; case LE: @@ -7551,13 +7670,13 @@ case EQ: scratch = expand_binop (SImode, sub_optab, operands[2], operands[3], NULL_RTX, 0, OPTAB_WIDEN); - emit_insn (gen_cstoresi_eq0_thumb (operands[0], scratch)); + emit_insn (gen_cstoresi_eq0_thumb1 (operands[0], scratch)); break; case NE: scratch = expand_binop (SImode, sub_optab, operands[2], operands[3], NULL_RTX, 0, OPTAB_WIDEN); - emit_insn (gen_cstoresi_ne0_thumb (operands[0], scratch)); + emit_insn (gen_cstoresi_ne0_thumb1 (operands[0], scratch)); break; case LE: @@ -7567,51 +7686,51 @@ NULL_RTX, 1, OPTAB_WIDEN); scratch2 = expand_binop (SImode, ashr_optab, op3, GEN_INT (31), NULL_RTX, 0, OPTAB_WIDEN); - emit_insn (gen_thumb_addsi3_addgeu (operands[0], scratch, scratch2, + emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch2, op3, operands[2])); break; case GE: op3 = operands[3]; - if (!thumb_cmp_operand (op3, SImode)) + if (!thumb1_cmp_operand (op3, SImode)) op3 = force_reg (SImode, op3); scratch = expand_binop (SImode, ashr_optab, operands[2], GEN_INT (31), NULL_RTX, 0, OPTAB_WIDEN); scratch2 = expand_binop (SImode, lshr_optab, op3, GEN_INT (31), NULL_RTX, 1, OPTAB_WIDEN); - emit_insn (gen_thumb_addsi3_addgeu (operands[0], scratch, scratch2, + emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch2, operands[2], op3)); break; case LEU: op3 = force_reg (SImode, operands[3]); scratch = force_reg (SImode, const0_rtx); - emit_insn (gen_thumb_addsi3_addgeu (operands[0], scratch, scratch, + emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch, op3, operands[2])); break; case GEU: op3 = operands[3]; - if (!thumb_cmp_operand (op3, SImode)) + if (!thumb1_cmp_operand (op3, SImode)) op3 = force_reg (SImode, op3); scratch = force_reg (SImode, const0_rtx); - emit_insn (gen_thumb_addsi3_addgeu (operands[0], scratch, scratch, + emit_insn (gen_thumb1_addsi3_addgeu (operands[0], scratch, scratch, operands[2], op3)); break; case LTU: op3 = operands[3]; - if (!thumb_cmp_operand (op3, SImode)) + if (!thumb1_cmp_operand (op3, SImode)) op3 = force_reg (SImode, op3); scratch = gen_reg_rtx (SImode); - emit_insn (gen_cstoresi_nltu_thumb (scratch, operands[2], op3)); + emit_insn (gen_cstoresi_nltu_thumb1 (scratch, operands[2], op3)); emit_insn (gen_negsi2 (operands[0], scratch)); break; case GTU: op3 = force_reg (SImode, operands[3]); scratch = gen_reg_rtx (SImode); - emit_insn (gen_cstoresi_nltu_thumb (scratch, op3, operands[2])); + emit_insn (gen_cstoresi_nltu_thumb1 (scratch, op3, operands[2])); emit_insn (gen_negsi2 (operands[0], scratch)); break; @@ -7622,65 +7741,65 @@ DONE; }") -(define_expand "cstoresi_eq0_thumb" +(define_expand "cstoresi_eq0_thumb1" [(parallel [(set (match_operand:SI 0 "s_register_operand" "") (eq:SI (match_operand:SI 1 "s_register_operand" "") (const_int 0))) (clobber (match_dup:SI 2))])] - "TARGET_THUMB" + "TARGET_THUMB1" "operands[2] = gen_reg_rtx (SImode);" ) -(define_expand "cstoresi_ne0_thumb" +(define_expand "cstoresi_ne0_thumb1" [(parallel [(set (match_operand:SI 0 "s_register_operand" "") (ne:SI (match_operand:SI 1 "s_register_operand" "") (const_int 0))) (clobber (match_dup:SI 2))])] - "TARGET_THUMB" + "TARGET_THUMB1" "operands[2] = gen_reg_rtx (SImode);" ) -(define_insn "*cstoresi_eq0_thumb_insn" +(define_insn "*cstoresi_eq0_thumb1_insn" [(set (match_operand:SI 0 "s_register_operand" "=&l,l") (eq:SI (match_operand:SI 1 "s_register_operand" "l,0") (const_int 0))) (clobber (match_operand:SI 2 "s_register_operand" "=X,l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "@ neg\\t%0, %1\;adc\\t%0, %0, %1 neg\\t%2, %1\;adc\\t%0, %1, %2" [(set_attr "length" "4")] ) -(define_insn "*cstoresi_ne0_thumb_insn" +(define_insn "*cstoresi_ne0_thumb1_insn" [(set (match_operand:SI 0 "s_register_operand" "=l") (ne:SI (match_operand:SI 1 "s_register_operand" "0") (const_int 0))) (clobber (match_operand:SI 2 "s_register_operand" "=l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "sub\\t%2, %1, #1\;sbc\\t%0, %1, %2" [(set_attr "length" "4")] ) -(define_insn "cstoresi_nltu_thumb" +(define_insn "cstoresi_nltu_thumb1" [(set (match_operand:SI 0 "s_register_operand" "=l,l") (neg:SI (gtu:SI (match_operand:SI 1 "s_register_operand" "l,*h") - (match_operand:SI 2 "thumb_cmp_operand" "lI*h,*r"))))] - "TARGET_THUMB" + (match_operand:SI 2 "thumb1_cmp_operand" "lI*h,*r"))))] + "TARGET_THUMB1" "cmp\\t%1, %2\;sbc\\t%0, %0, %0" [(set_attr "length" "4")] ) ;; Used as part of the expansion of thumb les sequence. -(define_insn "thumb_addsi3_addgeu" +(define_insn "thumb1_addsi3_addgeu" [(set (match_operand:SI 0 "s_register_operand" "=l") (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%0") (match_operand:SI 2 "s_register_operand" "l")) (geu:SI (match_operand:SI 3 "s_register_operand" "l") - (match_operand:SI 4 "thumb_cmp_operand" "lI"))))] - "TARGET_THUMB" + (match_operand:SI 4 "thumb1_cmp_operand" "lI"))))] + "TARGET_THUMB1" "cmp\\t%3, %4\;adc\\t%0, %1, %2" [(set_attr "length" "4")] ) @@ -7693,7 +7812,7 @@ (if_then_else:SI (match_operand 1 "arm_comparison_operator" "") (match_operand:SI 2 "arm_not_operand" "") (match_operand:SI 3 "arm_not_operand" "")))] - "TARGET_ARM" + "TARGET_32BIT" " { enum rtx_code code = GET_CODE (operands[1]); @@ -7712,7 +7831,7 @@ (if_then_else:SF (match_operand 1 "arm_comparison_operator" "") (match_operand:SF 2 "s_register_operand" "") (match_operand:SF 3 "nonmemory_operand" "")))] - "TARGET_ARM" + "TARGET_32BIT" " { enum rtx_code code = GET_CODE (operands[1]); @@ -7737,7 +7856,7 @@ (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") (match_operand:DF 2 "s_register_operand" "") (match_operand:DF 3 "arm_float_add_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" " { enum rtx_code code = GET_CODE (operands[1]); @@ -7798,7 +7917,7 @@ (define_insn "*arm_jump" [(set (pc) (label_ref (match_operand 0 "" "")))] - "TARGET_ARM" + "TARGET_32BIT" "* { if (arm_ccfsm_state == 1 || arm_ccfsm_state == 2) @@ -7815,7 +7934,7 @@ (define_insn "*thumb_jump" [(set (pc) (label_ref (match_operand 0 "" "")))] - "TARGET_THUMB" + "TARGET_THUMB1" "* if (get_attr_length (insn) == 2) return \"b\\t%l0\"; @@ -7905,23 +8024,23 @@ (set_attr "type" "call")] ) -(define_insn "*call_reg_thumb_v5" +(define_insn "*call_reg_thumb1_v5" [(call (mem:SI (match_operand:SI 0 "register_operand" "l*r")) (match_operand 1 "" "")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))] - "TARGET_THUMB && arm_arch5" + "TARGET_THUMB1 && arm_arch5" "blx\\t%0" [(set_attr "length" "2") (set_attr "type" "call")] ) -(define_insn "*call_reg_thumb" +(define_insn "*call_reg_thumb1" [(call (mem:SI (match_operand:SI 0 "register_operand" "l*r")) (match_operand 1 "" "")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))] - "TARGET_THUMB && !arm_arch5" + "TARGET_THUMB1 && !arm_arch5" "* { if (!TARGET_CALLER_INTERWORKING) @@ -7999,25 +8118,25 @@ (set_attr "type" "call")] ) -(define_insn "*call_value_reg_thumb_v5" +(define_insn "*call_value_reg_thumb1_v5" [(set (match_operand 0 "" "") (call (mem:SI (match_operand:SI 1 "register_operand" "l*r")) (match_operand 2 "" ""))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))] - "TARGET_THUMB && arm_arch5" + "TARGET_THUMB1 && arm_arch5" "blx\\t%1" [(set_attr "length" "2") (set_attr "type" "call")] ) -(define_insn "*call_value_reg_thumb" +(define_insn "*call_value_reg_thumb1" [(set (match_operand 0 "" "") (call (mem:SI (match_operand:SI 1 "register_operand" "l*r")) (match_operand 2 "" ""))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))] - "TARGET_THUMB && !arm_arch5" + "TARGET_THUMB1 && !arm_arch5" "* { if (!TARGET_CALLER_INTERWORKING) @@ -8371,7 +8490,7 @@ (match_operand:SI 2 "const_int_operand" "") ; total range (match_operand:SI 3 "" "") ; table label (match_operand:SI 4 "" "")] ; Out of range label - "TARGET_ARM" + "TARGET_32BIT" " { rtx reg; @@ -8387,15 +8506,28 @@ if (!const_ok_for_arm (INTVAL (operands[2]))) operands[2] = force_reg (SImode, operands[2]); - emit_jump_insn (gen_casesi_internal (operands[0], operands[2], operands[3], - operands[4])); + if (TARGET_ARM) + { + emit_jump_insn (gen_arm_casesi_internal (operands[0], operands[2], + operands[3], operands[4])); + } + else if (flag_pic) + { + emit_jump_insn (gen_thumb2_casesi_internal_pic (operands[0], + operands[2], operands[3], operands[4])); + } + else + { + emit_jump_insn (gen_thumb2_casesi_internal (operands[0], operands[2], + operands[3], operands[4])); + } DONE; }" ) ;; The USE in this pattern is needed to tell flow analysis that this is ;; a CASESI insn. It has no other purpose. -(define_insn "casesi_internal" +(define_insn "arm_casesi_internal" [(parallel [(set (pc) (if_then_else (leu (match_operand:SI 0 "s_register_operand" "r") @@ -8419,7 +8551,17 @@ [(set (pc) (match_operand:SI 0 "s_register_operand" ""))] "TARGET_EITHER" - "" + " + /* Thumb-2 doesn't have mov pc, reg. Explicitly set the low bit of the + address and use bx. */ + if (TARGET_THUMB2) + { + rtx tmp; + tmp = gen_reg_rtx (SImode); + emit_insn (gen_iorsi3 (tmp, operands[0], GEN_INT(1))); + operands[0] = tmp; + } + " ) ;; NB Never uses BX. @@ -8443,10 +8585,10 @@ ) ;; NB Never uses BX. -(define_insn "*thumb_indirect_jump" +(define_insn "*thumb1_indirect_jump" [(set (pc) (match_operand:SI 0 "register_operand" "l*r"))] - "TARGET_THUMB" + "TARGET_THUMB1" "mov\\tpc, %0" [(set_attr "conds" "clob") (set_attr "length" "2")] @@ -8459,6 +8601,8 @@ [(const_int 0)] "TARGET_EITHER" "* + if (TARGET_UNIFIED_ASM) + return \"nop\"; if (TARGET_ARM) return \"mov%?\\t%|r0, %|r0\\t%@ nop\"; return \"mov\\tr8, r8\"; @@ -8518,7 +8662,7 @@ (match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)]) (match_dup 2)]))] "TARGET_ARM" - "%i1%?s\\t%0, %2, %4%S3" + "%i1%.\\t%0, %2, %4%S3" [(set_attr "conds" "set") (set_attr "shift" "4") (set (attr "type") (if_then_else (match_operand 5 "const_int_operand" "") @@ -8536,7 +8680,7 @@ (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "TARGET_ARM" - "%i1%?s\\t%0, %2, %4%S3" + "%i1%.\\t%0, %2, %4%S3" [(set_attr "conds" "set") (set_attr "shift" "4") (set (attr "type") (if_then_else (match_operand 5 "const_int_operand" "") @@ -8571,7 +8715,7 @@ (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) (match_dup 4)])))] "TARGET_ARM" - "sub%?s\\t%0, %1, %3%S2" + "sub%.\\t%0, %1, %3%S2" [(set_attr "conds" "set") (set_attr "shift" "3") (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") @@ -8589,7 +8733,7 @@ (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "TARGET_ARM" - "sub%?s\\t%0, %1, %3%S2" + "sub%.\\t%0, %1, %3%S2" [(set_attr "conds" "set") (set_attr "shift" "3") (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") @@ -8731,6 +8875,7 @@ (set_attr "length" "8,12")] ) +;; ??? Is it worth using these conditional patterns in Thumb-2 mode? (define_insn "*cmp_ite0" [(set (match_operand 6 "dominant_cc_register" "") (compare @@ -9057,6 +9202,7 @@ (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1)) (const_int 0)))] "") +;; ??? The conditional patterns above need checking for Thumb-2 usefulness (define_insn "*negscc" [(set (match_operand:SI 0 "s_register_operand" "=r") @@ -9146,6 +9292,8 @@ (set_attr "length" "8,8,12")] ) +;; ??? The patterns below need checking for Thumb-2 usefulness. + (define_insn "*ifcompare_plus_move" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (if_then_else:SI (match_operator 6 "arm_comparison_operator" @@ -9738,7 +9886,7 @@ if (val1 == 4 || val2 == 4) /* Other val must be 8, since we know they are adjacent and neither is zero. */ - output_asm_insn (\"ldm%?ib\\t%0, {%1, %2}\", ldm); + output_asm_insn (\"ldm%(ib%)\\t%0, {%1, %2}\", ldm); else if (const_ok_for_arm (val1) || const_ok_for_arm (-val1)) { ldm[0] = ops[0] = operands[4]; @@ -9746,9 +9894,9 @@ ops[2] = GEN_INT (val1); output_add_immediate (ops); if (val1 < val2) - output_asm_insn (\"ldm%?ia\\t%0, {%1, %2}\", ldm); + output_asm_insn (\"ldm%(ia%)\\t%0, {%1, %2}\", ldm); else - output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm); + output_asm_insn (\"ldm%(da%)\\t%0, {%1, %2}\", ldm); } else { @@ -9765,16 +9913,16 @@ else if (val1 != 0) { if (val1 < val2) - output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm); + output_asm_insn (\"ldm%(da%)\\t%0, {%1, %2}\", ldm); else - output_asm_insn (\"ldm%?ia\\t%0, {%1, %2}\", ldm); + output_asm_insn (\"ldm%(ia%)\\t%0, {%1, %2}\", ldm); } else { if (val1 < val2) - output_asm_insn (\"ldm%?ia\\t%0, {%1, %2}\", ldm); + output_asm_insn (\"ldm%(ia%)\\t%0, {%1, %2}\", ldm); else - output_asm_insn (\"ldm%?da\\t%0, {%1, %2}\", ldm); + output_asm_insn (\"ldm%(da%)\\t%0, {%1, %2}\", ldm); } output_asm_insn (\"%I3%?\\t%0, %1, %2\", arith); return \"\"; @@ -9913,14 +10061,15 @@ operands[1] = GEN_INT (((unsigned long) INTVAL (operands[1])) >> 24); " ) +;; ??? Check the patterns above for Thumb-2 usefulness (define_expand "prologue" [(clobber (const_int 0))] "TARGET_EITHER" - "if (TARGET_ARM) + "if (TARGET_32BIT) arm_expand_prologue (); else - thumb_expand_prologue (); + thumb1_expand_prologue (); DONE; " ) @@ -9931,8 +10080,8 @@ " if (current_function_calls_eh_return) emit_insn (gen_prologue_use (gen_rtx_REG (Pmode, 2))); - if (TARGET_THUMB) - thumb_expand_epilogue (); + if (TARGET_THUMB1) + thumb1_expand_epilogue (); else if (USE_RETURN_INSN (FALSE)) { emit_jump_insn (gen_return ()); @@ -9954,7 +10103,7 @@ (define_insn "sibcall_epilogue" [(parallel [(unspec:SI [(reg:SI LR_REGNUM)] UNSPEC_PROLOGUE_USE) (unspec_volatile [(return)] VUNSPEC_EPILOGUE)])] - "TARGET_ARM" + "TARGET_32BIT" "* if (use_return_insn (FALSE, next_nonnote_insn (insn))) return output_return_instruction (const_true_rtx, FALSE, FALSE); @@ -9973,9 +10122,9 @@ [(unspec_volatile [(return)] VUNSPEC_EPILOGUE)] "TARGET_EITHER" "* - if (TARGET_ARM) + if (TARGET_32BIT) return arm_output_epilogue (NULL); - else /* TARGET_THUMB */ + else /* TARGET_THUMB1 */ return thumb_unexpanded_epilogue (); " ; Length is absolute worst case @@ -10015,6 +10164,9 @@ ;; some extent with the conditional data operations, so we have to split them ;; up again here. +;; ??? Need to audit these splitters for Thumb-2. Why isn't normal +;; conditional execution sufficient? + (define_split [(set (match_operand:SI 0 "s_register_operand" "") (if_then_else:SI (match_operator 1 "arm_comparison_operator" @@ -10177,6 +10329,7 @@ [(set_attr "conds" "clob") (set_attr "length" "12")] ) +;; ??? The above patterns need auditing for Thumb-2 ;; Push multiple registers to the stack. Registers are in parallel (use ...) ;; expressions. For simplicity, the first register is also in the unspec @@ -10186,21 +10339,26 @@ [(set (match_operand:BLK 0 "memory_operand" "=m") (unspec:BLK [(match_operand:SI 1 "s_register_operand" "r")] UNSPEC_PUSH_MULT))])] - "TARGET_ARM" + "TARGET_32BIT" "* { int num_saves = XVECLEN (operands[2], 0); /* For the StrongARM at least it is faster to - use STR to store only a single register. */ - if (num_saves == 1) + use STR to store only a single register. + In Thumb mode always use push, and the assmebler will pick + something approporiate. */ + if (num_saves == 1 && TARGET_ARM) output_asm_insn (\"str\\t%1, [%m0, #-4]!\", operands); else { int i; char pattern[100]; - strcpy (pattern, \"stmfd\\t%m0!, {%1\"); + if (TARGET_ARM) + strcpy (pattern, \"stmfd\\t%m0!, {%1\"); + else + strcpy (pattern, \"push\\t{%1\"); for (i = 1; i < num_saves; i++) { @@ -10234,7 +10392,7 @@ [(set (match_operand:BLK 0 "memory_operand" "=m") (unspec:BLK [(match_operand:XF 1 "f_register_operand" "f")] UNSPEC_PUSH_MULT))])] - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPA" "* { char pattern[100]; @@ -10277,7 +10435,7 @@ (define_insn "consttable_1" [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_1)] - "TARGET_THUMB" + "TARGET_THUMB1" "* making_const_table = TRUE; assemble_integer (operands[0], 1, BITS_PER_WORD, 1); @@ -10289,7 +10447,7 @@ (define_insn "consttable_2" [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_2)] - "TARGET_THUMB" + "TARGET_THUMB1" "* making_const_table = TRUE; assemble_integer (operands[0], 2, BITS_PER_WORD, 1); @@ -10352,7 +10510,7 @@ (define_expand "tablejump" [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "")) (use (label_ref (match_operand 1 "" "")))])] - "TARGET_THUMB" + "TARGET_THUMB1" " if (flag_pic) { @@ -10367,10 +10525,10 @@ ) ;; NB never uses BX. -(define_insn "*thumb_tablejump" +(define_insn "*thumb1_tablejump" [(set (pc) (match_operand:SI 0 "register_operand" "l*r")) (use (label_ref (match_operand 1 "" "")))] - "TARGET_THUMB" + "TARGET_THUMB1" "mov\\t%|pc, %0" [(set_attr "length" "2")] ) @@ -10380,14 +10538,14 @@ (define_insn "clzsi2" [(set (match_operand:SI 0 "s_register_operand" "=r") (clz:SI (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_ARM && arm_arch5" + "TARGET_32BIT && arm_arch5" "clz%?\\t%0, %1" [(set_attr "predicable" "yes")]) (define_expand "ffssi2" [(set (match_operand:SI 0 "s_register_operand" "") (ffs:SI (match_operand:SI 1 "s_register_operand" "")))] - "TARGET_ARM && arm_arch5" + "TARGET_32BIT && arm_arch5" " { rtx t1, t2, t3; @@ -10407,7 +10565,7 @@ (define_expand "ctzsi2" [(set (match_operand:SI 0 "s_register_operand" "") (ctz:SI (match_operand:SI 1 "s_register_operand" "")))] - "TARGET_ARM && arm_arch5" + "TARGET_32BIT && arm_arch5" " { rtx t1, t2, t3; @@ -10430,7 +10588,7 @@ [(prefetch (match_operand:SI 0 "address_operand" "p") (match_operand:SI 1 "" "") (match_operand:SI 2 "" ""))] - "TARGET_ARM && arm_arch5e" + "TARGET_32BIT && arm_arch5e" "pld\\t%a0") ;; General predication pattern @@ -10439,7 +10597,7 @@ [(match_operator 0 "arm_comparison_operator" [(match_operand 1 "cc_register" "") (const_int 0)])] - "TARGET_ARM" + "TARGET_32BIT" "" ) @@ -10457,7 +10615,7 @@ "TARGET_EITHER" " { - if (TARGET_ARM) + if (TARGET_32BIT) emit_insn (gen_arm_eh_return (operands[0])); else emit_insn (gen_thumb_eh_return (operands[0])); @@ -10485,7 +10643,7 @@ [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "l")] VUNSPEC_EH_RETURN) (clobber (match_scratch:SI 1 "=&l"))] - "TARGET_THUMB" + "TARGET_THUMB1" "#" "&& reload_completed" [(const_int 0)] @@ -10526,4 +10684,6 @@ (include "iwmmxt.md") ;; Load the VFP co-processor patterns (include "vfp.md") +;; Thumb-2 patterns +(include "thumb2.md") |