diff options
Diffstat (limited to 'gcc/config/arm/arm.md')
| -rw-r--r-- | gcc/config/arm/arm.md | 192 |
1 files changed, 100 insertions, 92 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 744f60607cb..4fb12aac35b 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -330,8 +330,12 @@ ; than one on the main cpu execution unit. (define_attr "core_cycles" "single,multi" (if_then_else (eq_attr "type" - "arlo_imm, arlo_reg,\ - extend, shift, arlo_shift, float, fdivd, fdivs,\ + "adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_reg,\ + alu_shift_imm, alu_shift_reg, alus_ext, alus_imm, alus_reg,\ + alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\ + logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\ + logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\ + fdivd, fdivs,\ wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\ wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\ wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\ @@ -616,8 +620,8 @@ (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no") (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") - (const_string "arlo_imm") - (const_string "arlo_reg"))) + (const_string "alu_imm") + (const_string "alu_reg"))) ] ) @@ -698,7 +702,7 @@ sub%.\\t%0, %1, #%n2 add%.\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "arlo_imm,arlo_imm,*")] + (set_attr "type" "alus_imm,alus_imm,*")] ) (define_insn "*addsi3_compare0_scratch" @@ -714,7 +718,7 @@ cmn%?\\t%0, %1" [(set_attr "conds" "set") (set_attr "predicable" "yes") - (set_attr "type" "arlo_imm,arlo_imm,*") + (set_attr "type" "alus_imm,alus_imm,*") ] ) @@ -804,7 +808,7 @@ sub%.\\t%0, %1, #%n2 add%.\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "arlo_imm,arlo_imm,*")] + (set_attr "type" "alus_imm,alus_imm,alus_reg")] ) (define_insn "*addsi3_compare_op2" @@ -821,7 +825,7 @@ add%.\\t%0, %1, %2 sub%.\\t%0, %1, #%n2" [(set_attr "conds" "set") - (set_attr "type" "arlo_imm,arlo_imm,*")] + (set_attr "type" "alus_imm,alus_imm,alus_reg")] ) (define_insn "*compare_addsi2_op0" @@ -842,7 +846,7 @@ (set_attr "arch" "t2,t2,*,*,*") (set_attr "predicable_short_it" "yes,yes,no,no,no") (set_attr "length" "2,2,4,4,4") - (set_attr "type" "arlo_imm,*,arlo_imm,arlo_imm,*")] + (set_attr "type" "alus_imm,alus_reg,alus_imm,alus_imm,alus_reg")] ) (define_insn "*compare_addsi2_op1" @@ -863,8 +867,7 @@ (set_attr "arch" "t2,t2,*,*,*") (set_attr "predicable_short_it" "yes,yes,no,no,no") (set_attr "length" "2,2,4,4,4") - (set_attr "type" - "arlo_imm,*,arlo_imm,arlo_imm,*")] + (set_attr "type" "alus_imm,alus_reg,alus_imm,alus_imm,alus_reg")] ) (define_insn "*addsi3_carryin_<optab>" @@ -915,8 +918,8 @@ (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") - (const_string "arlo_shift") - (const_string "arlo_shift_reg")))] + (const_string "alu_shift_imm") + (const_string "alu_shift_reg")))] ) (define_insn "*addsi3_carryin_clobercc_<optab>" @@ -994,8 +997,8 @@ [(set_attr "conds" "use") (set_attr "predicable" "yes") (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") - (const_string "arlo_shift") - (const_string "arlo_shift_reg")))] + (const_string "alu_shift_imm") + (const_string "alu_shift_reg")))] ) (define_insn "*rsbsi3_carryin_shift" @@ -1011,8 +1014,8 @@ [(set_attr "conds" "use") (set_attr "predicable" "yes") (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") - (const_string "arlo_shift") - (const_string "arlo_shift_reg")))] + (const_string "alu_shift_imm") + (const_string "alu_shift_reg")))] ) ; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant. @@ -1285,7 +1288,7 @@ (set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no") - (set_attr "type" "*,*,*,*,arlo_imm,arlo_imm,*,*,arlo_imm")] + (set_attr "type" "*,*,*,*,alu_imm,alu_imm,*,*,alu_imm")] ) (define_peephole2 @@ -1315,7 +1318,7 @@ sub%.\\t%0, %1, %2 rsb%.\\t%0, %2, %1" [(set_attr "conds" "set") - (set_attr "type" "arlo_imm,*,*")] + (set_attr "type" "alus_imm,alus_reg,alus_reg")] ) (define_insn "subsi3_compare" @@ -1330,7 +1333,7 @@ sub%.\\t%0, %1, %2 rsb%.\\t%0, %2, %1" [(set_attr "conds" "set") - (set_attr "type" "arlo_imm,*,*")] + (set_attr "type" "alus_imm,alus_reg,alus_reg")] ) (define_expand "subsf3" @@ -2279,8 +2282,7 @@ [(set_attr "length" "4,4,4,4,16") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no,yes,no,no,no") - (set_attr "type" - "arlo_imm,arlo_imm,*,*,arlo_imm")] + (set_attr "type" "logic_imm,logic_imm,logic_reg,logic_reg,logic_imm")] ) (define_insn "*thumb1_andsi3_insn" @@ -2290,7 +2292,7 @@ "TARGET_THUMB1" "and\\t%0, %2" [(set_attr "length" "2") - (set_attr "type" "arlo_imm") + (set_attr "type" "logic_imm") (set_attr "conds" "set")]) (define_insn "*andsi3_compare0" @@ -2307,7 +2309,7 @@ bic%.\\t%0, %1, #%B2 and%.\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "arlo_imm,arlo_imm,*")] + (set_attr "type" "logics_imm,logics_imm,logics_reg")] ) (define_insn "*andsi3_compare0_scratch" @@ -2323,7 +2325,7 @@ bic%.\\t%2, %0, #%B1 tst%?\\t%0, %1" [(set_attr "conds" "set") - (set_attr "type" "arlo_imm,arlo_imm,*")] + (set_attr "type" "logics_imm,logics_imm,logics_reg")] ) (define_insn "*zeroextractsi_compare0_scratch" @@ -2347,7 +2349,7 @@ [(set_attr "conds" "set") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "arlo_imm")] + (set_attr "type" "logics_imm")] ) (define_insn_and_split "*ne_zeroextractsi" @@ -2775,7 +2777,8 @@ "bfc%?\t%0, %2, %1" [(set_attr "length" "4") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable_short_it" "no") + (set_attr "type" "bfm")] ) (define_insn "insv_t2" @@ -2787,7 +2790,8 @@ "bfi%?\t%0, %3, %2, %1" [(set_attr "length" "4") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable_short_it" "no") + (set_attr "type" "bfm")] ) ; constants for op 2 will never be given to these patterns. @@ -2897,8 +2901,8 @@ [(set_attr "predicable" "yes") (set_attr "shift" "2") (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") - (const_string "arlo_shift") - (const_string "arlo_shift_reg")))] + (const_string "logic_shift_imm") + (const_string "logic_shift_reg")))] ) (define_insn "*andsi_notsi_si_compare0" @@ -2911,7 +2915,8 @@ (and:SI (not:SI (match_dup 2)) (match_dup 1)))] "TARGET_32BIT" "bic%.\\t%0, %1, %2" - [(set_attr "conds" "set")] + [(set_attr "conds" "set") + (set_attr "type" "logics_shift_reg")] ) (define_insn "*andsi_notsi_si_compare0_scratch" @@ -2923,7 +2928,8 @@ (clobber (match_scratch:SI 0 "=r"))] "TARGET_32BIT" "bic%.\\t%0, %1, %2" - [(set_attr "conds" "set")] + [(set_attr "conds" "set") + (set_attr "type" "logics_shift_reg")] ) (define_expand "iordi3" @@ -3057,7 +3063,7 @@ (set_attr "arch" "32,t2,t2,32,32") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no,yes,no,no,no") - (set_attr "type" "arlo_imm,*,arlo_imm,*,*")] + (set_attr "type" "logic_imm,logic_reg,logic_imm,logic_reg,logic_reg")] ) (define_insn "*thumb1_iorsi3_insn" @@ -3092,7 +3098,7 @@ "TARGET_32BIT" "orr%.\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "arlo_imm,*")] + (set_attr "type" "logics_imm,logics_reg")] ) (define_insn "*iorsi3_compare0_scratch" @@ -3104,7 +3110,7 @@ "TARGET_32BIT" "orr%.\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "arlo_imm,*")] + (set_attr "type" "logics_imm,logics_reg")] ) (define_expand "xordi3" @@ -3230,7 +3236,7 @@ [(set_attr "length" "4,4,4,16") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no,yes,no,no") - (set_attr "type" "arlo_imm,*,*,*")] + (set_attr "type" "logic_imm,logic_reg,logic_reg,logic_reg")] ) (define_insn "*thumb1_xorsi3_insn" @@ -3241,7 +3247,7 @@ "eor\\t%0, %2" [(set_attr "length" "2") (set_attr "conds" "set") - (set_attr "type" "arlo_imm")] + (set_attr "type" "logics_reg")] ) (define_insn "*xorsi3_compare0" @@ -3254,7 +3260,7 @@ "TARGET_32BIT" "eor%.\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "arlo_imm,*")] + (set_attr "type" "logics_imm,logics_reg")] ) (define_insn "*xorsi3_compare0_scratch" @@ -3265,7 +3271,7 @@ "TARGET_32BIT" "teq%?\\t%0, %1" [(set_attr "conds" "set") - (set_attr "type" "arlo_imm,*")] + (set_attr "type" "logics_imm,logics_reg")] ) ; By splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C), @@ -3754,7 +3760,7 @@ [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") (set_attr "shift" "3") - (set_attr "type" "arlo_shift")]) + (set_attr "type" "logic_shift_reg")]) ;; Shift and rotation insns @@ -3857,7 +3863,7 @@ "TARGET_THUMB1" "lsl\\t%0, %1, %2" [(set_attr "length" "2") - (set_attr "type" "shift,shift_reg") + (set_attr "type" "shift_imm,shift_reg") (set_attr "conds" "set")]) (define_expand "ashrdi3" @@ -3962,7 +3968,7 @@ "TARGET_THUMB1" "asr\\t%0, %1, %2" [(set_attr "length" "2") - (set_attr "type" "shift,shift_reg") + (set_attr "type" "shift_imm,shift_reg") (set_attr "conds" "set")]) (define_expand "lshrdi3" @@ -4059,7 +4065,7 @@ "TARGET_THUMB1" "lsr\\t%0, %1, %2" [(set_attr "length" "2") - (set_attr "type" "shift,shift_reg") + (set_attr "type" "shift_imm,shift_reg") (set_attr "conds" "set")]) (define_expand "rotlsi3" @@ -4121,7 +4127,7 @@ (set_attr "predicable_short_it" "yes,no,no") (set_attr "length" "4") (set_attr "shift" "1") - (set_attr "type" "arlo_shift_reg,arlo_shift,arlo_shift_reg")] + (set_attr "type" "alu_shift_reg,alu_shift_imm,alu_shift_reg")] ) (define_insn "*shiftsi3_compare" @@ -4136,7 +4142,7 @@ "* return arm_output_shift(operands, 1);" [(set_attr "conds" "set") (set_attr "shift" "1") - (set_attr "type" "arlo_shift,arlo_shift_reg")] + (set_attr "type" "alus_shift_imm,alus_shift_reg")] ) (define_insn "*shiftsi3_compare0" @@ -4151,7 +4157,7 @@ "* return arm_output_shift(operands, 1);" [(set_attr "conds" "set") (set_attr "shift" "1") - (set_attr "type" "arlo_shift,arlo_shift_reg")] + (set_attr "type" "alus_shift_imm,alus_shift_reg")] ) (define_insn "*shiftsi3_compare0_scratch" @@ -4165,7 +4171,7 @@ "* return arm_output_shift(operands, 1);" [(set_attr "conds" "set") (set_attr "shift" "1") - (set_attr "type" "shift,shift_reg")] + (set_attr "type" "shift_imm,shift_reg")] ) (define_insn "*not_shiftsi" @@ -4507,7 +4513,8 @@ "sbfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable_short_it" "no") + (set_attr "type" "bfm")] ) (define_insn "extzv_t2" @@ -4519,7 +4526,8 @@ "ubfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "no")] + (set_attr "predicable_short_it" "no") + (set_attr "type" "bfm")] ) @@ -5241,7 +5249,7 @@ "@ # ldr%(h%)\\t%0, %1" - [(set_attr "type" "arlo_shift,load_byte") + [(set_attr "type" "alu_shift_reg,load_byte") (set_attr "predicable" "yes")] ) @@ -5262,7 +5270,7 @@ (match_operand:SI 2 "s_register_operand" "r")))] "TARGET_INT_SIMD" "uxtah%?\\t%0, %2, %1" - [(set_attr "type" "arlo_shift") + [(set_attr "type" "alu_shift_reg") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")] ) @@ -5312,7 +5320,7 @@ # ldrb\\t%0, %1" [(set_attr "length" "4,2") - (set_attr "type" "arlo_shift,load_byte") + (set_attr "type" "alu_shift_reg,load_byte") (set_attr "pool_range" "*,32")] ) @@ -5335,7 +5343,7 @@ # ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2" [(set_attr "length" "8,4") - (set_attr "type" "arlo_shift,load_byte") + (set_attr "type" "alu_shift_reg,load_byte") (set_attr "predicable" "yes")] ) @@ -5358,7 +5366,7 @@ "uxtab%?\\t%0, %2, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "arlo_shift")] + (set_attr "type" "alu_shift_reg")] ) (define_split @@ -5580,7 +5588,7 @@ # ldr%(sh%)\\t%0, %1" [(set_attr "length" "8,4") - (set_attr "type" "arlo_shift,load_byte") + (set_attr "type" "alu_shift_reg,load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") (set_attr "neg_pool_range" "*,244")] @@ -5681,7 +5689,7 @@ # ldr%(sb%)\\t%0, %1" [(set_attr "length" "8,4") - (set_attr "type" "arlo_shift,load_byte") + (set_attr "type" "alu_shift_reg,load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "*,256") (set_attr "neg_pool_range" "*,244")] @@ -5707,7 +5715,7 @@ (match_operand:SI 2 "s_register_operand" "r")))] "TARGET_INT_SIMD" "sxtab%?\\t%0, %2, %1" - [(set_attr "type" "arlo_shift") + [(set_attr "type" "alu_shift_reg") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no")] ) @@ -6484,7 +6492,7 @@ cmp%?\\t%0, #0 sub%.\\t%0, %1, #0" [(set_attr "conds" "set") - (set_attr "type" "arlo_imm,arlo_imm")] + (set_attr "type" "alus_imm,alus_imm")] ) ;; Subroutine to store a half word from a register into memory. @@ -7078,7 +7086,7 @@ mov\\t%0, %1 mov\\t%0, %1" [(set_attr "length" "2") - (set_attr "type" "arlo_imm,load1,store1,mov_reg,mov_imm,mov_imm") + (set_attr "type" "alu_imm,load1,store1,mov_reg,mov_imm,mov_imm") (set_attr "pool_range" "*,32,*,*,*,*") (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")]) @@ -8164,34 +8172,34 @@ (set_attr "arch" "t2,t2,any,any") (set_attr "length" "2,2,4,4") (set_attr "predicable" "yes") - (set_attr "type" "*,*,*,arlo_imm")] + (set_attr "type" "alus_reg,alus_reg,alus_reg,alus_imm")] ) (define_insn "*cmpsi_shiftsi" [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:SI 0 "s_register_operand" "r,r") + (compare:CC (match_operand:SI 0 "s_register_operand" "r,r,r") (match_operator:SI 3 "shift_operator" - [(match_operand:SI 1 "s_register_operand" "r,r") - (match_operand:SI 2 "shift_amount_operand" "M,rM")])))] + [(match_operand:SI 1 "s_register_operand" "r,r,r") + (match_operand:SI 2 "shift_amount_operand" "M,r,M")])))] "TARGET_32BIT" "cmp%?\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") - (set_attr "arch" "32,a") - (set_attr "type" "arlo_shift,arlo_shift_reg")]) + (set_attr "arch" "32,a,a") + (set_attr "type" "alus_shift_imm,alu_shift_reg,alus_shift_imm")]) (define_insn "*cmpsi_shiftsi_swp" [(set (reg:CC_SWP CC_REGNUM) (compare:CC_SWP (match_operator:SI 3 "shift_operator" - [(match_operand:SI 1 "s_register_operand" "r,r") - (match_operand:SI 2 "shift_amount_operand" "M,rM")]) - (match_operand:SI 0 "s_register_operand" "r,r")))] + [(match_operand:SI 1 "s_register_operand" "r,r,r") + (match_operand:SI 2 "shift_amount_operand" "M,r,M")]) + (match_operand:SI 0 "s_register_operand" "r,r,r")))] "TARGET_32BIT" "cmp%?\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") - (set_attr "arch" "32,a") - (set_attr "type" "arlo_shift,arlo_shift_reg")]) + (set_attr "arch" "32,a,a") + (set_attr "type" "alus_shift_imm,alu_shift_reg,alus_shift_imm")]) (define_insn "*arm_cmpsi_negshiftsi_si" [(set (reg:CC_Z CC_REGNUM) @@ -8204,8 +8212,8 @@ "cmn%?\\t%0, %2%S1" [(set_attr "conds" "set") (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") - (const_string "arlo_shift") - (const_string "arlo_shift_reg"))) + (const_string "alus_shift_imm") + (const_string "alus_shift_reg"))) (set_attr "predicable" "yes")] ) @@ -9747,7 +9755,7 @@ (if_then_else (match_operand:SI 3 "mult_operator" "") (const_string "no") (const_string "yes"))]) - (set_attr "type" "arlo_shift,arlo_shift,arlo_shift,arlo_shift_reg")]) + (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_imm,alu_shift_reg")]) (define_split [(set (match_operand:SI 0 "s_register_operand" "") @@ -9784,7 +9792,7 @@ [(set_attr "conds" "set") (set_attr "shift" "4") (set_attr "arch" "32,a") - (set_attr "type" "arlo_shift,arlo_shift_reg")]) + (set_attr "type" "alus_shift_imm,alus_shift_reg")]) (define_insn "*arith_shiftsi_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) @@ -9801,7 +9809,7 @@ [(set_attr "conds" "set") (set_attr "shift" "4") (set_attr "arch" "32,a") - (set_attr "type" "arlo_shift,arlo_shift_reg")]) + (set_attr "type" "alus_shift_imm,alus_shift_reg")]) (define_insn "*sub_shiftsi" [(set (match_operand:SI 0 "s_register_operand" "=r,r") @@ -9814,41 +9822,41 @@ [(set_attr "predicable" "yes") (set_attr "shift" "3") (set_attr "arch" "32,a") - (set_attr "type" "arlo_shift,arlo_shift_reg")]) + (set_attr "type" "alus_shift_imm,alus_shift_reg")]) (define_insn "*sub_shiftsi_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV - (minus:SI (match_operand:SI 1 "s_register_operand" "r,r") + (minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r") (match_operator:SI 2 "shift_operator" - [(match_operand:SI 3 "s_register_operand" "r,r") - (match_operand:SI 4 "shift_amount_operand" "M,rM")])) + [(match_operand:SI 3 "s_register_operand" "r,r,r") + (match_operand:SI 4 "shift_amount_operand" "M,r,M")])) (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r,r") + (set (match_operand:SI 0 "s_register_operand" "=r,r,r") (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3) (match_dup 4)])))] "TARGET_32BIT" "sub%.\\t%0, %1, %3%S2" [(set_attr "conds" "set") (set_attr "shift" "3") - (set_attr "arch" "32,a") - (set_attr "type" "arlo_shift,arlo_shift_reg")]) + (set_attr "arch" "32,a,a") + (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")]) (define_insn "*sub_shiftsi_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV - (minus:SI (match_operand:SI 1 "s_register_operand" "r,r") + (minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r") (match_operator:SI 2 "shift_operator" - [(match_operand:SI 3 "s_register_operand" "r,r") - (match_operand:SI 4 "shift_amount_operand" "M,rM")])) + [(match_operand:SI 3 "s_register_operand" "r,r,r") + (match_operand:SI 4 "shift_amount_operand" "M,r,M")])) (const_int 0))) - (clobber (match_scratch:SI 0 "=r,r"))] + (clobber (match_scratch:SI 0 "=r,r,r"))] "TARGET_32BIT" "sub%.\\t%0, %1, %3%S2" [(set_attr "conds" "set") (set_attr "shift" "3") - (set_attr "arch" "32,a") - (set_attr "type" "arlo_shift,arlo_shift_reg")]) + (set_attr "arch" "32,a,a") + (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")]) (define_insn_and_split "*and_scc" @@ -10900,9 +10908,9 @@ (set_attr "length" "4,4,8,8") (set_attr_alternative "type" [(if_then_else (match_operand 3 "const_int_operand" "") - (const_string "arlo_imm" ) + (const_string "alu_imm" ) (const_string "*")) - (const_string "arlo_imm") + (const_string "alu_imm") (const_string "*") (const_string "*")])] ) @@ -10942,9 +10950,9 @@ (set_attr "length" "4,4,8,8") (set_attr_alternative "type" [(if_then_else (match_operand 3 "const_int_operand" "") - (const_string "arlo_imm" ) + (const_string "alu_imm" ) (const_string "*")) - (const_string "arlo_imm") + (const_string "alu_imm") (const_string "*") (const_string "*")])] ) |