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-rw-r--r--gcc/config/bfin/bfin.md8
1 files changed, 8 insertions, 0 deletions
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 494b27e3730..63fc99ca1fe 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -908,6 +908,14 @@
"%0 = %h1 * %h2 (FU);"
[(set_attr "type" "dsp32")])
+(define_insn "usmulhisi3"
+ [(set (match_operand:SI 0 "register_operand" "=W")
+ (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "W"))
+ (sign_extend:SI (match_operand:HI 2 "register_operand" "W"))))]
+ ""
+ "%0 = %h2 * %h1 (IS,M);"
+ [(set_attr "type" "dsp32")])
+
;; The processor also supports ireg += mreg or ireg -= mreg, but these
;; are unusable if we don't ensure that the corresponding lreg is zero.
;; The same applies to the add/subtract constant versions involving