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-rw-r--r--gcc/config/i386/i386.md111
1 files changed, 33 insertions, 78 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index f50bcc19320..26bbc9a5234 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -57,7 +57,6 @@
;; X -- don't print any sort of PIC '@' suffix for a symbol.
;; & -- print some in-use local-dynamic symbol name.
;; H -- print a memory address offset by 8; used for sse high-parts
-;; Y -- print condition for SSE5 com* instruction.
;; + -- print a branch hint as 'cs' or 'ds' prefix
;; ; -- print a semicolon (after prefixes due to bug in older gas).
@@ -196,15 +195,6 @@
(UNSPEC_PCMPESTR 144)
(UNSPEC_PCMPISTR 145)
- ;; For SSE5
- (UNSPEC_SSE5_INTRINSIC 150)
- (UNSPEC_SSE5_UNSIGNED_CMP 151)
- (UNSPEC_SSE5_TRUEFALSE 152)
- (UNSPEC_SSE5_PERMUTE 153)
- (UNSPEC_FRCZ 154)
- (UNSPEC_CVTPH2PS 155)
- (UNSPEC_CVTPS2PH 156)
-
; For AES support
(UNSPEC_AESENC 159)
(UNSPEC_AESENCLAST 160)
@@ -259,20 +249,6 @@
(COM_TRUE_P 5)
])
-;; Constants used in the SSE5 pperm instruction
-(define_constants
- [(PPERM_SRC 0x00) /* copy source */
- (PPERM_INVERT 0x20) /* invert source */
- (PPERM_REVERSE 0x40) /* bit reverse source */
- (PPERM_REV_INV 0x60) /* bit reverse & invert src */
- (PPERM_ZERO 0x80) /* all 0's */
- (PPERM_ONES 0xa0) /* all 1's */
- (PPERM_SIGN 0xc0) /* propagate sign bit */
- (PPERM_INV_SIGN 0xe0) /* invert & propagate sign */
- (PPERM_SRC1 0x00) /* use first source byte */
- (PPERM_SRC2 0x10) /* use second source byte */
- ])
-
;; Registers by name.
(define_constants
[(AX_REG 0)
@@ -465,7 +441,7 @@
]
(const_int 0)))
-;; There are also additional prefixes in 3DNOW, SSSE3 or SSE5.
+;; There are also additional prefixes in 3DNOW, SSSE3.
;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte,
;; sseiadd1,ssecvt1 to 0f7a with no DREX byte.
;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a.
@@ -1555,7 +1531,7 @@
#ifdef HAVE_AS_IX86_SAHF
return "sahf";
#else
- return ".byte\t0x9e";
+ return ASM_BYTE "0x9e";
#endif
}
[(set_attr "length" "1")
@@ -8879,8 +8855,6 @@
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"")
-;; SSE5 scalar multiply/add instructions are defined in sse.md.
-
;; Divide instructions
@@ -14826,23 +14800,11 @@
(match_operator:MODEF 1 "sse_comparison_operator"
[(match_operand:MODEF 2 "register_operand" "0")
(match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
- "SSE_FLOAT_MODE_P (<MODE>mode) && !TARGET_SSE5"
+ "SSE_FLOAT_MODE_P (<MODE>mode)"
"cmp%D1s<ssemodefsuffix>\t{%3, %0|%0, %3}"
[(set_attr "type" "ssecmp")
(set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
-
-(define_insn "*sse5_setcc<mode>"
- [(set (match_operand:MODEF 0 "register_operand" "=x")
- (match_operator:MODEF 1 "sse5_comparison_float_operator"
- [(match_operand:MODEF 2 "register_operand" "x")
- (match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE5"
- "com%Y1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "sse4arg")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "<MODE>")])
-
;; Basic conditional jump instructions.
;; We ignore the overflow flag for signed branch instructions.
@@ -15476,22 +15438,25 @@
(match_operand:SI 1 "" ""))
(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
(match_operand:SI 2 "immediate_operand" "i")))]
- "!TARGET_64BIT"
+ "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
{
if (constant_call_address_operand (operands[0], Pmode))
- {
- if (SIBLING_CALL_P (insn))
- return "jmp\t%P0";
- else
- return "call\t%P0";
- }
- if (SIBLING_CALL_P (insn))
- return "jmp\t%A0";
- else
- return "call\t%A0";
+ return "call\t%P0";
+ return "call\t%A0";
}
[(set_attr "type" "call")])
+(define_insn "*sibcall_pop_1"
+ [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,U"))
+ (match_operand:SI 1 "" ""))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 2 "immediate_operand" "i,i")))]
+ "SIBLING_CALL_P (insn) && !TARGET_64BIT"
+ "@
+ jmp\t%P0
+ jmp\t%A0"
+ [(set_attr "type" "call")])
+
(define_expand "call"
[(call (match_operand:QI 0 "" "")
(match_operand 1 "" ""))
@@ -16473,7 +16438,7 @@
(unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
UNSPEC_TLS_GD)]
"TARGET_64BIT"
- { return ".byte\t0x66\n\tlea{q}\t{%a1@TLSGD(%%rip), %%rdi|rdi, %a1@TLSGD[rip]}\n" ASM_SHORT "0x6666\n\trex64\n\tcall\t%P2"; }
+ { return ASM_BYTE "0x66\n\tlea{q}\t{%a1@TLSGD(%%rip), %%rdi|rdi, %a1@TLSGD[rip]}\n" ASM_SHORT "0x6666\n\trex64\n\tcall\t%P2"; }
[(set_attr "type" "multi")
(set_attr "length" "16")])
@@ -20640,20 +20605,6 @@
[(set_attr "type" "fcmov")
(set_attr "mode" "XF")])
-;; All moves in SSE5 pcmov instructions are 128 bits and hence we restrict
-;; the scalar versions to have only XMM registers as operands.
-
-;; SSE5 conditional move
-(define_insn "*sse5_pcmov_<mode>"
- [(set (match_operand:MODEF 0 "register_operand" "=x,x")
- (if_then_else:MODEF
- (match_operand:MODEF 1 "register_operand" "x,0")
- (match_operand:MODEF 2 "register_operand" "0,x")
- (match_operand:MODEF 3 "register_operand" "x,x")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)"
- "pcmov\t{%1, %3, %2, %0|%0, %2, %3, %1}"
- [(set_attr "type" "sse4arg")])
-
;; These versions of the min/max patterns are intentionally ignorant of
;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
@@ -22092,22 +22043,26 @@
(match_operand:SI 2 "" "")))
(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
(match_operand:SI 3 "immediate_operand" "i")))]
- "!TARGET_64BIT"
+ "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
{
if (constant_call_address_operand (operands[1], Pmode))
- {
- if (SIBLING_CALL_P (insn))
- return "jmp\t%P1";
- else
- return "call\t%P1";
- }
- if (SIBLING_CALL_P (insn))
- return "jmp\t%A1";
- else
- return "call\t%A1";
+ return "call\t%P1";
+ return "call\t%A1";
}
[(set_attr "type" "callv")])
+(define_insn "*sibcall_value_pop_1"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,U"))
+ (match_operand:SI 2 "" "")))
+ (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 3 "immediate_operand" "i,i")))]
+ "SIBLING_CALL_P (insn) && !TARGET_64BIT"
+ "@
+ jmp\t%P1
+ jmp\t%A1"
+ [(set_attr "type" "callv")])
+
(define_insn "*call_value_0"
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
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