diff options
Diffstat (limited to 'gcc/config/m32r/m32r.md')
| -rw-r--r-- | gcc/config/m32r/m32r.md | 415 |
1 files changed, 20 insertions, 395 deletions
diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md index d117e1e6928..0c76a044ccc 100644 --- a/gcc/config/m32r/m32r.md +++ b/gcc/config/m32r/m32r.md @@ -1180,18 +1180,6 @@ ;; thus merge the compare and branch into one instruction, so they are ;; preferred. -(define_expand "cmpsi" - [(set (reg:CC 17) - (compare:CC (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "reg_or_cmp_int16_operand" "")))] - "" - " -{ - m32r_compare_op0 = operands[0]; - m32r_compare_op1 = operands[1]; - DONE; -}") - (define_insn "cmp_eqsi_zero_insn" [(set (reg:CC 17) (eq:CC (match_operand:SI 0 "register_operand" "r,r") @@ -1256,114 +1244,20 @@ ;; These control RTL generation for conditional jump insns. -(define_expand "beq" - [(set (pc) - (if_then_else (match_dup 1) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - " -{ - operands[1] = gen_compare (EQ, m32r_compare_op0, m32r_compare_op1, FALSE); -}") - -(define_expand "bne" - [(set (pc) - (if_then_else (match_dup 1) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - " -{ - operands[1] = gen_compare (NE, m32r_compare_op0, m32r_compare_op1, FALSE); -}") - -(define_expand "bgt" - [(set (pc) - (if_then_else (match_dup 1) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - " -{ - operands[1] = gen_compare (GT, m32r_compare_op0, m32r_compare_op1, FALSE); -}") - -(define_expand "ble" - [(set (pc) - (if_then_else (match_dup 1) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - " -{ - operands[1] = gen_compare (LE, m32r_compare_op0, m32r_compare_op1, FALSE); -}") - -(define_expand "bge" - [(set (pc) - (if_then_else (match_dup 1) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - " -{ - operands[1] = gen_compare (GE, m32r_compare_op0, m32r_compare_op1, FALSE); -}") - -(define_expand "blt" - [(set (pc) - (if_then_else (match_dup 1) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - " -{ - operands[1] = gen_compare (LT, m32r_compare_op0, m32r_compare_op1, FALSE); -}") - -(define_expand "bgtu" - [(set (pc) - (if_then_else (match_dup 1) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - " -{ - operands[1] = gen_compare (GTU, m32r_compare_op0, m32r_compare_op1, FALSE); -}") - -(define_expand "bleu" - [(set (pc) - (if_then_else (match_dup 1) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - " -{ - operands[1] = gen_compare (LEU, m32r_compare_op0, m32r_compare_op1, FALSE); -}") - -(define_expand "bgeu" - [(set (pc) - (if_then_else (match_dup 1) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - " -{ - operands[1] = gen_compare (GEU, m32r_compare_op0, m32r_compare_op1, FALSE); -}") - -(define_expand "bltu" +(define_expand "cbranchsi4" + ; the comparison is emitted by gen_compare if needed. [(set (pc) - (if_then_else (match_dup 1) - (label_ref (match_operand 0 "" "")) + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(match_operand:SI 1 "register_operand" "") + (match_operand:SI 2 "reg_or_cmp_int16_operand" "")]) + (label_ref (match_operand 3 "" "")) (pc)))] "" " { - operands[1] = gen_compare (LTU, m32r_compare_op0, m32r_compare_op1, FALSE); + operands[0] = gen_compare (GET_CODE (operands[0]), operands[1], operands[2], FALSE); + operands[1] = XEXP (operands[0], 0); + operands[2] = XEXP (operands[0], 1); }") ;; Now match both normal and inverted jump. @@ -1597,40 +1491,21 @@ ;; S<cc> operations to set a register to 1/0 based on a comparison -(define_expand "seq" - [(match_operand:SI 0 "register_operand" "")] +(define_expand "cstoresi4" + [(match_operand:SI 0 "register_operand" "") + (match_operator:SI 1 "ordered_comparison_operator" + [(match_operand:SI 2 "register_operand" "") + (match_operand:SI 3 "reg_or_cmp_int16_operand" "")])] "" " { - rtx op0 = operands[0]; - rtx op1 = m32r_compare_op0; - rtx op2 = m32r_compare_op1; - enum machine_mode mode = GET_MODE (op0); - - if (mode != SImode) + if (GET_MODE (operands[0]) != SImode) FAIL; - if (! register_operand (op1, mode)) - op1 = force_reg (mode, op1); - - if (TARGET_M32RX || TARGET_M32R2) - { - if (! reg_or_zero_operand (op2, mode)) - op2 = force_reg (mode, op2); - - emit_insn (gen_seq_insn_m32rx (op0, op1, op2)); - DONE; - } - if (GET_CODE (op2) == CONST_INT && INTVAL (op2) == 0) - { - emit_insn (gen_seq_zero_insn (op0, op1)); - DONE; - } - - if (! reg_or_eq_int16_operand (op2, mode)) - op2 = force_reg (mode, op2); + if (!gen_cond_store (GET_CODE (operands[1]), + operands[0], operands[2], operands[3])) + FAIL; - emit_insn (gen_seq_insn (op0, op1, op2)); DONE; }") @@ -1739,41 +1614,6 @@ end_sequence (); }") -(define_expand "sne" - [(match_operand:SI 0 "register_operand" "")] - "" - " -{ - rtx op0 = operands[0]; - rtx op1 = m32r_compare_op0; - rtx op2 = m32r_compare_op1; - enum machine_mode mode = GET_MODE (op0); - - if (mode != SImode) - FAIL; - - if (GET_CODE (op2) != CONST_INT - || (INTVAL (op2) != 0 && satisfies_constraint_K (op2))) - { - rtx reg; - - if (reload_completed || reload_in_progress) - FAIL; - - reg = gen_reg_rtx (SImode); - emit_insn (gen_xorsi3 (reg, op1, op2)); - op1 = reg; - - if (! register_operand (op1, mode)) - op1 = force_reg (mode, op1); - - emit_insn (gen_sne_zero_insn (op0, op1)); - DONE; - } - else - FAIL; -}") - (define_insn "sne_zero_insn" [(set (match_operand:SI 0 "register_operand" "=r") (ne:SI (match_operand:SI 1 "register_operand" "r") @@ -1801,29 +1641,6 @@ (ne:SI (reg:CC 17) (const_int 0)))] "") -(define_expand "slt" - [(match_operand:SI 0 "register_operand" "")] - "" - " -{ - rtx op0 = operands[0]; - rtx op1 = m32r_compare_op0; - rtx op2 = m32r_compare_op1; - enum machine_mode mode = GET_MODE (op0); - - if (mode != SImode) - FAIL; - - if (! register_operand (op1, mode)) - op1 = force_reg (mode, op1); - - if (! reg_or_int16_operand (op2, mode)) - op2 = force_reg (mode, op2); - - emit_insn (gen_slt_insn (op0, op1, op2)); - DONE; -}") - (define_insn "slt_insn" [(set (match_operand:SI 0 "register_operand" "=r,r") (lt:SI (match_operand:SI 1 "register_operand" "r,r") @@ -1847,46 +1664,6 @@ (ne:SI (reg:CC 17) (const_int 0)))] "") -(define_expand "sle" - [(match_operand:SI 0 "register_operand" "")] - "" - " -{ - rtx op0 = operands[0]; - rtx op1 = m32r_compare_op0; - rtx op2 = m32r_compare_op1; - enum machine_mode mode = GET_MODE (op0); - - if (mode != SImode) - FAIL; - - if (! register_operand (op1, mode)) - op1 = force_reg (mode, op1); - - if (GET_CODE (op2) == CONST_INT) - { - HOST_WIDE_INT value = INTVAL (op2); - if (value >= 2147483647) - { - emit_move_insn (op0, const1_rtx); - DONE; - } - - op2 = GEN_INT (value+1); - if (value < -32768 || value >= 32767) - op2 = force_reg (mode, op2); - - emit_insn (gen_slt_insn (op0, op1, op2)); - DONE; - } - - if (! register_operand (op2, mode)) - op2 = force_reg (mode, op2); - - emit_insn (gen_sle_insn (op0, op1, op2)); - DONE; -}") - (define_insn "sle_insn" [(set (match_operand:SI 0 "register_operand" "=r") (le:SI (match_operand:SI 1 "register_operand" "r") @@ -1933,52 +1710,6 @@ (neg:SI (match_dup 0)))] "") -(define_expand "sgt" - [(match_operand:SI 0 "register_operand" "")] - "" - " -{ - rtx op0 = operands[0]; - rtx op1 = m32r_compare_op0; - rtx op2 = m32r_compare_op1; - enum machine_mode mode = GET_MODE (op0); - - if (mode != SImode) - FAIL; - - if (! register_operand (op1, mode)) - op1 = force_reg (mode, op1); - - if (! register_operand (op2, mode)) - op2 = force_reg (mode, op2); - - emit_insn (gen_slt_insn (op0, op2, op1)); - DONE; -}") - -(define_expand "sge" - [(match_operand:SI 0 "register_operand" "")] - "" - " -{ - rtx op0 = operands[0]; - rtx op1 = m32r_compare_op0; - rtx op2 = m32r_compare_op1; - enum machine_mode mode = GET_MODE (op0); - - if (mode != SImode) - FAIL; - - if (! register_operand (op1, mode)) - op1 = force_reg (mode, op1); - - if (! reg_or_int16_operand (op2, mode)) - op2 = force_reg (mode, op2); - - emit_insn (gen_sge_insn (op0, op1, op2)); - DONE; -}") - (define_insn "sge_insn" [(set (match_operand:SI 0 "register_operand" "=r,r") (ge:SI (match_operand:SI 1 "register_operand" "r,r") @@ -2025,29 +1756,6 @@ (neg:SI (match_dup 0)))] "") -(define_expand "sltu" - [(match_operand:SI 0 "register_operand" "")] - "" - " -{ - rtx op0 = operands[0]; - rtx op1 = m32r_compare_op0; - rtx op2 = m32r_compare_op1; - enum machine_mode mode = GET_MODE (op0); - - if (mode != SImode) - FAIL; - - if (! register_operand (op1, mode)) - op1 = force_reg (mode, op1); - - if (! reg_or_int16_operand (op2, mode)) - op2 = force_reg (mode, op2); - - emit_insn (gen_sltu_insn (op0, op1, op2)); - DONE; -}") - (define_insn "sltu_insn" [(set (match_operand:SI 0 "register_operand" "=r,r") (ltu:SI (match_operand:SI 1 "register_operand" "r,r") @@ -2071,43 +1779,6 @@ (ne:SI (reg:CC 17) (const_int 0)))] "") -(define_expand "sleu" - [(match_operand:SI 0 "register_operand" "")] - "" - " -{ - rtx op0 = operands[0]; - rtx op1 = m32r_compare_op0; - rtx op2 = m32r_compare_op1; - enum machine_mode mode = GET_MODE (op0); - - if (mode != SImode) - FAIL; - - if (GET_CODE (op2) == CONST_INT) - { - HOST_WIDE_INT value = INTVAL (op2); - if (value >= 2147483647) - { - emit_move_insn (op0, const1_rtx); - DONE; - } - - op2 = GEN_INT (value+1); - if (value < 0 || value >= 32767) - op2 = force_reg (mode, op2); - - emit_insn (gen_sltu_insn (op0, op1, op2)); - DONE; - } - - if (! register_operand (op2, mode)) - op2 = force_reg (mode, op2); - - emit_insn (gen_sleu_insn (op0, op1, op2)); - DONE; -}") - (define_insn "sleu_insn" [(set (match_operand:SI 0 "register_operand" "=r") (leu:SI (match_operand:SI 1 "register_operand" "r") @@ -2154,52 +1825,6 @@ (neg:SI (match_dup 0)))] "") -(define_expand "sgtu" - [(match_operand:SI 0 "register_operand" "")] - "" - " -{ - rtx op0 = operands[0]; - rtx op1 = m32r_compare_op0; - rtx op2 = m32r_compare_op1; - enum machine_mode mode = GET_MODE (op0); - - if (mode != SImode) - FAIL; - - if (! register_operand (op1, mode)) - op1 = force_reg (mode, op1); - - if (! register_operand (op2, mode)) - op2 = force_reg (mode, op2); - - emit_insn (gen_sltu_insn (op0, op2, op1)); - DONE; -}") - -(define_expand "sgeu" - [(match_operand:SI 0 "register_operand" "")] - "" - " -{ - rtx op0 = operands[0]; - rtx op1 = m32r_compare_op0; - rtx op2 = m32r_compare_op1; - enum machine_mode mode = GET_MODE (op0); - - if (mode != SImode) - FAIL; - - if (! register_operand (op1, mode)) - op1 = force_reg (mode, op1); - - if (! reg_or_int16_operand (op2, mode)) - op2 = force_reg (mode, op2); - - emit_insn (gen_sgeu_insn (op0, op1, op2)); - DONE; -}") - (define_insn "sgeu_insn" [(set (match_operand:SI 0 "register_operand" "=r,r") (geu:SI (match_operand:SI 1 "register_operand" "r,r") @@ -2546,8 +2171,8 @@ FAIL; /* Generate the comparison that will set the carry flag. */ - operands[1] = gen_compare (GET_CODE (operands[1]), m32r_compare_op0, - m32r_compare_op1, TRUE); + operands[1] = gen_compare (GET_CODE (operands[1]), XEXP (operands[1], 0), + XEXP (operands[1], 1), TRUE); /* See other movsicc pattern below for reason why. */ emit_insn (gen_blockage ()); |