diff options
Diffstat (limited to 'gcc/config/m68k/m68k.md')
| -rw-r--r-- | gcc/config/m68k/m68k.md | 420 |
1 files changed, 237 insertions, 183 deletions
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 68c665cc214..1917717076d 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -24,7 +24,7 @@ ;;- The MCF5200 "ColdFire" architecture is a reduced version of the ;;- 68k ISA. Differences include reduced support for byte and word ;;- operands and the removal of BCD, bitfield, rotate, and integer -;;- divide instructions. The TARGET_5200 flag turns the use of the +;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the ;;- removed opcodes and addressing modes off. ;;- @@ -199,7 +199,7 @@ "" "* { - if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0])) + if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0])) return \"tst%.l %0\"; /* If you think that the 68020 does not support tstl a0, reread page B-167 of the 68020 manual more carefully. */ @@ -333,7 +333,7 @@ [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>") (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) @@ -373,7 +373,7 @@ [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r") (match_operand:SI 1 "general_operand" "r,mrKs")))] - "TARGET_5200" + "TARGET_COLDFIRE" "* { if (REG_P (operands[1]) @@ -396,14 +396,14 @@ [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_src_operand" "") (match_operand:HI 1 "general_src_operand" "")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "m68k_last_compare_had_fp_operands = 0;") (define_insn "" [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>") (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) @@ -432,14 +432,14 @@ [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_src_operand" "") (match_operand:QI 1 "general_src_operand" "")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "m68k_last_compare_had_fp_operands = 0;") (define_insn "" [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>") (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) @@ -557,7 +557,7 @@ (const_int 1) (minus:SI (const_int 7) (match_operand:SI 1 "general_operand" "di"))))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") ;; This is the same as the above pattern except for the constraints. The 'i' @@ -568,7 +568,7 @@ (const_int 1) (minus:SI (const_int 7) (match_operand:SI 1 "general_operand" "d"))))] - "TARGET_5200" + "TARGET_COLDFIRE" "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") (define_insn "" @@ -609,7 +609,7 @@ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m") (const_int 1) (match_operand:SI 1 "const_int_operand" "n")))] - "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200" + "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE" "* { operands[1] = GEN_INT (7 - INTVAL (operands[1])); @@ -620,7 +620,7 @@ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do") (const_int 1) (match_operand:SI 1 "const_int_operand" "n")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[0]) == MEM) @@ -641,7 +641,7 @@ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ") (const_int 1) (match_operand:SI 1 "const_int_operand" "n")))] - "TARGET_5200" + "TARGET_COLDFIRE" "* { if (GET_CODE (operands[0]) == MEM) @@ -688,7 +688,7 @@ (const_int 0))] ;; clr insns on 68000 read before writing. ;; This isn't so on the 68010, but we have no TARGET_68010. - "((TARGET_68020 || TARGET_5200) + "((TARGET_68020 || TARGET_COLDFIRE) || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))" "* { @@ -712,7 +712,7 @@ } } /* moveq is faster on the 68000. */ - if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200)) + if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_COLDFIRE)) return \"moveq %#0,%0\"; return \"clr%.l %0\"; }") @@ -763,7 +763,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<") (match_operand:SI 1 "general_src_operand" "daymSKT,n,i"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { return output_move_simode (operands); @@ -772,7 +772,7 @@ (define_insn "" [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g") (match_operand:SI 1 "general_operand" "g,r<Q>"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_move_simode (operands);") ;; Special case of fullword move, where we need to get a non-GOT PIC @@ -797,13 +797,13 @@ (define_insn "" [(set (match_operand:HI 0 "nonimmediate_operand" "=g") (match_operand:HI 1 "general_src_operand" "gS"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* return output_move_himode (operands);") (define_insn "" [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g") (match_operand:HI 1 "general_operand" "g,r<Q>"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_move_himode (operands);") (define_expand "movstricthi" @@ -815,13 +815,13 @@ (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) (match_operand:HI 1 "general_src_operand" "rmSn"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* return output_move_stricthi (operands);") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m")) (match_operand:HI 1 "general_src_operand" "rmn,r"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_move_stricthi (operands);") (define_expand "movqi" @@ -833,13 +833,13 @@ (define_insn "" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m") (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* return output_move_qimode (operands);") (define_insn "" [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,d*a") (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_move_qimode (operands);") (define_expand "movstrictqi" @@ -851,20 +851,20 @@ (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) (match_operand:QI 1 "general_src_operand" "dmSn"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* return output_move_strictqi (operands);") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m")) (match_operand:QI 1 "general_src_operand" "dmn,d"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_move_strictqi (operands);") (define_expand "pushqi1" [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int -2))) (set (mem:QI (plus:SI (reg:SI 15) (const_int 1))) (match_operand:QI 0 "general_operand" ""))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "") (define_expand "movsf" @@ -876,7 +876,7 @@ (define_insn "" [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf") (match_operand:SF 1 "general_operand" "rmfF"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (FP_REG_P (operands[0])) @@ -898,7 +898,7 @@ if (operands[1] == CONST0_RTX (SFmode) /* clr insns on 68000 read before writing. This isn't so on the 68010, but we have no TARGET_68010. */ - && ((TARGET_68020 || TARGET_5200) + && ((TARGET_68020 || TARGET_COLDFIRE) || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) { if (ADDRESS_REG_P (operands[0])) @@ -921,7 +921,7 @@ } } /* moveq is faster on the 68000. */ - if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200)) + if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_COLDFIRE)) { return \"moveq %#0,%0\"; } @@ -933,7 +933,7 @@ (define_insn "" [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g") (match_operand:SF 1 "general_operand" "g,r"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return \"move%.l %1,%0\";") (define_expand "movdf" @@ -947,7 +947,7 @@ (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))] ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>") ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (FP_REG_P (operands[0])) @@ -983,7 +983,7 @@ (define_insn "" [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g") (match_operand:DF 1 "general_operand" "g,r"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_move_double (operands);") ;; ??? The XFmode patterns are schizophrenic about whether constants are @@ -1062,7 +1062,7 @@ (define_insn "" [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>") (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))] - "! TARGET_68881 && ! TARGET_5200" + "! TARGET_68881 && ! TARGET_COLDFIRE" "* { if (FP_REG_P (operands[0])) @@ -1103,7 +1103,7 @@ (define_insn "" [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g") (match_operand:XF 1 "nonimmediate_operand" "g,r"))] - "! TARGET_68881 && TARGET_5200" + "! TARGET_68881 && TARGET_COLDFIRE" "* return output_move_double (operands);") (define_expand "movdi" @@ -1122,7 +1122,7 @@ ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))] ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f") ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (FP_REG_P (operands[0])) @@ -1158,7 +1158,7 @@ (define_insn "" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g") (match_operand:DI 1 "general_operand" "g,r"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_move_double (operands);") ;; Thus goes after the move instructions @@ -1273,7 +1273,7 @@ (define_insn "*zero_extendsidi2_cf" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m") (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,r")))] - "TARGET_5200" + "TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -1297,7 +1297,7 @@ (define_insn "*zero_extendsidi2" [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -1398,9 +1398,9 @@ { if (GET_CODE (operands[1]) == REG && REGNO (operands[0]) == REGNO (operands[1])) - return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\"); + return (!TARGET_COLDFIRE ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\"); if (reg_mentioned_p (operands[0], operands[1])) - return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\" + return (!TARGET_COLDFIRE ? \"move%.b %1,%0\;and%.w %#0xFF,%0\" : \"move%.b %1,%0\;and%.l %#0xFF,%0\"); return \"clr%.w %0\;move%.b %1,%0\"; } @@ -1490,7 +1490,7 @@ { CC_STATUS_INIT; operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); - if (TARGET_68020 || TARGET_5200) + if (TARGET_68020 || TARGET_COLDFIRE) return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\"; else return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\"; @@ -1505,7 +1505,7 @@ { CC_STATUS_INIT; operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); - if (TARGET_68020 || TARGET_5200) + if (TARGET_68020 || TARGET_COLDFIRE) return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\"; else return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\"; @@ -1520,7 +1520,7 @@ { CC_STATUS_INIT; operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); - if (TARGET_68020 || TARGET_5200) + if (TARGET_68020 || TARGET_COLDFIRE) return \"move%.l %1,%2\;smi %0\;extb%.l %0\"; else return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\"; @@ -1552,7 +1552,7 @@ output_asm_insn (\"add%.l %2,%3\", operands); else output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands); - if (TARGET_68020 || TARGET_5200) + if (TARGET_68020 || TARGET_COLDFIRE) return \"smi %0\;extb%.l %0\"; else return \"smi %0\;ext%.w %0\;ext%.l %0\"; @@ -1579,7 +1579,7 @@ (define_insn "extendqisi2" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))] - "TARGET_68020 || TARGET_5200" + "TARGET_68020 || TARGET_COLDFIRE" "extb%.l %0") ;; Conversions between float and double. @@ -1836,7 +1836,7 @@ && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) output_asm_insn (\"move%.l %4,%3\", operands); output_asm_insn (\"move%.l %1,%0\;smi %2\", operands); - if (TARGET_68020 || TARGET_5200) + if (TARGET_68020 || TARGET_COLDFIRE) output_asm_insn (\"extb%.l %2\", operands); else output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands); @@ -1853,7 +1853,7 @@ (const_int 32)) (match_operand:DI 2 "general_operand" "0,0,0,0"))) (clobber (match_scratch:SI 3 "=&d,X,a,?d"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -2031,14 +2031,14 @@ (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))] - "! TARGET_5200" + "! TARGET_COLDFIRE" "* return output_addsi3 (operands);") (define_insn "*addsi3_5200" [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r") (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0") (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_addsi3 (operands);") (define_insn "" @@ -2046,14 +2046,14 @@ (plus:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "add%.w %2,%0") (define_insn "addhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r") (plus:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_src_operand" "dn,rmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[2]) == CONST_INT) @@ -2113,7 +2113,7 @@ [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) (plus:HI (match_dup 0) (match_operand:HI 1 "general_src_operand" "dn,rmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[1]) == CONST_INT) @@ -2167,7 +2167,7 @@ [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[1]) == CONST_INT) @@ -2221,7 +2221,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") (plus:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[2]) == CONST_INT) @@ -2245,7 +2245,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) (plus:QI (match_dup 0) (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[1]) == CONST_INT) @@ -2269,7 +2269,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[1]) == CONST_INT) @@ -2377,7 +2377,7 @@ (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm")) (const_int 32)))) (clobber (match_scratch:SI 3 "=&d,X,a,?d"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -2501,35 +2501,35 @@ (minus:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "sub%.w %2,%0") (define_insn "subhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r") (minus:HI (match_operand:HI 1 "general_operand" "0,0") (match_operand:HI 2 "general_src_operand" "dn,rmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "sub%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) (minus:HI (match_dup 0) (match_operand:HI 1 "general_src_operand" "dn,rmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "sub%.w %1,%0") (define_insn "subqi3" [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") (minus:QI (match_operand:QI 1 "general_operand" "0,0") (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "sub%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) (minus:QI (match_dup 0) (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "sub%.b %1,%0") (define_expand "subdf3" @@ -2663,7 +2663,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "") (mult:SI (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" "")))] - "TARGET_68020 || TARGET_5200" + "TARGET_68020 || TARGET_COLDFIRE" "") (define_insn "" @@ -2678,7 +2678,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (mult:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "d<Q>")))] - "TARGET_5200" + "TARGET_COLDFIRE" "muls%.l %2,%0") (define_insn "umulhisi3" @@ -2724,7 +2724,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) (zero_extend:DI (match_dup 2))) (const_int 32))))])] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "") (define_insn "" @@ -2735,7 +2735,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) (zero_extend:DI (match_dup 2))) (const_int 32))))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "mulu%.l %2,%3:%0") ; Match immediate case. For 2.4 only match things < 2^31. @@ -2750,7 +2750,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) (match_dup 2)) (const_int 32))))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200 + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE && (unsigned) INTVAL (operands[2]) <= 0x7fffffff" "mulu%.l %2,%3:%0") @@ -2763,7 +2763,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) (sign_extend:DI (match_dup 2))) (const_int 32))))])] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "") (define_insn "" @@ -2774,7 +2774,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) (sign_extend:DI (match_dup 2))) (const_int 32))))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "muls%.l %2,%3:%0") (define_insn "" @@ -2785,7 +2785,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) (match_dup 2)) (const_int 32))))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "muls%.l %2,%3:%0") (define_expand "umulsi3_highpart" @@ -2797,7 +2797,7 @@ (zero_extend:DI (match_operand:SI 2 "general_operand" ""))) (const_int 32)))) (clobber (match_dup 3))])] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" " { operands[3] = gen_reg_rtx (SImode); @@ -2822,7 +2822,7 @@ (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm"))) (const_int 32)))) (clobber (match_operand:SI 1 "register_operand" "=d"))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "mulu%.l %3,%0:%1") (define_insn "const_umulsi3_highpart" @@ -2833,7 +2833,7 @@ (match_operand:DI 3 "const_uint32_operand" "n")) (const_int 32)))) (clobber (match_operand:SI 1 "register_operand" "=d"))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "mulu%.l %3,%0:%1") (define_expand "smulsi3_highpart" @@ -2845,7 +2845,7 @@ (sign_extend:DI (match_operand:SI 2 "general_operand" ""))) (const_int 32)))) (clobber (match_dup 3))])] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" " { operands[3] = gen_reg_rtx (SImode); @@ -2866,7 +2866,7 @@ (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm"))) (const_int 32)))) (clobber (match_operand:SI 1 "register_operand" "=d"))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "muls%.l %3,%0:%1") (define_insn "const_smulsi3_highpart" @@ -2877,7 +2877,7 @@ (match_operand:DI 3 "const_sint32_operand" "n")) (const_int 32)))) (clobber (match_operand:SI 1 "register_operand" "=d"))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "muls%.l %3,%0:%1") (define_expand "muldf3" @@ -3089,13 +3089,40 @@ ;; Remainder instructions. -(define_insn "divmodsi4" +(define_expand "divmodsi4" + [(parallel + [(set (match_operand:SI 0 "nonimmediate_operand" "") + (div:SI (match_operand:SI 1 "general_operand" "") + (match_operand:SI 2 "general_src_operand" ""))) + (set (match_operand:SI 3 "nonimmediate_operand" "") + (mod:SI (match_dup 1) (match_dup 2)))])] + "TARGET_68020 || TARGET_CF_HWDIV" + "") + +(define_insn "" + [(set (match_operand:SI 0 "nonimmediate_operand" "=d") + (div:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_src_operand" "d<Q>U"))) + (set (match_operand:SI 3 "nonimmediate_operand" "=&d") + (mod:SI (match_dup 1) (match_dup 2)))] + "TARGET_CF_HWDIV" + "* +{ + if (find_reg_note (insn, REG_UNUSED, operands[3])) + return \"divs%.l %2,%0\"; + else if (find_reg_note (insn, REG_UNUSED, operands[0])) + return \"rems%.l %2,%3:%0\"; + else + return \"rems%.l %2,%3:%0\;divs%.l %2,%0\"; +}") + +(define_insn "" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (div:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_src_operand" "dmSTK"))) (set (match_operand:SI 3 "nonimmediate_operand" "=d") (mod:SI (match_dup 1) (match_dup 2)))] - "TARGET_68020 && !TARGET_5200" + "TARGET_68020" "* { if (find_reg_note (insn, REG_UNUSED, operands[3])) @@ -3104,13 +3131,40 @@ return \"divsl%.l %2,%3:%0\"; }") -(define_insn "udivmodsi4" +(define_expand "udivmodsi4" + [(parallel + [(set (match_operand:SI 0 "nonimmediate_operand" "=d") + (udiv:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_src_operand" "dmSTK"))) + (set (match_operand:SI 3 "nonimmediate_operand" "=d") + (umod:SI (match_dup 1) (match_dup 2)))])] + "TARGET_68020 || TARGET_CF_HWDIV" + "") + +(define_insn "" + [(set (match_operand:SI 0 "nonimmediate_operand" "=d") + (udiv:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_src_operand" "d<Q>U"))) + (set (match_operand:SI 3 "nonimmediate_operand" "=&d") + (umod:SI (match_dup 1) (match_dup 2)))] + "TARGET_CF_HWDIV" + "* +{ + if (find_reg_note (insn, REG_UNUSED, operands[3])) + return \"divu%.l %2,%0\"; + else if (find_reg_note (insn, REG_UNUSED, operands[0])) + return \"remu%.l %2,%3:%0\"; + else + return \"remu%.l %2,%3:%0\;divu%.l %2,%0\"; +}") + +(define_insn "" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (udiv:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_src_operand" "dmSTK"))) (set (match_operand:SI 3 "nonimmediate_operand" "=d") (umod:SI (match_dup 1) (match_dup 2)))] - "TARGET_68020 && !TARGET_5200" + "TARGET_68020 && !TARGET_COLDFIRE" "* { if (find_reg_note (insn, REG_UNUSED, operands[3])) @@ -3125,7 +3179,7 @@ (match_operand:HI 2 "general_src_operand" "dmSKT"))) (set (match_operand:HI 3 "nonimmediate_operand" "=d") (mod:HI (match_dup 1) (match_dup 2)))] - "!TARGET_5200" + "!TARGET_COLDFIRE || TARGET_CF_HWDIV" "* { #ifdef MOTOROLA @@ -3148,7 +3202,7 @@ (match_operand:HI 2 "general_src_operand" "dmSKT"))) (set (match_operand:HI 3 "nonimmediate_operand" "=d") (umod:HI (match_dup 1) (match_dup 2)))] - "!TARGET_5200" + "!TARGET_COLDFIRE || TARGET_CF_HWDIV" "* { #ifdef MOTOROLA @@ -3172,7 +3226,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d") (and:DI (match_operand:DI 1 "general_operand" "%0,0") (match_operand:DI 2 "general_operand" "dn,don")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -3249,7 +3303,7 @@ [(set (match_operand:SI 0 "not_sp_operand" "=m,d") (and:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { return output_andsi3 (operands); @@ -3259,49 +3313,49 @@ [(set (match_operand:SI 0 "not_sp_operand" "=m,d") (and:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_src_operand" "d,dmsK")))] - "TARGET_5200" + "TARGET_COLDFIRE" "and%.l %2,%0") (define_insn "andhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d") (and:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "and%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) (and:HI (match_dup 0) (match_operand:HI 1 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "and%.w %1,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "and%.w %1,%0") (define_insn "andqi3" [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") (and:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "and%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) (and:QI (match_dup 0) (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "and%.b %1,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "and%.b %1,%0") ;; inclusive-or instructions @@ -3310,7 +3364,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d") (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn")) (match_operand:DI 2 "general_operand" "0,0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { int byte_mode; @@ -3337,7 +3391,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d") (ior:DI (match_operand:DI 1 "general_operand" "%0,0") (match_operand:DI 2 "general_operand" "dn,don")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -3414,7 +3468,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d") (ior:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))] - "! TARGET_5200" + "! TARGET_COLDFIRE" "* { return output_iorsi3 (operands); @@ -3424,49 +3478,49 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d") (ior:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_src_operand" "d,dmsK")))] - "TARGET_5200" + "TARGET_COLDFIRE" "or%.l %2,%0") (define_insn "iorhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d") (ior:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "or%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) (ior:HI (match_dup 0) (match_operand:HI 1 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "or%.w %1,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "or%.w %1,%0") (define_insn "iorqi3" [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") (ior:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "or%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) (ior:QI (match_dup 0) (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "or%.b %1,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "or%.b %1,%0") ;; On all 68k models, this makes faster code in a special case. @@ -3493,7 +3547,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d") (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn")) (match_operand:SI 2 "general_operand" "0,0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { int byte_mode; @@ -3516,7 +3570,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=od") (xor:DI (match_operand:DI 1 "general_operand" "%0") (match_operand:DI 2 "general_operand" "dn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -3597,7 +3651,7 @@ (xor:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_operand" "di,dKT")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { return output_xorsi3 (operands); @@ -3607,49 +3661,49 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d") (xor:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_operand" "d,Ks")))] - "TARGET_5200" + "TARGET_COLDFIRE" "eor%.l %2,%0") (define_insn "xorhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") (xor:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "dn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "eor%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) (xor:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "eor%.w %1,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) (xor:HI (match_operand:HI 1 "general_operand" "dn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "eor%.w %1,%0") (define_insn "xorqi3" [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") (xor:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "general_operand" "dn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "eor%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) (xor:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "eor%.b %1,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) (xor:QI (match_operand:QI 1 "general_operand" "dn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "eor%.b %1,%0") ;; negation instructions @@ -3660,7 +3714,7 @@ "" " { - if (TARGET_5200) + if (TARGET_COLDFIRE) emit_insn (gen_negdi2_5200 (operands[0], operands[1])); else emit_insn (gen_negdi2_internal (operands[0], operands[1])); @@ -3670,7 +3724,7 @@ (define_insn "negdi2_internal" [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a") (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (which_alternative == 0) @@ -3688,7 +3742,7 @@ (define_insn "negdi2_5200" [(set (match_operand:DI 0 "nonimmediate_operand" "=d") (neg:DI (match_operand:DI 1 "general_operand" "0")))] - "TARGET_5200" + "TARGET_COLDFIRE" "* { operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); @@ -3701,7 +3755,7 @@ "" " { - if (TARGET_5200) + if (TARGET_COLDFIRE) emit_insn (gen_negsi2_5200 (operands[0], operands[1])); else emit_insn (gen_negsi2_internal (operands[0], operands[1])); @@ -3711,37 +3765,37 @@ (define_insn "negsi2_internal" [(set (match_operand:SI 0 "nonimmediate_operand" "=dm") (neg:SI (match_operand:SI 1 "general_operand" "0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "neg%.l %0") (define_insn "negsi2_5200" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (neg:SI (match_operand:SI 1 "general_operand" "0")))] - "TARGET_5200" + "TARGET_COLDFIRE" "neg%.l %0") (define_insn "neghi2" [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") (neg:HI (match_operand:HI 1 "general_operand" "0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "neg%.w %0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) (neg:HI (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "neg%.w %0") (define_insn "negqi2" [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") (neg:QI (match_operand:QI 1 "general_operand" "0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "neg%.b %0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) (neg:QI (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "neg%.b %0") ;; If using software floating point, just flip the sign bit. @@ -3957,7 +4011,7 @@ (define_insn "one_cmpldi2" [(set (match_operand:DI 0 "nonimmediate_operand" "=dm") (not:DI (match_operand:DI 1 "general_operand" "0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -3977,7 +4031,7 @@ "" " { - if (TARGET_5200) + if (TARGET_COLDFIRE) emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1])); else emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1])); @@ -3987,37 +4041,37 @@ (define_insn "one_cmplsi2_internal" [(set (match_operand:SI 0 "nonimmediate_operand" "=dm") (not:SI (match_operand:SI 1 "general_operand" "0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "not%.l %0") (define_insn "one_cmplsi2_5200" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (not:SI (match_operand:SI 1 "general_operand" "0")))] - "TARGET_5200" + "TARGET_COLDFIRE" "not%.l %0") (define_insn "one_cmplhi2" [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") (not:HI (match_operand:HI 1 "general_operand" "0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "not%.w %0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) (not:HI (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "not%.w %0") (define_insn "one_cmplqi2" [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") (not:QI (match_operand:QI 1 "general_operand" "0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "not%.b %0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) (not:QI (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "not%.b %0") ;; arithmetic shift instructions @@ -4101,7 +4155,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") (ashift:DI (match_operand:DI 1 "general_operand" "0") (match_operand 2 "const_int_operand" "n")))] - "(!TARGET_5200 + "(!TARGET_COLDFIRE && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))" @@ -4133,7 +4187,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "") (ashift:DI (match_operand:DI 1 "general_operand" "") (match_operand 2 "const_int_operand" "")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" " { /* ??? This is a named pattern like this is not allowed to FAIL based @@ -4167,7 +4221,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (ashift:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] - "(! TARGET_68020 && !TARGET_5200 + "(! TARGET_68020 && !TARGET_COLDFIRE && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" "* { @@ -4196,28 +4250,28 @@ [(set (match_operand:HI 0 "register_operand" "=d") (ashift:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsl%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (ashift:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsl%.w %1,%0") (define_insn "ashlqi3" [(set (match_operand:QI 0 "register_operand" "=d") (ashift:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsl%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (ashift:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsl%.b %1,%0") ;; On most 68k models, this makes faster code in a special case. @@ -4235,7 +4289,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] - "(! TARGET_68020 && !TARGET_5200 + "(! TARGET_68020 && !TARGET_COLDFIRE && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" "* { @@ -4304,7 +4358,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") (ashiftrt:DI (match_operand:DI 1 "general_operand" "0") (match_operand 2 "const_int_operand" "n")))] - "(!TARGET_5200 + "(!TARGET_COLDFIRE && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 31 @@ -4344,7 +4398,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "") (ashiftrt:DI (match_operand:DI 1 "general_operand" "") (match_operand 2 "const_int_operand" "")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" " { /* ??? This is a named pattern like this is not allowed to FAIL based @@ -4379,28 +4433,28 @@ [(set (match_operand:HI 0 "register_operand" "=d") (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "asr%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (ashiftrt:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "asr%.w %1,%0") (define_insn "ashrqi3" [(set (match_operand:QI 0 "register_operand" "=d") (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "asr%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (ashiftrt:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "asr%.b %1,%0") ;; logical shift instructions @@ -4477,7 +4531,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") (lshiftrt:DI (match_operand:DI 1 "general_operand" "0") (match_operand 2 "const_int_operand" "n")))] - "(!TARGET_5200 + "(!TARGET_COLDFIRE && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))" @@ -4512,7 +4566,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "") (lshiftrt:DI (match_operand:DI 1 "general_operand" "") (match_operand 2 "const_int_operand" "")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" " { /* ??? This is a named pattern like this is not allowed to FAIL based @@ -4555,7 +4609,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] - "(! TARGET_68020 && !TARGET_5200 + "(! TARGET_68020 && !TARGET_COLDFIRE && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" "* { @@ -4575,28 +4629,28 @@ [(set (match_operand:HI 0 "register_operand" "=d") (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsr%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (lshiftrt:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsr%.w %1,%0") (define_insn "lshrqi3" [(set (match_operand:QI 0 "register_operand" "=d") (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsr%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (lshiftrt:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsr%.b %1,%0") ;; rotate instructions @@ -4605,7 +4659,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (rotate:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "dINO")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16) @@ -4623,7 +4677,7 @@ [(set (match_operand:HI 0 "register_operand" "=d") (rotate:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dIP")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8) @@ -4639,7 +4693,7 @@ [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (rotate:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dIP")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8) @@ -4655,7 +4709,7 @@ [(set (match_operand:QI 0 "register_operand" "=d") (rotate:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4) @@ -4671,7 +4725,7 @@ [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (rotate:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4) @@ -4687,35 +4741,35 @@ [(set (match_operand:SI 0 "register_operand" "=d") (rotatert:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "ror%.l %2,%0") (define_insn "rotrhi3" [(set (match_operand:HI 0 "register_operand" "=d") (rotatert:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "ror%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (rotatert:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "ror%.w %1,%0") (define_insn "rotrqi3" [(set (match_operand:QI 0 "register_operand" "=d") (rotatert:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "ror%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (rotatert:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "ror%.b %1,%0") @@ -5179,7 +5233,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") (match_operator 1 "valid_dbcc_comparison_p" [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))] - "! TARGET_5200" + "! TARGET_COLDFIRE" "* { return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]); @@ -5189,7 +5243,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=d") (match_operator 1 "valid_dbcc_comparison_p" [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))] - "TARGET_5200" + "TARGET_COLDFIRE" "* { return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]); @@ -5200,7 +5254,7 @@ (match_operator 1 "valid_dbcc_comparison_p" [(match_operand:DI 2 "general_operand" "ro,r") (match_operand:DI 3 "general_operand" "r,ro")]))] - "! TARGET_5200" + "! TARGET_COLDFIRE" "* { return output_scc_di (operands[1], operands[2], operands[3], operands[0]); @@ -5211,7 +5265,7 @@ (match_operator 1 "valid_dbcc_comparison_p" [(match_operand:DI 2 "general_operand" "ro,r") (match_operand:DI 3 "general_operand" "r,ro")]))] - "TARGET_5200" + "TARGET_COLDFIRE" "* { return output_scc_di (operands[1], operands[2], operands[3], operands[0]); @@ -5658,7 +5712,7 @@ #endif } operands[4] = gen_label_rtx(); - if (TARGET_68020 || TARGET_5200) + if (TARGET_68020 || TARGET_COLDFIRE) { #ifdef MOTOROLA output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands); @@ -5737,7 +5791,7 @@ return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\"; #endif } - if (TARGET_68020 || TARGET_5200) + if (TARGET_68020 || TARGET_COLDFIRE) { #ifdef MOTOROLA return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\"; @@ -5792,7 +5846,7 @@ } } CC_STATUS_INIT; - if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0])) + if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0])) output_asm_insn(\"tst%.l %0\", operands); else { @@ -5844,7 +5898,7 @@ } } CC_STATUS_INIT; - if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0])) + if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0])) output_asm_insn(\"tst%.l %0\", operands); else { @@ -6463,7 +6517,7 @@ #else #ifdef SGS #ifdef ASM_OUTPUT_CASE_LABEL - if (TARGET_5200) + if (TARGET_COLDFIRE) { if (ADDRESS_REG_P (operands[0])) return \"jmp 6(%%pc,%0.l)\"; @@ -6473,7 +6527,7 @@ else return \"jmp 6(%%pc,%0.w)\"; #else - if (TARGET_5200) + if (TARGET_COLDFIRE) { if (ADDRESS_REG_P (operands[0])) return \"jmp 2(%%pc,%0.l)\"; @@ -6484,7 +6538,7 @@ return \"jmp 2(%%pc,%0.w)\"; #endif #else /* not SGS */ - if (TARGET_5200) + if (TARGET_COLDFIRE) { if (ADDRESS_REG_P (operands[0])) { @@ -6526,7 +6580,7 @@ (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -6561,7 +6615,7 @@ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -6597,7 +6651,7 @@ (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))] - "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)" + "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)" "* { CC_STATUS_INIT; @@ -6645,7 +6699,7 @@ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))] - "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)" + "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)" "* { CC_STATUS_INIT; @@ -6973,7 +7027,7 @@ xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4); if (INTVAL (xoperands[1]) <= 8) { - if (!TARGET_5200) + if (!TARGET_COLDFIRE) output_asm_insn (\"addq%.w %1,%0\", xoperands); else output_asm_insn (\"addq%.l %1,%0\", xoperands); @@ -7020,7 +7074,7 @@ xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4); if (INTVAL (xoperands[1]) <= 8) { - if (!TARGET_5200) + if (!TARGET_COLDFIRE) output_asm_insn (\"addq%.w %1,%0\", xoperands); else output_asm_insn (\"addq%.l %1,%0\", xoperands); @@ -7069,7 +7123,7 @@ xoperands[2] = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3)); xoperands[3] = stack_pointer_rtx; - if (!TARGET_5200) + if (!TARGET_COLDFIRE) output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands); else output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands); @@ -7091,7 +7145,7 @@ || GET_CODE (operands[0]) == MEM) /* clr insns on 68000 read before writing. This isn't so on the 68010, but we have no TARGET_68010. */ - && ((TARGET_68020 || TARGET_5200) + && ((TARGET_68020 || TARGET_COLDFIRE) || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) return \"clr%.w %0\"; @@ -7131,7 +7185,7 @@ (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))])] - "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" + "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" "* { CC_STATUS_INIT; @@ -7154,7 +7208,7 @@ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))])] - "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" + "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" "* { CC_STATUS_INIT; @@ -7178,7 +7232,7 @@ (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))])] - "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" + "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" "* { CC_STATUS_INIT; @@ -7202,7 +7256,7 @@ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))])] - "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" + "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" "* { CC_STATUS_INIT; |